NetBom: EP Verify


NetList: packaged_20210921_02/pstxnet.dat	PinReport: xc200_cpld_phys.pad

Match Score	Endpoint: U1_CPLD	Net Name	Net Volt	Sig Name	Pin Name	Pin Type	Pin / Bank Volt	Io Std	Bank
-	U1_CPLD.A1 A1	CPLD_P3R3V CPLD_P3R3V	3.3	VCC	VCC	POWER		none	-
100	U1_CPLD.A2 A2	NC NC		NC	NC	BIDIR		none	-
93	U1_CPLD.A3 A3	STAT_LED_ON_F<0>_CPLD STAT_LED_ON_F<0>_CPLD		stat_led_on_f0	IO9_PT12A_0	OUTPUT	1.8V	LVCMOS18	0
-	U1_CPLD.A4 A4	UNNAMED_7_SM050TP_I166_1_CPLD UNNAMED_7_SM050TP_I166_1_CPLD		UNUSED	IO5_PT10A_0	INOUT	1.8V	none	0
-	U1_CPLD.A5 A5	UNNAMED_7_SM050TP_I164_1_CPLD UNNAMED_7_SM050TP_I164_1_CPLD		UNUSED	IO7_PT11A_0	INOUT	1.8V	none	0
-	U1_CPLD.A6 A6	CPLD_TDI_PIN_CPLD CPLD_TDI_PIN_CPLD		UNUSED	IO10_PT13D_TDI_0	INOUT	1.8V	none	0
-	U1_CPLD.A7 A7	CPLD_TCK_PIN_CPLD CPLD_TCK_PIN_CPLD		UNUSED	IO19_PT15C_TCK_0	INOUT	1.8V	none	0
93	U1_CPLD.A8 A8	RGB_LED_GREEN<2>_CPLD RGB_LED_GREEN<2>_CPLD		rgb_led_green2	IO22_PT18B_PCLKC0_1_0	OUTPUT	1.8V	LVCMOS18	0
96	U1_CPLD.A9 A9	BASE_3R3V_SCL_2 BASE_3R3V_SCL_2	3.3V	base_3r3v_scl	IO27_PT20C_SCL/PCLKT0_0_0	INOUT	1.8V	LVCMOS18	0
96	U1_CPLD.A10 A10	FPGA_CPLD_RSVD<1>_1 FPGA_CPLD_RSVD<1>_1		fpga_cpld_rsvd1	IO30_PT21B_0	OUTPUT	1.8V	LVCMOS18	0
100	U1_CPLD.A11 A11	JT_FPGA_TMS JT_FPGA_TMS		jt_fpga_tms	IO41_PT24A_0	INOUT	1.8V	LVCMOS18	0
100	U1_CPLD.A12 A12	JT_FPGA_TDO JT_FPGA_TDO		jt_fpga_tdo	IO42_PT25B_0	OUTPUT	1.8V	LVCMOS18	0
62	U1_CPLD.A13 A13	JT_CPLD_TDO JT_CPLD_TDO		cpld_self_tdo	IO49_PT28C_INITN_0	INPUT	1.8V	LVCMOS18	0
100	U1_CPLD.A14 A14	JT_FPGA_TCK JT_FPGA_TCK		jt_fpga_tck	IO44_PT26B_0	INOUT	1.8V	LVCMOS18	0
93	U1_CPLD.A15 A15	CPLD_SELF_TDI_CPLD CPLD_SELF_TDI_CPLD		cpld_self_tdi	IO50_PT28B_0	OUTPUT	1.8V	LVCMOS18	0
-	U1_CPLD.A16 A16	CPLD_P3R3V CPLD_P3R3V	3.3	VCC	VCC	POWER		none	-
-	U1_CPLD.B1 B1	NC NC		UNUSED	IO2_PL2C_5	INOUT	1.8V	none	5
100	U1_CPLD.B2 B2	GND GND	0V	GND	GND	GROUND		none	-
-	U1_CPLD.B3 B3	NC NC		UNUSED	IO1_PT9C_0	INOUT	1.8V	none	0
-	U1_CPLD.B4 B4	UNNAMED_7_SM050TP_I163_1_CPLD UNNAMED_7_SM050TP_I163_1_CPLD		UNUSED	IO8_PT12B_0	INOUT	1.8V	none	0
-	U1_CPLD.B5 B5	UNNAMED_7_SM050TP_I165_1_CPLD UNNAMED_7_SM050TP_I165_1_CPLD		UNUSED	IO2_PT9B_0	INOUT	1.8V	none	0
-	U1_CPLD.B6 B6	NC NC		UNUSED	IO6_PT11B_0	INOUT	1.8V	none	0
93	U1_CPLD.B7 B7	RGB_LED_BLUE<2>_CPLD RGB_LED_BLUE<2>_CPLD		rgb_led_blue2	IO17_PT14A_0	OUTPUT	1.8V	LVCMOS18	0
-	U1_CPLD.B8 B8	CPLD_TMS_PIN_CPLD CPLD_TMS_PIN_CPLD		UNUSED	IO18_PT15D_TMS_0	INOUT	1.8V	none	0
96	U1_CPLD.B9 B9	FPGA_CPLD_RSVD<2>_1 FPGA_CPLD_RSVD<2>_1		fpga_cpld_rsvd2	IO31_PT21A_0	OUTPUT	1.8V	LVCMOS18	0
98	U1_CPLD.B10 B10	CPLD_FPGA_DQ<0> CPLD_FPGA_DQ<0>		cpld_fpga_dq0	IO34_PT23D_PROGRAMN_0	OUTPUT	1.8V	LVCMOS18	0
100	U1_CPLD.B11 B11	JT_FPGA_TDI JT_FPGA_TDI		jt_fpga_tdi	IO43_PT25A_0	INOUT	1.8V	LVCMOS18	0
100	U1_CPLD.B12 B12	HOST_3R3V_SDA HOST_3R3V_SDA	3.3V	host_3r3v_sda	IO46_PT27B_0	OUTPUT	1.8V	LVCMOS18	0
100	U1_CPLD.B13 B13	JT_FPGA_INST_F JT_FPGA_INST_F		jt_fpga_inst_f	IO45_PT26A_0	INPUT	1.8V	LVCMOS18	0
93	U1_CPLD.B14 B14	CPLD_SELF_TCK_CPLD CPLD_SELF_TCK_CPLD		cpld_self_tck	IO51_PT28A_0	OUTPUT	1.8V	LVCMOS18	0
100	U1_CPLD.B15 B15	GND GND	0V	GND	GND	GROUND		none	-
83	U1_CPLD.B16 B16	UNNAMED_7_SM050TP_I153_1_CPLD UNNAMED_7_SM050TP_I153_1_CPLD		tp11_cpld	IO1_PR2D_1	OUTPUT	3.3V	LVCMOS33	1
100	U1_CPLD.C1 C1	SI5341_INTR SI5341_INTR		si5341_intr	IO6_PL4C_5	INPUT	1.8V	LVCMOS18	5
-	U1_CPLD.C2 C2	NC NC		UNUSED	IO1_PL2D_5	INOUT	1.8V	none	5
100	U1_CPLD.C3 C3	GND GND	0V	GND	GND	GROUND		none	-
-	U1_CPLD.C4 C4	NC NC		UNUSED	IO3_PT9A_0	INOUT	1.8V	none	0
-	U1_CPLD.C5 C5	NC NC		UNUSED	IO4_PT10B_0	INOUT	1.8V	none	0
-	U1_CPLD.C6 C6	JT_CPLD_TDO JT_CPLD_TDO		UNUSED	IO11_PT13C_TDO_0	INOUT	1.8V	none	0
93	U1_CPLD.C7 C7	RGB_LED_BLUE<1>_CPLD RGB_LED_BLUE<1>_CPLD		rgb_led_blue1	IO16_PT14B_0	OUTPUT	1.8V	LVCMOS18	0
96	U1_CPLD.C8 C8	FPGA_CPLD_DCLK_1 FPGA_CPLD_DCLK_1		fpga_cpld_dclk	IO23_PT18A_PCLKT0_1_0	INPUT	1.8V	LVCMOS18	0
96	U1_CPLD.C9 C9	BASE_3R3V_SDA_2 BASE_3R3V_SDA_2	3.3V	base_3r3v_sda	IO26_PT20D_SDA/PCLKC0_0_0	INOUT	1.8V	LVCMOS18	0
-	U1_CPLD.C10 C10	NC NC		UNUSED	IO35_PT23C_JTAGENB_0	INOUT	1.8V	none	0
96	U1_CPLD.C11 C11	FPGA_CPLD_DQ<1>_1 FPGA_CPLD_DQ<1>_1		fpga_cpld_dq1	IO40_PT24B_0	OUTPUT	1.8V	LVCMOS18	0
100	U1_CPLD.C12 C12	HOST_3R3V_SCL HOST_3R3V_SCL	3.3V	host_3r3v_scl	IO47_PT27A_0	OUTPUT	1.8V	LVCMOS18	0
93	U1_CPLD.C13 C13	CPLD_SELF_TMS_CPLD CPLD_SELF_TMS_CPLD		cpld_self_tms	IO48_PT28D_DONE_0	OUTPUT	1.8V	LVCMOS18	0
100	U1_CPLD.C14 C14	GND GND	0V	GND	GND	GROUND		none	-
83	U1_CPLD.C15 C15	UNNAMED_7_SM050TP_I154_1_CPLD UNNAMED_7_SM050TP_I154_1_CPLD		tp14_cpld	IO2_PR2C_1	OUTPUT	3.3V	LVCMOS33	1
-	U1_CPLD.C16 C16	NC NC		UNUSED	IO8_PR4C_1	INOUT	3.3V	none	1
-	U1_CPLD.D1 D1	NC NC		UNUSED	IO3_PL3B_L_GPLLC_FB_5	INOUT	1.8V	none	5
100	U1_CPLD.D2 D2	SI5341_LOL_N SI5341_LOL_N		si5341_lol_n	IO5_PL4D_5	INPUT	1.8V	LVCMOS18	5
100	U1_CPLD.D3 D3	CFG_FLASH_RST_F CFG_FLASH_RST_F		cfg_flash_rst_f	IO4_PL3A_L_GPLLT_FB_5	OUTPUT	1.8V	LVCMOS18	5
100	U1_CPLD.D4 D4	GND GND	0V	GND	GND	GROUND		none	-
-	U1_CPLD.D5 D5	CPLD_P1R8V_1 CPLD_P1R8V_1	1.8	VCCIO0	VCCIO0	POWER	1.8V	none	0
93	U1_CPLD.D6 D6	STAT_LED_ON_F<2>_CPLD STAT_LED_ON_F<2>_CPLD		stat_led_on_f2	IO13_PT13A_0	OUTPUT	1.8V	LVCMOS18	0
93	U1_CPLD.D7 D7	STAT_LED_ON_F<3>_CPLD STAT_LED_ON_F<3>_CPLD		stat_led_on_f3	IO14_PT14D_0	OUTPUT	1.8V	LVCMOS18	0
93	U1_CPLD.D8 D8	RGB_LED_RED<1>_CPLD RGB_LED_RED<1>_CPLD		rgb_led_red1	IO25_PT19A_0	OUTPUT	1.8V	LVCMOS18	0
93	U1_CPLD.D9 D9	RGB_LED_RED<2>_CPLD RGB_LED_RED<2>_CPLD		rgb_led_red2	IO28_PT20B_0	OUTPUT	1.8V	LVCMOS18	0
96	U1_CPLD.D10 D10	CPLD_FPGA_DCLK_1 CPLD_FPGA_DCLK_1		cpld_fpga_dclk	IO37_PT23A_0	OUTPUT	1.8V	LVCMOS18	0
96	U1_CPLD.D11 D11	FPGA_CPLD_DVAL_1 FPGA_CPLD_DVAL_1		fpga_cpld_dval	IO38_PT24D_0	INPUT	1.8V	LVCMOS18	0
-	U1_CPLD.D12 D12	CPLD_P1R8V_1 CPLD_P1R8V_1	1.8	VCCIO0	VCCIO0	POWER	1.8V	none	0
100	U1_CPLD.D13 D13	GND GND	0V	GND	GND	GROUND		none	-
-	U1_CPLD.D14 D14	NC NC		UNUSED	IO4_PR2A_R_GPLLT_FB_1	INOUT	3.3V	none	1
84	U1_CPLD.D15 D15	UNNAMED_7_SM050TP_I157_1_CPLD UNNAMED_7_SM050TP_I157_1_CPLD		tp9_cpld	IO7_PR4D_1	OUTPUT	3.3V	LVCMOS33	1
-	U1_CPLD.D16 D16	NC NC		UNUSED	IO6_PR3A_R_GPLLT_IN_1	INOUT	3.3V	none	1
97	U1_CPLD.E1 E1	TDO_JTAG_CTL TDO_JTAG_CTL		tdo_jtag_ctl0	IO12_PL6A_PCLKT5_0_5	OUTPUT	1.8V	LVCMOS18	5
100	U1_CPLD.E2 E2	SI5341_RST_N SI5341_RST_N		si5341_rst_n	IO8_PL4A_L_GPLLT_IN_5	OUTPUT	1.8V	LVCMOS18	5
100	U1_CPLD.E3 E3	SI5341_SYNC_N SI5341_SYNC_N		si5341_sync_n	IO7_PL4B_L_GPLLC_IN_5	OUTPUT	1.8V	LVCMOS18	5
-	U1_CPLD.E4 E4	CPLD_P1R8V_1 CPLD_P1R8V_1	1.8	VCCIO5	VCCIO5	POWER	1.8V	none	5
100	U1_CPLD.E5 E5	GND GND	0V	GND	GND	GROUND		none	-
93	U1_CPLD.E6 E6	RGB_LED_BLUE<0>_CPLD RGB_LED_BLUE<0>_CPLD		rgb_led_blue0	IO15_PT14C_0	OUTPUT	1.8V	LVCMOS18	0
93	U1_CPLD.E7 E7	STAT_LED_ON_F<1>_CPLD STAT_LED_ON_F<1>_CPLD		stat_led_on_f1	IO12_PT13B_0	OUTPUT	1.8V	LVCMOS18	0
93	U1_CPLD.E8 E8	RGB_LED_GREEN<0>_CPLD RGB_LED_GREEN<0>_CPLD		rgb_led_green0	IO20_PT15B_0	OUTPUT	1.8V	LVCMOS18	0
93	U1_CPLD.E9 E9	RGB_LED_RED<0>_CPLD RGB_LED_RED<0>_CPLD		rgb_led_red0	IO24_PT19B_0	OUTPUT	1.8V	LVCMOS18	0
98	U1_CPLD.E10 E10	CPLD_FPGA_DQ<1> CPLD_FPGA_DQ<1>		cpld_fpga_dq1	IO36_PT23B_0	OUTPUT	1.8V	LVCMOS18	0
96	U1_CPLD.E11 E11	FPGA_CPLD_RSVD<3>_1 FPGA_CPLD_RSVD<3>_1		fpga_cpld_rsvd3	IO32_PT22B_0	OUTPUT	1.8V	LVCMOS18	0
100	U1_CPLD.E12 E12	GND GND	0V	GND	GND	GROUND		none	-
-	U1_CPLD.E13 E13	CPLD_P3R3V CPLD_P3R3V	3.3	VCCIO1	VCCIO1	POWER	3.3V	none	1
-	U1_CPLD.E14 E14	NC NC		UNUSED	IO5_PR3B_R_GPLLC_IN_1	INOUT	3.3V	none	1
83	U1_CPLD.E15 E15	UNNAMED_7_SM050TP_I155_1_CPLD UNNAMED_7_SM050TP_I155_1_CPLD		tp10_cpld	IO3_PR2B_R_GPLLC_FB_1	OUTPUT	3.3V	LVCMOS33	1
100	U1_CPLD.E16 E16	PCIE1_RST_F PCIE1_RST_F		pcie1_rst_f	IO12_PR5A_1	OUTPUT	3.3V	LVCMOS33	1
97	U1_CPLD.F1 F1	JTAG_CTL_TCK JTAG_CTL_TCK		jtag_ctl_tck0	IO15_PL7B_5	INPUT	1.8V	LVCMOS18	5
100	U1_CPLD.F2 F2	SI5341_DIS_CLKS SI5341_DIS_CLKS		si5341_dis_clks	IO11_PL6B_PCLKC5_0_5	OUTPUT	1.8V	LVCMOS18	5
100	U1_CPLD.F3 F3	FPGA_P1R8V_TMS FPGA_P1R8V_TMS	1.8V	fpga_p1r8v_tms	IO16_PL7A_5	OUTPUT	1.8V	LVCMOS18	5
100	U1_CPLD.F4 F4	SI5341_FDEC SI5341_FDEC		si5341_fdec	IO10_PL6C_5	OUTPUT	1.8V	LVCMOS18	5
100	U1_CPLD.F5 F5	FPGA_P1R8V_TDI FPGA_P1R8V_TDI	1.8V	fpga_p1r8v_tdi	IO18_PL8C_5	OUTPUT	1.8V	LVCMOS18	5
100	U1_CPLD.F6 F6	GND GND	0V	GND	GND	GROUND		none	-
93	U1_CPLD.F7 F7	RGB_LED_GREEN<1>_CPLD RGB_LED_GREEN<1>_CPLD		rgb_led_green1	IO21_PT15A_0	OUTPUT	1.8V	LVCMOS18	0
96	U1_CPLD.F8 F8	FPGA_CPLD_RSVD<0>_1 FPGA_CPLD_RSVD<0>_1		fpga_cpld_rsvd0	IO29_PT20A_0	OUTPUT	1.8V	LVCMOS18	0
96	U1_CPLD.F9 F9	CPLD_FPGA_DVAL_1 CPLD_FPGA_DVAL_1		cpld_fpga_dval	IO33_PT22A_0	OUTPUT	1.8V	LVCMOS18	0
96	U1_CPLD.F10 F10	FPGA_CPLD_DQ<0>_1 FPGA_CPLD_DQ<0>_1		fpga_cpld_dq0	IO39_PT24C_0	OUTPUT	1.8V	LVCMOS18	0
100	U1_CPLD.F11 F11	GND GND	0V	GND	GND	GROUND		none	-
100	U1_CPLD.F12 F12	PCIE_X1_RESET_3V_F PCIE_X1_RESET_3V_F	3V	pcie_x1_reset_3v_f	IO14_PR6C_1	INPUT	3.3V	LVCMOS33	1
-	U1_CPLD.F13 F13	NC NC		UNUSED	IO10_PR5C_1	INOUT	3.3V	none	1
100	U1_CPLD.F14 F14	PCIE0_RESET_3V_F PCIE0_RESET_3V_F	3V	pcie0_reset_3v_f	IO16_PR6A_1	INPUT	3.3V	LVCMOS33	1
100	U1_CPLD.F15 F15	PCIE_X1_RST_F PCIE_X1_RST_F		pcie_x1_rst_f	IO11_PR5B_1	OUTPUT	3.3V	LVCMOS33	1
100	U1_CPLD.F16 F16	PCIE1_RESET_3V_F PCIE1_RESET_3V_F	3V	pcie1_reset_3v_f	IO15_PR6B_1	INPUT	3.3V	LVCMOS33	1
96	U1_CPLD.G1 G1	FPGA_CFG_MODE<1>_1 FPGA_CFG_MODE<1>_1		fpga_cfg_mode1	IO4_PL9A_4	OUTPUT	1.8V	LVCMOS18	4
96	U1_CPLD.G2 G2	FPGA_PROG_F_1 FPGA_PROG_F_1		fpga_prog_f	IO20_PL8A_5	OUTPUT	1.8V	LVCMOS18	5
100	U1_CPLD.G3 G3	FPGA_P1R8V_TCK FPGA_P1R8V_TCK	1.8V	fpga_p1r8v_tck	IO19_PL8B_5	OUTPUT	1.8V	LVCMOS18	5
97	U1_CPLD.G4 G4	JTAG_CTL_TMS JTAG_CTL_TMS		jtag_ctl_tms0	IO13_PL7D_5	INPUT	1.8V	LVCMOS18	5
97	U1_CPLD.G5 G5	JTAG_CTL_TDI JTAG_CTL_TDI		jtag_ctl_tdi0	IO14_PL7C_5	INPUT	1.8V	LVCMOS18	5
100	U1_CPLD.G6 G6	SI5341_FINC SI5341_FINC		si5341_finc	IO9_PL6D_5	OUTPUT	1.8V	LVCMOS18	5
-	U1_CPLD.G7 G7	CPLD_P3R3V CPLD_P3R3V	3.3	VCC	VCC	POWER		none	-
-	U1_CPLD.G8 G8	CPLD_P1R8V_1 CPLD_P1R8V_1	1.8	VCCIO0	VCCIO0	POWER	1.8V	none	0
-	U1_CPLD.G9 G9	CPLD_P1R8V_1 CPLD_P1R8V_1	1.8	VCCIO0	VCCIO0	POWER	1.8V	none	0
-	U1_CPLD.G10 G10	CPLD_P3R3V CPLD_P3R3V	3.3	VCC	VCC	POWER		none	-
98	U1_CPLD.G11 G11	FAN_TACH_OD<2> FAN_TACH_OD<2>		fan_tach_od2	IO18_PR8C_1	INPUT	3.3V	LVCMOS33	1
-	U1_CPLD.G12 G12	NC NC		UNUSED	IO9_PR5D_1	INOUT	3.3V	none	1
100	U1_CPLD.G13 G13	PCIE0_RST_F PCIE0_RST_F		pcie0_rst_f	IO13_PR6D_1	OUTPUT	3.3V	LVCMOS33	1
98	U1_CPLD.G14 G14	FAN_TACH_OD<3> FAN_TACH_OD<3>		fan_tach_od3	IO19_PR8B_1	INPUT	3.3V	LVCMOS33	1
98	U1_CPLD.G15 G15	FAN_TACH_OD<4> FAN_TACH_OD<4>		fan_tach_od4	IO20_PR8A_1	INPUT	3.3V	LVCMOS33	1
98	U1_CPLD.G16 G16	FP_LAN_ACTLED_N<2> FP_LAN_ACTLED_N<2>		fp_lan_actled_n2	IO24_PR9A_1	OUTPUT	3.3V	LVCMOS33	1
96	U1_CPLD.H1 H1	FPGA_CFG_DONE_1 FPGA_CFG_DONE_1		fpga_cfg_done	IO7_PL10B_4	INPUT	1.8V	LVCMOS18	4
96	U1_CPLD.H2 H2	FPGA_CFG_MODE<0>_1 FPGA_CFG_MODE<0>_1		fpga_cfg_mode0	IO3_PL9B_4	OUTPUT	1.8V	LVCMOS18	4
100	U1_CPLD.H3 H3	DIS_1R8V_I2C_XLAT_F DIS_1R8V_I2C_XLAT_F	1.8V	dis_1r8v_i2c_xlat_f	IO8_PL10A_4	OUTPUT	1.8V	LVCMOS18	4
100	U1_CPLD.H4 H4	FPGA_DCM_LOCK_F FPGA_DCM_LOCK_F		fpga_dcm_lock_f	IO2_PL9C_4	INPUT	1.8V	LVCMOS18	4
100	U1_CPLD.H5 H5	CLK125M_FROM_CPLD CLK125M_FROM_CPLD		clk125m_from_cpld	IO10_PL13C_4	OUTPUT	1.8V	LVCMOS18	4
100	U1_CPLD.H6 H6	FPGA_P1R8V_TDO FPGA_P1R8V_TDO	1.8V	fpga_p1r8v_tdo	IO17_PL8D_5	INPUT	1.8V	LVCMOS18	5
-	U1_CPLD.H7 H7	CPLD_P1R8V_1 CPLD_P1R8V_1	1.8	VCCIO4	VCCIO4	POWER	1.8V	none	4
100	U1_CPLD.H8 H8	GND GND	0V	GND	GND	GROUND		none	-
100	U1_CPLD.H9 H9	GND GND	0V	GND	GND	GROUND		none	-
-	U1_CPLD.H10 H10	CPLD_P3R3V CPLD_P3R3V	3.3	VCCIO1	VCCIO1	POWER	3.3V	none	1
100	U1_CPLD.H11 H11	FP_PWR_SW_N FP_PWR_SW_N		fp_pwr_sw_n	IO30_PR13C_1	INPUT	3.3V	LVCMOS33	1
98	U1_CPLD.H12 H12	FAN_TACH_OD<1> FAN_TACH_OD<1>		fan_tach_od1	IO17_PR8D_1	INPUT	3.3V	LVCMOS33	1
100	U1_CPLD.H13 H13	ID_LED_N ID_LED_N		id_led_n	IO22_PR9C_1	OUTPUT	3.3V	LVCMOS33	1
100	U1_CPLD.H14 H14	FP_SYSID_SW_N FP_SYSID_SW_N		fp_sysid_sw_n	IO28_PR10A_PCLKT1_0_1	INPUT	3.3V	LVCMOS33	1
98	U1_CPLD.H15 H15	FP_LAN_ACTLED_N<1> FP_LAN_ACTLED_N<1>		fp_lan_actled_n1	IO23_PR9B_1	OUTPUT	3.3V	LVCMOS33	1
98	U1_CPLD.H16 H16	FP_FAULT_LED_N<2> FP_FAULT_LED_N<2>		fp_fault_led_n2	IO27_PR10B_PCLKC1_0_1	OUTPUT	3.3V	LVCMOS33	1
100	U1_CPLD.J1 J1	FPGA_CPLD_SSTAT_CLK FPGA_CPLD_SSTAT_CLK		fpga_cpld_sstat_clk	IO6_PL10C_PCLKT4_0_4	INPUT	1.8V	LVCMOS18	4
100	U1_CPLD.J2 J2	CPLD_FPGA_SSTAT CPLD_FPGA_SSTAT		cpld_fpga_sstat	IO12_PL13A_4	OUTPUT	1.8V	LVCMOS18	4
96	U1_CPLD.J3 J3	FPGA_CFG_MODE<2>_1 FPGA_CFG_MODE<2>_1		fpga_cfg_mode2	IO5_PL10D_PCLKC4_0_4	OUTPUT	1.8V	LVCMOS18	4
100	U1_CPLD.J4 J4	CPLD_SEL_CFG_FLASH CPLD_SEL_CFG_FLASH		cpld_sel_cfg_flash	IO9_PL13D_4	OUTPUT	1.8V	LVCMOS18	4
96	U1_CPLD.J5 J5	FPGA_ERR_VIS<0>_1 FPGA_ERR_VIS<0>_1		fpga_err_vis0	IO14_PL14C_4	INPUT	1.8V	LVCMOS18	4
96	U1_CPLD.J6 J6	FPGA_INIT_F_1 FPGA_INIT_F_1		fpga_init_f	IO1_PL9D_4	INOUT	1.8V	LVCMOS18	4
-	U1_CPLD.J7 J7	CPLD_P1R8V_1 CPLD_P1R8V_1	1.8	VCCIO4	VCCIO4	POWER	1.8V	none	4
100	U1_CPLD.J8 J8	GND GND	0V	GND	GND	GROUND		none	-
100	U1_CPLD.J9 J9	GND GND	0V	GND	GND	GROUND		none	-
-	U1_CPLD.J10 J10	CPLD_P3R3V CPLD_P3R3V	3.3	VCCIO1	VCCIO1	POWER	3.3V	none	1
100	U1_CPLD.J11 J11	LTC2975_CPLD_ENB_B LTC2975_CPLD_ENB_B		ltc2975_cpld_enb_b	IO34_PR14C_1	INPUT	3.3V	LVCMOS33	1
100	U1_CPLD.J12 J12	FAN_PWM_OD FAN_PWM_OD		fan_pwm_od	IO21_PR9D_1	OUTPUT	3.3V	LVCMOS33	1
100	U1_CPLD.J13 J13	FP_RST_SW_N FP_RST_SW_N		fp_rst_sw_n	IO29_PR13D_1	INPUT	3.3V	LVCMOS33	1
100	U1_CPLD.J14 J14	FP_HDD_LED_N FP_HDD_LED_N		fp_hdd_led_n	IO25_PR10D_1	OUTPUT	3.3V	LVCMOS33	1
100	U1_CPLD.J15 J15	LTC2975_CPLD_ENB_D LTC2975_CPLD_ENB_D		ltc2975_cpld_enb_d	IO32_PR13A_1	INPUT	3.3V	LVCMOS33	1
98	U1_CPLD.J16 J16	FP_FAULT_LED_N<1> FP_FAULT_LED_N<1>		fp_fault_led_n1	IO26_PR10C_1	OUTPUT	3.3V	LVCMOS33	1
100	U1_CPLD.K1 K1	FPGA_CPLD_SSTAT FPGA_CPLD_SSTAT		fpga_cpld_sstat	IO11_PL13B_4	INPUT	1.8V	LVCMOS18	4
96	U1_CPLD.K2 K2	FPGA_ERR_VIS<1>_1 FPGA_ERR_VIS<1>_1		fpga_err_vis1	IO15_PL14B_4	INPUT	1.8V	LVCMOS18	4
96	U1_CPLD.K3 K3	FPGA_ERR_VIS<2>_1 FPGA_ERR_VIS<2>_1		fpga_err_vis2	IO16_PL14A_4	INPUT	1.8V	LVCMOS18	4
-	U1_CPLD.K4 K4	NC NC		UNUSED	IO2_PL16C_3	INOUT	1.8V	none	3
-	U1_CPLD.K5 K5	NC NC		UNUSED	IO6_PL17C_3	INOUT	1.8V	none	3
100	U1_CPLD.K6 K6	CPLD_FPGA_SSTAT_CLK CPLD_FPGA_SSTAT_CLK		cpld_fpga_sstat_clk	IO13_PL14D_4	OUTPUT	1.8V	LVCMOS18	4
-	U1_CPLD.K7 K7	CPLD_P3R3V CPLD_P3R3V	3.3	VCC	VCC	POWER		none	-
-	U1_CPLD.K8 K8	CPLD_P3R3V CPLD_P3R3V	3.3	VCCIO2	VCCIO2	POWER	3.3V	none	2
-	U1_CPLD.K9 K9	CPLD_P3R3V CPLD_P3R3V	3.3	VCCIO2	VCCIO2	POWER	3.3V	none	2
-	U1_CPLD.K10 K10	CPLD_P3R3V CPLD_P3R3V	3.3	VCC	VCC	POWER		none	-
93	U1_CPLD.K11 K11	SP_ENB3V_SEQ_L_CPLD SP_ENB3V_SEQ_L_CPLD		sp_enb3v_seq_l	IO42_PR16C_1	OUTPUT	3.3V	LVCMOS33	1
98	U1_CPLD.K12 K12	DIMM_EVENT_OD_F<1> DIMM_EVENT_OD_F<1>		dimm_event_od_f1	IO37_PR15D_1	INPUT	3.3V	LVCMOS33	1
98	U1_CPLD.K13 K13	DIMM_EVENT_OD_F<2> DIMM_EVENT_OD_F<2>		dimm_event_od_f2	IO38_PR15C_1	INPUT	3.3V	LVCMOS33	1
98	U1_CPLD.K14 K14	DIMM_EVENT_OD_F<0> DIMM_EVENT_OD_F<0>		dimm_event_od_f0	IO36_PR14A_1	INPUT	3.3V	LVCMOS33	1
100	U1_CPLD.K15 K15	LTC2975_CPLD_ENB_A LTC2975_CPLD_ENB_A		ltc2975_cpld_enb_a	IO35_PR14B_1	INPUT	3.3V	LVCMOS33	1
100	U1_CPLD.K16 K16	FP_INTRUSION_N FP_INTRUSION_N		fp_intrusion_n	IO31_PR13B_1	INPUT	3.3V	LVCMOS33	1
-	U1_CPLD.L1 L1	UNNAMED_7_SM050TP_I169_1_CPLD UNNAMED_7_SM050TP_I169_1_CPLD		UNUSED	IO4_PL16A_3	INOUT	1.8V	none	3
-	U1_CPLD.L2 L2	NC NC		UNUSED	IO8_PL17A_PCLKT3_0_3	INOUT	1.8V	none	3
-	U1_CPLD.L3 L3	NC NC		UNUSED	IO3_PL16B_3	INOUT	1.8V	none	3
-	U1_CPLD.L4 L4	NC NC		UNUSED	IO5_PL17D_3	INOUT	1.8V	none	3
-	U1_CPLD.L5 L5	NC NC		UNUSED	IO1_PL16D_3	INOUT	1.8V	none	3
100	U1_CPLD.L6 L6	GND GND	0V	GND	GND	GROUND		none	-
-	U1_CPLD.L7 L7	NC NC		UNUSED	IO11_PB9D_2	INOUT	3.3V	none	2
100	U1_CPLD.L8 L8	SDIMM_LTM4675_ALERT_OD_F SDIMM_LTM4675_ALERT_OD_F		sdimm_ltm4675_alert_od_f	IO19_PB12B_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.L9 L9	POK_OD_SDIMM_VDD_SW POK_OD_SDIMM_VDD_SW		pok_od_sdimm_vdd_sw	IO23_PB15D_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.L10 L10	POK_OD_AVTT_RLC_LIN POK_OD_AVTT_RLC_LIN		pok_od_avtt_rlc_lin	IO31_PB21D_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.L11 L11	GND GND	0V	GND	GND	GROUND		none	-
100	U1_CPLD.L12 L12	LTC2975_CPLD_ENB_C LTC2975_CPLD_ENB_C		ltc2975_cpld_enb_c	IO33_PR14D_1	INPUT	3.3V	LVCMOS33	1
93	U1_CPLD.L13 L13	SP_ENB3V_SEQ_M_CPLD SP_ENB3V_SEQ_M_CPLD		sp_enb3v_seq_m	IO41_PR16D_1	OUTPUT	3.3V	LVCMOS33	1
98	U1_CPLD.L14 L14	DIMM_EVENT_OD_F<3> DIMM_EVENT_OD_F<3>		dimm_event_od_f3	IO39_PR15B_1	INPUT	3.3V	LVCMOS33	1
93	U1_CPLD.L15 L15	ENB3V_SEQ_J_CPLD ENB3V_SEQ_J_CPLD		enb3v_seq_j	IO44_PR16A_1	OUTPUT	3.3V	LVCMOS33	1
93	U1_CPLD.L16 L16	SP_ENB3V_SEQ_N_CPLD SP_ENB3V_SEQ_N_CPLD		sp_enb3v_seq_n	IO40_PR15A_1	OUTPUT	3.3V	LVCMOS33	1
-	U1_CPLD.M1 M1	NC NC		UNUSED	IO7_PL17B_PCLKC3_0_3	INOUT	1.8V	none	3
98	U1_CPLD.M2 M2	BOARD_CFG_SW<3> BOARD_CFG_SW<3>		board_cfg_sw3	IO16_PL20A_3	INPUT	1.8V	LVCMOS18	3
-	U1_CPLD.M3 M3	NC NC		UNUSED	IO12_PL19A_3	INOUT	1.8V	none	3
-	U1_CPLD.M4 M4	CPLD_P1R8V_1 CPLD_P1R8V_1	1.8	VCCIO3	VCCIO3	POWER	1.8V	none	3
100	U1_CPLD.M5 M5	GND GND	0V	GND	GND	GROUND		none	-
96	U1_CPLD.M6 M6	NDIMM_LTM4675_ALERT_OD_F_1 NDIMM_LTM4675_ALERT_OD_F_1		ndimm_ltm4675_alert_od_f	IO20_PB12A_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.M7 M7	PSU_SMBALERTN_OD PSU_SMBALERTN_OD		psu_smbalertn_od	IO16_PB10C_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.M8 M8	POK_OD_VCCAUX_A_LIN POK_OD_VCCAUX_A_LIN		pok_od_vccaux_a_lin	IO28_PB18A_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.M9 M9	POK_OD_AVTT_RUC_LIN POK_OD_AVTT_RUC_LIN		pok_od_avtt_ruc_lin	IO32_PB21C_2	INPUT	3.3V	LVCMOS33	2
98	U1_CPLD.M10 M10	POK_OD_AVCC_SW_P<1> POK_OD_AVCC_SW_P<1>		pok_od_avcc_sw_p1	IO40_PB24C_2	INPUT	3.3V	LVCMOS33	2
98	U1_CPLD.M11 M11	POK_OD_AVTT_SW_P<1> POK_OD_AVTT_SW_P<1>		pok_od_avtt_sw_p1	IO35_PB23D_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.M12 M12	GND GND	0V	GND	GND	GROUND		none	-
-	U1_CPLD.M13 M13	CPLD_P3R3V CPLD_P3R3V	3.3	VCCIO1	VCCIO1	POWER	3.3V	none	1
100	U1_CPLD.M14 M14	ENB3V_SEQ_E ENB3V_SEQ_E		enb3v_seq_e	IO48_PR18A_1	OUTPUT	3.3V	LVCMOS33	1
100	U1_CPLD.M15 M15	ENB3V_SEQ_F ENB3V_SEQ_F		enb3v_seq_f	IO47_PR18B_1	OUTPUT	3.3V	LVCMOS33	1
96	U1_CPLD.M16 M16	ENB3V_SEQ_K ENB3V_SEQ_K		enb3v_seq_k_n	IO43_PR16B_1	OUTPUT	3.3V	LVCMOS33	1
-	U1_CPLD.N1 N1	UNNAMED_7_SM050TP_I167_1_CPLD UNNAMED_7_SM050TP_I167_1_CPLD		UNUSED	IO11_PL19B_3	INOUT	1.8V	none	3
-	U1_CPLD.N2 N2	UNNAMED_7_SM050TP_I170_1_CPLD UNNAMED_7_SM050TP_I170_1_CPLD		UNUSED	IO10_PL18C_3	INOUT	1.8V	none	3
98	U1_CPLD.N3 N3	BOARD_CFG_SW<2> BOARD_CFG_SW<2>		board_cfg_sw2	IO15_PL20B_3	INPUT	1.8V	LVCMOS18	3
100	U1_CPLD.N4 N4	GND GND	0V	GND	GND	GROUND		none	-
-	U1_CPLD.N5 N5	CPLD_P3R3V CPLD_P3R3V	3.3	VCCIO2	VCCIO2	POWER	3.3V	none	2
100	U1_CPLD.N6 N6	CPLD_PWR_ALERT_OD_F CPLD_PWR_ALERT_OD_F		cpld_pwr_alert_od_f	IO12_PB9C_2	OUTPUT	3.3V	LVCMOS33	2
100	U1_CPLD.N7 N7	EMC1428_ALERT_OD_F EMC1428_ALERT_OD_F		emc1428_alert_od_f	IO15_PB10D_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.N8 N8	POK_OD_NDIMM_VPP_SW POK_OD_NDIMM_VPP_SW		pok_od_ndimm_vpp_sw	IO24_PB15C_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.N9 N9	POK_OD_VCCAUX_B_LIN POK_OD_VCCAUX_B_LIN		pok_od_vccaux_b_lin	IO27_PB18B_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.N10 N10	POK_OD_AVCC_RS_RLC_LIN POK_OD_AVCC_RS_RLC_LIN		pok_od_avcc_rs_rlc_lin	IO36_PB23C_2	INPUT	3.3V	LVCMOS33	2
98	U1_CPLD.N11 N11	POK_OD_AVCC_SW_P<0> POK_OD_AVCC_SW_P<0>		pok_od_avcc_sw_p0	IO39_PB24D_2	INPUT	3.3V	LVCMOS33	2
-	U1_CPLD.N12 N12	CPLD_P3R3V CPLD_P3R3V	3.3	VCCIO2	VCCIO2	POWER	3.3V	none	2
100	U1_CPLD.N13 N13	GND GND	0V	GND	GND	GROUND		none	-
100	U1_CPLD.N14 N14	ENB3V_SEQ_D ENB3V_SEQ_D		enb3v_seq_d	IO49_PR19B_1	OUTPUT	3.3V	LVCMOS33	1
93	U1_CPLD.N15 N15	ENB3V_SEQ_G_CPLD ENB3V_SEQ_G_CPLD		enb3v_seq_g	IO46_PR18C_1	OUTPUT	3.3V	LVCMOS33	1
100	U1_CPLD.N16 N16	ENB3V_SEQ_C ENB3V_SEQ_C		enb3v_seq_c	IO50_PR19A_1	OUTPUT	3.3V	LVCMOS33	1
-	U1_CPLD.P1 P1	UNNAMED_7_SM050TP_I168_1_CPLD UNNAMED_7_SM050TP_I168_1_CPLD		UNUSED	IO9_PL18D_3	INOUT	1.8V	none	3
98	U1_CPLD.P2 P2	BOARD_CFG_SW<0> BOARD_CFG_SW<0>		board_cfg_sw0	IO13_PL20D_3	INPUT	1.8V	LVCMOS18	3
100	U1_CPLD.P3 P3	GND GND	0V	GND	GND	GROUND		none	-
-	U1_CPLD.P4 P4	NC NC		UNUSED	IO4_PB3A_2	INOUT	3.3V	none	2
-	U1_CPLD.P5 P5	NC NC		UNUSED	IO5_PB4B_2	INOUT	3.3V	none	2
100	U1_CPLD.P6 P6	EMC1428_SYS_SHDN_OD_F EMC1428_SYS_SHDN_OD_F		emc1428_sys_shdn_od_f	IO14_PB9A_MCLK/CCLK_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.P7 P7	PSU_PWR_ON PSU_PWR_ON		psu_pwr_on	IO17_PB10B_2	OUTPUT	3.3V	LVCMOS33	2
100	U1_CPLD.P8 P8	POK_OD_NDIMM_VDD_SW POK_OD_NDIMM_VDD_SW		pok_od_ndimm_vdd_sw	IO26_PB15A_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.P9 P9	POK_OD_VCCAUX_SW POK_OD_VCCAUX_SW		pok_od_vccaux_sw	IO29_PB20B_PCLKC2_1_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.P10 P10	POK_OD_AVCC_RN_LIN POK_OD_AVCC_RN_LIN		pok_od_avcc_rn_lin	IO38_PB23A_2	INPUT	3.3V	LVCMOS33	2
98	U1_CPLD.P11 P11	POK_OD_VCCINT_BLSW_P<0> POK_OD_VCCINT_BLSW_P<0>		pok_od_vccint_blsw_p0	IO41_PB24B_2	INPUT	3.3V	LVCMOS33	2
98	U1_CPLD.P12 P12	POK_OD_VCCINT_TRSW_P<1> POK_OD_VCCINT_TRSW_P<1>		pok_od_vccint_trsw_p1	IO48_PB29A_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.P13 P13	LTC2975_ALERT_OD_F LTC2975_ALERT_OD_F		ltc2975_alert_od_f	IO51_PB30B_SI/SISPI_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.P14 P14	GND GND	0V	GND	GND	GROUND		none	-
100	U1_CPLD.P15 P15	ENB3V_SEQ_A ENB3V_SEQ_A		enb3v_seq_a	IO52_PR20C_1	OUTPUT	3.3V	LVCMOS33	1
93	U1_CPLD.P16 P16	ENB3V_SEQ_H_CPLD ENB3V_SEQ_H_CPLD		enb3v_seq_h	IO45_PR18D_1	OUTPUT	3.3V	LVCMOS33	1
98	U1_CPLD.R1 R1	BOARD_CFG_SW<1> BOARD_CFG_SW<1>		board_cfg_sw1	IO14_PL20C_3	INPUT	1.8V	LVCMOS18	3
100	U1_CPLD.R2 R2	GND GND	0V	GND	GND	GROUND		none	-
83	U1_CPLD.R3 R3	UNNAMED_7_SM050TP_I158_1_CPLD UNNAMED_7_SM050TP_I158_1_CPLD		tp16_cpld	IO1_PB3D_2	OUTPUT	3.3V	LVCMOS33	2
-	U1_CPLD.R4 R4	NC NC		UNUSED	IO7_PB6B_2	INOUT	3.3V	none	2
83	U1_CPLD.R5 R5	UNNAMED_7_SM050TP_I161_1_CPLD UNNAMED_7_SM050TP_I161_1_CPLD		tp12_cpld	IO6_PB4A_CSSPIN_2	OUTPUT	3.3V	LVCMOS33	2
-	U1_CPLD.R6 R6	NC NC		UNUSED	IO9_PB7B_2	INOUT	3.3V	none	2
100	U1_CPLD.R7 R7	PSU_PWR_OK PSU_PWR_OK		psu_pwr_ok	IO18_PB10A_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.R8 R8	POK_OD_SDIMM_VPP_SW POK_OD_SDIMM_VPP_SW		pok_od_sdimm_vpp_sw	IO21_PB13B_PCLKC2_0_2	INPUT	3.3V	LVCMOS33	2
98	U1_CPLD.R9 R9	POK_OD_AVTT_SW_P<0> POK_OD_AVTT_SW_P<0>		pok_od_avtt_sw_p0	IO34_PB21A_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.R10 R10	POK_OD_AVCC_RUC_LIN POK_OD_AVCC_RUC_LIN		pok_od_avcc_ruc_lin	IO37_PB23B_2	INPUT	3.3V	LVCMOS33	2
98	U1_CPLD.R11 R11	POK_OD_VCCINT_TLSW_P<1> POK_OD_VCCINT_TLSW_P<1>		pok_od_vccint_tlsw_p1	IO46_PB27A_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.R12 R12	ENB3V_LTC2975 ENB3V_LTC2975		enb3v_ltc2975	IO52_PB30A_SN_2	OUTPUT	3.3V	LVCMOS33	2
98	U1_CPLD.R13 R13	POK_OD_VCCINT_BRSW_P<1> POK_OD_VCCINT_BRSW_P<1>		pok_od_vccint_brsw_p1	IO44_PB26A_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.R14 R14	LTC2975_AUXFAULT_F LTC2975_AUXFAULT_F		ltc2975_auxfault_f	IO49_PB30D_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.R15 R15	GND GND	0V	GND	GND	GROUND		none	-
100	U1_CPLD.R16 R16	ENB3V_SEQ_B ENB3V_SEQ_B		enb3v_seq_b	IO51_PR20D_1	OUTPUT	3.3V	LVCMOS33	1
-	U1_CPLD.T1 T1	CPLD_P3R3V CPLD_P3R3V	3.3	VCC	VCC	POWER		none	-
83	U1_CPLD.T2 T2	UNNAMED_7_SM050TP_I159_1_CPLD UNNAMED_7_SM050TP_I159_1_CPLD		tp13_cpld	IO2_PB3C_2	OUTPUT	3.3V	LVCMOS33	2
83	U1_CPLD.T3 T3	UNNAMED_7_SM050TP_I160_1_CPLD UNNAMED_7_SM050TP_I160_1_CPLD		tp15_cpld	IO8_PB6A_2	OUTPUT	3.3V	LVCMOS33	2
-	U1_CPLD.T4 T4	NC NC		UNUSED	IO3_PB3B_2	INOUT	3.3V	none	2
-	U1_CPLD.T5 T5	NC NC		UNUSED	IO10_PB7A_2	INOUT	3.3V	none	2
100	U1_CPLD.T6 T6	TSE2002_EVENT_OD_F TSE2002_EVENT_OD_F		tse2002_event_od_f	IO13_PB9B_SO/SPISO_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.T7 T7	POK_OD_SDIMM_VTT_LIN POK_OD_SDIMM_VTT_LIN		pok_od_sdimm_vtt_lin	IO22_PB13A_PCLKT2_0_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.T8 T8	POK_OD_NDIMM_VTT_LIN POK_OD_NDIMM_VTT_LIN		pok_od_ndimm_vtt_lin	IO25_PB15B_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.T9 T9	POK_OD_AVTT_RS_LIN POK_OD_AVTT_RS_LIN		pok_od_avtt_rs_lin	IO30_PB20A_PCLKT2_1_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.T10 T10	POK_OD_AVTT_RN_LIN POK_OD_AVTT_RN_LIN		pok_od_avtt_rn_lin	IO33_PB21B_2	INPUT	3.3V	LVCMOS33	2
98	U1_CPLD.T11 T11	POK_OD_VCCINT_BLSW_P<1> POK_OD_VCCINT_BLSW_P<1>		pok_od_vccint_blsw_p1	IO42_PB24A_2	INPUT	3.3V	LVCMOS33	2
98	U1_CPLD.T12 T12	POK_OD_VCCINT_TLSW_P<0> POK_OD_VCCINT_TLSW_P<0>		pok_od_vccint_tlsw_p0	IO45_PB27B_2	INPUT	3.3V	LVCMOS33	2
98	U1_CPLD.T13 T13	POK_OD_VCCINT_TRSW_P<0> POK_OD_VCCINT_TRSW_P<0>		pok_od_vccint_trsw_p0	IO47_PB29B_2	INPUT	3.3V	LVCMOS33	2
98	U1_CPLD.T14 T14	POK_OD_VCCINT_BRSW_P<0> POK_OD_VCCINT_BRSW_P<0>		pok_od_vccint_brsw_p0	IO43_PB26B_2	INPUT	3.3V	LVCMOS33	2
100	U1_CPLD.T15 T15	POK_OD_LTC2975 POK_OD_LTC2975		pok_od_ltc2975	IO50_PB30C_2	INPUT	3.3V	LVCMOS33	2
-	U1_CPLD.T16 T16	CPLD_P3R3V CPLD_P3R3V	3.3	VCC	VCC	POWER		none	-

Name	Value	Description
BOM_NO_POP_PROP	DNI	This Setting is used to pick a list of properties that excludes a reference designators from installation, but keeps the part in the BOM for purchasing When the BOM is generated by the netlist convert routine, any parts with this property found to be true will be printed on a separate row.
BOM_NO_POP_TRUE_VALS	TRUE,YES,1	This Setting is used to pick a property and value that excludes reference designators from installation, but keeps the part in the BOM for purchasing When the BOM is generated by the netlist convert routine, any parts with this property enabled will be printed on a separate row. ###This was recently renamed from BOM_NO_PROP_TRUE_VALS and this setting is not yet Used
CAPACITANCE_DERATING	90	Capacitance derating value (percentage). Used as the default derating value for capacitors in the power rail report. Capacitors are multiplied by this value to determine the real capacitance value.
CAP_VOLTAGE_DERATING	25	Capacitance voltage derating setpoint (percentage). Used as pass/fail limit for calculated voltage derating The calculated voltage derating shown in the rail capacitance tables is 100*(1-netVoltage/CapVoltage) If the calculated voltage derating is less than this setpoint, the capacitor on that rail will be flagged and added to overvoltage capacitor report
DNI_TRUE_VALS	TRUE,1,YES,DNI	This is a list of the values that make the DO_NOT_INSTALL_PROP true (comma separated vals like:TRUE,1,YES)
DO_NOT_INSTALL_PROP	VALUE,DNI	This is a comma separated list of properties that will be used to determine if a part is not included in a BOM Could look like BOM_IGNORE,DNI. Any part with this Property found True will not be included in the BOM (unlike the BOM_NO_POP_PROP)
EP_VERIFY_CONFIG	C:/CadEnhance/workdir/NetBom/EndPointVerify/XilinxLattice/endpoint_verify_config.txt	EP_VERIFY_CONFIG is the path to the endpoint config file. In order to edit an existing configuration file, select the path to your desired file and then press the Create button to the right of the field. To create a new configuration file, leave this field blank and press the Create button. If no configuration controls are appearing (the GUI is nearly blank), make sure the VERIFY_ENDPOINT_PARTLIST field is populated with your endpoints. This configuration file contains information such as the pin report type, file path, optional package file, and match score override information. The file and field is required for successful endpoint verification operation.
HIDE_EMPTY_REPORT_COLUMNS	1	If a Property does not exist for all instances in a design (or sub-set of design instances like added nets) we will not add that property column to the reports even if the report is configured to use it.
HIDE_GLOBALLY_ABSENT_PROPERTIES	0	When we compare Net Properties, Node Properties, or Part Properties between 2 designs, we will not create a difference if the Property exists in one design but is globally absent in the other design
IGNORE_NET_PROP_DIFFS	0	Property names listed in this comma separated list will be ignored when properties for the same NET_NAME in the 2 netLists are compared The following properties are never compared so they should not need to be added NET_NAME NET_CONNS NET_ID_FROM_PINS NET_ID_XCHECKED NL_INDEX NODE_LIST HIER_NET_NAME LOGICAL_PATH C_SIGNAL The user can look at the net_prop difference report and add any properties to this list that they do not want to include in the comparison
IS_BOM_COMPARE	0	If set, NetBom will only Compare PartLists, and the Netlist compare operation will be skipped. NetBom will help detect this for the user on the first pass of a diff or convert opeartion if one of the NETLIST files is a BOM spreadsheet. If this is not set, the user will be asked if they want to set it when the operation is run.
KEY_PROP_IGNORE_LIST	C_PATH,P_PATH,ALT_SYMBOLS,UNIQUE_NET_CONNS	The BOM_DIFF engine will filter any of these props out of the KEY_PROP_LIST before comparing part properties it is entered as a single PropName or comma separated list of Propertieeslike: MY_LIB,Validate_,GEOMETRY.HEIGHT
KEY_PROP_LIST	BODY_NAME,BOM_IGNORE,CDS_LIB,CDS_PART_NAME,CLASS,COLOR,CURRENT,C_TEMPERATURE,DCR,DESC,DESCRIPTION,DIELECTRIC,DOCUMENT,DRAWING,EXC_MNG_MATCHING,FREQ,HEIGHT,INSTANCE,IS_CAPACITOR,JEDEC_TYPE,J_TEMPERATURE,LIB_INFO,LOCATION,MANUFACTURER,MANUFACTURER_PN,MAX_CASE_DISS_LIMIT,MAX_POWER_DISS,MGTOL_VAR1,MGTOL_VAR2,MGTOL_VAR3,MULT_QTY,NAME,NOT_FEEDTHRU,OC_LIBRARY,OHM_LIMIT,OHM_RESISTANCE,ORIENTATION,PACK_TYPE,PAGE,PARENT_PART_TYPE,PARENT_PPT,PARENT_PPT_PART,PART_CAPACITANCE,PART_IN_LIB,PART_LIB_MODIFIER,PART_NAME,PART_NUMBER,PART_TYPE,PATH,PHYS_DES_PREFIX,PHYS_PAGE,PHY_DES_PREFIX,PN,POWER,PRIMITIVE,PRIM_FILE,REF_DES,REMOTE,REMOVE,REUSE_INSTANCE,REUSE_NAME,REUSE_PID,REVISION,ROOM,ROT,R_FREQ,SCH_MODIFIED_PART,SEC,SECTION_NUM,SECTION_PAGE_INFO,SEC_TYPE,SPEED,STOP_POWER_TRACE_REASON,SUBDESIGN_NAME,SUBDESIGN_SUFFIX,SYMBOL_NAME,TECH,TEMP,TH_JA_RES,TH_JC_RES,TOL,TYPE,TYP_POWER_DISS,VALUE,VARIANT,VENDOR,VENDOR_PN,VER,VIN,VOLT,VOLTAGE,VOUT,WX2_FPGA_VARIANT,XC2_FPGA_VARIANT,XY	The BOM_DIFF engine will compare these properties for each refdes in the 2 bom revisions and report if they are different... it can be entered as a single propName or as a comma separated list like: JEDEC_TYPE,VALUE,TYPE If you leave this blank(New Default), NetBom will gather all the part properties it detects and create the list for you (while excluding any props in the KEY_PROP_IGNORE_LIST)
NET_PROP_RENAME_RULES	0	Comma Separated List of Was:Is rules to change Net Property Names in an existing netlist. This Example: ^_(.*):$1 This will remove a leading '_' from a property _WebLink:WebLink will rename the _WebLink property to WebLink
NET_TRACE_COMPONENT_STOP	CONNECTOR,IC	This comma-separated list of part types tells NetBom which nodes should stop the net trace when encountered. By default it is assumed that connector/ic parts should be used. These part types can be configured to be matched to parts in the Part Type Configuration GUI.
NET_TRACE_NET_NODE_LIMIT	0	This setting governs the max number of pins that a net can have in a net trace before the trace stops. Use 0 in order to remove this limit. A higher number represents more pins that the net trace will tolerate before it stops tracing. Higher numbers means more complex traces, which can be desireable in some cases and undeseriable in other cases.
NET_TRACE_PINCNT_WARN_LIMIT	15	If NetBom encounters a part that exceeds this number and isn't assigned one of the part types in NET_TRACE_COMPONENT_STOP, it will warn the user that a large part exists in the netlist that won't be stopped during net tracing. Large parts slow down the net tracing and should be avoided unless neccessary.
NET_TRACE_PIN_LIMIT	0	This setting governs the max number of pins that a node can have in a net trace before the net trace stops. Use 0 in order to remove this limit. The higher the pin limit, the further the net trace will go. Along with this, the higher the limit, the exponentially longer time the net trace will take. If a net trace is taking too long, it may be because this number is too high.
NEW_NETLIST	CET-1009-NetBom_FPGA_Endpoint_Verify\test_case_1_xilinx_lattice\packaged_20210921_02\pstxnet.dat	NEW_NETLIST use for diffing and converting netlists. For Orcad/AllegroHDL You choose the pstxnet.dat file and netBom will find the matching pstxprt.dat and pstchip.dat files For Mentor, you can choose the .kyn or nets.fwd file For EDIF netlists, you choose the .edf file
NEW_PART_TYPE_CONFIG_FILE	part_type_config.json.txt	This will point to the location of the part type settings file for New Designs.
NODE_PROP_RENAME_RULES	0	Comma Separated List of Was:Is rules to change Node Property Names in an existing netlist. This Example: ^_(.*):$1 This will remove a leading '_' from a property _WebLink:WebLink will rename the _WebLink property to WebLink
OLD_NETLIST	0	OLD_NETLIST for diffing BOMs and NETLISTS. For Orcad/AllegroHDL You choose the pstxnet.dat file and netBom will find the matching pstxprt.dat and pstchip.dat files For Mentor, you can choose the .kyn or nets.fwd file For EDIF netlists, you choose the .edf file
OLD_PART_TYPE_CONFIG_FILE	part_type_config.js.txt	This will point to the location of the part type settings file for Old Designs.
PART_NUMBER_PROPS	PART_NUMBER,ID,MPN	The BOM_DIFF engine and NETLIST Creators will use this comma separated list of properties to search for the device part-number, It will use the first one it finds in this list The property name is case insensitive.
PART_PROPVAL_RENAME_RULES	0	Comma Separated List of Was:Is rules to change Part Property Values in an existing netlist. This Example: ^_(.*):$1 This will remove a leading '_' from a property _WebLink:WebLink will rename the _WebLink property to WebLink
PART_PROP_RENAME_RULES	0	Comma Separated List of Was:Is rules to change Part Property Names in an existing netlist. This Example: ^_(.*):$1 This will remove a leading '_' from a property _WebLink:WebLink will rename the _WebLink property to WebLink
POLAR_CAP_PART_TYPES	POLARIZED_CAP	These part types will be considered polar capacitors when auditing for reversed voltage capacitors.
POLAR_CAP_VOLTAGE_DERATING	25	This setting overrides the CAP_VOLTAGE_DERATING setting for part types identified as polar capacitors. Polar capacitance voltage derating setpoint (percentage). Used as pass/fail limit for calculated voltage derating. The calculated voltage derating shown in the rail capacitance tables is 100*(1-netVoltage/CapVoltage). If the calculated voltage derating is less than this setpoint, the capacitor on that rail will be flagged and added to overvoltage capacitor report.
POWER_RAIL_CAP_PART_TYPES	CAPACITOR,POLARIZED_CAP	These are the part types that will be considered a capacitor when determining power rails.
POWER_RAIL_CAP_VALUE_MIN	50	Minimum value (in pF) that a capacitor needs in order to be included in the power rail report. Set to zero in order to have no minimum. Example: A rail is identified with three caps. Capacitor 1: 1uf Capacitor 2: 2.5uF Capacitor 3: 45pF If the minimum value is set to 50pF, then capacitor 3 will not be included in the report. Furthermore, if POWER_RAIL_MIN_CAP_COUNT is set to 3 or more (the default is 3), then this will be excluded from the report entirely because it does not have enough capacitors.
POWER_RAIL_MIN_CAP_COUNT	3	Minimum number of capacitors that a net needs in order to be considered a power rail. This number is combined with net name voltage matching to determine which nets are power rails. The voltage matching system can be configured through the VOLTAGE_MATCH_OVERRIDE CSET.
POWER_RAIL_RESISTOR_OHM_LIMIT	10	This is the maximum value (in OHMs) that a resistor can have in order for it to be traced through when determining power rails. When we are evaluating a potential power net, we check the number of caps that are connected to the net. We trace through small components, including resistors, to find the capacitors, and this settings governs if we stop at a given resistor based on its OHM value.
POWER_RAIL_TOTAL_CAP_VALUE_MIN	1	Minimum value (in uF) that the caps on a rail should have in order for the rail to be considered a power rail and to be included in the power rail report. For example, with the default miniumum of 1uF, if there is a power rail with five 0.1uF caps and no other caps, the total cap value for the rail will be 0.5uF and will be excluded from the power rail report.
REFDES_RENAME_RULES	0	Comma Separated List of Was:Is rules to change reference designators in an existing netlist. This can be used when the user knows they are changing many refdes in the new NetList and they don't want them to show up in the difference reports Example: _57$:_S5_S7,_46$:_S4_S6,_02$:_S0_S2,_13$:_S1_S3 this will replace any location ending in _57 with _S5_S7, _46 with S4_S6, _02 with S2_S2, _13 with S1_S3,
SINGLE_NODE_NET_FILTERS	NC_,_NC,NC,^$UN	This comma-separated list is used to validate single node nets. If a net name of a single node net contains any of these matches it will not be included in the single node net reports.
USE_PSTCMDB_PROPS	1	If enabled, this setting will make NetBom merge all net and part properties found in the PSTCMDB.dat file into the netlist and partlist databases.
VERIFY_ENDPOINT_PARTLIST	NO VALUE	NO DESCRIPTION
VOLTAGE_MATCH_OVERRIDE	customer_volt_match_rules.txt	This will allow the user to have custom voltage matching algorithms beyond what is available in NetBom by default. VOLTAGE_MATCH_OVERRIDE holds a file path to a txt file. If this field is populated, NetBom will attempt to parse and use it instead of the default matching algorithms. If the file is not found or is unable to be parsed, NetBom will use the default matching as a fall-back.

NetBom: EP Verify

Version v22.12.2 | Thu Dec 15 2022 15:59:06

New Design: CET-1009-NetBom_FPGA_Endpoint_Verify/test_case_1_xilinx_lattice/packaged_20210921_02/pstxnet.dat

NetBom: EP Verify

Version v22.12.2 | Thu Dec 15 2022 15:59:06

New Design: CET-1009-NetBom_FPGA_Endpoint_Verify/test_case_1_xilinx_lattice/packaged_20210921_02/pstxnet.dat

Build Information

CSETs