NetBom: EP Verify


NetList: packaged_20210921_02/pstxnet.dat					PinReport: xil_fpga_auto.pad

Match Score	Endpoint: U1_XF	Net Name	Net Volt	Sig Name	Pin Name	Pin Volt
100	U1_XF.A4 A4	GND GND	0V	GND	GND
100	U1_XF.A5 A5	GND GND	0V	GND	GND
92	U1_XF.A6 A6	AC_E1S0_PET_N<3>_XF AC_E1S0_PET_N<3>_XF		e1s0_pet_n[3]	MGTYTXN3_238
92	U1_XF.A7 A7	AC_E1S0_PET_P<3>_XF AC_E1S0_PET_P<3>_XF		e1s0_pet_p[3]	MGTYTXP3_238
100	U1_XF.A8 A8	GND GND	0V	GND	GND
100	U1_XF.A9 A9	GND GND	0V	GND	GND
92	U1_XF.A10 A10	AC_E1S0_PET_N<2>_XF AC_E1S0_PET_N<2>_XF		e1s0_pet_n[2]	MGTYTXN2_238
92	U1_XF.A11 A11	AC_E1S0_PET_P<2>_XF AC_E1S0_PET_P<2>_XF		e1s0_pet_p[2]	MGTYTXP2_238
100	U1_XF.A12 A12	GND GND	0V	GND	GND
100	U1_XF.A13 A13	GND GND	0V	GND	GND
100	U1_XF.A14 A14	GND GND	0V	GND	GND
35	U1_XF.A15 A15	C3_DDR4_DQ<62>_XF C3_DDR4_DQ<62>_XF		c3_ddr4_dq[69]	IO_L21N_T3L_N5_AD8N_77
35	U1_XF.A16 A16	C3_DDR4_DQ<63>_XF C3_DDR4_DQ<63>_XF		c3_ddr4_dq[68]	IO_L21P_T3L_N4_AD8P_77
35	U1_XF.A17 A17	C3_DDR4_DQ<60>_XF C3_DDR4_DQ<60>_XF		c3_ddr4_dq[70]	IO_L20N_T3L_N3_AD1N_77
35	U1_XF.A18 A18	C3_DDR4_DQ<61>_XF C3_DDR4_DQ<61>_XF		c3_ddr4_dq[71]	IO_L20P_T3L_N2_AD1P_77
100	U1_XF.A19 A19	GND GND	0V	GND	GND
35	U1_XF.A20 A20	C3_DDR4_DQ<57>_XF C3_DDR4_DQ<57>_XF		c3_ddr4_dq[65]	IO_L24N_T3U_N11_77
35	U1_XF.A21 A21	C3_DDR4_DQ<47>_XF C3_DDR4_DQ<47>_XF		c3_ddr4_dq[21]	IO_L9N_T1L_N5_AD12N_76
16	U1_XF.A22 A22	C3_RDIMM_DQS_C<14>_XF C3_RDIMM_DQS_C<14>_XF		c3_ddr4_dqs_c[5]	IO_L7N_T1L_N1_QBC_AD13N_76
16	U1_XF.A23 A23	C3_RDIMM_DQS_T<14>_XF C3_RDIMM_DQS_T<14>_XF		c3_ddr4_dqs_t[5]	IO_L7P_T1L_N0_QBC_AD13P_76
100	U1_XF.A24 A24	GND GND	0V	GND	GND
36	U1_XF.A25 A25	C3_DDR4_DQ<33>_XF C3_DDR4_DQ<33>_XF		c3_ddr4_dq[9]	IO_L5N_T0U_N9_AD14N_76
36	U1_XF.A26 A26	C3_DDR4_DQ<32>_XF C3_DDR4_DQ<32>_XF		c3_ddr4_dq[8]	IO_L5P_T0U_N8_AD14P_76
35	U1_XF.A27 A27	C3_DDR4_DQ<38>_XF C3_DDR4_DQ<38>_XF		c3_ddr4_dq[14]	IO_L3N_T0L_N5_AD15N_76
35	U1_XF.A28 A28	C3_DDR4_DQ<39>_XF C3_DDR4_DQ<39>_XF		c3_ddr4_dq[15]	IO_L3P_T0L_N4_AD15P_76
100	U1_XF.A29 A29	GND GND	0V	GND	GND
100	U1_XF.A30 A30	NC NC		IO_L21N_T3L_N5_AD8N_71	IO_L21N_T3L_N5_AD8N_71
100	U1_XF.A31 A31	NC NC		IO_L19N_T3L_N1_DBC_AD9N_71	IO_L19N_T3L_N1_DBC_AD9N_71
100	U1_XF.A32 A32	NC NC		IO_T2U_N12_71	IO_T2U_N12_71
100	U1_XF.A33 A33	NC NC		IO_L15N_T2L_N5_AD11N_71	IO_L15N_T2L_N5_AD11N_71
100	U1_XF.A34 A34	GND GND	0V	GND	GND
100	U1_XF.A35 A35	NC NC		IO_L8P_T1L_N2_AD5P_71	IO_L8P_T1L_N2_AD5P_71
100	U1_XF.A36 A36	NC NC		IO_L8N_T1L_N3_AD5N_71	IO_L8N_T1L_N3_AD5N_71
100	U1_XF.A37 A37	NC NC		IO_L6P_T0U_N10_AD6P_71	IO_L6P_T0U_N10_AD6P_71
100	U1_XF.A38 A38	NC NC		IO_L6N_T0U_N11_AD6N_71	IO_L6N_T0U_N11_AD6N_71
100	U1_XF.A39 A39	GND GND	0V	GND	GND
100	U1_XF.A40 A40	NC NC		IO_L22P_T3U_N6_DBC_AD0P_37	IO_L22P_T3U_N6_DBC_AD0P_37
100	U1_XF.A41 A41	NC NC		IO_L22N_T3U_N7_DBC_AD0N_37	IO_L22N_T3U_N7_DBC_AD0N_37
100	U1_XF.A42 A42	NC NC		IO_L20P_T3L_N2_AD1P_37	IO_L20P_T3L_N2_AD1P_37
100	U1_XF.A43 A43	NC NC		IO_L20N_T3L_N3_AD1N_37	IO_L20N_T3L_N3_AD1N_37
100	U1_XF.A44 A44	GND GND	0V	GND	GND
100	U1_XF.A45 A45	NC NC		IO_L16N_T2U_N7_QBC_AD3N_37	IO_L16N_T2U_N7_QBC_AD3N_37
100	U1_XF.A46 A46	NC NC		IO_L10P_T1U_N6_QBC_AD4P_37	IO_L10P_T1U_N6_QBC_AD4P_37
100	U1_XF.A47 A47	NC NC		IO_L10N_T1U_N7_QBC_AD4N_37	IO_L10N_T1U_N7_QBC_AD4N_37
100	U1_XF.A48 A48	NC NC		IO_L8N_T1L_N3_AD5N_37	IO_L8N_T1L_N3_AD5N_37
100	U1_XF.A49 A49	GND GND	0V	GND	GND
100	U1_XF.A50 A50	NC NC		IO_L3N_T0L_N5_AD15N_37	IO_L3N_T0L_N5_AD15N_37
100	U1_XF.A51 A51	NC NC		IO_L1N_T0L_N1_DBC_37	IO_L1N_T0L_N1_DBC_37
35	U1_XF.A52 A52	C2_DDR4_DQ<43>_XF C2_DDR4_DQ<43>_XF		c2_ddr4_dq[51]	IO_L24P_T3U_N10_35
35	U1_XF.A53 A53	C2_DDR4_DQ<41>_XF C2_DDR4_DQ<41>_XF		c2_ddr4_dq[50]	IO_L24N_T3U_N11_35
100	U1_XF.A54 A54	GND GND	0V	GND	GND
100	U1_XF.A55 A55	NC NC		IO_T2U_N12_35	IO_T2U_N12_35
35	U1_XF.A56 A56	C2_DDR4_DQ<33>_XF C2_DDR4_DQ<33>_XF		c2_ddr4_dq[67]	IO_L17P_T2U_N8_AD10P_35
35	U1_XF.A57 A57	C2_DDR4_DQ<32>_XF C2_DDR4_DQ<32>_XF		c2_ddr4_dq[66]	IO_L17N_T2U_N9_AD10N_35
35	U1_XF.A58 A58	C2_DDR4_DQ<70>_XF C2_DDR4_DQ<70>_XF		c2_ddr4_dq[62]	IO_L9N_T1L_N5_AD12N_35
100	U1_XF.A59 A59	GND GND	0V	GND	GND
100	U1_XF.A60 A60	GND GND	0V	GND	GND
95	U1_XF.AA1 AA1	E1S2_PER_N<1>_XF E1S2_PER_N<1>_XF		e1s2_per_n[1]	MGTYRXN1_233
95	U1_XF.AA2 AA2	E1S2_PER_P<1>_XF E1S2_PER_P<1>_XF		e1s2_per_p[1]	MGTYRXP1_233
100	U1_XF.AA3 AA3	GND GND	0V	GND	GND
100	U1_XF.AA4 AA4	GND GND	0V	GND	GND
95	U1_XF.AA5 AA5	E1S2_PER_N<0>_XF E1S2_PER_N<0>_XF		e1s2_per_n[0]	MGTYRXN0_233
95	U1_XF.AA6 AA6	E1S2_PER_P<0>_XF E1S2_PER_P<0>_XF		e1s2_per_p[0]	MGTYRXP0_233
100	U1_XF.AA7 AA7	GND GND	0V	GND	GND
100	U1_XF.AA8 AA8	GND GND	0V	GND	GND
23	U1_XF.AA9 AA9	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
92	U1_XF.AA10 AA10	AC_E1S2_PET_N<6>_XF AC_E1S2_PET_N<6>_XF		e1s2_pet_n[6]	MGTYTXN2_232
92	U1_XF.AA11 AA11	AC_E1S2_PET_P<6>_XF AC_E1S2_PET_P<6>_XF		e1s2_pet_p[6]	MGTYTXP2_232
100	U1_XF.AA12 AA12	GND GND	0V	GND	GND
23	U1_XF.AA13 AA13	PWR_AVCC_RUC_XF PWR_AVCC_RUC_XF	0.9	MGTAVCC_RUC	MGTAVCC_RUC	0.9
85	U1_XF.AA14 AA14	E1S2_FPGA_REFCLK_N<1>_XF E1S2_FPGA_REFCLK_N<1>_XF		e1s2_refclk_n[1]	MGTREFCLK0N_232
85	U1_XF.AA15 AA15	E1S2_FPGA_REFCLK_P<1>_XF E1S2_FPGA_REFCLK_P<1>_XF		e1s2_refclk_p[1]	MGTREFCLK0P_232
100	U1_XF.AA16 AA16	GND GND	0V	GND	GND
84	U1_XF.AA17 AA17	E1S0_3R3V_LED_XF E1S0_3R3V_LED_XF	3.3V	e1s_3r3v_led[0]	IO_L9N_AD3N_93
84	U1_XF.AA18 AA18	E1S0_3R3V_PWRDIS_XF E1S0_3R3V_PWRDIS_XF	3.3V	e1s_3r3v_pwrdis[0]	IO_L9P_AD3P_93
100	U1_XF.AA19 AA19	GND GND	0V	GND	GND
91	U1_XF.AA20 AA20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA21 AA21	GND GND	0V	GND	GND
91	U1_XF.AA22 AA22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA23 AA23	GND GND	0V	GND	GND
91	U1_XF.AA24 AA24	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA25 AA25	GND GND	0V	GND	GND
91	U1_XF.AA26 AA26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA27 AA27	GND GND	0V	GND	GND
91	U1_XF.AA28 AA28	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA29 AA29	GND GND	0V	GND	GND
91	U1_XF.AA30 AA30	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA31 AA31	GND GND	0V	GND	GND
91	U1_XF.AA32 AA32	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA33 AA33	GND GND	0V	GND	GND
91	U1_XF.AA34 AA34	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA35 AA35	GND GND	0V	GND	GND
91	U1_XF.AA36 AA36	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA37 AA37	GND GND	0V	GND	GND
91	U1_XF.AA38 AA38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA39 AA39	GND GND	0V	GND	GND
91	U1_XF.AA40 AA40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA41 AA41	GND GND	0V	GND	GND
91	U1_XF.AA42 AA42	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA43 AA43	GND GND	0V	GND	GND
91	U1_XF.AA44 AA44	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AA45 AA45	NC NC		IO_L23P_T3U_N8_32	IO_L23P_T3U_N8_32
100	U1_XF.AA46 AA46	NC NC		IO_L24N_T3U_N11_32	IO_L24N_T3U_N11_32
100	U1_XF.AA47 AA47	NC NC		IO_T3U_N12_32	IO_T3U_N12_32
100	U1_XF.AA48 AA48	NC NC		IO_L18P_T2U_N10_AD2P_32	IO_L18P_T2U_N10_AD2P_32
100	U1_XF.AA49 AA49	NC NC		VCCO_32	VCCO_32	1.8
100	U1_XF.AA50 AA50	NC NC		IO_L14N_T2L_N3_GC_32	IO_L14N_T2L_N3_GC_32
100	U1_XF.AA51 AA51	NC NC		IO_L13N_T2L_N1_GC_QBC_32	IO_L13N_T2L_N1_GC_QBC_32
100	U1_XF.AA52 AA52	NC NC		IO_L12P_T1U_N10_GC_32	IO_L12P_T1U_N10_GC_32
100	U1_XF.AA53 AA53	NC NC		IO_L11P_T1U_N8_GC_32	IO_L11P_T1U_N8_GC_32
100	U1_XF.AA54 AA54	GND GND	0V	GND	GND
100	U1_XF.AA55 AA55	NC NC		IO_L5N_T0U_N9_AD14N_32	IO_L5N_T0U_N9_AD14N_32
100	U1_XF.AA56 AA56	NC NC		IO_L3N_T0L_N5_AD15N_32	IO_L3N_T0L_N5_AD15N_32
100	U1_XF.AA57 AA57	NC NC		IO_L2P_T0L_N2_32	IO_L2P_T0L_N2_32
100	U1_XF.AA58 AA58	NC NC		IO_L18P_T2U_N10_AD2P_31	IO_L18P_T2U_N10_AD2P_31
100	U1_XF.AA59 AA59	NC NC		VCCO_31	VCCO_31	1.8
100	U1_XF.AA60 AA60	NC NC		IO_L14N_T2L_N3_GC_31	IO_L14N_T2L_N3_GC_31
100	U1_XF.AA61 AA61	NC NC		IO_L13N_T2L_N1_GC_QBC_31	IO_L13N_T2L_N1_GC_QBC_31
100	U1_XF.AA62 AA62	NC NC		IO_T2U_N12_31	IO_T2U_N12_31
100	U1_XF.AA63 AA63	NC NC		IO_L17N_T2U_N9_AD10N_31	IO_L17N_T2U_N9_AD10N_31
100	U1_XF.AB1 AB1	GND GND	0V	GND	GND
100	U1_XF.AB2 AB2	GND GND	0V	GND	GND
95	U1_XF.AB3 AB3	E1S2_PER_N<7>_XF E1S2_PER_N<7>_XF		e1s2_per_n[7]	MGTYRXN3_232
95	U1_XF.AB4 AB4	E1S2_PER_P<7>_XF E1S2_PER_P<7>_XF		e1s2_per_p[7]	MGTYRXP3_232
100	U1_XF.AB5 AB5	GND GND	0V	GND	GND
100	U1_XF.AB6 AB6	GND GND	0V	GND	GND
100	U1_XF.AB7 AB7	GND GND	0V	GND	GND
92	U1_XF.AB8 AB8	AC_E1S2_PET_N<5>_XF AC_E1S2_PET_N<5>_XF		e1s2_pet_n[5]	MGTYTXN1_232
92	U1_XF.AB9 AB9	AC_E1S2_PET_P<5>_XF AC_E1S2_PET_P<5>_XF		e1s2_pet_p[5]	MGTYTXP1_232
100	U1_XF.AB10 AB10	GND GND	0V	GND	GND
100	U1_XF.AB11 AB11	GND GND	0V	GND	GND
100	U1_XF.AB12 AB12	NC NC		MGTREFCLK1N_231	MGTREFCLK1N_231
100	U1_XF.AB13 AB13	NC NC		MGTREFCLK1P_231	MGTREFCLK1P_231
100	U1_XF.AB14 AB14	GND GND	0V	GND	GND
23	U1_XF.AB15 AB15	PWR_AVCC_RUC_XF PWR_AVCC_RUC_XF	0.9	MGTAVCC_RUC	MGTAVCC_RUC	0.9
100	U1_XF.AB16 AB16	GND GND	0V	GND	GND
-	U1_XF.AB17 AB17	PWR_FPGA_3R3V PWR_FPGA_3R3V	3.3	VCCO_93	VCCO_93	3.3
83	U1_XF.AB18 AB18	E1S0_3R3V_SMB_RST_F_XF E1S0_3R3V_SMB_RST_F_XF	3.3V	e1s_3r3v_smb_rst_f[0]	IO_L8N_HDGC_AD4N_93
80	U1_XF.AB19 AB19	E1S0_3R3V_DUALPORTEN_F_XF E1S0_3R3V_DUALPORTEN_F_XF		e1s_3r3v_dualporten_f[0]	IO_L8P_HDGC_AD4P_93
100	U1_XF.AB20 AB20	GND GND	0V	GND	GND
91	U1_XF.AB21 AB21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AB22 AB22	GND GND	0V	GND	GND
91	U1_XF.AB23 AB23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AB24 AB24	GND GND	0V	GND	GND
91	U1_XF.AB25 AB25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AB26 AB26	GND GND	0V	GND	GND
91	U1_XF.AB27 AB27	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AB28 AB28	GND GND	0V	GND	GND
91	U1_XF.AB29 AB29	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AB30 AB30	GND GND	0V	GND	GND
91	U1_XF.AB31 AB31	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AB32 AB32	GND GND	0V	GND	GND
91	U1_XF.AB33 AB33	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AB34 AB34	GND GND	0V	GND	GND
91	U1_XF.AB35 AB35	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AB36 AB36	GND GND	0V	GND	GND
91	U1_XF.AB37 AB37	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AB38 AB38	GND GND	0V	GND	GND
91	U1_XF.AB39 AB39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AB40 AB40	GND GND	0V	GND	GND
91	U1_XF.AB41 AB41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AB42 AB42	GND GND	0V	GND	GND
91	U1_XF.AB43 AB43	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AB44 AB44	GND GND	0V	GND	GND
100	U1_XF.AB45 AB45	NC NC		VREF_32	VREF_32
100	U1_XF.AB46 AB46	NC NC		IO_L24P_T3U_N10_32	IO_L24P_T3U_N10_32
100	U1_XF.AB47 AB47	GND GND	0V	GND	GND
100	U1_XF.AB48 AB48	NC NC		IO_L22N_T3U_N7_DBC_AD0N_32	IO_L22N_T3U_N7_DBC_AD0N_32
100	U1_XF.AB49 AB49	NC NC		IO_L16N_T2U_N7_QBC_AD3N_32	IO_L16N_T2U_N7_QBC_AD3N_32
100	U1_XF.AB50 AB50	NC NC		IO_L14P_T2L_N2_GC_32	IO_L14P_T2L_N2_GC_32
100	U1_XF.AB51 AB51	NC NC		IO_L13P_T2L_N0_GC_QBC_32	IO_L13P_T2L_N0_GC_QBC_32
100	U1_XF.AB52 AB52	NC NC		VCCO_32	VCCO_32	1.8
100	U1_XF.AB53 AB53	NC NC		IO_L9N_T1L_N5_AD12N_32	IO_L9N_T1L_N5_AD12N_32
100	U1_XF.AB54 AB54	NC NC		IO_L7N_T1L_N1_QBC_AD13N_32	IO_L7N_T1L_N1_QBC_AD13N_32
100	U1_XF.AB55 AB55	NC NC		IO_L5P_T0U_N8_AD14P_32	IO_L5P_T0U_N8_AD14P_32
100	U1_XF.AB56 AB56	NC NC		IO_L3P_T0L_N4_AD15P_32	IO_L3P_T0L_N4_AD15P_32
100	U1_XF.AB57 AB57	GND GND	0V	GND	GND
100	U1_XF.AB58 AB58	NC NC		IO_L16P_T2U_N6_QBC_AD3P_31	IO_L16P_T2U_N6_QBC_AD3P_31
100	U1_XF.AB59 AB59	NC NC		IO_L16N_T2U_N7_QBC_AD3N_31	IO_L16N_T2U_N7_QBC_AD3N_31
100	U1_XF.AB60 AB60	NC NC		IO_L14P_T2L_N2_GC_31	IO_L14P_T2L_N2_GC_31
100	U1_XF.AB61 AB61	NC NC		IO_L13P_T2L_N0_GC_QBC_31	IO_L13P_T2L_N0_GC_QBC_31
100	U1_XF.AB62 AB62	GND GND	0V	GND	GND
100	U1_XF.AB63 AB63	NC NC		IO_L17P_T2U_N8_AD10P_31	IO_L17P_T2U_N8_AD10P_31
95	U1_XF.AC1 AC1	E1S2_PER_N<6>_XF E1S2_PER_N<6>_XF		e1s2_per_n[6]	MGTYRXN2_232
95	U1_XF.AC2 AC2	E1S2_PER_P<6>_XF E1S2_PER_P<6>_XF		e1s2_per_p[6]	MGTYRXP2_232
100	U1_XF.AC3 AC3	GND GND	0V	GND	GND
100	U1_XF.AC4 AC4	GND GND	0V	GND	GND
95	U1_XF.AC5 AC5	E1S2_PER_N<5>_XF E1S2_PER_N<5>_XF		e1s2_per_n[5]	MGTYRXN1_232
95	U1_XF.AC6 AC6	E1S2_PER_P<5>_XF E1S2_PER_P<5>_XF		e1s2_per_p[5]	MGTYRXP1_232
100	U1_XF.AC7 AC7	GND GND	0V	GND	GND
100	U1_XF.AC8 AC8	GND GND	0V	GND	GND
23	U1_XF.AC9 AC9	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
92	U1_XF.AC10 AC10	AC_E1S2_PET_N<4>_XF AC_E1S2_PET_N<4>_XF		e1s2_pet_n[4]	MGTYTXN0_232
92	U1_XF.AC11 AC11	AC_E1S2_PET_P<4>_XF AC_E1S2_PET_P<4>_XF		e1s2_pet_p[4]	MGTYTXP0_232
100	U1_XF.AC12 AC12	GND GND	0V	GND	GND
23	U1_XF.AC13 AC13	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
100	U1_XF.AC14 AC14	NC NC		MGTREFCLK0N_231	MGTREFCLK0N_231
100	U1_XF.AC15 AC15	NC NC		MGTREFCLK0P_231	MGTREFCLK0P_231
100	U1_XF.AC16 AC16	GND GND	0V	GND	GND
33	U1_XF.AC17 AC17	E1S1_3R3V_CKEN_F<0>_XF E1S1_3R3V_CKEN_F<0>_XF		e1s_3r3v_cken0_f[1]	IO_L6N_HDGC_AD6N_93
84	U1_XF.AC18 AC18	E1S0_3R3V_SDA_XF E1S0_3R3V_SDA_XF	3.3V	e1s_3r3v_sda[0]	IO_L7N_HDGC_AD5N_93
85	U1_XF.AC19 AC19	E1S0_3R3V_SCL_XF E1S0_3R3V_SCL_XF	3.3V	e1s_3r3v_scl[0]	IO_L7P_HDGC_AD5P_93
90	U1_XF.AC20 AC20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT_IO	VCCINT_IO	0.85
100	U1_XF.AC21 AC21	GND GND	0V	GND	GND
91	U1_XF.AC22 AC22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AC23 AC23	GND GND	0V	GND	GND
91	U1_XF.AC24 AC24	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AC25 AC25	GND GND	0V	GND	GND
91	U1_XF.AC26 AC26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AC27 AC27	GND GND	0V	GND	GND
91	U1_XF.AC28 AC28	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AC29 AC29	GND GND	0V	GND	GND
91	U1_XF.AC30 AC30	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AC31 AC31	GND GND	0V	GND	GND
91	U1_XF.AC32 AC32	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AC33 AC33	GND GND	0V	GND	GND
91	U1_XF.AC34 AC34	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AC35 AC35	GND GND	0V	GND	GND
91	U1_XF.AC36 AC36	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AC37 AC37	GND GND	0V	GND	GND
91	U1_XF.AC38 AC38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AC39 AC39	GND GND	0V	GND	GND
91	U1_XF.AC40 AC40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AC41 AC41	GND GND	0V	GND	GND
91	U1_XF.AC42 AC42	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AC43 AC43	GND GND	0V	GND	GND
91	U1_XF.AC44 AC44	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AC45 AC45	GND GND	0V	GND	GND
100	U1_XF.AC46 AC46	NC NC		IO_L20P_T3L_N2_AD1P_32	IO_L20P_T3L_N2_AD1P_32
100	U1_XF.AC47 AC47	NC NC		IO_L20N_T3L_N3_AD1N_32	IO_L20N_T3L_N3_AD1N_32
100	U1_XF.AC48 AC48	NC NC		IO_L22P_T3U_N6_DBC_AD0P_32	IO_L22P_T3U_N6_DBC_AD0P_32
100	U1_XF.AC49 AC49	NC NC		IO_L16P_T2U_N6_QBC_AD3P_32	IO_L16P_T2U_N6_QBC_AD3P_32
100	U1_XF.AC50 AC50	GND GND	0V	GND	GND
100	U1_XF.AC51 AC51	NC NC		IO_T2U_N12_32	IO_T2U_N12_32
100	U1_XF.AC52 AC52	NC NC		IO_T1U_N12_32	IO_T1U_N12_32
100	U1_XF.AC53 AC53	NC NC		IO_L9P_T1L_N4_AD12P_32	IO_L9P_T1L_N4_AD12P_32
100	U1_XF.AC54 AC54	NC NC		IO_L7P_T1L_N0_QBC_AD13P_32	IO_L7P_T1L_N0_QBC_AD13P_32
100	U1_XF.AC55 AC55	GND GND	0V	GND	GND
100	U1_XF.AC56 AC56	NC NC		IO_L1P_T0L_N0_DBC_32	IO_L1P_T0L_N0_DBC_32
100	U1_XF.AC57 AC57	NC NC		IO_L1N_T0L_N1_DBC_32	IO_L1N_T0L_N1_DBC_32
100	U1_XF.AC58 AC58	NC NC		IO_L9P_T1L_N4_AD12P_31	IO_L9P_T1L_N4_AD12P_31
100	U1_XF.AC59 AC59	NC NC		IO_L9N_T1L_N5_AD12N_31	IO_L9N_T1L_N5_AD12N_31
100	U1_XF.AC60 AC60	GND GND	0V	GND	GND
100	U1_XF.AC61 AC61	NC NC		IO_L12N_T1U_N11_GC_31	IO_L12N_T1U_N11_GC_31
100	U1_XF.AC62 AC62	NC NC		IO_L15P_T2L_N4_AD11P_31	IO_L15P_T2L_N4_AD11P_31
100	U1_XF.AC63 AC63	NC NC		IO_L15N_T2L_N5_AD11N_31	IO_L15N_T2L_N5_AD11N_31
100	U1_XF.AD1 AD1	GND GND	0V	GND	GND
100	U1_XF.AD2 AD2	GND GND	0V	GND	GND
95	U1_XF.AD3 AD3	E1S2_PER_N<4>_XF E1S2_PER_N<4>_XF		e1s2_per_n[4]	MGTYRXN0_232
95	U1_XF.AD4 AD4	E1S2_PER_P<4>_XF E1S2_PER_P<4>_XF		e1s2_per_p[4]	MGTYRXP0_232
100	U1_XF.AD5 AD5	GND GND	0V	GND	GND
100	U1_XF.AD6 AD6	GND GND	0V	GND	GND
100	U1_XF.AD7 AD7	GND GND	0V	GND	GND
100	U1_XF.AD8 AD8	NC NC		MGTYTXN3_231	MGTYTXN3_231
100	U1_XF.AD9 AD9	NC NC		MGTYTXP3_231	MGTYTXP3_231
100	U1_XF.AD10 AD10	GND GND	0V	GND	GND
100	U1_XF.AD11 AD11	GND GND	0V	GND	GND
100	U1_XF.AD12 AD12	NC NC		MGTYTXN2_231	MGTYTXN2_231
100	U1_XF.AD13 AD13	NC NC		MGTYTXP2_231	MGTYTXP2_231
100	U1_XF.AD14 AD14	GND GND	0V	GND	GND
23	U1_XF.AD15 AD15	PWR_AVCC_RUC_XF PWR_AVCC_RUC_XF	0.9	MGTAVCC_RUC	MGTAVCC_RUC	0.9
100	U1_XF.AD16 AD16	GND GND	0V	GND	GND
83	U1_XF.AD17 AD17	E1S1_3R3V_CKEN_F<1>_XF E1S1_3R3V_CKEN_F<1>_XF		e1s_3r3v_cken1_f[1]	IO_L6P_HDGC_AD6P_93
100	U1_XF.AD18 AD18	GND GND	0V	GND	GND
34	U1_XF.AD19 AD19	E1S1_3R3V_PRSNT_F<0>_XF E1S1_3R3V_PRSNT_F<0>_XF	3.3V	e1s_3r3v_prsnt0_f[1]	IO_L5N_HDGC_AD7N_93
100	U1_XF.AD20 AD20	GND GND	0V	GND	GND
-	U1_XF.AD21 AD21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCBRAM	VCCBRAM	0.85
100	U1_XF.AD22 AD22	GND GND	0V	GND	GND
91	U1_XF.AD23 AD23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AD24 AD24	GND GND	0V	GND	GND
91	U1_XF.AD25 AD25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AD26 AD26	GND GND	0V	GND	GND
91	U1_XF.AD27 AD27	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AD28 AD28	GND GND	0V	GND	GND
91	U1_XF.AD29 AD29	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AD30 AD30	GND GND	0V	GND	GND
91	U1_XF.AD31 AD31	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AD32 AD32	GND GND	0V	GND	GND
91	U1_XF.AD33 AD33	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AD34 AD34	GND GND	0V	GND	GND
91	U1_XF.AD35 AD35	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AD36 AD36	GND GND	0V	GND	GND
91	U1_XF.AD37 AD37	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AD38 AD38	GND GND	0V	GND	GND
91	U1_XF.AD39 AD39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AD40 AD40	GND GND	0V	GND	GND
91	U1_XF.AD41 AD41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AD42 AD42	GND GND	0V	GND	GND
86	U1_XF.AD43 AD43	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX_IO	VCCAUX_IO	1.8
100	U1_XF.AD44 AD44	GND GND	0V	GND	GND
100	U1_XF.AD45 AD45	NC NC		IO_L21P_T3L_N4_AD8P_30	IO_L21P_T3L_N4_AD8P_30
100	U1_XF.AD46 AD46	NC NC		IO_L21N_T3L_N5_AD8N_30	IO_L21N_T3L_N5_AD8N_30
100	U1_XF.AD47 AD47	NC NC		IO_L19N_T3L_N1_DBC_AD9N_30	IO_L19N_T3L_N1_DBC_AD9N_30
100	U1_XF.AD48 AD48	GND GND	0V	GND	GND
100	U1_XF.AD49 AD49	NC NC		IO_L16N_T2U_N7_QBC_AD3N_30	IO_L16N_T2U_N7_QBC_AD3N_30
100	U1_XF.AD50 AD50	NC NC		IO_L17N_T2U_N9_AD10N_30	IO_L17N_T2U_N9_AD10N_30
100	U1_XF.AD51 AD51	NC NC		IO_L10P_T1U_N6_QBC_AD4P_30	IO_L10P_T1U_N6_QBC_AD4P_30
100	U1_XF.AD52 AD52	NC NC		IO_L10N_T1U_N7_QBC_AD4N_30	IO_L10N_T1U_N7_QBC_AD4N_30
100	U1_XF.AD53 AD53	GND GND	0V	GND	GND
100	U1_XF.AD54 AD54	NC NC		IO_T1U_N12_30	IO_T1U_N12_30
100	U1_XF.AD55 AD55	NC NC		IO_L6N_T0U_N11_AD6N_30	IO_L6N_T0U_N11_AD6N_30
100	U1_XF.AD56 AD56	NC NC		IO_L4P_T0U_N6_DBC_AD7P_30	IO_L4P_T0U_N6_DBC_AD7P_30
100	U1_XF.AD57 AD57	NC NC		IO_L4N_T0U_N7_DBC_AD7N_30	IO_L4N_T0U_N7_DBC_AD7N_30
100	U1_XF.AD58 AD58	GND GND	0V	GND	GND
100	U1_XF.AD59 AD59	NC NC		IO_L11P_T1U_N8_GC_31	IO_L11P_T1U_N8_GC_31
100	U1_XF.AD60 AD60	NC NC		IO_L11N_T1U_N9_GC_31	IO_L11N_T1U_N9_GC_31
100	U1_XF.AD61 AD61	NC NC		IO_L12P_T1U_N10_GC_31	IO_L12P_T1U_N10_GC_31
100	U1_XF.AD62 AD62	NC NC		IO_L7N_T1L_N1_QBC_AD13N_31	IO_L7N_T1L_N1_QBC_AD13N_31
100	U1_XF.AD63 AD63	GND GND	0V	GND	GND
100	U1_XF.AE1 AE1	NC NC		MGTYRXN3_231	MGTYRXN3_231
100	U1_XF.AE2 AE2	NC NC		MGTYRXP3_231	MGTYRXP3_231
100	U1_XF.AE3 AE3	GND GND	0V	GND	GND
100	U1_XF.AE4 AE4	GND GND	0V	GND	GND
100	U1_XF.AE5 AE5	NC NC		MGTYRXN2_231	MGTYRXN2_231
100	U1_XF.AE6 AE6	NC NC		MGTYRXP2_231	MGTYRXP2_231
100	U1_XF.AE7 AE7	GND GND	0V	GND	GND
100	U1_XF.AE8 AE8	GND GND	0V	GND	GND
23	U1_XF.AE9 AE9	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
100	U1_XF.AE10 AE10	NC NC		MGTYTXN1_231	MGTYTXN1_231
100	U1_XF.AE11 AE11	NC NC		MGTYTXP1_231	MGTYTXP1_231
100	U1_XF.AE12 AE12	GND GND	0V	GND	GND
23	U1_XF.AE13 AE13	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
100	U1_XF.AE14 AE14	NC NC		MGTREFCLK1N_230	MGTREFCLK1N_230
100	U1_XF.AE15 AE15	NC NC		MGTREFCLK1P_230	MGTREFCLK1P_230
100	U1_XF.AE16 AE16	GND GND	0V	GND	GND
33	U1_XF.AE17 AE17	E1S1_3R3V_PERST_F<0>_XF E1S1_3R3V_PERST_F<0>_XF	3.3V	e1s_3r3v_perst0_f[1]	IO_L4N_AD8N_93
81	U1_XF.AE18 AE18	E1S1_3R3V_PERST_CLKREQ_F<1>_XF E1S1_3R3V_PERST_CLKREQ_F<1>_XF	3.3V	e1s_3r3v_perst1_clkreq_f[1]	IO_L4P_AD8P_93
84	U1_XF.AE19 AE19	E1S1_3R3V_PRSNT_F<1>_XF E1S1_3R3V_PRSNT_F<1>_XF	3.3V	e1s_3r3v_prsnt1_f[1]	IO_L5P_HDGC_AD7P_93
90	U1_XF.AE20 AE20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT_IO	VCCINT_IO	0.85
100	U1_XF.AE21 AE21	GND GND	0V	GND	GND
91	U1_XF.AE22 AE22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AE23 AE23	GND GND	0V	GND	GND
91	U1_XF.AE24 AE24	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AE25 AE25	GND GND	0V	GND	GND
91	U1_XF.AE26 AE26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AE27 AE27	GND GND	0V	GND	GND
91	U1_XF.AE28 AE28	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AE29 AE29	GND GND	0V	GND	GND
91	U1_XF.AE30 AE30	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AE31 AE31	GND GND	0V	GND	GND
91	U1_XF.AE32 AE32	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AE33 AE33	GND GND	0V	GND	GND
91	U1_XF.AE34 AE34	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AE35 AE35	GND GND	0V	GND	GND
91	U1_XF.AE36 AE36	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AE37 AE37	GND GND	0V	GND	GND
91	U1_XF.AE38 AE38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AE39 AE39	GND GND	0V	GND	GND
91	U1_XF.AE40 AE40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AE41 AE41	GND GND	0V	GND	GND
91	U1_XF.AE42 AE42	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AE43 AE43	GND GND	0V	GND	GND
87	U1_XF.AE44 AE44	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX	VCCAUX	1.8
100	U1_XF.AE45 AE45	NC NC		IO_L22N_T3U_N7_DBC_AD0N_30	IO_L22N_T3U_N7_DBC_AD0N_30
100	U1_XF.AE46 AE46	GND GND	0V	GND	GND
100	U1_XF.AE47 AE47	NC NC		IO_L19P_T3L_N0_DBC_AD9P_30	IO_L19P_T3L_N0_DBC_AD9P_30
100	U1_XF.AE48 AE48	NC NC		IO_L18N_T2U_N11_AD2N_30	IO_L18N_T2U_N11_AD2N_30
100	U1_XF.AE49 AE49	NC NC		IO_L16P_T2U_N6_QBC_AD3P_30	IO_L16P_T2U_N6_QBC_AD3P_30
100	U1_XF.AE50 AE50	NC NC		IO_L17P_T2U_N8_AD10P_30	IO_L17P_T2U_N8_AD10P_30
100	U1_XF.AE51 AE51	GND GND	0V	GND	GND
100	U1_XF.AE52 AE52	NC NC		IO_L12N_T1U_N11_GC_30	IO_L12N_T1U_N11_GC_30
100	U1_XF.AE53 AE53	NC NC		IO_L8P_T1L_N2_AD5P_30	IO_L8P_T1L_N2_AD5P_30
100	U1_XF.AE54 AE54	NC NC		IO_L8N_T1L_N3_AD5N_30	IO_L8N_T1L_N3_AD5N_30
100	U1_XF.AE55 AE55	NC NC		IO_L6P_T0U_N10_AD6P_30	IO_L6P_T0U_N10_AD6P_30
100	U1_XF.AE56 AE56	NC NC		VCCO_30	VCCO_30	1.8
100	U1_XF.AE57 AE57	NC NC		IO_L5N_T0U_N9_AD14N_30	IO_L5N_T0U_N9_AD14N_30
100	U1_XF.AE58 AE58	NC NC		VREF_31	VREF_31
100	U1_XF.AE59 AE59	NC NC		IO_L10P_T1U_N6_QBC_AD4P_31	IO_L10P_T1U_N6_QBC_AD4P_31
100	U1_XF.AE60 AE60	NC NC		IO_L10N_T1U_N7_QBC_AD4N_31	IO_L10N_T1U_N7_QBC_AD4N_31
100	U1_XF.AE61 AE61	NC NC		VCCO_31	VCCO_31	1.8
100	U1_XF.AE62 AE62	NC NC		IO_L7P_T1L_N0_QBC_AD13P_31	IO_L7P_T1L_N0_QBC_AD13P_31
100	U1_XF.AE63 AE63	NC NC		IO_L8N_T1L_N3_AD5N_31	IO_L8N_T1L_N3_AD5N_31
100	U1_XF.AF1 AF1	GND GND	0V	GND	GND
100	U1_XF.AF2 AF2	GND GND	0V	GND	GND
100	U1_XF.AF3 AF3	NC NC		MGTYRXN1_231	MGTYRXN1_231
100	U1_XF.AF4 AF4	NC NC		MGTYRXP1_231	MGTYRXP1_231
100	U1_XF.AF5 AF5	GND GND	0V	GND	GND
100	U1_XF.AF6 AF6	GND GND	0V	GND	GND
100	U1_XF.AF7 AF7	GND GND	0V	GND	GND
100	U1_XF.AF8 AF8	NC NC		MGTYTXN0_231	MGTYTXN0_231
100	U1_XF.AF9 AF9	NC NC		MGTYTXP0_231	MGTYTXP0_231
100	U1_XF.AF10 AF10	GND GND	0V	GND	GND
100	U1_XF.AF11 AF11	GND GND	0V	GND	GND
92	U1_XF.AF12 AF12	AC_E1S3_PET_N<3>_XF AC_E1S3_PET_N<3>_XF		e1s3_pet_n[3]	MGTYTXN3_230
92	U1_XF.AF13 AF13	AC_E1S3_PET_P<3>_XF AC_E1S3_PET_P<3>_XF		e1s3_pet_p[3]	MGTYTXP3_230
100	U1_XF.AF14 AF14	GND GND	0V	GND	GND
23	U1_XF.AF15 AF15	PWR_AVCC_RUC_XF PWR_AVCC_RUC_XF	0.9	MGTAVCC_RUC	MGTAVCC_RUC	0.9
100	U1_XF.AF16 AF16	GND GND	0V	GND	GND
84	U1_XF.AF17 AF17	E1S1_3R3V_LED_XF E1S1_3R3V_LED_XF	3.3V	e1s_3r3v_led[1]	IO_L3N_AD9N_93
84	U1_XF.AF18 AF18	E1S1_3R3V_PWRDIS_XF E1S1_3R3V_PWRDIS_XF	3.3V	e1s_3r3v_pwrdis[1]	IO_L3P_AD9P_93
-	U1_XF.AF19 AF19	PWR_FPGA_3R3V PWR_FPGA_3R3V	3.3	VCCO_93	VCCO_93	3.3
100	U1_XF.AF20 AF20	GND GND	0V	GND	GND
-	U1_XF.AF21 AF21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCBRAM	VCCBRAM	0.85
100	U1_XF.AF22 AF22	GND GND	0V	GND	GND
91	U1_XF.AF23 AF23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AF24 AF24	GND GND	0V	GND	GND
91	U1_XF.AF25 AF25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AF26 AF26	GND GND	0V	GND	GND
91	U1_XF.AF27 AF27	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AF28 AF28	GND GND	0V	GND	GND
91	U1_XF.AF29 AF29	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AF30 AF30	GND GND	0V	GND	GND
91	U1_XF.AF31 AF31	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AF32 AF32	GND GND	0V	GND	GND
91	U1_XF.AF33 AF33	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AF34 AF34	GND GND	0V	GND	GND
91	U1_XF.AF35 AF35	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AF36 AF36	GND GND	0V	GND	GND
91	U1_XF.AF37 AF37	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AF38 AF38	GND GND	0V	GND	GND
91	U1_XF.AF39 AF39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AF40 AF40	GND GND	0V	GND	GND
91	U1_XF.AF41 AF41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AF42 AF42	GND GND	0V	GND	GND
86	U1_XF.AF43 AF43	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX_IO	VCCAUX_IO	1.8
100	U1_XF.AF44 AF44	GND GND	0V	GND	GND
100	U1_XF.AF45 AF45	NC NC		IO_L22P_T3U_N6_DBC_AD0P_30	IO_L22P_T3U_N6_DBC_AD0P_30
100	U1_XF.AF46 AF46	NC NC		IO_L23P_T3U_N8_30	IO_L23P_T3U_N8_30
100	U1_XF.AF47 AF47	NC NC		IO_L23N_T3U_N9_30	IO_L23N_T3U_N9_30
100	U1_XF.AF48 AF48	NC NC		IO_L18P_T2U_N10_AD2P_30	IO_L18P_T2U_N10_AD2P_30
100	U1_XF.AF49 AF49	NC NC		VCCO_30	VCCO_30	1.8
100	U1_XF.AF50 AF50	NC NC		IO_L14N_T2L_N3_GC_30	IO_L14N_T2L_N3_GC_30
100	U1_XF.AF51 AF51	NC NC		IO_L13N_T2L_N1_GC_QBC_30	IO_L13N_T2L_N1_GC_QBC_30
100	U1_XF.AF52 AF52	NC NC		IO_L12P_T1U_N10_GC_30	IO_L12P_T1U_N10_GC_30
100	U1_XF.AF53 AF53	NC NC		IO_L11N_T1U_N9_GC_30	IO_L11N_T1U_N9_GC_30
100	U1_XF.AF54 AF54	GND GND	0V	GND	GND
100	U1_XF.AF55 AF55	NC NC		IO_L2P_T0L_N2_30	IO_L2P_T0L_N2_30
100	U1_XF.AF56 AF56	NC NC		IO_L2N_T0L_N3_30	IO_L2N_T0L_N3_30
100	U1_XF.AF57 AF57	NC NC		IO_L5P_T0U_N8_AD14P_30	IO_L5P_T0U_N8_AD14P_30
100	U1_XF.AF58 AF58	NC NC		IO_L6N_T0U_N11_AD6N_31	IO_L6N_T0U_N11_AD6N_31
100	U1_XF.AF59 AF59	GND GND	0V	GND	GND
100	U1_XF.AF60 AF60	NC NC		IO_L5P_T0U_N8_AD14P_31	IO_L5P_T0U_N8_AD14P_31
100	U1_XF.AF61 AF61	NC NC		IO_L5N_T0U_N9_AD14N_31	IO_L5N_T0U_N9_AD14N_31
100	U1_XF.AF62 AF62	NC NC		IO_T1U_N12_31	IO_T1U_N12_31
100	U1_XF.AF63 AF63	NC NC		IO_L8P_T1L_N2_AD5P_31	IO_L8P_T1L_N2_AD5P_31
100	U1_XF.AG1 AG1	NC NC		MGTYRXN0_231	MGTYRXN0_231
100	U1_XF.AG2 AG2	NC NC		MGTYRXP0_231	MGTYRXP0_231
100	U1_XF.AG3 AG3	GND GND	0V	GND	GND
100	U1_XF.AG4 AG4	GND GND	0V	GND	GND
95	U1_XF.AG5 AG5	E1S3_PER_N<3>_XF E1S3_PER_N<3>_XF		e1s3_per_n[3]	MGTYRXN3_230
95	U1_XF.AG6 AG6	E1S3_PER_P<3>_XF E1S3_PER_P<3>_XF		e1s3_per_p[3]	MGTYRXP3_230
100	U1_XF.AG7 AG7	GND GND	0V	GND	GND
100	U1_XF.AG8 AG8	GND GND	0V	GND	GND
23	U1_XF.AG9 AG9	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
92	U1_XF.AG10 AG10	AC_E1S3_PET_N<2>_XF AC_E1S3_PET_N<2>_XF		e1s3_pet_n[2]	MGTYTXN2_230
92	U1_XF.AG11 AG11	AC_E1S3_PET_P<2>_XF AC_E1S3_PET_P<2>_XF		e1s3_pet_p[2]	MGTYTXP2_230
100	U1_XF.AG12 AG12	GND GND	0V	GND	GND
23	U1_XF.AG13 AG13	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
85	U1_XF.AG14 AG14	E1S3_FPGA_REFCLK_N<0>_XF E1S3_FPGA_REFCLK_N<0>_XF		e1s3_refclk_n[0]	MGTREFCLK0N_230
85	U1_XF.AG15 AG15	E1S3_FPGA_REFCLK_P<0>_XF E1S3_FPGA_REFCLK_P<0>_XF		e1s3_refclk_p[0]	MGTREFCLK0P_230
100	U1_XF.AG16 AG16	GND GND	0V	GND	GND
100	U1_XF.AG17 AG17	GND GND	0V	GND	GND
84	U1_XF.AG18 AG18	E1S1_3R3V_SDA_XF E1S1_3R3V_SDA_XF	3.3V	e1s_3r3v_sda[1]	IO_L1N_AD11N_93
85	U1_XF.AG19 AG19	E1S1_3R3V_SCL_XF E1S1_3R3V_SCL_XF	3.3V	e1s_3r3v_scl[1]	IO_L1P_AD11P_93
90	U1_XF.AG20 AG20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT_IO	VCCINT_IO	0.85
100	U1_XF.AG21 AG21	GND GND	0V	GND	GND
91	U1_XF.AG22 AG22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AG23 AG23	GND GND	0V	GND	GND
91	U1_XF.AG24 AG24	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AG25 AG25	GND GND	0V	GND	GND
91	U1_XF.AG26 AG26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.AG38 AG38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AG39 AG39	GND GND	0V	GND	GND
91	U1_XF.AG40 AG40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AG41 AG41	GND GND	0V	GND	GND
86	U1_XF.AG42 AG42	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX_IO	VCCAUX_IO	1.8
100	U1_XF.AG43 AG43	GND GND	0V	GND	GND
87	U1_XF.AG44 AG44	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX	VCCAUX	1.8
100	U1_XF.AG45 AG45	NC NC		IO_L24P_T3U_N10_30	IO_L24P_T3U_N10_30
100	U1_XF.AG46 AG46	NC NC		IO_L24N_T3U_N11_30	IO_L24N_T3U_N11_30
100	U1_XF.AG47 AG47	GND GND	0V	GND	GND
100	U1_XF.AG48 AG48	NC NC		IO_L20N_T3L_N3_AD1N_30	IO_L20N_T3L_N3_AD1N_30
100	U1_XF.AG49 AG49	NC NC		IO_L15N_T2L_N5_AD11N_30	IO_L15N_T2L_N5_AD11N_30
100	U1_XF.AG50 AG50	NC NC		IO_L14P_T2L_N2_GC_30	IO_L14P_T2L_N2_GC_30
100	U1_XF.AG51 AG51	NC NC		IO_L13P_T2L_N0_GC_QBC_30	IO_L13P_T2L_N0_GC_QBC_30
100	U1_XF.AG52 AG52	NC NC		VCCO_30	VCCO_30	1.8
100	U1_XF.AG53 AG53	NC NC		IO_L11P_T1U_N8_GC_30	IO_L11P_T1U_N8_GC_30
100	U1_XF.AG54 AG54	NC NC		IO_L7N_T1L_N1_QBC_AD13N_30	IO_L7N_T1L_N1_QBC_AD13N_30
100	U1_XF.AG55 AG55	NC NC		IO_L3P_T0L_N4_AD15P_30	IO_L3P_T0L_N4_AD15P_30
100	U1_XF.AG56 AG56	NC NC		IO_L3N_T0L_N5_AD15N_30	IO_L3N_T0L_N5_AD15N_30
100	U1_XF.AG57 AG57	GND GND	0V	GND	GND
100	U1_XF.AG58 AG58	NC NC		IO_L6P_T0U_N10_AD6P_31	IO_L6P_T0U_N10_AD6P_31
100	U1_XF.AG59 AG59	NC NC		IO_L4P_T0U_N6_DBC_AD7P_31	IO_L4P_T0U_N6_DBC_AD7P_31
100	U1_XF.AG60 AG60	NC NC		IO_L4N_T0U_N7_DBC_AD7N_31	IO_L4N_T0U_N7_DBC_AD7N_31
100	U1_XF.AG61 AG61	NC NC		IO_T0U_N12_VRP_31	IO_T0U_N12_VRP_31
100	U1_XF.AG62 AG62	GND GND	0V	GND	GND
100	U1_XF.AG63 AG63	NC NC		IO_L3N_T0L_N5_AD15N_31	IO_L3N_T0L_N5_AD15N_31
100	U1_XF.AH1 AH1	GND GND	0V	GND	GND
100	U1_XF.AH2 AH2	GND GND	0V	GND	GND
95	U1_XF.AH3 AH3	E1S3_PER_N<2>_XF E1S3_PER_N<2>_XF		e1s3_per_n[2]	MGTYRXN2_230
95	U1_XF.AH4 AH4	E1S3_PER_P<2>_XF E1S3_PER_P<2>_XF		e1s3_per_p[2]	MGTYRXP2_230
100	U1_XF.AH5 AH5	GND GND	0V	GND	GND
100	U1_XF.AH6 AH6	GND GND	0V	GND	GND
100	U1_XF.AH7 AH7	GND GND	0V	GND	GND
92	U1_XF.AH8 AH8	AC_E1S3_PET_N<1>_XF AC_E1S3_PET_N<1>_XF		e1s3_pet_n[1]	MGTYTXN1_230
92	U1_XF.AH9 AH9	AC_E1S3_PET_P<1>_XF AC_E1S3_PET_P<1>_XF		e1s3_pet_p[1]	MGTYTXP1_230
100	U1_XF.AH10 AH10	GND GND	0V	GND	GND
100	U1_XF.AH11 AH11	GND GND	0V	GND	GND
92	U1_XF.AH12 AH12	AC_E1S3_PET_N<0>_XF AC_E1S3_PET_N<0>_XF		e1s3_pet_n[0]	MGTYTXN0_230
92	U1_XF.AH13 AH13	AC_E1S3_PET_P<0>_XF AC_E1S3_PET_P<0>_XF		e1s3_pet_p[0]	MGTYTXP0_230
100	U1_XF.AH14 AH14	GND GND	0V	GND	GND
23	U1_XF.AH15 AH15	PWR_AVCC_RUC_XF PWR_AVCC_RUC_XF	0.9	MGTAVCC_RUC	MGTAVCC_RUC	0.9
100	U1_XF.AH16 AH16	GND GND	0V	GND	GND
38	U1_XF.AH17 AH17	FPGA_CFG_MODE<0>_1 FPGA_CFG_MODE<0>_1		M0_0	M0_0
83	U1_XF.AH18 AH18	E1S1_3R3V_SMB_RST_F_XF E1S1_3R3V_SMB_RST_F_XF	3.3V	e1s_3r3v_smb_rst_f[1]	IO_L2N_AD10N_93
80	U1_XF.AH19 AH19	E1S1_3R3V_DUALPORTEN_F_XF E1S1_3R3V_DUALPORTEN_F_XF		e1s_3r3v_dualporten_f[1]	IO_L2P_AD10P_93
100	U1_XF.AH20 AH20	GND GND	0V	GND	GND
-	U1_XF.AH21 AH21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCBRAM	VCCBRAM	0.85
100	U1_XF.AH22 AH22	GND GND	0V	GND	GND
91	U1_XF.AH23 AH23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AH24 AH24	GND GND	0V	GND	GND
91	U1_XF.AH25 AH25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AH26 AH26	GND GND	0V	GND	GND
100	U1_XF.AH38 AH38	GND GND	0V	GND	GND
91	U1_XF.AH39 AH39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AH40 AH40	GND GND	0V	GND	GND
91	U1_XF.AH41 AH41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AH42 AH42	GND GND	0V	GND	GND
87	U1_XF.AH43 AH43	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX	VCCAUX	1.8
100	U1_XF.AH44 AH44	GND GND	0V	GND	GND
100	U1_XF.AH45 AH45	GND GND	0V	GND	GND
100	U1_XF.AH46 AH46	NC NC		VREF_30	VREF_30
100	U1_XF.AH47 AH47	NC NC		IO_T3U_N12_30	IO_T3U_N12_30
100	U1_XF.AH48 AH48	NC NC		IO_L20P_T3L_N2_AD1P_30	IO_L20P_T3L_N2_AD1P_30
100	U1_XF.AH49 AH49	NC NC		IO_L15P_T2L_N4_AD11P_30	IO_L15P_T2L_N4_AD11P_30
100	U1_XF.AH50 AH50	GND GND	0V	GND	GND
100	U1_XF.AH51 AH51	NC NC		IO_T2U_N12_30	IO_T2U_N12_30
100	U1_XF.AH52 AH52	NC NC		IO_L9P_T1L_N4_AD12P_30	IO_L9P_T1L_N4_AD12P_30
100	U1_XF.AH53 AH53	NC NC		IO_L9N_T1L_N5_AD12N_30	IO_L9N_T1L_N5_AD12N_30
100	U1_XF.AH54 AH54	NC NC		IO_L7P_T1L_N0_QBC_AD13P_30	IO_L7P_T1L_N0_QBC_AD13P_30
100	U1_XF.AH55 AH55	GND GND	0V	GND	GND
100	U1_XF.AH56 AH56	NC NC		IO_L1P_T0L_N0_DBC_30	IO_L1P_T0L_N0_DBC_30
100	U1_XF.AH57 AH57	NC NC		IO_L1N_T0L_N1_DBC_30	IO_L1N_T0L_N1_DBC_30
100	U1_XF.AH58 AH58	NC NC		IO_L2P_T0L_N2_31	IO_L2P_T0L_N2_31
100	U1_XF.AH59 AH59	NC NC		IO_L2N_T0L_N3_31	IO_L2N_T0L_N3_31
100	U1_XF.AH60 AH60	GND GND	0V	GND	GND
100	U1_XF.AH61 AH61	NC NC		IO_L1P_T0L_N0_DBC_31	IO_L1P_T0L_N0_DBC_31
100	U1_XF.AH62 AH62	NC NC		IO_L1N_T0L_N1_DBC_31	IO_L1N_T0L_N1_DBC_31
100	U1_XF.AH63 AH63	NC NC		IO_L3P_T0L_N4_AD15P_31	IO_L3P_T0L_N4_AD15P_31
95	U1_XF.AJ1 AJ1	E1S3_PER_N<1>_XF E1S3_PER_N<1>_XF		e1s3_per_n[1]	MGTYRXN1_230
95	U1_XF.AJ2 AJ2	E1S3_PER_P<1>_XF E1S3_PER_P<1>_XF		e1s3_per_p[1]	MGTYRXP1_230
100	U1_XF.AJ3 AJ3	GND GND	0V	GND	GND
100	U1_XF.AJ4 AJ4	GND GND	0V	GND	GND
95	U1_XF.AJ5 AJ5	E1S3_PER_N<0>_XF E1S3_PER_N<0>_XF		e1s3_per_n[0]	MGTYRXN0_230
95	U1_XF.AJ6 AJ6	E1S3_PER_P<0>_XF E1S3_PER_P<0>_XF		e1s3_per_p[0]	MGTYRXP0_230
100	U1_XF.AJ7 AJ7	GND GND	0V	GND	GND
100	U1_XF.AJ8 AJ8	GND GND	0V	GND	GND
23	U1_XF.AJ9 AJ9	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
92	U1_XF.AJ10 AJ10	AC_E1S3_PET_N<7>_XF AC_E1S3_PET_N<7>_XF		e1s3_pet_n[7]	MGTYTXN3_229
92	U1_XF.AJ11 AJ11	AC_E1S3_PET_P<7>_XF AC_E1S3_PET_P<7>_XF		e1s3_pet_p[7]	MGTYTXP3_229
100	U1_XF.AJ12 AJ12	GND GND	0V	GND	GND
23	U1_XF.AJ13 AJ13	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
31	U1_XF.AJ14 AJ14	MGTRREF_LN_XF MGTRREF_LN_XF		MGTRREF_RUC	MGTRREF_RUC
23	U1_XF.AJ15 AJ15	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTTRCAL_RUC	MGTAVTTRCAL_RUC	1.2
100	U1_XF.AJ16 AJ16	GND GND	0V	GND	GND
38	U1_XF.AJ17 AJ17	FPGA_CFG_MODE<1>_1 FPGA_CFG_MODE<1>_1		M1_0	M1_0
100	U1_XF.AJ18 AJ18	GND GND	0V	GND	GND
31	U1_XF.AJ19 AJ19	FPGA_INIT_F_1 FPGA_INIT_F_1		INIT_B_0	INIT_B_0
90	U1_XF.AJ20 AJ20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT_IO	VCCINT_IO	0.85
100	U1_XF.AJ21 AJ21	GND GND	0V	GND	GND
91	U1_XF.AJ22 AJ22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AJ23 AJ23	GND GND	0V	GND	GND
91	U1_XF.AJ24 AJ24	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AJ25 AJ25	GND GND	0V	GND	GND
91	U1_XF.AJ26 AJ26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.AJ38 AJ38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AJ39 AJ39	GND GND	0V	GND	GND
91	U1_XF.AJ40 AJ40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AJ41 AJ41	GND GND	0V	GND	GND
86	U1_XF.AJ42 AJ42	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX_IO	VCCAUX_IO	1.8
100	U1_XF.AJ43 AJ43	GND GND	0V	GND	GND
100	U1_XF.AJ44 AJ44	NC NC		IO_L23P_T3U_N8_29	IO_L23P_T3U_N8_29
100	U1_XF.AJ45 AJ45	NC NC		IO_L23N_T3U_N9_29	IO_L23N_T3U_N9_29
100	U1_XF.AJ46 AJ46	NC NC		IO_T3U_N12_29	IO_T3U_N12_29
100	U1_XF.AJ47 AJ47	NC NC		IO_T2U_N12_29	IO_T2U_N12_29
100	U1_XF.AJ48 AJ48	GND GND	0V	GND	GND
100	U1_XF.AJ49 AJ49	NC NC		IO_L15N_T2L_N5_AD11N_29	IO_L15N_T2L_N5_AD11N_29
100	U1_XF.AJ50 AJ50	NC NC		IO_T1U_N12_29	IO_T1U_N12_29
100	U1_XF.AJ51 AJ51	NC NC		IO_L9P_T1L_N4_AD12P_29	IO_L9P_T1L_N4_AD12P_29
100	U1_XF.AJ52 AJ52	NC NC		IO_L9N_T1L_N5_AD12N_29	IO_L9N_T1L_N5_AD12N_29
100	U1_XF.AJ53 AJ53	GND GND	0V	GND	GND
100	U1_XF.AJ54 AJ54	NC NC		IO_L5N_T0U_N9_AD14N_29	IO_L5N_T0U_N9_AD14N_29
100	U1_XF.AJ55 AJ55	NC NC		IO_L4P_T0U_N6_DBC_AD7P_29	IO_L4P_T0U_N6_DBC_AD7P_29
100	U1_XF.AJ56 AJ56	NC NC		IO_L4N_T0U_N7_DBC_AD7N_29	IO_L4N_T0U_N7_DBC_AD7N_29
100	U1_XF.AJ57 AJ57	NC NC		IO_T0U_N12_VRP_30	IO_T0U_N12_VRP_30
100	U1_XF.AJ58 AJ58	GND GND	0V	GND	GND
100	U1_XF.AJ59 AJ59	NC NC		IO_L23P_T3U_N8_28	IO_L23P_T3U_N8_28
100	U1_XF.AJ60 AJ60	NC NC		IO_L23N_T3U_N9_28	IO_L23N_T3U_N9_28
100	U1_XF.AJ61 AJ61	NC NC		IO_L17P_T2U_N8_AD10P_28	IO_L17P_T2U_N8_AD10P_28
100	U1_XF.AJ62 AJ62	NC NC		IO_L17N_T2U_N9_AD10N_28	IO_L17N_T2U_N9_AD10N_28
100	U1_XF.AJ63 AJ63	GND GND	0V	GND	GND
100	U1_XF.AK1 AK1	GND GND	0V	GND	GND
100	U1_XF.AK2 AK2	GND GND	0V	GND	GND
95	U1_XF.AK3 AK3	E1S3_PER_N<7>_XF E1S3_PER_N<7>_XF		e1s3_per_n[7]	MGTYRXN3_229
95	U1_XF.AK4 AK4	E1S3_PER_P<7>_XF E1S3_PER_P<7>_XF		e1s3_per_p[7]	MGTYRXP3_229
100	U1_XF.AK5 AK5	GND GND	0V	GND	GND
100	U1_XF.AK6 AK6	GND GND	0V	GND	GND
100	U1_XF.AK7 AK7	GND GND	0V	GND	GND
92	U1_XF.AK8 AK8	AC_E1S3_PET_N<6>_XF AC_E1S3_PET_N<6>_XF		e1s3_pet_n[6]	MGTYTXN2_229
92	U1_XF.AK9 AK9	AC_E1S3_PET_P<6>_XF AC_E1S3_PET_P<6>_XF		e1s3_pet_p[6]	MGTYTXP2_229
100	U1_XF.AK10 AK10	GND GND	0V	GND	GND
100	U1_XF.AK11 AK11	GND GND	0V	GND	GND
92	U1_XF.AK12 AK12	AC_E1S3_PET_N<5>_XF AC_E1S3_PET_N<5>_XF		e1s3_pet_n[5]	MGTYTXN1_229
92	U1_XF.AK13 AK13	AC_E1S3_PET_P<5>_XF AC_E1S3_PET_P<5>_XF		e1s3_pet_p[5]	MGTYTXP1_229
100	U1_XF.AK14 AK14	GND GND	0V	GND	GND
79	U1_XF.AK15 AK15	PWR_RN_RUC_MGTVCCAUX_XF PWR_RN_RUC_MGTVCCAUX_XF	1.8	MGTVCCAUX_RUC	MGTVCCAUX_RUC	1.8
100	U1_XF.AK16 AK16	GND GND	0V	GND	GND
38	U1_XF.AK17 AK17	FPGA_CFG_MODE<2>_1 FPGA_CFG_MODE<2>_1		M2_0	M2_0
-	U1_XF.AK18 AK18	FPGA_PROG_F_1 FPGA_PROG_F_1		PROGRAM_B_0	PROGRAM_B_0
86	U1_XF.AK19 AK19	POR_OVERRIDE_XF POR_OVERRIDE_XF		POR_OVERRIDE_0	POR_OVERRIDE_0
100	U1_XF.AK20 AK20	GND GND	0V	GND	GND
-	U1_XF.AK21 AK21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCBRAM	VCCBRAM	0.85
100	U1_XF.AK22 AK22	GND GND	0V	GND	GND
91	U1_XF.AK23 AK23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AK24 AK24	GND GND	0V	GND	GND
91	U1_XF.AK25 AK25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AK26 AK26	GND GND	0V	GND	GND
100	U1_XF.AK38 AK38	GND GND	0V	GND	GND
91	U1_XF.AK39 AK39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AK40 AK40	GND GND	0V	GND	GND
91	U1_XF.AK41 AK41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AK42 AK42	GND GND	0V	GND	GND
87	U1_XF.AK43 AK43	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX	VCCAUX	1.8
100	U1_XF.AK44 AK44	NC NC		IO_L21P_T3L_N4_AD8P_29	IO_L21P_T3L_N4_AD8P_29
100	U1_XF.AK45 AK45	NC NC		IO_L21N_T3L_N5_AD8N_29	IO_L21N_T3L_N5_AD8N_29
100	U1_XF.AK46 AK46	GND GND	0V	GND	GND
100	U1_XF.AK47 AK47	NC NC		IO_L17P_T2U_N8_AD10P_29	IO_L17P_T2U_N8_AD10P_29
100	U1_XF.AK48 AK48	NC NC		IO_L17N_T2U_N9_AD10N_29	IO_L17N_T2U_N9_AD10N_29
100	U1_XF.AK49 AK49	NC NC		IO_L15P_T2L_N4_AD11P_29	IO_L15P_T2L_N4_AD11P_29
100	U1_XF.AK50 AK50	NC NC		IO_L14N_T2L_N3_GC_29	IO_L14N_T2L_N3_GC_29
100	U1_XF.AK51 AK51	GND GND	0V	GND	GND
100	U1_XF.AK52 AK52	NC NC		IO_L11N_T1U_N9_GC_29	IO_L11N_T1U_N9_GC_29
100	U1_XF.AK53 AK53	NC NC		IO_L8N_T1L_N3_AD5N_29	IO_L8N_T1L_N3_AD5N_29
100	U1_XF.AK54 AK54	NC NC		IO_L5P_T0U_N8_AD14P_29	IO_L5P_T0U_N8_AD14P_29
100	U1_XF.AK55 AK55	NC NC		IO_L6N_T0U_N11_AD6N_29	IO_L6N_T0U_N11_AD6N_29
100	U1_XF.AK56 AK56	NC NC		VCCO_29	VCCO_29	1.8
100	U1_XF.AK57 AK57	NC NC		IO_T0U_N12_VRP_29	IO_T0U_N12_VRP_29
100	U1_XF.AK58 AK58	NC NC		IO_L21P_T3L_N4_AD8P_28	IO_L21P_T3L_N4_AD8P_28
100	U1_XF.AK59 AK59	NC NC		IO_L21N_T3L_N5_AD8N_28	IO_L21N_T3L_N5_AD8N_28
100	U1_XF.AK60 AK60	NC NC		IO_L24P_T3U_N10_28	IO_L24P_T3U_N10_28
100	U1_XF.AK61 AK61	NC NC		VCCO_28	VCCO_28	1.8
100	U1_XF.AK62 AK62	NC NC		IO_L15P_T2L_N4_AD11P_28	IO_L15P_T2L_N4_AD11P_28
100	U1_XF.AK63 AK63	NC NC		IO_L15N_T2L_N5_AD11N_28	IO_L15N_T2L_N5_AD11N_28
95	U1_XF.AL1 AL1	E1S3_PER_N<6>_XF E1S3_PER_N<6>_XF		e1s3_per_n[6]	MGTYRXN2_229
95	U1_XF.AL2 AL2	E1S3_PER_P<6>_XF E1S3_PER_P<6>_XF		e1s3_per_p[6]	MGTYRXP2_229
100	U1_XF.AL3 AL3	GND GND	0V	GND	GND
100	U1_XF.AL4 AL4	GND GND	0V	GND	GND
95	U1_XF.AL5 AL5	E1S3_PER_N<5>_XF E1S3_PER_N<5>_XF		e1s3_per_n[5]	MGTYRXN1_229
95	U1_XF.AL6 AL6	E1S3_PER_P<5>_XF E1S3_PER_P<5>_XF		e1s3_per_p[5]	MGTYRXP1_229
100	U1_XF.AL7 AL7	GND GND	0V	GND	GND
100	U1_XF.AL8 AL8	GND GND	0V	GND	GND
23	U1_XF.AL9 AL9	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
92	U1_XF.AL10 AL10	AC_E1S3_PET_N<4>_XF AC_E1S3_PET_N<4>_XF		e1s3_pet_n[4]	MGTYTXN0_229
92	U1_XF.AL11 AL11	AC_E1S3_PET_P<4>_XF AC_E1S3_PET_P<4>_XF		e1s3_pet_p[4]	MGTYTXP0_229
100	U1_XF.AL12 AL12	GND GND	0V	GND	GND
23	U1_XF.AL13 AL13	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
100	U1_XF.AL14 AL14	NC NC		MGTREFCLK1N_229	MGTREFCLK1N_229
100	U1_XF.AL15 AL15	NC NC		MGTREFCLK1P_229	MGTREFCLK1P_229
100	U1_XF.AL16 AL16	GND GND	0V	GND	GND
18	U1_XF.AL17 AL17	FPGA_CFG_PUDC_F_XF FPGA_CFG_PUDC_F_XF		PUDC_B_0	PUDC_B_0
91	U1_XF.AL18 AL18	FPGA_CFG_DONE_1 FPGA_CFG_DONE_1		DONE_0	DONE_0
100	U1_XF.AL19 AL19	GND GND	0V	GND	GND
90	U1_XF.AL20 AL20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT_IO	VCCINT_IO	0.85
100	U1_XF.AL21 AL21	GND GND	0V	GND	GND
91	U1_XF.AL22 AL22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AL23 AL23	GND GND	0V	GND	GND
91	U1_XF.AL24 AL24	GNDADC_XF GNDADC_XF	0V	GNDADC_0	GNDADC_0
91	U1_XF.AL25 AL25	VCCADC_XF VCCADC_XF	1.8	VCCADC_0	VCCADC_0	1.8
91	U1_XF.AL26 AL26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.AL38 AL38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AL39 AL39	GND GND	0V	GND	GND
91	U1_XF.AL40 AL40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AL41 AL41	GND GND	0V	GND	GND
86	U1_XF.AL42 AL42	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX_IO	VCCAUX_IO	1.8
100	U1_XF.AL43 AL43	GND GND	0V	GND	GND
100	U1_XF.AL44 AL44	GND GND	0V	GND	GND
100	U1_XF.AL45 AL45	NC NC		VREF_29	VREF_29
100	U1_XF.AL46 AL46	NC NC		IO_L24P_T3U_N10_29	IO_L24P_T3U_N10_29
100	U1_XF.AL47 AL47	NC NC		IO_L24N_T3U_N11_29	IO_L24N_T3U_N11_29
100	U1_XF.AL48 AL48	NC NC		IO_L18N_T2U_N11_AD2N_29	IO_L18N_T2U_N11_AD2N_29
100	U1_XF.AL49 AL49	NC NC		VCCO_29	VCCO_29	1.8
100	U1_XF.AL50 AL50	NC NC		IO_L14P_T2L_N2_GC_29	IO_L14P_T2L_N2_GC_29
100	U1_XF.AL51 AL51	NC NC		IO_L12N_T1U_N11_GC_29	IO_L12N_T1U_N11_GC_29
100	U1_XF.AL52 AL52	NC NC		IO_L11P_T1U_N8_GC_29	IO_L11P_T1U_N8_GC_29
100	U1_XF.AL53 AL53	NC NC		IO_L8P_T1L_N2_AD5P_29	IO_L8P_T1L_N2_AD5P_29
100	U1_XF.AL54 AL54	GND GND	0V	GND	GND
100	U1_XF.AL55 AL55	NC NC		IO_L6P_T0U_N10_AD6P_29	IO_L6P_T0U_N10_AD6P_29
100	U1_XF.AL56 AL56	NC NC		IO_L2N_T0L_N3_29	IO_L2N_T0L_N3_29
100	U1_XF.AL57 AL57	NC NC		IO_L19P_T3L_N0_DBC_AD9P_28	IO_L19P_T3L_N0_DBC_AD9P_28
100	U1_XF.AL58 AL58	NC NC		IO_L19N_T3L_N1_DBC_AD9N_28	IO_L19N_T3L_N1_DBC_AD9N_28
100	U1_XF.AL59 AL59	GND GND	0V	GND	GND
100	U1_XF.AL60 AL60	NC NC		IO_L24N_T3U_N11_28	IO_L24N_T3U_N11_28
100	U1_XF.AL61 AL61	NC NC		IO_T2U_N12_28	IO_T2U_N12_28
100	U1_XF.AL62 AL62	NC NC		IO_L18P_T2U_N10_AD2P_28	IO_L18P_T2U_N10_AD2P_28
100	U1_XF.AL63 AL63	NC NC		IO_L18N_T2U_N11_AD2N_28	IO_L18N_T2U_N11_AD2N_28
100	U1_XF.AM1 AM1	GND GND	0V	GND	GND
100	U1_XF.AM2 AM2	GND GND	0V	GND	GND
95	U1_XF.AM3 AM3	E1S3_PER_N<4>_XF E1S3_PER_N<4>_XF		e1s3_per_n[4]	MGTYRXN0_229
95	U1_XF.AM4 AM4	E1S3_PER_P<4>_XF E1S3_PER_P<4>_XF		e1s3_per_p[4]	MGTYRXP0_229
100	U1_XF.AM5 AM5	GND GND	0V	GND	GND
100	U1_XF.AM6 AM6	GND GND	0V	GND	GND
100	U1_XF.AM7 AM7	GND GND	0V	GND	GND
92	U1_XF.AM8 AM8	AC_PCIE1_TXN<0>_XF AC_PCIE1_TXN<0>_XF		pcie1_txn[0]	MGTYTXN3_228
92	U1_XF.AM9 AM9	AC_PCIE1_TXP<0>_XF AC_PCIE1_TXP<0>_XF		pcie1_txp[0]	MGTYTXP3_228
100	U1_XF.AM10 AM10	GND GND	0V	GND	GND
100	U1_XF.AM11 AM11	GND GND	0V	GND	GND
92	U1_XF.AM12 AM12	AC_PCIE1_TXN<1>_XF AC_PCIE1_TXN<1>_XF		pcie1_txn[1]	MGTYTXN2_228
92	U1_XF.AM13 AM13	AC_PCIE1_TXP<1>_XF AC_PCIE1_TXP<1>_XF		pcie1_txp[1]	MGTYTXP2_228
100	U1_XF.AM14 AM14	GND GND	0V	GND	GND
79	U1_XF.AM15 AM15	PWR_RN_RUC_MGTVCCAUX_XF PWR_RN_RUC_MGTVCCAUX_XF	1.8	MGTVCCAUX_RUC	MGTVCCAUX_RUC	1.8
100	U1_XF.AM16 AM16	GND GND	0V	GND	GND
88	U1_XF.AM17 AM17	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCO_0	VCCO_0	1.8
-	U1_XF.AM18 AM18	UNNAMED_18_RESISTOR_I23_A_XF UNNAMED_18_RESISTOR_I23_A_XF ->R40_XF->CFG_FLASH_CLK_XF		CCLK_0	CCLK_0
90	U1_XF.AM19 AM19	FPGA_P1R8V_TCK FPGA_P1R8V_TCK	1.8V	TCK_0	TCK_0
-	U1_XF.AM20 AM20	CFGBVS_0_XF CFGBVS_0_XF		RSVDGND_0	RSVDGND_0
-	U1_XF.AM21 AM21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCBRAM	VCCBRAM	0.85
100	U1_XF.AM22 AM22	GND GND	0V	GND	GND
91	U1_XF.AM23 AM23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
-	U1_XF.AM24 AM24	VREF_P1R25V_RET_XF VREF_P1R25V_RET_XF	1.25V	VREFN_0	VREFN_0
-	U1_XF.AM25 AM25	UNNAMED_17_BYPASSCAPNPOL_I48_A_XF UNNAMED_17_BYPASSCAPNPOL_I48_A_XF ->C138_XF->UNNAMED_17_BYPASSCAPNPOL_I48_B_XF ->R76_XF->UNNAMED_17_RESISTOR_I51_A_XF		vp	VP
100	U1_XF.AM26 AM26	GND GND	0V	GND	GND
100	U1_XF.AM38 AM38	GND GND	0V	GND	GND
91	U1_XF.AM39 AM39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AM40 AM40	GND GND	0V	GND	GND
91	U1_XF.AM41 AM41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AM42 AM42	GND GND	0V	GND	GND
87	U1_XF.AM43 AM43	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX	VCCAUX	1.8
100	U1_XF.AM44 AM44	NC NC		IO_L19N_T3L_N1_DBC_AD9N_29	IO_L19N_T3L_N1_DBC_AD9N_29
100	U1_XF.AM45 AM45	NC NC		IO_L22P_T3U_N6_DBC_AD0P_29	IO_L22P_T3U_N6_DBC_AD0P_29
100	U1_XF.AM46 AM46	NC NC		IO_L22N_T3U_N7_DBC_AD0N_29	IO_L22N_T3U_N7_DBC_AD0N_29
100	U1_XF.AM47 AM47	GND GND	0V	GND	GND
100	U1_XF.AM48 AM48	NC NC		IO_L18P_T2U_N10_AD2P_29	IO_L18P_T2U_N10_AD2P_29
100	U1_XF.AM49 AM49	NC NC		IO_L13P_T2L_N0_GC_QBC_29	IO_L13P_T2L_N0_GC_QBC_29
100	U1_XF.AM50 AM50	NC NC		IO_L13N_T2L_N1_GC_QBC_29	IO_L13N_T2L_N1_GC_QBC_29
100	U1_XF.AM51 AM51	NC NC		IO_L12P_T1U_N10_GC_29	IO_L12P_T1U_N10_GC_29
100	U1_XF.AM52 AM52	NC NC		VCCO_29	VCCO_29	1.8
100	U1_XF.AM53 AM53	NC NC		IO_L7N_T1L_N1_QBC_AD13N_29	IO_L7N_T1L_N1_QBC_AD13N_29
100	U1_XF.AM54 AM54	NC NC		IO_L1N_T0L_N1_DBC_29	IO_L1N_T0L_N1_DBC_29
100	U1_XF.AM55 AM55	NC NC		IO_L2P_T0L_N2_29	IO_L2P_T0L_N2_29
100	U1_XF.AM56 AM56	NC NC		IO_L3N_T0L_N5_AD15N_29	IO_L3N_T0L_N5_AD15N_29
100	U1_XF.AM57 AM57	GND GND	0V	GND	GND
100	U1_XF.AM58 AM58	NC NC		IO_L20P_T3L_N2_AD1P_28	IO_L20P_T3L_N2_AD1P_28
100	U1_XF.AM59 AM59	NC NC		IO_L22P_T3U_N6_DBC_AD0P_28	IO_L22P_T3U_N6_DBC_AD0P_28
100	U1_XF.AM60 AM60	NC NC		IO_L22N_T3U_N7_DBC_AD0N_28	IO_L22N_T3U_N7_DBC_AD0N_28
100	U1_XF.AM61 AM61	NC NC		IO_L13P_T2L_N0_GC_QBC_28	IO_L13P_T2L_N0_GC_QBC_28
100	U1_XF.AM62 AM62	GND GND	0V	GND	GND
100	U1_XF.AM63 AM63	NC NC		IO_L16P_T2U_N6_QBC_AD3P_28	IO_L16P_T2U_N6_QBC_AD3P_28
95	U1_XF.AN1 AN1	PCIE1_RXN<0>_XF PCIE1_RXN<0>_XF		pcie1_rxn[0]	MGTYRXN3_228
95	U1_XF.AN2 AN2	PCIE1_RXP<0>_XF PCIE1_RXP<0>_XF		pcie1_rxp[0]	MGTYRXP3_228
100	U1_XF.AN3 AN3	GND GND	0V	GND	GND
100	U1_XF.AN4 AN4	GND GND	0V	GND	GND
95	U1_XF.AN5 AN5	PCIE1_RXN<1>_XF PCIE1_RXN<1>_XF		pcie1_rxn[1]	MGTYRXN2_228
95	U1_XF.AN6 AN6	PCIE1_RXP<1>_XF PCIE1_RXP<1>_XF		pcie1_rxp[1]	MGTYRXP2_228
100	U1_XF.AN7 AN7	GND GND	0V	GND	GND
100	U1_XF.AN8 AN8	GND GND	0V	GND	GND
23	U1_XF.AN9 AN9	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
92	U1_XF.AN10 AN10	AC_PCIE1_TXN<2>_XF AC_PCIE1_TXN<2>_XF		pcie1_txn[2]	MGTYTXN1_228
92	U1_XF.AN11 AN11	AC_PCIE1_TXP<2>_XF AC_PCIE1_TXP<2>_XF		pcie1_txp[2]	MGTYTXP1_228
100	U1_XF.AN12 AN12	GND GND	0V	GND	GND
23	U1_XF.AN13 AN13	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
85	U1_XF.AN14 AN14	E1S3_FPGA_REFCLK_N<1>_XF E1S3_FPGA_REFCLK_N<1>_XF		e1s3_refclk_n[1]	MGTREFCLK0N_229
85	U1_XF.AN15 AN15	E1S3_FPGA_REFCLK_P<1>_XF E1S3_FPGA_REFCLK_P<1>_XF		e1s3_refclk_p[1]	MGTREFCLK0P_229
100	U1_XF.AN16 AN16	GND GND	0V	GND	GND
85	U1_XF.AN17 AN17	CFG_FLASH_RDWR_FCS_B_0_XF CFG_FLASH_RDWR_FCS_B_0_XF		RDWR_FCS_B_0	RDWR_FCS_B_0
89	U1_XF.AN18 AN18	FPGA_P1R8V_TDO UNNAMED_18_RESISTOR_I22_A_XF ->R41_XF->FPGA_P1R8V_TDO	1.8V**	TDO_0	TDO_0
89	U1_XF.AN19 AN19	FPGA_P1R8V_TDI FPGA_P1R8V_TDI	1.8V	TDI_0	TDI_0
90	U1_XF.AN20 AN20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT_IO	VCCINT_IO	0.85
100	U1_XF.AN21 AN21	GND GND	0V	GND	GND
91	U1_XF.AN22 AN22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AN23 AN23	GND GND	0V	GND	GND
-	U1_XF.AN24 AN24	UNNAMED_17_BYPASSCAPNPOL_I48_B_XF UNNAMED_17_BYPASSCAPNPOL_I48_B_XF ->C138_XF->UNNAMED_17_BYPASSCAPNPOL_I48_A_XF ->R77_XF->UNNAMED_17_RESISTOR_I52_A_XF		vn	VN
87	U1_XF.AN25 AN25	VREF_P1R25V_XF VREF_P1R25V_XF	1.25	VREFP_0	VREFP_0	1.25
91	U1_XF.AN26 AN26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.AN38 AN38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AN39 AN39	GND GND	0V	GND	GND
91	U1_XF.AN40 AN40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AN41 AN41	GND GND	0V	GND	GND
86	U1_XF.AN42 AN42	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX_IO	VCCAUX_IO	1.8
100	U1_XF.AN43 AN43	GND GND	0V	GND	GND
100	U1_XF.AN44 AN44	NC NC		IO_L19P_T3L_N0_DBC_AD9P_29	IO_L19P_T3L_N0_DBC_AD9P_29
100	U1_XF.AN45 AN45	GND GND	0V	GND	GND
100	U1_XF.AN46 AN46	NC NC		IO_L20P_T3L_N2_AD1P_29	IO_L20P_T3L_N2_AD1P_29
100	U1_XF.AN47 AN47	NC NC		IO_L20N_T3L_N3_AD1N_29	IO_L20N_T3L_N3_AD1N_29
100	U1_XF.AN48 AN48	NC NC		IO_L16P_T2U_N6_QBC_AD3P_29	IO_L16P_T2U_N6_QBC_AD3P_29
100	U1_XF.AN49 AN49	NC NC		IO_L16N_T2U_N7_QBC_AD3N_29	IO_L16N_T2U_N7_QBC_AD3N_29
100	U1_XF.AN50 AN50	GND GND	0V	GND	GND
100	U1_XF.AN51 AN51	NC NC		IO_L10P_T1U_N6_QBC_AD4P_29	IO_L10P_T1U_N6_QBC_AD4P_29
100	U1_XF.AN52 AN52	NC NC		IO_L10N_T1U_N7_QBC_AD4N_29	IO_L10N_T1U_N7_QBC_AD4N_29
100	U1_XF.AN53 AN53	NC NC		IO_L7P_T1L_N0_QBC_AD13P_29	IO_L7P_T1L_N0_QBC_AD13P_29
100	U1_XF.AN54 AN54	NC NC		IO_L1P_T0L_N0_DBC_29	IO_L1P_T0L_N0_DBC_29
100	U1_XF.AN55 AN55	GND GND	0V	GND	GND
100	U1_XF.AN56 AN56	NC NC		IO_L3P_T0L_N4_AD15P_29	IO_L3P_T0L_N4_AD15P_29
100	U1_XF.AN57 AN57	NC NC		VREF_28	VREF_28
100	U1_XF.AN58 AN58	NC NC		IO_L20N_T3L_N3_AD1N_28	IO_L20N_T3L_N3_AD1N_28
100	U1_XF.AN59 AN59	NC NC		IO_T3U_N12_28	IO_T3U_N12_28
100	U1_XF.AN60 AN60	NC NC		VCCO_28	VCCO_28	1.8
100	U1_XF.AN61 AN61	NC NC		IO_L13N_T2L_N1_GC_QBC_28	IO_L13N_T2L_N1_GC_QBC_28
100	U1_XF.AN62 AN62	NC NC		IO_L14P_T2L_N2_GC_28	IO_L14P_T2L_N2_GC_28
100	U1_XF.AN63 AN63	NC NC		IO_L16N_T2U_N7_QBC_AD3N_28	IO_L16N_T2U_N7_QBC_AD3N_28
100	U1_XF.AP1 AP1	GND GND	0V	GND	GND
100	U1_XF.AP2 AP2	GND GND	0V	GND	GND
95	U1_XF.AP3 AP3	PCIE1_RXN<2>_XF PCIE1_RXN<2>_XF		pcie1_rxn[2]	MGTYRXN1_228
95	U1_XF.AP4 AP4	PCIE1_RXP<2>_XF PCIE1_RXP<2>_XF		pcie1_rxp[2]	MGTYRXP1_228
100	U1_XF.AP5 AP5	GND GND	0V	GND	GND
100	U1_XF.AP6 AP6	GND GND	0V	GND	GND
100	U1_XF.AP7 AP7	GND GND	0V	GND	GND
92	U1_XF.AP8 AP8	AC_PCIE1_TXN<3>_XF AC_PCIE1_TXN<3>_XF		pcie1_txn[3]	MGTYTXN0_228
92	U1_XF.AP9 AP9	AC_PCIE1_TXP<3>_XF AC_PCIE1_TXP<3>_XF		pcie1_txp[3]	MGTYTXP0_228
100	U1_XF.AP10 AP10	GND GND	0V	GND	GND
100	U1_XF.AP11 AP11	GND GND	0V	GND	GND
92	U1_XF.AP12 AP12	AC_PCIE1_TXN<4>_XF AC_PCIE1_TXN<4>_XF		pcie1_txn[4]	MGTYTXN3_227
92	U1_XF.AP13 AP13	AC_PCIE1_TXP<4>_XF AC_PCIE1_TXP<4>_XF		pcie1_txp[4]	MGTYTXP3_227
100	U1_XF.AP14 AP14	GND GND	0V	GND	GND
79	U1_XF.AP15 AP15	PWR_RS_RLC_MGTVCCAUX_XF PWR_RS_RLC_MGTVCCAUX_XF	1.8	MGTVCCAUX_RLC	MGTVCCAUX_RLC	1.8
100	U1_XF.AP16 AP16	GND GND	0V	GND	GND
90	U1_XF.AP17 AP17	FPGA_P1R8V_TMS FPGA_P1R8V_TMS	1.8V	TMS_0	TMS_0
100	U1_XF.AP18 AP18	GND GND	0V	GND	GND
85	U1_XF.AP19 AP19	CFG_FLASH_D03_0_XF CFG_FLASH_D03_0_XF		D03_0	D03_0
100	U1_XF.AP20 AP20	GND GND	0V	GND	GND
-	U1_XF.AP21 AP21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCBRAM	VCCBRAM	0.85
100	U1_XF.AP22 AP22	GND GND	0V	GND	GND
91	U1_XF.AP23 AP23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
-	U1_XF.AP24 AP24	TS_FPGA_N_XF TS_FPGA_N_XF		DXN_0	DXN_0
-	U1_XF.AP25 AP25	TS_FPGA_P_XF TS_FPGA_P_XF		DXP_0	DXP_0
100	U1_XF.AP26 AP26	GND GND	0V	GND	GND
100	U1_XF.AP38 AP38	GND GND	0V	GND	GND
91	U1_XF.AP39 AP39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AP40 AP40	GND GND	0V	GND	GND
91	U1_XF.AP41 AP41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AP42 AP42	GND GND	0V	GND	GND
87	U1_XF.AP43 AP43	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX	VCCAUX	1.8
100	U1_XF.AP44 AP44	NC NC		IO_L24P_T3U_N10_27	IO_L24P_T3U_N10_27
100	U1_XF.AP45 AP45	NC NC		IO_L24N_T3U_N11_27	IO_L24N_T3U_N11_27
100	U1_XF.AP46 AP46	NC NC		IO_L18P_T2U_N10_AD2P_27	IO_L18P_T2U_N10_AD2P_27
100	U1_XF.AP47 AP47	NC NC		IO_L18N_T2U_N11_AD2N_27	IO_L18N_T2U_N11_AD2N_27
100	U1_XF.AP48 AP48	GND GND	0V	GND	GND
100	U1_XF.AP49 AP49	NC NC		IO_L15P_T2L_N4_AD11P_27	IO_L15P_T2L_N4_AD11P_27
100	U1_XF.AP50 AP50	NC NC		IO_L10P_T1U_N6_QBC_AD4P_27	IO_L10P_T1U_N6_QBC_AD4P_27
100	U1_XF.AP51 AP51	NC NC		IO_L8P_T1L_N2_AD5P_27	IO_L8P_T1L_N2_AD5P_27
100	U1_XF.AP52 AP52	NC NC		IO_L8N_T1L_N3_AD5N_27	IO_L8N_T1L_N3_AD5N_27
100	U1_XF.AP53 AP53	GND GND	0V	GND	GND
100	U1_XF.AP54 AP54	NC NC		IO_L6P_T0U_N10_AD6P_27	IO_L6P_T0U_N10_AD6P_27
100	U1_XF.AP55 AP55	NC NC		IO_L4P_T0U_N6_DBC_AD7P_27	IO_L4P_T0U_N6_DBC_AD7P_27
100	U1_XF.AP56 AP56	NC NC		IO_L4N_T0U_N7_DBC_AD7N_27	IO_L4N_T0U_N7_DBC_AD7N_27
100	U1_XF.AP57 AP57	NC NC		IO_L6P_T0U_N10_AD6P_28	IO_L6P_T0U_N10_AD6P_28
100	U1_XF.AP58 AP58	GND GND	0V	GND	GND
100	U1_XF.AP59 AP59	NC NC		IO_T0U_N12_VRP_28	IO_T0U_N12_VRP_28
100	U1_XF.AP60 AP60	NC NC		IO_L11P_T1U_N8_GC_28	IO_L11P_T1U_N8_GC_28
100	U1_XF.AP61 AP61	NC NC		IO_L11N_T1U_N9_GC_28	IO_L11N_T1U_N9_GC_28
100	U1_XF.AP62 AP62	NC NC		IO_L14N_T2L_N3_GC_28	IO_L14N_T2L_N3_GC_28
100	U1_XF.AP63 AP63	GND GND	0V	GND	GND
95	U1_XF.AR1 AR1	PCIE1_RXN<3>_XF PCIE1_RXN<3>_XF		pcie1_rxn[3]	MGTYRXN0_228
95	U1_XF.AR2 AR2	PCIE1_RXP<3>_XF PCIE1_RXP<3>_XF		pcie1_rxp[3]	MGTYRXP0_228
100	U1_XF.AR3 AR3	GND GND	0V	GND	GND
100	U1_XF.AR4 AR4	GND GND	0V	GND	GND
95	U1_XF.AR5 AR5	PCIE1_RXN<4>_XF PCIE1_RXN<4>_XF		pcie1_rxn[4]	MGTYRXN3_227
95	U1_XF.AR6 AR6	PCIE1_RXP<4>_XF PCIE1_RXP<4>_XF		pcie1_rxp[4]	MGTYRXP3_227
100	U1_XF.AR7 AR7	GND GND	0V	GND	GND
100	U1_XF.AR8 AR8	GND GND	0V	GND	GND
23	U1_XF.AR9 AR9	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
92	U1_XF.AR10 AR10	AC_PCIE1_TXN<5>_XF AC_PCIE1_TXN<5>_XF		pcie1_txn[5]	MGTYTXN2_227
92	U1_XF.AR11 AR11	AC_PCIE1_TXP<5>_XF AC_PCIE1_TXP<5>_XF		pcie1_txp[5]	MGTYTXP2_227
100	U1_XF.AR12 AR12	GND GND	0V	GND	GND
23	U1_XF.AR13 AR13	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
100	U1_XF.AR14 AR14	NC NC		MGTREFCLK1N_228	MGTREFCLK1N_228
100	U1_XF.AR15 AR15	NC NC		MGTREFCLK1P_228	MGTREFCLK1P_228
100	U1_XF.AR16 AR16	GND GND	0V	GND	GND
85	U1_XF.AR17 AR17	CFG_FLASH_D00_MOSI_0_XF CFG_FLASH_D00_MOSI_0_XF		D00_MOSI_0	D00_MOSI_0
85	U1_XF.AR18 AR18	CFG_FLASH_D01_DIN_0_XF CFG_FLASH_D01_DIN_0_XF		D01_DIN_0	D01_DIN_0
85	U1_XF.AR19 AR19	CFG_FLASH_D02_0_XF CFG_FLASH_D02_0_XF		D02_0	D02_0
90	U1_XF.AR20 AR20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT_IO	VCCINT_IO	0.85
100	U1_XF.AR21 AR21	GND GND	0V	GND	GND
91	U1_XF.AR22 AR22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AR23 AR23	GND GND	0V	GND	GND
91	U1_XF.AR24 AR24	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AR25 AR25	GND GND	0V	GND	GND
91	U1_XF.AR26 AR26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.AR38 AR38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AR39 AR39	GND GND	0V	GND	GND
91	U1_XF.AR40 AR40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AR41 AR41	GND GND	0V	GND	GND
86	U1_XF.AR42 AR42	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX_IO	VCCAUX_IO	1.8
100	U1_XF.AR43 AR43	GND GND	0V	GND	GND
100	U1_XF.AR44 AR44	NC NC		IO_L22P_T3U_N6_DBC_AD0P_27	IO_L22P_T3U_N6_DBC_AD0P_27
100	U1_XF.AR45 AR45	NC NC		IO_L22N_T3U_N7_DBC_AD0N_27	IO_L22N_T3U_N7_DBC_AD0N_27
100	U1_XF.AR46 AR46	GND GND	0V	GND	GND
100	U1_XF.AR47 AR47	NC NC		IO_L16P_T2U_N6_QBC_AD3P_27	IO_L16P_T2U_N6_QBC_AD3P_27
100	U1_XF.AR48 AR48	NC NC		IO_L16N_T2U_N7_QBC_AD3N_27	IO_L16N_T2U_N7_QBC_AD3N_27
100	U1_XF.AR49 AR49	NC NC		IO_L15N_T2L_N5_AD11N_27	IO_L15N_T2L_N5_AD11N_27
100	U1_XF.AR50 AR50	NC NC		IO_L10N_T1U_N7_QBC_AD4N_27	IO_L10N_T1U_N7_QBC_AD4N_27
100	U1_XF.AR51 AR51	GND GND	0V	GND	GND
100	U1_XF.AR52 AR52	NC NC		IO_L9P_T1L_N4_AD12P_27	IO_L9P_T1L_N4_AD12P_27
100	U1_XF.AR53 AR53	NC NC		IO_L9N_T1L_N5_AD12N_27	IO_L9N_T1L_N5_AD12N_27
100	U1_XF.AR54 AR54	NC NC		IO_L6N_T0U_N11_AD6N_27	IO_L6N_T0U_N11_AD6N_27
100	U1_XF.AR55 AR55	NC NC		IO_L2P_T0L_N2_27	IO_L2P_T0L_N2_27
100	U1_XF.AR56 AR56	GND GND	0V	GND	GND
100	U1_XF.AR57 AR57	NC NC		IO_L6N_T0U_N11_AD6N_28	IO_L6N_T0U_N11_AD6N_28
100	U1_XF.AR58 AR58	NC NC		IO_L5P_T0U_N8_AD14P_28	IO_L5P_T0U_N8_AD14P_28
100	U1_XF.AR59 AR59	NC NC		IO_L5N_T0U_N9_AD14N_28	IO_L5N_T0U_N9_AD14N_28
100	U1_XF.AR60 AR60	NC NC		IO_L12P_T1U_N10_GC_28	IO_L12P_T1U_N10_GC_28
100	U1_XF.AR61 AR61	GND GND	0V	GND	GND
100	U1_XF.AR62 AR62	NC NC		IO_L9P_T1L_N4_AD12P_28	IO_L9P_T1L_N4_AD12P_28
100	U1_XF.AR63 AR63	NC NC		IO_L9N_T1L_N5_AD12N_28	IO_L9N_T1L_N5_AD12N_28
100	U1_XF.AT1 AT1	GND GND	0V	GND	GND
100	U1_XF.AT2 AT2	GND GND	0V	GND	GND
95	U1_XF.AT3 AT3	PCIE1_RXN<5>_XF PCIE1_RXN<5>_XF		pcie1_rxn[5]	MGTYRXN2_227
95	U1_XF.AT4 AT4	PCIE1_RXP<5>_XF PCIE1_RXP<5>_XF		pcie1_rxp[5]	MGTYRXP2_227
100	U1_XF.AT5 AT5	GND GND	0V	GND	GND
100	U1_XF.AT6 AT6	GND GND	0V	GND	GND
100	U1_XF.AT7 AT7	GND GND	0V	GND	GND
92	U1_XF.AT8 AT8	AC_PCIE1_TXN<6>_XF AC_PCIE1_TXN<6>_XF		pcie1_txn[6]	MGTYTXN1_227
92	U1_XF.AT9 AT9	AC_PCIE1_TXP<6>_XF AC_PCIE1_TXP<6>_XF		pcie1_txp[6]	MGTYTXP1_227
100	U1_XF.AT10 AT10	GND GND	0V	GND	GND
100	U1_XF.AT11 AT11	GND GND	0V	GND	GND
92	U1_XF.AT12 AT12	AC_PCIE1_TXN<7>_XF AC_PCIE1_TXN<7>_XF		pcie1_txn[7]	MGTYTXN0_227
92	U1_XF.AT13 AT13	AC_PCIE1_TXP<7>_XF AC_PCIE1_TXP<7>_XF		pcie1_txp[7]	MGTYTXP0_227
100	U1_XF.AT14 AT14	GND GND	0V	GND	GND
79	U1_XF.AT15 AT15	PWR_RS_RLC_MGTVCCAUX_XF PWR_RS_RLC_MGTVCCAUX_XF	1.8	MGTVCCAUX_RLC	MGTVCCAUX_RLC	1.8
100	U1_XF.AT16 AT16	GND GND	0V	GND	GND
-	U1_XF.AT17 AT17	UNNAMED_18_RESISTOR_I52_A_XF UNNAMED_18_RESISTOR_I52_A_XF ->R140_XF->GND		VBATT_0	VBATT_0	1.8
-	U1_XF.AT18 AT18	NC NC		ocl_3r3v_extra_io[10]	IO_L12P_AD0P_88
88	U1_XF.AT19 AT19	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCO_0	VCCO_0	1.8
100	U1_XF.AT20 AT20	GND GND	0V	GND	GND
-	U1_XF.AT21 AT21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCBRAM	VCCBRAM	0.85
100	U1_XF.AT22 AT22	GND GND	0V	GND	GND
91	U1_XF.AT23 AT23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AT24 AT24	GND GND	0V	GND	GND
91	U1_XF.AT25 AT25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AT26 AT26	GND GND	0V	GND	GND
100	U1_XF.AT38 AT38	GND GND	0V	GND	GND
91	U1_XF.AT39 AT39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AT40 AT40	GND GND	0V	GND	GND
91	U1_XF.AT41 AT41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AT42 AT42	GND GND	0V	GND	GND
87	U1_XF.AT43 AT43	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX	VCCAUX	1.8
100	U1_XF.AT44 AT44	GND GND	0V	GND	GND
100	U1_XF.AT45 AT45	NC NC		VREF_27	VREF_27
100	U1_XF.AT46 AT46	NC NC		IO_L20P_T3L_N2_AD1P_27	IO_L20P_T3L_N2_AD1P_27
100	U1_XF.AT47 AT47	NC NC		IO_L20N_T3L_N3_AD1N_27	IO_L20N_T3L_N3_AD1N_27
100	U1_XF.AT48 AT48	NC NC		IO_T2U_N12_27	IO_T2U_N12_27
100	U1_XF.AT49 AT49	NC NC		VCCO_27	VCCO_27	1.8
100	U1_XF.AT50 AT50	NC NC		IO_L13P_T2L_N0_GC_QBC_27	IO_L13P_T2L_N0_GC_QBC_27
100	U1_XF.AT51 AT51	NC NC		IO_L12P_T1U_N10_GC_27	IO_L12P_T1U_N10_GC_27
100	U1_XF.AT52 AT52	NC NC		IO_L11P_T1U_N8_GC_27	IO_L11P_T1U_N8_GC_27
100	U1_XF.AT53 AT53	NC NC		IO_L11N_T1U_N9_GC_27	IO_L11N_T1U_N9_GC_27
100	U1_XF.AT54 AT54	GND GND	0V	GND	GND
100	U1_XF.AT55 AT55	NC NC		IO_L2N_T0L_N3_27	IO_L2N_T0L_N3_27
100	U1_XF.AT56 AT56	NC NC		IO_L3P_T0L_N4_AD15P_27	IO_L3P_T0L_N4_AD15P_27
100	U1_XF.AT57 AT57	NC NC		IO_L4P_T0U_N6_DBC_AD7P_28	IO_L4P_T0U_N6_DBC_AD7P_28
100	U1_XF.AT58 AT58	NC NC		IO_L4N_T0U_N7_DBC_AD7N_28	IO_L4N_T0U_N7_DBC_AD7N_28
100	U1_XF.AT59 AT59	NC NC		VCCO_28	VCCO_28	1.8
100	U1_XF.AT60 AT60	NC NC		IO_L12N_T1U_N11_GC_28	IO_L12N_T1U_N11_GC_28
100	U1_XF.AT61 AT61	NC NC		IO_L8P_T1L_N2_AD5P_28	IO_L8P_T1L_N2_AD5P_28
100	U1_XF.AT62 AT62	NC NC		IO_L10P_T1U_N6_QBC_AD4P_28	IO_L10P_T1U_N6_QBC_AD4P_28
100	U1_XF.AT63 AT63	NC NC		IO_L10N_T1U_N7_QBC_AD4N_28	IO_L10N_T1U_N7_QBC_AD4N_28
95	U1_XF.AU1 AU1	PCIE1_RXN<6>_XF PCIE1_RXN<6>_XF		pcie1_rxn[6]	MGTYRXN1_227
95	U1_XF.AU2 AU2	PCIE1_RXP<6>_XF PCIE1_RXP<6>_XF		pcie1_rxp[6]	MGTYRXP1_227
100	U1_XF.AU3 AU3	GND GND	0V	GND	GND
100	U1_XF.AU4 AU4	GND GND	0V	GND	GND
95	U1_XF.AU5 AU5	PCIE1_RXN<7>_XF PCIE1_RXN<7>_XF		pcie1_rxn[7]	MGTYRXN0_227
95	U1_XF.AU6 AU6	PCIE1_RXP<7>_XF PCIE1_RXP<7>_XF		pcie1_rxp[7]	MGTYRXP0_227
100	U1_XF.AU7 AU7	GND GND	0V	GND	GND
100	U1_XF.AU8 AU8	GND GND	0V	GND	GND
23	U1_XF.AU9 AU9	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
92	U1_XF.AU10 AU10	AC_PCIE0_TXN<0>_XF AC_PCIE0_TXN<0>_XF		pcie0_txn[0]	MGTYTXN3_226
92	U1_XF.AU11 AU11	AC_PCIE0_TXP<0>_XF AC_PCIE0_TXP<0>_XF		pcie0_txp[0]	MGTYTXP3_226
100	U1_XF.AU12 AU12	GND GND	0V	GND	GND
23	U1_XF.AU13 AU13	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
23	U1_XF.AU14 AU14	AC_PCIE1_REFN_XF AC_PCIE1_REFN_XF		pcie1_refclk_n	MGTREFCLK0N_228
23	U1_XF.AU15 AU15	AC_PCIE1_REFP_XF AC_PCIE1_REFP_XF		pcie1_refclk_p	MGTREFCLK0P_228
100	U1_XF.AU16 AU16	GND GND	0V	GND	GND
100	U1_XF.AU17 AU17	GND GND	0V	GND	GND
-	U1_XF.AU18 AU18	NC NC		ocl_3r3v_extra_io[11]	IO_L12N_AD0N_88
34	U1_XF.AU19 AU19	OCL2_3R3V_CKEN_F<1>_XF OCL2_3R3V_CKEN_F<1>_XF		ocl_3r3v_cken1_f[2]	IO_L10P_AD2P_88
90	U1_XF.AU20 AU20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT_IO	VCCINT_IO	0.85
100	U1_XF.AU21 AU21	GND GND	0V	GND	GND
91	U1_XF.AU22 AU22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AU23 AU23	GND GND	0V	GND	GND
91	U1_XF.AU24 AU24	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AU25 AU25	GND GND	0V	GND	GND
91	U1_XF.AU26 AU26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.AU38 AU38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AU39 AU39	GND GND	0V	GND	GND
91	U1_XF.AU40 AU40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AU41 AU41	GND GND	0V	GND	GND
86	U1_XF.AU42 AU42	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX_IO	VCCAUX_IO	1.8
100	U1_XF.AU43 AU43	GND GND	0V	GND	GND
87	U1_XF.AU44 AU44	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX	VCCAUX	1.8
100	U1_XF.AU45 AU45	NC NC		IO_L23P_T3U_N8_27	IO_L23P_T3U_N8_27
100	U1_XF.AU46 AU46	NC NC		IO_L23N_T3U_N9_27	IO_L23N_T3U_N9_27
100	U1_XF.AU47 AU47	GND GND	0V	GND	GND
100	U1_XF.AU48 AU48	NC NC		IO_L14P_T2L_N2_GC_27	IO_L14P_T2L_N2_GC_27
100	U1_XF.AU49 AU49	NC NC		IO_L14N_T2L_N3_GC_27	IO_L14N_T2L_N3_GC_27
100	U1_XF.AU50 AU50	NC NC		IO_L13N_T2L_N1_GC_QBC_27	IO_L13N_T2L_N1_GC_QBC_27
100	U1_XF.AU51 AU51	NC NC		IO_L12N_T1U_N11_GC_27	IO_L12N_T1U_N11_GC_27
100	U1_XF.AU52 AU52	NC NC		VCCO_27	VCCO_27	1.8
100	U1_XF.AU53 AU53	NC NC		IO_T1U_N12_27	IO_T1U_N12_27
100	U1_XF.AU54 AU54	NC NC		IO_L5P_T0U_N8_AD14P_27	IO_L5P_T0U_N8_AD14P_27
100	U1_XF.AU55 AU55	NC NC		IO_L5N_T0U_N9_AD14N_27	IO_L5N_T0U_N9_AD14N_27
100	U1_XF.AU56 AU56	NC NC		IO_L3N_T0L_N5_AD15N_27	IO_L3N_T0L_N5_AD15N_27
100	U1_XF.AU57 AU57	GND GND	0V	GND	GND
100	U1_XF.AU58 AU58	NC NC		IO_L1P_T0L_N0_DBC_28	IO_L1P_T0L_N0_DBC_28
100	U1_XF.AU59 AU59	NC NC		IO_L3P_T0L_N4_AD15P_28	IO_L3P_T0L_N4_AD15P_28
100	U1_XF.AU60 AU60	NC NC		IO_L3N_T0L_N5_AD15N_28	IO_L3N_T0L_N5_AD15N_28
100	U1_XF.AU61 AU61	NC NC		IO_L8N_T1L_N3_AD5N_28	IO_L8N_T1L_N3_AD5N_28
100	U1_XF.AU62 AU62	GND GND	0V	GND	GND
100	U1_XF.AU63 AU63	NC NC		IO_T1U_N12_28	IO_T1U_N12_28
100	U1_XF.AV1 AV1	GND GND	0V	GND	GND
100	U1_XF.AV2 AV2	GND GND	0V	GND	GND
95	U1_XF.AV3 AV3	PCIE0_RXN<0>_XF PCIE0_RXN<0>_XF		pcie0_rxn[0]	MGTYRXN3_226
95	U1_XF.AV4 AV4	PCIE0_RXP<0>_XF PCIE0_RXP<0>_XF		pcie0_rxp[0]	MGTYRXP3_226
100	U1_XF.AV5 AV5	GND GND	0V	GND	GND
100	U1_XF.AV6 AV6	GND GND	0V	GND	GND
100	U1_XF.AV7 AV7	GND GND	0V	GND	GND
92	U1_XF.AV8 AV8	AC_PCIE0_TXN<1>_XF AC_PCIE0_TXN<1>_XF		pcie0_txn[1]	MGTYTXN2_226
92	U1_XF.AV9 AV9	AC_PCIE0_TXP<1>_XF AC_PCIE0_TXP<1>_XF		pcie0_txp[1]	MGTYTXP2_226
100	U1_XF.AV10 AV10	GND GND	0V	GND	GND
100	U1_XF.AV11 AV11	GND GND	0V	GND	GND
92	U1_XF.AV12 AV12	AC_PCIE0_TXN<2>_XF AC_PCIE0_TXN<2>_XF		pcie0_txn[2]	MGTYTXN1_226
92	U1_XF.AV13 AV13	AC_PCIE0_TXP<2>_XF AC_PCIE0_TXP<2>_XF		pcie0_txp[2]	MGTYTXP1_226
100	U1_XF.AV14 AV14	GND GND	0V	GND	GND
18	U1_XF.AV15 AV15	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RLC	MGTAVCC_RLC	0.9
100	U1_XF.AV16 AV16	GND GND	0V	GND	GND
83	U1_XF.AV17 AV17	OCL2_3R3V_BP_TYPE_XF OCL2_3R3V_BP_TYPE_XF	3.3V	ocl_3r3v_bp_type[2]	IO_L11N_AD1N_88
-	U1_XF.AV18 AV18	NC NC		ocl_3r3v_extra_io[12]	IO_L11P_AD1P_88
83	U1_XF.AV19 AV19	OCL2_3R3V_CWAKE_F_XF OCL2_3R3V_CWAKE_F_XF	3.3V	ocl_3r3v_cwake_f[2]	IO_L10N_AD2N_88
100	U1_XF.AV20 AV20	GND GND	0V	GND	GND
-	U1_XF.AV21 AV21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCBRAM	VCCBRAM	0.85
100	U1_XF.AV22 AV22	GND GND	0V	GND	GND
91	U1_XF.AV23 AV23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AV24 AV24	GND GND	0V	GND	GND
91	U1_XF.AV25 AV25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AV26 AV26	GND GND	0V	GND	GND
91	U1_XF.AV27 AV27	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AV28 AV28	GND GND	0V	GND	GND
91	U1_XF.AV29 AV29	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AV30 AV30	GND GND	0V	GND	GND
91	U1_XF.AV31 AV31	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AV32 AV32	GND GND	0V	GND	GND
91	U1_XF.AV33 AV33	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AV34 AV34	GND GND	0V	GND	GND
91	U1_XF.AV35 AV35	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AV36 AV36	GND GND	0V	GND	GND
91	U1_XF.AV37 AV37	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AV38 AV38	GND GND	0V	GND	GND
91	U1_XF.AV39 AV39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AV40 AV40	GND GND	0V	GND	GND
91	U1_XF.AV41 AV41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AV42 AV42	GND GND	0V	GND	GND
86	U1_XF.AV43 AV43	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX_IO	VCCAUX_IO	1.8
100	U1_XF.AV44 AV44	GND GND	0V	GND	GND
100	U1_XF.AV45 AV45	GND GND	0V	GND	GND
100	U1_XF.AV46 AV46	NC NC		IO_L21P_T3L_N4_AD8P_27	IO_L21P_T3L_N4_AD8P_27
100	U1_XF.AV47 AV47	NC NC		IO_L21N_T3L_N5_AD8N_27	IO_L21N_T3L_N5_AD8N_27
100	U1_XF.AV48 AV48	NC NC		IO_L17P_T2U_N8_AD10P_27	IO_L17P_T2U_N8_AD10P_27
100	U1_XF.AV49 AV49	NC NC		IO_L17N_T2U_N9_AD10N_27	IO_L17N_T2U_N9_AD10N_27
100	U1_XF.AV50 AV50	GND GND	0V	GND	GND
100	U1_XF.AV51 AV51	NC NC		IO_L7P_T1L_N0_QBC_AD13P_27	IO_L7P_T1L_N0_QBC_AD13P_27
100	U1_XF.AV52 AV52	NC NC		IO_L7N_T1L_N1_QBC_AD13N_27	IO_L7N_T1L_N1_QBC_AD13N_27
100	U1_XF.AV53 AV53	NC NC		IO_L1P_T0L_N0_DBC_27	IO_L1P_T0L_N0_DBC_27
100	U1_XF.AV54 AV54	NC NC		IO_L1N_T0L_N1_DBC_27	IO_L1N_T0L_N1_DBC_27
100	U1_XF.AV55 AV55	NC NC		VCCO_27	VCCO_27	1.8
100	U1_XF.AV56 AV56	NC NC		IO_T0U_N12_VRP_27	IO_T0U_N12_VRP_27
100	U1_XF.AV57 AV57	NC NC		IO_L2P_T0L_N2_28	IO_L2P_T0L_N2_28
100	U1_XF.AV58 AV58	NC NC		IO_L2N_T0L_N3_28	IO_L2N_T0L_N3_28
100	U1_XF.AV59 AV59	NC NC		IO_L1N_T0L_N1_DBC_28	IO_L1N_T0L_N1_DBC_28
100	U1_XF.AV60 AV60	GND GND	0V	GND	GND
100	U1_XF.AV61 AV61	NC NC		IO_L7P_T1L_N0_QBC_AD13P_28	IO_L7P_T1L_N0_QBC_AD13P_28
100	U1_XF.AV62 AV62	NC NC		IO_L7N_T1L_N1_QBC_AD13N_28	IO_L7N_T1L_N1_QBC_AD13N_28
100	U1_XF.AV63 AV63	NC NC		IO_T3U_N12_25	IO_T3U_N12_25
95	U1_XF.AW1 AW1	PCIE0_RXN<1>_XF PCIE0_RXN<1>_XF		pcie0_rxn[1]	MGTYRXN2_226
95	U1_XF.AW2 AW2	PCIE0_RXP<1>_XF PCIE0_RXP<1>_XF		pcie0_rxp[1]	MGTYRXP2_226
100	U1_XF.AW3 AW3	GND GND	0V	GND	GND
100	U1_XF.AW4 AW4	GND GND	0V	GND	GND
95	U1_XF.AW5 AW5	PCIE0_RXN<2>_XF PCIE0_RXN<2>_XF		pcie0_rxn[2]	MGTYRXN1_226
95	U1_XF.AW6 AW6	PCIE0_RXP<2>_XF PCIE0_RXP<2>_XF		pcie0_rxp[2]	MGTYRXP1_226
100	U1_XF.AW7 AW7	GND GND	0V	GND	GND
100	U1_XF.AW8 AW8	GND GND	0V	GND	GND
23	U1_XF.AW9 AW9	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
92	U1_XF.AW10 AW10	AC_PCIE0_TXN<3>_XF AC_PCIE0_TXN<3>_XF		pcie0_txn[3]	MGTYTXN0_226
92	U1_XF.AW11 AW11	AC_PCIE0_TXP<3>_XF AC_PCIE0_TXP<3>_XF		pcie0_txp[3]	MGTYTXP0_226
100	U1_XF.AW12 AW12	GND GND	0V	GND	GND
23	U1_XF.AW13 AW13	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
100	U1_XF.AW14 AW14	NC NC		MGTREFCLK1N_227	MGTREFCLK1N_227
100	U1_XF.AW15 AW15	NC NC		MGTREFCLK1P_227	MGTREFCLK1P_227
100	U1_XF.AW16 AW16	GND GND	0V	GND	GND
85	U1_XF.AW17 AW17	OCL2_3R3V_CPRSNT_F_XF OCL2_3R3V_CPRSNT_F_XF	3.3V	ocl_3r3v_cprsnt_f[2]	IO_L9P_AD3P_88
-	U1_XF.AW18 AW18	PWR_FPGA_3R3V PWR_FPGA_3R3V	3.3	VCCO_88	VCCO_88	3.3
83	U1_XF.AW19 AW19	OCL3_3R3V_BP_TYPE_XF OCL3_3R3V_BP_TYPE_XF	3.3V	ocl_3r3v_bp_type[3]	IO_L7P_HDGC_AD5P_88
90	U1_XF.AW20 AW20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT_IO	VCCINT_IO	0.85
100	U1_XF.AW21 AW21	GND GND	0V	GND	GND
91	U1_XF.AW22 AW22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AW23 AW23	GND GND	0V	GND	GND
91	U1_XF.AW24 AW24	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AW25 AW25	GND GND	0V	GND	GND
91	U1_XF.AW26 AW26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AW27 AW27	GND GND	0V	GND	GND
91	U1_XF.AW28 AW28	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AW29 AW29	GND GND	0V	GND	GND
91	U1_XF.AW30 AW30	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AW31 AW31	GND GND	0V	GND	GND
91	U1_XF.AW32 AW32	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AW33 AW33	GND GND	0V	GND	GND
91	U1_XF.AW34 AW34	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AW35 AW35	GND GND	0V	GND	GND
91	U1_XF.AW36 AW36	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AW37 AW37	GND GND	0V	GND	GND
91	U1_XF.AW38 AW38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AW39 AW39	GND GND	0V	GND	GND
91	U1_XF.AW40 AW40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AW41 AW41	GND GND	0V	GND	GND
91	U1_XF.AW42 AW42	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AW43 AW43	GND GND	0V	GND	GND
87	U1_XF.AW44 AW44	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX	VCCAUX	1.8
100	U1_XF.AW45 AW45	NC NC		IO_T3U_N12_27	IO_T3U_N12_27
100	U1_XF.AW46 AW46	NC NC		IO_L19P_T3L_N0_DBC_AD9P_27	IO_L19P_T3L_N0_DBC_AD9P_27
100	U1_XF.AW47 AW47	NC NC		IO_L19N_T3L_N1_DBC_AD9N_27	IO_L19N_T3L_N1_DBC_AD9N_27
100	U1_XF.AW48 AW48	GND GND	0V	GND	GND
100	U1_XF.AW49 AW49	NC NC		IO_L8P_T1L_N2_AD5P_26	IO_L8P_T1L_N2_AD5P_26
100	U1_XF.AW50 AW50	NC NC		IO_L10P_T1U_N6_QBC_AD4P_26	IO_L10P_T1U_N6_QBC_AD4P_26
100	U1_XF.AW51 AW51	NC NC		IO_L7P_T1L_N0_QBC_AD13P_26	IO_L7P_T1L_N0_QBC_AD13P_26
100	U1_XF.AW52 AW52	NC NC		IO_L7N_T1L_N1_QBC_AD13N_26	IO_L7N_T1L_N1_QBC_AD13N_26
100	U1_XF.AW53 AW53	GND GND	0V	GND	GND
100	U1_XF.AW54 AW54	NC NC		IO_L18P_T2U_N10_AD2P_26	IO_L18P_T2U_N10_AD2P_26
100	U1_XF.AW55 AW55	NC NC		IO_L18N_T2U_N11_AD2N_26	IO_L18N_T2U_N11_AD2N_26
100	U1_XF.AW56 AW56	NC NC		IO_L24P_T3U_N10_26	IO_L24P_T3U_N10_26
100	U1_XF.AW57 AW57	NC NC		IO_L24N_T3U_N11_26	IO_L24N_T3U_N11_26
100	U1_XF.AW58 AW58	GND GND	0V	GND	GND
100	U1_XF.AW59 AW59	NC NC		IO_L24P_T3U_N10_25	IO_L24P_T3U_N10_25
100	U1_XF.AW60 AW60	NC NC		IO_L24N_T3U_N11_25	IO_L24N_T3U_N11_25
100	U1_XF.AW61 AW61	NC NC		IO_L22P_T3U_N6_DBC_AD0P_25	IO_L22P_T3U_N6_DBC_AD0P_25
100	U1_XF.AW62 AW62	NC NC		IO_L22N_T3U_N7_DBC_AD0N_25	IO_L22N_T3U_N7_DBC_AD0N_25
100	U1_XF.AW63 AW63	GND GND	0V	GND	GND
100	U1_XF.AY1 AY1	GND GND	0V	GND	GND
100	U1_XF.AY2 AY2	GND GND	0V	GND	GND
95	U1_XF.AY3 AY3	PCIE0_RXN<3>_XF PCIE0_RXN<3>_XF		pcie0_rxn[3]	MGTYRXN0_226
95	U1_XF.AY4 AY4	PCIE0_RXP<3>_XF PCIE0_RXP<3>_XF		pcie0_rxp[3]	MGTYRXP0_226
100	U1_XF.AY5 AY5	GND GND	0V	GND	GND
100	U1_XF.AY6 AY6	GND GND	0V	GND	GND
100	U1_XF.AY7 AY7	GND GND	0V	GND	GND
92	U1_XF.AY8 AY8	AC_PCIE0_TXN<4>_XF AC_PCIE0_TXN<4>_XF		pcie0_txn[4]	MGTYTXN3_225
92	U1_XF.AY9 AY9	AC_PCIE0_TXP<4>_XF AC_PCIE0_TXP<4>_XF		pcie0_txp[4]	MGTYTXP3_225
100	U1_XF.AY10 AY10	GND GND	0V	GND	GND
100	U1_XF.AY11 AY11	GND GND	0V	GND	GND
100	U1_XF.AY12 AY12	NC NC		MGTREFCLK0N_227	MGTREFCLK0N_227
100	U1_XF.AY13 AY13	NC NC		MGTREFCLK0P_227	MGTREFCLK0P_227
100	U1_XF.AY14 AY14	GND GND	0V	GND	GND
18	U1_XF.AY15 AY15	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RLC	MGTAVCC_RLC	0.9
100	U1_XF.AY16 AY16	GND GND	0V	GND	GND
84	U1_XF.AY17 AY17	OCL2_3R3V_PERST_F_XF OCL2_3R3V_PERST_F_XF	3.3V	ocl_3r3v_perst_f[2]	IO_L9N_AD3N_88
86	U1_XF.AY18 AY18	OCL2_3R3V_SCL_XF OCL2_3R3V_SCL_XF	3.3V	ocl_3r3v_scl[2]	IO_L8P_HDGC_AD4P_88
34	U1_XF.AY19 AY19	OCL3_3R3V_CKEN_F<1>_XF OCL3_3R3V_CKEN_F<1>_XF		ocl_3r3v_cken1_f[3]	IO_L7N_HDGC_AD5N_88
100	U1_XF.AY20 AY20	GND GND	0V	GND	GND
-	U1_XF.AY21 AY21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCBRAM	VCCBRAM	0.85
100	U1_XF.AY22 AY22	GND GND	0V	GND	GND
91	U1_XF.AY23 AY23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AY24 AY24	GND GND	0V	GND	GND
91	U1_XF.AY25 AY25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AY26 AY26	GND GND	0V	GND	GND
91	U1_XF.AY27 AY27	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AY28 AY28	GND GND	0V	GND	GND
91	U1_XF.AY29 AY29	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AY30 AY30	GND GND	0V	GND	GND
91	U1_XF.AY31 AY31	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AY32 AY32	GND GND	0V	GND	GND
91	U1_XF.AY33 AY33	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AY34 AY34	GND GND	0V	GND	GND
91	U1_XF.AY35 AY35	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AY36 AY36	GND GND	0V	GND	GND
91	U1_XF.AY37 AY37	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AY38 AY38	GND GND	0V	GND	GND
91	U1_XF.AY39 AY39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AY40 AY40	GND GND	0V	GND	GND
91	U1_XF.AY41 AY41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.AY42 AY42	GND GND	0V	GND	GND
86	U1_XF.AY43 AY43	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX_IO	VCCAUX_IO	1.8
100	U1_XF.AY44 AY44	GND GND	0V	GND	GND
100	U1_XF.AY45 AY45	NC NC		VREF_26	VREF_26
100	U1_XF.AY46 AY46	GND GND	0V	GND	GND
100	U1_XF.AY47 AY47	NC NC		IO_L4P_T0U_N6_DBC_AD7P_26	IO_L4P_T0U_N6_DBC_AD7P_26
100	U1_XF.AY48 AY48	NC NC		IO_L5P_T0U_N8_AD14P_26	IO_L5P_T0U_N8_AD14P_26
100	U1_XF.AY49 AY49	NC NC		IO_L8N_T1L_N3_AD5N_26	IO_L8N_T1L_N3_AD5N_26
100	U1_XF.AY50 AY50	NC NC		IO_L10N_T1U_N7_QBC_AD4N_26	IO_L10N_T1U_N7_QBC_AD4N_26
100	U1_XF.AY51 AY51	GND GND	0V	GND	GND
100	U1_XF.AY52 AY52	NC NC		IO_L14P_T2L_N2_GC_26	IO_L14P_T2L_N2_GC_26
100	U1_XF.AY53 AY53	NC NC		IO_L13P_T2L_N0_GC_QBC_26	IO_L13P_T2L_N0_GC_QBC_26
100	U1_XF.AY54 AY54	NC NC		IO_L16P_T2U_N6_QBC_AD3P_26	IO_L16P_T2U_N6_QBC_AD3P_26
100	U1_XF.AY55 AY55	NC NC		IO_L16N_T2U_N7_QBC_AD3N_26	IO_L16N_T2U_N7_QBC_AD3N_26
100	U1_XF.AY56 AY56	GND GND	0V	GND	GND
100	U1_XF.AY57 AY57	NC NC		IO_L23P_T3U_N8_26	IO_L23P_T3U_N8_26
100	U1_XF.AY58 AY58	NC NC		VREF_25	VREF_25
100	U1_XF.AY59 AY59	NC NC		IO_L23P_T3U_N8_25	IO_L23P_T3U_N8_25
100	U1_XF.AY60 AY60	NC NC		IO_L23N_T3U_N9_25	IO_L23N_T3U_N9_25
100	U1_XF.AY61 AY61	NC NC		VCCO_25	VCCO_25	1.8
100	U1_XF.AY62 AY62	NC NC		IO_L20P_T3L_N2_AD1P_25	IO_L20P_T3L_N2_AD1P_25
100	U1_XF.AY63 AY63	NC NC		IO_L20N_T3L_N3_AD1N_25	IO_L20N_T3L_N3_AD1N_25
100	U1_XF.B3 B3	GND GND	0V	GND	GND
100	U1_XF.B4 B4	GND GND	0V	GND	GND
100	U1_XF.B5 B5	GND GND	0V	GND	GND
100	U1_XF.B6 B6	GND GND	0V	GND	GND
100	U1_XF.B7 B7	GND GND	0V	GND	GND
92	U1_XF.B8 B8	AC_E1S0_PET_N<1>_XF AC_E1S0_PET_N<1>_XF		e1s0_pet_n[1]	MGTYTXN1_238
92	U1_XF.B9 B9	AC_E1S0_PET_P<1>_XF AC_E1S0_PET_P<1>_XF		e1s0_pet_p[1]	MGTYTXP1_238
100	U1_XF.B10 B10	GND GND	0V	GND	GND
100	U1_XF.B11 B11	GND GND	0V	GND	GND
100	U1_XF.B12 B12	NC NC		MGTREFCLK1N_238	MGTREFCLK1N_238
100	U1_XF.B13 B13	NC NC		MGTREFCLK1P_238	MGTREFCLK1P_238
100	U1_XF.B14 B14	GND GND	0V	GND	GND
16	U1_XF.B15 B15	C3_RDIMM_DQS_C<16>_XF C3_RDIMM_DQS_C<16>_XF		c3_ddr4_dqs_c[17]	IO_L19N_T3L_N1_DBC_AD9N_77
16	U1_XF.B16 B16	C3_RDIMM_DQS_T<16>_XF C3_RDIMM_DQS_T<16>_XF		c3_ddr4_dqs_t[17]	IO_L19P_T3L_N0_DBC_AD9P_77
100	U1_XF.B17 B17	GND GND	0V	GND	GND
16	U1_XF.B18 B18	C3_RDIMM_DQS_C<7>_XF C3_RDIMM_DQS_C<7>_XF		c3_ddr4_dqs_c[16]	IO_L22N_T3U_N7_DBC_AD0N_77
16	U1_XF.B19 B19	C3_RDIMM_DQS_T<7>_XF C3_RDIMM_DQS_T<7>_XF		c3_ddr4_dqs_t[16]	IO_L22P_T3U_N6_DBC_AD0P_77
35	U1_XF.B20 B20	C3_DDR4_DQ<56>_XF C3_DDR4_DQ<56>_XF		c3_ddr4_dq[64]	IO_L24P_T3U_N10_77
35	U1_XF.B21 B21	C3_DDR4_DQ<46>_XF C3_DDR4_DQ<46>_XF		c3_ddr4_dq[20]	IO_L9P_T1L_N4_AD12P_76
100	U1_XF.B22 B22	GND GND	0V	GND	GND
35	U1_XF.B23 B23	C3_DDR4_DQ<44>_XF C3_DDR4_DQ<44>_XF		c3_ddr4_dq[22]	IO_L8N_T1L_N3_AD5N_76
35	U1_XF.B24 B24	C3_DDR4_DQ<45>_XF C3_DDR4_DQ<45>_XF		c3_ddr4_dq[23]	IO_L8P_T1L_N2_AD5P_76
35	U1_XF.B25 B25	C3_DDR4_DQ<37>_XF C3_DDR4_DQ<37>_XF		c3_ddr4_dq[13]	IO_L2N_T0L_N3_76
35	U1_XF.B26 B26	C3_DDR4_DQ<36>_XF C3_DDR4_DQ<36>_XF		c3_ddr4_dq[12]	IO_L2P_T0L_N2_76
100	U1_XF.B27 B27	GND GND	0V	GND	GND
24	U1_XF.B28 B28	C3_RDIMM_DQS_C<13>_XF C3_RDIMM_DQS_C<13>_XF		c3_ddr4_dqs_c[3]	IO_L1N_T0L_N1_DBC_76
100	U1_XF.B29 B29	NC NC		IO_L22N_T3U_N7_DBC_AD0N_71	IO_L22N_T3U_N7_DBC_AD0N_71
100	U1_XF.B30 B30	NC NC		IO_L21P_T3L_N4_AD8P_71	IO_L21P_T3L_N4_AD8P_71
100	U1_XF.B31 B31	NC NC		IO_L19P_T3L_N0_DBC_AD9P_71	IO_L19P_T3L_N0_DBC_AD9P_71
100	U1_XF.B32 B32	GND GND	0V	GND	GND
100	U1_XF.B33 B33	NC NC		IO_L15P_T2L_N4_AD11P_71	IO_L15P_T2L_N4_AD11P_71
100	U1_XF.B34 B34	NC NC		IO_L10P_T1U_N6_QBC_AD4P_71	IO_L10P_T1U_N6_QBC_AD4P_71
100	U1_XF.B35 B35	NC NC		IO_L10N_T1U_N7_QBC_AD4N_71	IO_L10N_T1U_N7_QBC_AD4N_71
100	U1_XF.B36 B36	NC NC		IO_T1U_N12_71	IO_T1U_N12_71
100	U1_XF.B37 B37	GND GND	0V	GND	GND
100	U1_XF.B38 B38	NC NC		IO_L4P_T0U_N6_DBC_AD7P_71	IO_L4P_T0U_N6_DBC_AD7P_71
100	U1_XF.B39 B39	NC NC		IO_L4N_T0U_N7_DBC_AD7N_71	IO_L4N_T0U_N7_DBC_AD7N_71
100	U1_XF.B40 B40	NC NC		IO_L24P_T3U_N10_37	IO_L24P_T3U_N10_37
100	U1_XF.B41 B41	NC NC		IO_L24N_T3U_N11_37	IO_L24N_T3U_N11_37
100	U1_XF.B42 B42	GND GND	0V	GND	GND
100	U1_XF.B43 B43	NC NC		IO_L18N_T2U_N11_AD2N_37	IO_L18N_T2U_N11_AD2N_37
100	U1_XF.B44 B44	NC NC		IO_L15N_T2L_N5_AD11N_37	IO_L15N_T2L_N5_AD11N_37
100	U1_XF.B45 B45	NC NC		IO_L16P_T2U_N6_QBC_AD3P_37	IO_L16P_T2U_N6_QBC_AD3P_37
100	U1_XF.B46 B46	NC NC		IO_L14N_T2L_N3_GC_37	IO_L14N_T2L_N3_GC_37
100	U1_XF.B47 B47	GND GND	0V	GND	GND
100	U1_XF.B48 B48	NC NC		IO_L8P_T1L_N2_AD5P_37	IO_L8P_T1L_N2_AD5P_37
100	U1_XF.B49 B49	NC NC		IO_T1U_N12_37	IO_T1U_N12_37
100	U1_XF.B50 B50	NC NC		IO_L3P_T0L_N4_AD15P_37	IO_L3P_T0L_N4_AD15P_37
100	U1_XF.B51 B51	NC NC		IO_L1P_T0L_N0_DBC_37	IO_L1P_T0L_N0_DBC_37
100	U1_XF.B52 B52	GND GND	0V	GND	GND
35	U1_XF.B53 B53	C2_DDR4_DQ<42>_XF C2_DDR4_DQ<42>_XF		c2_ddr4_dq[48]	IO_L23P_T3U_N8_35
35	U1_XF.B54 B54	C2_DDR4_DQ<40>_XF C2_DDR4_DQ<40>_XF		c2_ddr4_dq[49]	IO_L23N_T3U_N9_35
35	U1_XF.B55 B55	C2_DDR4_DQ<39>_XF C2_DDR4_DQ<39>_XF		c2_ddr4_dq[71]	IO_L15P_T2L_N4_AD11P_35
35	U1_XF.B56 B56	C2_DDR4_DQ<38>_XF C2_DDR4_DQ<38>_XF		c2_ddr4_dq[70]	IO_L15N_T2L_N5_AD11N_35
100	U1_XF.B57 B57	GND GND	0V	GND	GND
35	U1_XF.B58 B58	C2_DDR4_DQ<71>_XF C2_DDR4_DQ<71>_XF		c2_ddr4_dq[63]	IO_L9P_T1L_N4_AD12P_35
16	U1_XF.B59 B59	C2_RDIMM_DQS_T<8>_XF C2_RDIMM_DQS_T<8>_XF		c2_ddr4_dqs_t[14]	IO_L10P_T1U_N6_QBC_AD4P_35
16	U1_XF.B60 B60	C2_RDIMM_DQS_C<8>_XF C2_RDIMM_DQS_C<8>_XF		c2_ddr4_dqs_c[14]	IO_L10N_T1U_N7_QBC_AD4N_35
100	U1_XF.B61 B61	GND GND	0V	GND	GND
95	U1_XF.BA1 BA1	PCIE0_RXN<4>_XF PCIE0_RXN<4>_XF		pcie0_rxn[4]	MGTYRXN3_225
95	U1_XF.BA2 BA2	PCIE0_RXP<4>_XF PCIE0_RXP<4>_XF		pcie0_rxp[4]	MGTYRXP3_225
100	U1_XF.BA3 BA3	GND GND	0V	GND	GND
100	U1_XF.BA4 BA4	GND GND	0V	GND	GND
95	U1_XF.BA5 BA5	PCIE0_RXN<5>_XF PCIE0_RXN<5>_XF		pcie0_rxn[5]	MGTYRXN2_225
95	U1_XF.BA6 BA6	PCIE0_RXP<5>_XF PCIE0_RXP<5>_XF		pcie0_rxp[5]	MGTYRXP2_225
100	U1_XF.BA7 BA7	GND GND	0V	GND	GND
100	U1_XF.BA8 BA8	GND GND	0V	GND	GND
23	U1_XF.BA9 BA9	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
92	U1_XF.BA10 BA10	AC_PCIE0_TXN<5>_XF AC_PCIE0_TXN<5>_XF		pcie0_txn[5]	MGTYTXN2_225
92	U1_XF.BA11 BA11	AC_PCIE0_TXP<5>_XF AC_PCIE0_TXP<5>_XF		pcie0_txp[5]	MGTYTXP2_225
100	U1_XF.BA12 BA12	GND GND	0V	GND	GND
18	U1_XF.BA13 BA13	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RLC	MGTAVCC_RLC	0.9
100	U1_XF.BA14 BA14	NC NC		MGTREFCLK1N_226	MGTREFCLK1N_226
100	U1_XF.BA15 BA15	NC NC		MGTREFCLK1P_226	MGTREFCLK1P_226
100	U1_XF.BA16 BA16	GND GND	0V	GND	GND
85	U1_XF.BA17 BA17	OCL2_3R3V_SDA_XF OCL2_3R3V_SDA_XF	3.3V	ocl_3r3v_sda[2]	IO_L8N_HDGC_AD4N_88
83	U1_XF.BA18 BA18	OCL3_3R3V_CWAKE_F_XF OCL3_3R3V_CWAKE_F_XF	3.3V	ocl_3r3v_cwake_f[3]	IO_L6P_HDGC_AD6P_88
100	U1_XF.BA19 BA19	GND GND	0V	GND	GND
-	U1_XF.BA20 BA20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCBRAM	VCCBRAM	0.85
100	U1_XF.BA21 BA21	GND GND	0V	GND	GND
91	U1_XF.BA22 BA22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BA23 BA23	GND GND	0V	GND	GND
91	U1_XF.BA24 BA24	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BA25 BA25	GND GND	0V	GND	GND
91	U1_XF.BA26 BA26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BA27 BA27	GND GND	0V	GND	GND
91	U1_XF.BA28 BA28	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BA29 BA29	GND GND	0V	GND	GND
91	U1_XF.BA30 BA30	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BA31 BA31	GND GND	0V	GND	GND
91	U1_XF.BA32 BA32	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BA33 BA33	GND GND	0V	GND	GND
91	U1_XF.BA34 BA34	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BA35 BA35	GND GND	0V	GND	GND
91	U1_XF.BA36 BA36	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BA37 BA37	GND GND	0V	GND	GND
91	U1_XF.BA38 BA38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BA39 BA39	GND GND	0V	GND	GND
91	U1_XF.BA40 BA40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BA41 BA41	GND GND	0V	GND	GND
91	U1_XF.BA42 BA42	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BA43 BA43	GND GND	0V	GND	GND
87	U1_XF.BA44 BA44	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCAUX	VCCAUX	1.8
100	U1_XF.BA45 BA45	NC NC		IO_L2P_T0L_N2_26	IO_L2P_T0L_N2_26
100	U1_XF.BA46 BA46	NC NC		IO_L6P_T0U_N10_AD6P_26	IO_L6P_T0U_N10_AD6P_26
100	U1_XF.BA47 BA47	NC NC		IO_L4N_T0U_N7_DBC_AD7N_26	IO_L4N_T0U_N7_DBC_AD7N_26
100	U1_XF.BA48 BA48	NC NC		IO_L5N_T0U_N9_AD14N_26	IO_L5N_T0U_N9_AD14N_26
100	U1_XF.BA49 BA49	NC NC		VCCO_26	VCCO_26	1.8
100	U1_XF.BA50 BA50	NC NC		IO_L12P_T1U_N10_GC_26	IO_L12P_T1U_N10_GC_26
100	U1_XF.BA51 BA51	NC NC		IO_L11P_T1U_N8_GC_26	IO_L11P_T1U_N8_GC_26
100	U1_XF.BA52 BA52	NC NC		IO_L14N_T2L_N3_GC_26	IO_L14N_T2L_N3_GC_26
100	U1_XF.BA53 BA53	NC NC		IO_L13N_T2L_N1_GC_QBC_26	IO_L13N_T2L_N1_GC_QBC_26
100	U1_XF.BA54 BA54	GND GND	0V	GND	GND
100	U1_XF.BA55 BA55	NC NC		IO_L20P_T3L_N2_AD1P_26	IO_L20P_T3L_N2_AD1P_26
100	U1_XF.BA56 BA56	NC NC		IO_L22P_T3U_N6_DBC_AD0P_26	IO_L22P_T3U_N6_DBC_AD0P_26
100	U1_XF.BA57 BA57	NC NC		IO_L23N_T3U_N9_26	IO_L23N_T3U_N9_26
100	U1_XF.BA58 BA58	NC NC		IO_T2U_N12_25	IO_T2U_N12_25
100	U1_XF.BA59 BA59	GND GND	0V	GND	GND
100	U1_XF.BA60 BA60	NC NC		IO_L21P_T3L_N4_AD8P_25	IO_L21P_T3L_N4_AD8P_25
100	U1_XF.BA61 BA61	NC NC		IO_L21N_T3L_N5_AD8N_25	IO_L21N_T3L_N5_AD8N_25
100	U1_XF.BA62 BA62	NC NC		IO_L19P_T3L_N0_DBC_AD9P_25	IO_L19P_T3L_N0_DBC_AD9P_25
100	U1_XF.BA63 BA63	NC NC		IO_L19N_T3L_N1_DBC_AD9N_25	IO_L19N_T3L_N1_DBC_AD9N_25
100	U1_XF.BB1 BB1	GND GND	0V	GND	GND
100	U1_XF.BB2 BB2	GND GND	0V	GND	GND
95	U1_XF.BB3 BB3	PCIE0_RXN<6>_XF PCIE0_RXN<6>_XF		pcie0_rxn[6]	MGTYRXN1_225
95	U1_XF.BB4 BB4	PCIE0_RXP<6>_XF PCIE0_RXP<6>_XF		pcie0_rxp[6]	MGTYRXP1_225
100	U1_XF.BB5 BB5	GND GND	0V	GND	GND
100	U1_XF.BB6 BB6	GND GND	0V	GND	GND
100	U1_XF.BB7 BB7	GND GND	0V	GND	GND
92	U1_XF.BB8 BB8	AC_PCIE0_TXN<6>_XF AC_PCIE0_TXN<6>_XF		pcie0_txn[6]	MGTYTXN1_225
92	U1_XF.BB9 BB9	AC_PCIE0_TXP<6>_XF AC_PCIE0_TXP<6>_XF		pcie0_txp[6]	MGTYTXP1_225
100	U1_XF.BB10 BB10	GND GND	0V	GND	GND
23	U1_XF.BB11 BB11	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
23	U1_XF.BB12 BB12	AC_PCIE0_REFN_XF AC_PCIE0_REFN_XF		pcie0_refclk_n	MGTREFCLK0N_226
23	U1_XF.BB13 BB13	AC_PCIE0_REFP_XF AC_PCIE0_REFP_XF		pcie0_refclk_p	MGTREFCLK0P_226
100	U1_XF.BB14 BB14	GND GND	0V	GND	GND
18	U1_XF.BB15 BB15	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RLC	MGTAVCC_RLC	0.9
100	U1_XF.BB16 BB16	GND GND	0V	GND	GND
-	U1_XF.BB17 BB17	PWR_FPGA_3R3V PWR_FPGA_3R3V	3.3	VCCO_88	VCCO_88	3.3
85	U1_XF.BB18 BB18	OCL3_3R3V_CPRSNT_F_XF OCL3_3R3V_CPRSNT_F_XF	3.3V	ocl_3r3v_cprsnt_f[3]	IO_L6N_HDGC_AD6N_88
84	U1_XF.BB19 BB19	OCL3_3R3V_PERST_F_XF OCL3_3R3V_PERST_F_XF	3.3V	ocl_3r3v_perst_f[3]	IO_L5P_HDGC_AD7P_88
100	U1_XF.BB20 BB20	GND GND	0V	GND	GND
91	U1_XF.BB21 BB21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BB22 BB22	GND GND	0V	GND	GND
91	U1_XF.BB23 BB23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BB24 BB24	GND GND	0V	GND	GND
91	U1_XF.BB25 BB25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BB26 BB26	GND GND	0V	GND	GND
91	U1_XF.BB27 BB27	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BB28 BB28	GND GND	0V	GND	GND
91	U1_XF.BB29 BB29	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BB30 BB30	GND GND	0V	GND	GND
91	U1_XF.BB31 BB31	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BB32 BB32	GND GND	0V	GND	GND
91	U1_XF.BB33 BB33	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BB34 BB34	GND GND	0V	GND	GND
91	U1_XF.BB35 BB35	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BB36 BB36	GND GND	0V	GND	GND
91	U1_XF.BB37 BB37	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BB38 BB38	GND GND	0V	GND	GND
91	U1_XF.BB39 BB39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BB40 BB40	GND GND	0V	GND	GND
91	U1_XF.BB41 BB41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BB42 BB42	GND GND	0V	GND	GND
91	U1_XF.BB43 BB43	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BB44 BB44	GND GND	0V	GND	GND
100	U1_XF.BB45 BB45	NC NC		IO_L2N_T0L_N3_26	IO_L2N_T0L_N3_26
100	U1_XF.BB46 BB46	NC NC		IO_L6N_T0U_N11_AD6N_26	IO_L6N_T0U_N11_AD6N_26
100	U1_XF.BB47 BB47	GND GND	0V	GND	GND
100	U1_XF.BB48 BB48	NC NC		IO_L3P_T0L_N4_AD15P_26	IO_L3P_T0L_N4_AD15P_26
100	U1_XF.BB49 BB49	NC NC		IO_T1U_N12_26	IO_T1U_N12_26
100	U1_XF.BB50 BB50	NC NC		IO_L12N_T1U_N11_GC_26	IO_L12N_T1U_N11_GC_26
100	U1_XF.BB51 BB51	NC NC		IO_L11N_T1U_N9_GC_26	IO_L11N_T1U_N9_GC_26
100	U1_XF.BB52 BB52	NC NC		VCCO_26	VCCO_26	1.8
100	U1_XF.BB53 BB53	NC NC		IO_L15P_T2L_N4_AD11P_26	IO_L15P_T2L_N4_AD11P_26
100	U1_XF.BB54 BB54	NC NC		IO_L17P_T2U_N8_AD10P_26	IO_L17P_T2U_N8_AD10P_26
100	U1_XF.BB55 BB55	NC NC		IO_L20N_T3L_N3_AD1N_26	IO_L20N_T3L_N3_AD1N_26
100	U1_XF.BB56 BB56	NC NC		IO_L22N_T3U_N7_DBC_AD0N_26	IO_L22N_T3U_N7_DBC_AD0N_26
100	U1_XF.BB57 BB57	GND GND	0V	GND	GND
100	U1_XF.BB58 BB58	NC NC		IO_L17P_T2U_N8_AD10P_25	IO_L17P_T2U_N8_AD10P_25
100	U1_XF.BB59 BB59	NC NC		IO_L17N_T2U_N9_AD10N_25	IO_L17N_T2U_N9_AD10N_25
100	U1_XF.BB60 BB60	NC NC		IO_L16P_T2U_N6_QBC_AD3P_25	IO_L16P_T2U_N6_QBC_AD3P_25
100	U1_XF.BB61 BB61	NC NC		IO_L16N_T2U_N7_QBC_AD3N_25	IO_L16N_T2U_N7_QBC_AD3N_25
100	U1_XF.BB62 BB62	GND GND	0V	GND	GND
100	U1_XF.BB63 BB63	NC NC		IO_L18P_T2U_N10_AD2P_25	IO_L18P_T2U_N10_AD2P_25
95	U1_XF.BC1 BC1	PCIE0_RXN<7>_XF PCIE0_RXN<7>_XF		pcie0_rxn[7]	MGTYRXN0_225
95	U1_XF.BC2 BC2	PCIE0_RXP<7>_XF PCIE0_RXP<7>_XF		pcie0_rxp[7]	MGTYRXP0_225
100	U1_XF.BC3 BC3	GND GND	0V	GND	GND
100	U1_XF.BC4 BC4	GND GND	0V	GND	GND
100	U1_XF.BC5 BC5	NC NC		MGTYRXN3_224	MGTYRXN3_224
100	U1_XF.BC6 BC6	NC NC		MGTYRXP3_224	MGTYRXP3_224
100	U1_XF.BC7 BC7	GND GND	0V	GND	GND
100	U1_XF.BC8 BC8	GND GND	0V	GND	GND
23	U1_XF.BC9 BC9	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
92	U1_XF.BC10 BC10	AC_PCIE0_TXN<7>_XF AC_PCIE0_TXN<7>_XF		pcie0_txn[7]	MGTYTXN0_225
92	U1_XF.BC11 BC11	AC_PCIE0_TXP<7>_XF AC_PCIE0_TXP<7>_XF		pcie0_txp[7]	MGTYTXP0_225
100	U1_XF.BC12 BC12	GND GND	0V	GND	GND
18	U1_XF.BC13 BC13	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RLC	MGTAVCC_RLC	0.9
100	U1_XF.BC14 BC14	NC NC		MGTREFCLK1N_225	MGTREFCLK1N_225
100	U1_XF.BC15 BC15	NC NC		MGTREFCLK1P_225	MGTREFCLK1P_225
100	U1_XF.BC16 BC16	GND GND	0V	GND	GND
62	U1_XF.BC17 BC17	PCIE0_CLKREQ_XF PCIE0_CLKREQ_XF		pcie0_clkreq_f	IO_L4N_AD8N_88
85	U1_XF.BC18 BC18	OCL3_3R3V_SDA_XF OCL3_3R3V_SDA_XF	3.3V	ocl_3r3v_sda[3]	IO_L4P_AD8P_88
86	U1_XF.BC19 BC19	OCL3_3R3V_SCL_XF OCL3_3R3V_SCL_XF	3.3V	ocl_3r3v_scl[3]	IO_L5N_HDGC_AD7N_88
91	U1_XF.BC20 BC20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC21 BC21	GND GND	0V	GND	GND
91	U1_XF.BC22 BC22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC23 BC23	GND GND	0V	GND	GND
91	U1_XF.BC24 BC24	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC25 BC25	GND GND	0V	GND	GND
91	U1_XF.BC26 BC26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC27 BC27	GND GND	0V	GND	GND
91	U1_XF.BC28 BC28	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC29 BC29	GND GND	0V	GND	GND
91	U1_XF.BC30 BC30	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC31 BC31	GND GND	0V	GND	GND
91	U1_XF.BC32 BC32	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC33 BC33	GND GND	0V	GND	GND
91	U1_XF.BC34 BC34	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC35 BC35	GND GND	0V	GND	GND
91	U1_XF.BC36 BC36	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC37 BC37	GND GND	0V	GND	GND
91	U1_XF.BC38 BC38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC39 BC39	GND GND	0V	GND	GND
91	U1_XF.BC40 BC40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC41 BC41	GND GND	0V	GND	GND
91	U1_XF.BC42 BC42	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC43 BC43	GND GND	0V	GND	GND
91	U1_XF.BC44 BC44	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BC45 BC45	GND GND	0V	GND	GND
100	U1_XF.BC46 BC46	NC NC		IO_L1P_T0L_N0_DBC_26	IO_L1P_T0L_N0_DBC_26
100	U1_XF.BC47 BC47	NC NC		IO_L1N_T0L_N1_DBC_26	IO_L1N_T0L_N1_DBC_26
100	U1_XF.BC48 BC48	NC NC		IO_L3N_T0L_N5_AD15N_26	IO_L3N_T0L_N5_AD15N_26
100	U1_XF.BC49 BC49	NC NC		IO_T0U_N12_VRP_26	IO_T0U_N12_VRP_26
100	U1_XF.BC50 BC50	GND GND	0V	GND	GND
100	U1_XF.BC51 BC51	NC NC		IO_L9P_T1L_N4_AD12P_26	IO_L9P_T1L_N4_AD12P_26
100	U1_XF.BC52 BC52	NC NC		IO_L9N_T1L_N5_AD12N_26	IO_L9N_T1L_N5_AD12N_26
100	U1_XF.BC53 BC53	NC NC		IO_L15N_T2L_N5_AD11N_26	IO_L15N_T2L_N5_AD11N_26
100	U1_XF.BC54 BC54	NC NC		IO_L17N_T2U_N9_AD10N_26	IO_L17N_T2U_N9_AD10N_26
100	U1_XF.BC55 BC55	NC NC		VCCO_26	VCCO_26	1.8
100	U1_XF.BC56 BC56	NC NC		IO_L19P_T3L_N0_DBC_AD9P_26	IO_L19P_T3L_N0_DBC_AD9P_26
100	U1_XF.BC57 BC57	NC NC		IO_L21P_T3L_N4_AD8P_26	IO_L21P_T3L_N4_AD8P_26
100	U1_XF.BC58 BC58	NC NC		IO_L15P_T2L_N4_AD11P_25	IO_L15P_T2L_N4_AD11P_25
100	U1_XF.BC59 BC59	NC NC		IO_L15N_T2L_N5_AD11N_25	IO_L15N_T2L_N5_AD11N_25
100	U1_XF.BC60 BC60	NC NC		VCCO_25	VCCO_25	1.8
100	U1_XF.BC61 BC61	NC NC		IO_L14P_T2L_N2_GC_25	IO_L14P_T2L_N2_GC_25
100	U1_XF.BC62 BC62	NC NC		IO_L14N_T2L_N3_GC_25	IO_L14N_T2L_N3_GC_25
100	U1_XF.BC63 BC63	NC NC		IO_L18N_T2U_N11_AD2N_25	IO_L18N_T2U_N11_AD2N_25
100	U1_XF.BD1 BD1	GND GND	0V	GND	GND
100	U1_XF.BD2 BD2	GND GND	0V	GND	GND
100	U1_XF.BD3 BD3	NC NC		MGTYRXN2_224	MGTYRXN2_224
100	U1_XF.BD4 BD4	NC NC		MGTYRXP2_224	MGTYRXP2_224
100	U1_XF.BD5 BD5	GND GND	0V	GND	GND
100	U1_XF.BD6 BD6	GND GND	0V	GND	GND
100	U1_XF.BD7 BD7	GND GND	0V	GND	GND
100	U1_XF.BD8 BD8	NC NC		MGTYTXN3_224	MGTYTXN3_224
100	U1_XF.BD9 BD9	NC NC		MGTYTXP3_224	MGTYTXP3_224
100	U1_XF.BD10 BD10	GND GND	0V	GND	GND
23	U1_XF.BD11 BD11	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
100	U1_XF.BD12 BD12	NC NC		MGTREFCLK0N_225	MGTREFCLK0N_225
100	U1_XF.BD13 BD13	NC NC		MGTREFCLK0P_225	MGTREFCLK0P_225
100	U1_XF.BD14 BD14	GND GND	0V	GND	GND
18	U1_XF.BD15 BD15	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RLC	MGTAVCC_RLC	0.9
100	U1_XF.BD16 BD16	GND GND	0V	GND	GND
95	U1_XF.BD17 BD17	PCIE0_WAKE_F_XF PCIE0_WAKE_F_XF		pcie0_wake_f	IO_L3P_AD9P_88
100	U1_XF.BD18 BD18	GND GND	0V	GND	GND
95	U1_XF.BD19 BD19	PCIE_X1_WAKE_F_XF PCIE_X1_WAKE_F_XF		pcie_x1_wake_f	IO_L1P_AD11P_88
100	U1_XF.BD20 BD20	GND GND	0V	GND	GND
91	U1_XF.BD21 BD21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BD22 BD22	GND GND	0V	GND	GND
91	U1_XF.BD23 BD23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BD24 BD24	GND GND	0V	GND	GND
91	U1_XF.BD25 BD25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BD26 BD26	GND GND	0V	GND	GND
91	U1_XF.BD27 BD27	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BD28 BD28	GND GND	0V	GND	GND
91	U1_XF.BD29 BD29	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BD30 BD30	GND GND	0V	GND	GND
91	U1_XF.BD31 BD31	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BD32 BD32	GND GND	0V	GND	GND
91	U1_XF.BD33 BD33	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BD34 BD34	GND GND	0V	GND	GND
91	U1_XF.BD35 BD35	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BD36 BD36	GND GND	0V	GND	GND
91	U1_XF.BD37 BD37	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BD38 BD38	GND GND	0V	GND	GND
91	U1_XF.BD39 BD39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BD40 BD40	GND GND	0V	GND	GND
91	U1_XF.BD41 BD41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BD42 BD42	GND GND	0V	GND	GND
91	U1_XF.BD43 BD43	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BD44 BD44	GND GND	0V	GND	GND
100	U1_XF.BD45 BD45	NC NC		VREF_24	VREF_24
100	U1_XF.BD46 BD46	NC NC		IO_L2P_T0L_N2_24	IO_L2P_T0L_N2_24
100	U1_XF.BD47 BD47	NC NC		IO_L2N_T0L_N3_24	IO_L2N_T0L_N3_24
100	U1_XF.BD48 BD48	GND GND	0V	GND	GND
100	U1_XF.BD49 BD49	NC NC		IO_L10P_T1U_N6_QBC_AD4P_24	IO_L10P_T1U_N6_QBC_AD4P_24
100	U1_XF.BD50 BD50	NC NC		IO_L7P_T1L_N0_QBC_AD13P_24	IO_L7P_T1L_N0_QBC_AD13P_24
100	U1_XF.BD51 BD51	NC NC		IO_L16P_T2U_N6_QBC_AD3P_24	IO_L16P_T2U_N6_QBC_AD3P_24
100	U1_XF.BD52 BD52	NC NC		IO_L16N_T2U_N7_QBC_AD3N_24	IO_L16N_T2U_N7_QBC_AD3N_24
100	U1_XF.BD53 BD53	GND GND	0V	GND	GND
100	U1_XF.BD54 BD54	NC NC		IO_T2U_N12_26	IO_T2U_N12_26
100	U1_XF.BD55 BD55	NC NC		IO_T3U_N12_26	IO_T3U_N12_26
100	U1_XF.BD56 BD56	NC NC		IO_L19N_T3L_N1_DBC_AD9N_26	IO_L19N_T3L_N1_DBC_AD9N_26
100	U1_XF.BD57 BD57	NC NC		IO_L21N_T3L_N5_AD8N_26	IO_L21N_T3L_N5_AD8N_26
100	U1_XF.BD58 BD58	GND GND	0V	GND	GND
100	U1_XF.BD59 BD59	NC NC		IO_L12P_T1U_N10_GC_25	IO_L12P_T1U_N10_GC_25
100	U1_XF.BD60 BD60	NC NC		IO_L12N_T1U_N11_GC_25	IO_L12N_T1U_N11_GC_25
100	U1_XF.BD61 BD61	NC NC		IO_L13P_T2L_N0_GC_QBC_25	IO_L13P_T2L_N0_GC_QBC_25
100	U1_XF.BD62 BD62	NC NC		IO_L13N_T2L_N1_GC_QBC_25	IO_L13N_T2L_N1_GC_QBC_25
100	U1_XF.BD63 BD63	GND GND	0V	GND	GND
100	U1_XF.BE1 BE1	NC NC		MGTYRXN1_224	MGTYRXN1_224
100	U1_XF.BE2 BE2	NC NC		MGTYRXP1_224	MGTYRXP1_224
100	U1_XF.BE3 BE3	GND GND	0V	GND	GND
100	U1_XF.BE4 BE4	GND GND	0V	GND	GND
100	U1_XF.BE5 BE5	GND GND	0V	GND	GND
100	U1_XF.BE6 BE6	NC NC		MGTYTXN2_224	MGTYTXN2_224
100	U1_XF.BE7 BE7	NC NC		MGTYTXP2_224	MGTYTXP2_224
100	U1_XF.BE8 BE8	GND GND	0V	GND	GND
23	U1_XF.BE9 BE9	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
100	U1_XF.BE10 BE10	NC NC		MGTYTXN1_224	MGTYTXN1_224
100	U1_XF.BE11 BE11	NC NC		MGTYTXP1_224	MGTYTXP1_224
100	U1_XF.BE12 BE12	GND GND	0V	GND	GND
18	U1_XF.BE13 BE13	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RLC	MGTAVCC_RLC	0.9
31	U1_XF.BE14 BE14	MGTRREF_LS_XF MGTRREF_LS_XF		MGTRREF_RLC	MGTRREF_RLC
23	U1_XF.BE15 BE15	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTTRCAL_RLC	MGTAVTTRCAL_RLC	1.2
100	U1_XF.BE16 BE16	GND GND	0V	GND	GND
62	U1_XF.BE17 BE17	PCIE1_CLKREQ_XF PCIE1_CLKREQ_XF		pcie1_clkreq_f	IO_L3N_AD9N_88
95	U1_XF.BE18 BE18	PCIE1_WAKE_F_XF PCIE1_WAKE_F_XF		pcie1_wake_f	IO_L2P_AD10P_88
100	U1_XF.BE19 BE19	PCIE_X1_RST_F PCIE_X1_RST_F		pcie_x1_rst_f	IO_L1N_AD11N_88
91	U1_XF.BE20 BE20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.BE21 BE21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.BE22 BE22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BE23 BE23	GND GND	0V	GND	GND
91	U1_XF.BE24 BE24	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BE25 BE25	GND GND	0V	GND	GND
91	U1_XF.BE26 BE26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BE27 BE27	GND GND	0V	GND	GND
91	U1_XF.BE28 BE28	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BE29 BE29	GND GND	0V	GND	GND
91	U1_XF.BE30 BE30	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BE31 BE31	GND GND	0V	GND	GND
91	U1_XF.BE32 BE32	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BE33 BE33	GND GND	0V	GND	GND
91	U1_XF.BE34 BE34	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BE35 BE35	GND GND	0V	GND	GND
91	U1_XF.BE36 BE36	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BE37 BE37	GND GND	0V	GND	GND
91	U1_XF.BE38 BE38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BE39 BE39	GND GND	0V	GND	GND
91	U1_XF.BE40 BE40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BE41 BE41	GND GND	0V	GND	GND
91	U1_XF.BE42 BE42	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.BE43 BE43	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.BE44 BE44	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BE45 BE45	NC NC		IO_L4P_T0U_N6_DBC_AD7P_24	IO_L4P_T0U_N6_DBC_AD7P_24
100	U1_XF.BE46 BE46	GND GND	0V	GND	GND
100	U1_XF.BE47 BE47	NC NC		IO_T0U_N12_VRP_24	IO_T0U_N12_VRP_24
100	U1_XF.BE48 BE48	NC NC		IO_L5P_T0U_N8_AD14P_24	IO_L5P_T0U_N8_AD14P_24
100	U1_XF.BE49 BE49	NC NC		IO_L10N_T1U_N7_QBC_AD4N_24	IO_L10N_T1U_N7_QBC_AD4N_24
100	U1_XF.BE50 BE50	NC NC		IO_L7N_T1L_N1_QBC_AD13N_24	IO_L7N_T1L_N1_QBC_AD13N_24
100	U1_XF.BE51 BE51	GND GND	0V	GND	GND
100	U1_XF.BE52 BE52	NC NC		IO_L14P_T2L_N2_GC_24	IO_L14P_T2L_N2_GC_24
100	U1_XF.BE53 BE53	NC NC		IO_L13P_T2L_N0_GC_QBC_24	IO_L13P_T2L_N0_GC_QBC_24
100	U1_XF.BE54 BE54	NC NC		IO_L24P_T3U_N10_24	IO_L24P_T3U_N10_24
100	U1_XF.BE55 BE55	NC NC		IO_L24N_T3U_N11_24	IO_L24N_T3U_N11_24
100	U1_XF.BE56 BE56	GND GND	0V	GND	GND
100	U1_XF.BE57 BE57	NC NC		IO_L23P_T3U_N8_24	IO_L23P_T3U_N8_24
100	U1_XF.BE58 BE58	NC NC		IO_L10P_T1U_N6_QBC_AD4P_25	IO_L10P_T1U_N6_QBC_AD4P_25
100	U1_XF.BE59 BE59	NC NC		IO_L11P_T1U_N8_GC_25	IO_L11P_T1U_N8_GC_25
100	U1_XF.BE60 BE60	NC NC		IO_L11N_T1U_N9_GC_25	IO_L11N_T1U_N9_GC_25
100	U1_XF.BE61 BE61	GND GND	0V	GND	GND
100	U1_XF.BE62 BE62	NC NC		IO_L8P_T1L_N2_AD5P_25	IO_L8P_T1L_N2_AD5P_25
100	U1_XF.BE63 BE63	NC NC		IO_L8N_T1L_N3_AD5N_25	IO_L8N_T1L_N3_AD5N_25
100	U1_XF.BF1 BF1	GND GND	0V	GND	GND
100	U1_XF.BF2 BF2	GND GND	0V	GND	GND
95	U1_XF.BF3 BF3	PCIE_X1_RXN_XF PCIE_X1_RXN_XF		pcie_x1_rxn	MGTYRXN0_224
95	U1_XF.BF4 BF4	PCIE_X1_RXP_XF PCIE_X1_RXP_XF		pcie_x1_rxp	MGTYRXP0_224
100	U1_XF.BF5 BF5	GND GND	0V	GND	GND
100	U1_XF.BF6 BF6	GND GND	0V	GND	GND
100	U1_XF.BF7 BF7	GND GND	0V	GND	GND
92	U1_XF.BF8 BF8	AC_PCIE_X1_TXN_XF AC_PCIE_X1_TXN_XF		pcie_x1_txn	MGTYTXN0_224
92	U1_XF.BF9 BF9	AC_PCIE_X1_TXP_XF AC_PCIE_X1_TXP_XF		pcie_x1_txp	MGTYTXP0_224
100	U1_XF.BF10 BF10	GND GND	0V	GND	GND
23	U1_XF.BF11 BF11	PWR_AVTT_RLC_XF PWR_AVTT_RLC_XF	1.2	MGTAVTT_RLC	MGTAVTT_RLC	1.2
100	U1_XF.BF12 BF12	NC NC		MGTREFCLK1N_224	MGTREFCLK1N_224
100	U1_XF.BF13 BF13	NC NC		MGTREFCLK1P_224	MGTREFCLK1P_224
100	U1_XF.BF14 BF14	GND GND	0V	GND	GND
18	U1_XF.BF15 BF15	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RLC	MGTAVCC_RLC	0.9
100	U1_XF.BF16 BF16	GND GND	0V	GND	GND
69	U1_XF.BF17 BF17	PCIE_X1_CLKREQ_XF PCIE_X1_CLKREQ_XF		pcie_x1_clkreq_f	IO_L2N_AD10N_88
-	U1_XF.BF18 BF18	NC NC		ocl_3r3v_extra_io[2]	IO_L11P_AD1P_83
100	U1_XF.BF19 BF19	GND GND	0V	GND	GND
100	U1_XF.BF20 BF20	GND GND	0V	GND	GND
91	U1_XF.BF21 BF21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BF22 BF22	GND GND	0V	GND	GND
91	U1_XF.BF23 BF23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BF24 BF24	GND GND	0V	GND	GND
91	U1_XF.BF25 BF25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BF26 BF26	GND GND	0V	GND	GND
91	U1_XF.BF27 BF27	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BF28 BF28	GND GND	0V	GND	GND
91	U1_XF.BF29 BF29	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BF30 BF30	GND GND	0V	GND	GND
91	U1_XF.BF31 BF31	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BF32 BF32	GND GND	0V	GND	GND
91	U1_XF.BF33 BF33	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BF34 BF34	GND GND	0V	GND	GND
91	U1_XF.BF35 BF35	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BF36 BF36	GND GND	0V	GND	GND
91	U1_XF.BF37 BF37	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BF38 BF38	GND GND	0V	GND	GND
91	U1_XF.BF39 BF39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BF40 BF40	GND GND	0V	GND	GND
91	U1_XF.BF41 BF41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BF42 BF42	GND GND	0V	GND	GND
91	U1_XF.BF43 BF43	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.BF44 BF44	GND GND	0V	GND	GND
100	U1_XF.BF45 BF45	NC NC		IO_L4N_T0U_N7_DBC_AD7N_24	IO_L4N_T0U_N7_DBC_AD7N_24
100	U1_XF.BF46 BF46	NC NC		IO_L6P_T0U_N10_AD6P_24	IO_L6P_T0U_N10_AD6P_24
100	U1_XF.BF47 BF47	NC NC		IO_L6N_T0U_N11_AD6N_24	IO_L6N_T0U_N11_AD6N_24
100	U1_XF.BF48 BF48	NC NC		IO_L5N_T0U_N9_AD14N_24	IO_L5N_T0U_N9_AD14N_24
100	U1_XF.BF49 BF49	NC NC		VCCO_24	VCCO_24	1.8
100	U1_XF.BF50 BF50	NC NC		IO_L12P_T1U_N10_GC_24	IO_L12P_T1U_N10_GC_24
100	U1_XF.BF51 BF51	NC NC		IO_L11P_T1U_N8_GC_24	IO_L11P_T1U_N8_GC_24
100	U1_XF.BF52 BF52	NC NC		IO_L14N_T2L_N3_GC_24	IO_L14N_T2L_N3_GC_24
100	U1_XF.BF53 BF53	NC NC		IO_L13N_T2L_N1_GC_QBC_24	IO_L13N_T2L_N1_GC_QBC_24
100	U1_XF.BF54 BF54	GND GND	0V	GND	GND
100	U1_XF.BF55 BF55	NC NC		IO_L19P_T3L_N0_DBC_AD9P_24	IO_L19P_T3L_N0_DBC_AD9P_24
100	U1_XF.BF56 BF56	NC NC		IO_L19N_T3L_N1_DBC_AD9N_24	IO_L19N_T3L_N1_DBC_AD9N_24
100	U1_XF.BF57 BF57	NC NC		IO_L23N_T3U_N9_24	IO_L23N_T3U_N9_24
100	U1_XF.BF58 BF58	NC NC		IO_L10N_T1U_N7_QBC_AD4N_25	IO_L10N_T1U_N7_QBC_AD4N_25
100	U1_XF.BF59 BF59	GND GND	0V	GND	GND
100	U1_XF.BF60 BF60	NC NC		IO_T1U_N12_25	IO_T1U_N12_25
100	U1_XF.BF61 BF61	NC NC		IO_L6P_T0U_N10_AD6P_25	IO_L6P_T0U_N10_AD6P_25
100	U1_XF.BF62 BF62	NC NC		IO_L9P_T1L_N4_AD12P_25	IO_L9P_T1L_N4_AD12P_25
100	U1_XF.BF63 BF63	NC NC		IO_L9N_T1L_N5_AD12N_25	IO_L9N_T1L_N5_AD12N_25
95	U1_XF.BG1 BG1	OCL3_PER_N<3>_XF OCL3_PER_N<3>_XF		ocl3_per_n[3]	MGTYRXN3_223
95	U1_XF.BG2 BG2	OCL3_PER_P<3>_XF OCL3_PER_P<3>_XF		ocl3_per_p[3]	MGTYRXP3_223
100	U1_XF.BG3 BG3	GND GND	0V	GND	GND
100	U1_XF.BG4 BG4	GND GND	0V	GND	GND
100	U1_XF.BG5 BG5	GND GND	0V	GND	GND
92	U1_XF.BG6 BG6	AC_OCL3_PET_N<3>_XF AC_OCL3_PET_N<3>_XF		ocl3_pet_n[3]	MGTYTXN3_223
92	U1_XF.BG7 BG7	AC_OCL3_PET_P<3>_XF AC_OCL3_PET_P<3>_XF		ocl3_pet_p[3]	MGTYTXP3_223
100	U1_XF.BG8 BG8	GND GND	0V	GND	GND
23	U1_XF.BG9 BG9	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
92	U1_XF.BG10 BG10	AC_OCL3_PET_N<2>_XF AC_OCL3_PET_N<2>_XF		ocl3_pet_n[2]	MGTYTXN2_223
92	U1_XF.BG11 BG11	AC_OCL3_PET_P<2>_XF AC_OCL3_PET_P<2>_XF		ocl3_pet_p[2]	MGTYTXP2_223
100	U1_XF.BG12 BG12	GND GND	0V	GND	GND
18	U1_XF.BG13 BG13	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RS	MGTAVCC_RS	0.9
36	U1_XF.BG14 BG14	AC_PCIE_X1_REFN_XF AC_PCIE_X1_REFN_XF		pcie_x1_refclk_n	MGTREFCLK0N_224
36	U1_XF.BG15 BG15	AC_PCIE_X1_REFP_XF AC_PCIE_X1_REFP_XF		pcie_x1_refclk_p	MGTREFCLK0P_224
100	U1_XF.BG16 BG16	GND GND	0V	GND	GND
-	U1_XF.BG17 BG17	PWR_FPGA_3R3V PWR_FPGA_3R3V	3.3	VCCO_83	VCCO_83	3.3
-	U1_XF.BG18 BG18	NC NC		ocl_3r3v_extra_io[3]	IO_L11N_AD1N_83
-	U1_XF.BG19 BG19	NC NC		ocl_3r3v_extra_io[4]	IO_L10P_AD2P_83
-	U1_XF.BG20 BG20	NC NC		ocl_3r3v_extra_io[1]	IO_L12N_AD0N_83
-	U1_XF.BG21 BG21	NC NC		ocl_3r3v_extra_io[0]	IO_L12P_AD0P_83
100	U1_XF.BG22 BG22	GND GND	0V	GND	GND
16	U1_XF.BG23 BG23	C0_RDIMM_DQS_T<6>_XF C0_RDIMM_DQS_T<6>_XF		c0_ddr4_dqs_t[8]	IO_L16P_T2U_N6_QBC_AD3P_61
35	U1_XF.BG24 BG24	C0_DDR4_DQ<49>_XF C0_DDR4_DQ<49>_XF		c0_ddr4_dq[35]	IO_L18P_T2U_N10_AD2P_61
35	U1_XF.BG25 BG25	C0_DDR4_DQ<62>_XF C0_DDR4_DQ<62>_XF		c0_ddr4_dq[68]	IO_L21N_T3L_N5_AD8N_61
35	U1_XF.BG26 BG26	C0_DDR4_DQ<63>_XF C0_DDR4_DQ<63>_XF		c0_ddr4_dq[69]	IO_L21P_T3L_N4_AD8P_61
100	U1_XF.BG27 BG27	GND GND	0V	GND	GND
35	U1_XF.BG28 BG28	C0_DDR4_DQ<56>_XF C0_DDR4_DQ<56>_XF		c0_ddr4_dq[64]	IO_L23N_T3U_N9_61
35	U1_XF.BG29 BG29	C0_DDR4_DQ<58>_XF C0_DDR4_DQ<58>_XF		c0_ddr4_dq[66]	IO_L23P_T3U_N8_61
-	U1_XF.BG30 BG30	UNNAMED_22_RESISTOR_I45_B_XF UNNAMED_22_RESISTOR_I45_B_XF ->R60_XF->GND		VREF_65	VREF_65
100	U1_XF.BG31 BG31	NC NC		IO_L19P_T3L_N0_DBC_AD9P_D10_65	IO_L19P_T3L_N0_DBC_AD9P_D10_65
100	U1_XF.BG32 BG32	GND GND	0V	GND	GND
100	U1_XF.BG33 BG33	NC NC		IO_L22P_T3U_N6_DBC_AD0P_D04_65	IO_L22P_T3U_N6_DBC_AD0P_D04_65
100	U1_XF.BG34 BG34	PCIE1_RST_F UNNAMED_11_RESISTOR_I773_B_XF ->R156_XF->PCIE1_RST_F ->R158_XF->GND		pcie1_rst_f	IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65
100	U1_XF.BG35 BG35	NC NC		IO_L23P_T3U_N8_I2C_SCLK_65	IO_L23P_T3U_N8_I2C_SCLK_65
100	U1_XF.BG36 BG36	NC NC		VREF_67	VREF_67
100	U1_XF.BG37 BG37	GND GND	0V	GND	GND
100	U1_XF.BG38 BG38	NC NC		IO_L22P_T3U_N6_DBC_AD0P_67	IO_L22P_T3U_N6_DBC_AD0P_67
100	U1_XF.BG39 BG39	NC NC		IO_L23P_T3U_N8_67	IO_L23P_T3U_N8_67
100	U1_XF.BG40 BG40	NC NC		IO_L21P_T3L_N4_AD8P_67	IO_L21P_T3L_N4_AD8P_67
100	U1_XF.BG41 BG41	NC NC		IO_L21N_T3L_N5_AD8N_67	IO_L21N_T3L_N5_AD8N_67
100	U1_XF.BG42 BG42	GND GND	0V	GND	GND
100	U1_XF.BG43 BG43	NC NC		IO_L19P_T3L_N0_DBC_AD9P_19	IO_L19P_T3L_N0_DBC_AD9P_19
100	U1_XF.BG44 BG44	NC NC		IO_L19N_T3L_N1_DBC_AD9N_19	IO_L19N_T3L_N1_DBC_AD9N_19
100	U1_XF.BG45 BG45	NC NC		IO_L1P_T0L_N0_DBC_24	IO_L1P_T0L_N0_DBC_24
100	U1_XF.BG46 BG46	NC NC		IO_L1N_T0L_N1_DBC_24	IO_L1N_T0L_N1_DBC_24
100	U1_XF.BG47 BG47	GND GND	0V	GND	GND
100	U1_XF.BG48 BG48	NC NC		IO_L3P_T0L_N4_AD15P_24	IO_L3P_T0L_N4_AD15P_24
100	U1_XF.BG49 BG49	NC NC		IO_L3N_T0L_N5_AD15N_24	IO_L3N_T0L_N5_AD15N_24
100	U1_XF.BG50 BG50	NC NC		IO_L12N_T1U_N11_GC_24	IO_L12N_T1U_N11_GC_24
100	U1_XF.BG51 BG51	NC NC		IO_L11N_T1U_N9_GC_24	IO_L11N_T1U_N9_GC_24
100	U1_XF.BG52 BG52	NC NC		VCCO_24	VCCO_24	1.8
100	U1_XF.BG53 BG53	NC NC		IO_L18P_T2U_N10_AD2P_24	IO_L18P_T2U_N10_AD2P_24
100	U1_XF.BG54 BG54	NC NC		IO_L15P_T2L_N4_AD11P_24	IO_L15P_T2L_N4_AD11P_24
100	U1_XF.BG55 BG55	NC NC		IO_L20P_T3L_N2_AD1P_24	IO_L20P_T3L_N2_AD1P_24
100	U1_XF.BG56 BG56	NC NC		IO_L20N_T3L_N3_AD1N_24	IO_L20N_T3L_N3_AD1N_24
100	U1_XF.BG57 BG57	GND GND	0V	GND	GND
100	U1_XF.BG58 BG58	NC NC		IO_T0U_N12_VRP_25	IO_T0U_N12_VRP_25
100	U1_XF.BG59 BG59	NC NC		IO_L7P_T1L_N0_QBC_AD13P_25	IO_L7P_T1L_N0_QBC_AD13P_25
100	U1_XF.BG60 BG60	NC NC		IO_L7N_T1L_N1_QBC_AD13N_25	IO_L7N_T1L_N1_QBC_AD13N_25
100	U1_XF.BG61 BG61	NC NC		IO_L6N_T0U_N11_AD6N_25	IO_L6N_T0U_N11_AD6N_25
100	U1_XF.BG62 BG62	GND GND	0V	GND	GND
100	U1_XF.BG63 BG63	NC NC		IO_L4P_T0U_N6_DBC_AD7P_25	IO_L4P_T0U_N6_DBC_AD7P_25
100	U1_XF.BH1 BH1	GND GND	0V	GND	GND
100	U1_XF.BH2 BH2	GND GND	0V	GND	GND
95	U1_XF.BH3 BH3	OCL3_PER_N<2>_XF OCL3_PER_N<2>_XF		ocl3_per_n[2]	MGTYRXN2_223
95	U1_XF.BH4 BH4	OCL3_PER_P<2>_XF OCL3_PER_P<2>_XF		ocl3_per_p[2]	MGTYRXP2_223
100	U1_XF.BH5 BH5	GND GND	0V	GND	GND
100	U1_XF.BH6 BH6	GND GND	0V	GND	GND
100	U1_XF.BH7 BH7	GND GND	0V	GND	GND
92	U1_XF.BH8 BH8	AC_OCL3_PET_N<1>_XF AC_OCL3_PET_N<1>_XF		ocl3_pet_n[1]	MGTYTXN1_223
92	U1_XF.BH9 BH9	AC_OCL3_PET_P<1>_XF AC_OCL3_PET_P<1>_XF		ocl3_pet_p[1]	MGTYTXP1_223
100	U1_XF.BH10 BH10	GND GND	0V	GND	GND
23	U1_XF.BH11 BH11	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
100	U1_XF.BH12 BH12	NC NC		MGTREFCLK1N_223	MGTREFCLK1N_223
100	U1_XF.BH13 BH13	NC NC		MGTREFCLK1P_223	MGTREFCLK1P_223
100	U1_XF.BH14 BH14	GND GND	0V	GND	GND
80	U1_XF.BH15 BH15	PWR_RS_RLC_MGTVCCAUX_XF PWR_RS_RLC_MGTVCCAUX_XF	1.8	MGTVCCAUX_RS	MGTVCCAUX_RS	1.8
100	U1_XF.BH16 BH16	GND GND	0V	GND	GND
-	U1_XF.BH17 BH17	NC NC		ocl_3r3v_extra_io[7]	IO_L9N_AD3N_83
-	U1_XF.BH18 BH18	NC NC		ocl_3r3v_extra_io[6]	IO_L9P_AD3P_83
-	U1_XF.BH19 BH19	NC NC		ocl_3r3v_extra_io[5]	IO_L10N_AD2N_83
100	U1_XF.BH20 BH20	GND GND	0V	GND	GND
35	U1_XF.BH21 BH21	C0_DDR4_DQ<48>_XF C0_DDR4_DQ<48>_XF		c0_ddr4_dq[32]	IO_L17N_T2U_N9_AD10N_61
35	U1_XF.BH22 BH22	C0_DDR4_DQ<50>_XF C0_DDR4_DQ<50>_XF		c0_ddr4_dq[34]	IO_L17P_T2U_N8_AD10P_61
16	U1_XF.BH23 BH23	C0_RDIMM_DQS_C<6>_XF C0_RDIMM_DQS_C<6>_XF		c0_ddr4_dqs_c[8]	IO_L16N_T2U_N7_QBC_AD3N_61
35	U1_XF.BH24 BH24	C0_DDR4_DQ<51>_XF C0_DDR4_DQ<51>_XF		c0_ddr4_dq[33]	IO_L18N_T2U_N11_AD2N_61
100	U1_XF.BH25 BH25	GND GND	0V	GND	GND
35	U1_XF.BH26 BH26	C0_DDR4_DQ<57>_XF C0_DDR4_DQ<57>_XF		c0_ddr4_dq[65]	IO_L24N_T3U_N11_61
35	U1_XF.BH27 BH27	C0_DDR4_DQ<59>_XF C0_DDR4_DQ<59>_XF		c0_ddr4_dq[67]	IO_L24P_T3U_N10_61
16	U1_XF.BH28 BH28	C0_RDIMM_DQS_C<16>_XF C0_RDIMM_DQS_C<16>_XF		c0_ddr4_dqs_c[17]	IO_L19N_T3L_N1_DBC_AD9N_61
16	U1_XF.BH29 BH29	C0_RDIMM_DQS_T<16>_XF C0_RDIMM_DQS_T<16>_XF		c0_ddr4_dqs_t[17]	IO_L19P_T3L_N0_DBC_AD9P_61
100	U1_XF.BH30 BH30	GND GND	0V	GND	GND
100	U1_XF.BH31 BH31	NC NC		IO_L19N_T3L_N1_DBC_AD9N_D11_65	IO_L19N_T3L_N1_DBC_AD9N_D11_65
100	U1_XF.BH32 BH32	NC NC		IO_L21P_T3L_N4_AD8P_D06_65	IO_L21P_T3L_N4_AD8P_D06_65
100	U1_XF.BH33 BH33	NC NC		IO_L22N_T3U_N7_DBC_AD0N_D05_65	IO_L22N_T3U_N7_DBC_AD0N_D05_65
100	U1_XF.BH34 BH34	NC NC		IO_L24P_T3U_N10_EMCCLK_65	IO_L24P_T3U_N10_EMCCLK_65
100	U1_XF.BH35 BH35	GND GND	0V	GND	GND
100	U1_XF.BH36 BH36	NC NC		IO_L19P_T3L_N0_DBC_AD9P_67	IO_L19P_T3L_N0_DBC_AD9P_67
100	U1_XF.BH37 BH37	NC NC		IO_L19N_T3L_N1_DBC_AD9N_67	IO_L19N_T3L_N1_DBC_AD9N_67
100	U1_XF.BH38 BH38	NC NC		IO_L22N_T3U_N7_DBC_AD0N_67	IO_L22N_T3U_N7_DBC_AD0N_67
100	U1_XF.BH39 BH39	NC NC		IO_L23N_T3U_N9_67	IO_L23N_T3U_N9_67
100	U1_XF.BH40 BH40	GND GND	0V	GND	GND
100	U1_XF.BH41 BH41	NC NC		IO_L24P_T3U_N10_19	IO_L24P_T3U_N10_19
100	U1_XF.BH42 BH42	NC NC		IO_L22P_T3U_N6_DBC_AD0P_19	IO_L22P_T3U_N6_DBC_AD0P_19
100	U1_XF.BH43 BH43	NC NC		IO_L21P_T3L_N4_AD8P_19	IO_L21P_T3L_N4_AD8P_19
100	U1_XF.BH44 BH44	NC NC		IO_L21N_T3L_N5_AD8N_19	IO_L21N_T3L_N5_AD8N_19
100	U1_XF.BH45 BH45	GND GND	0V	GND	GND
100	U1_XF.BH46 BH46	NC NC		IO_L15P_T2L_N4_AD11P_19	IO_L15P_T2L_N4_AD11P_19
100	U1_XF.BH47 BH47	NC NC		IO_L15N_T2L_N5_AD11N_19	IO_L15N_T2L_N5_AD11N_19
100	U1_XF.BH48 BH48	NC NC		IO_T2U_N12_19	IO_T2U_N12_19
100	U1_XF.BH49 BH49	NC NC		IO_L8P_T1L_N2_AD5P_24	IO_L8P_T1L_N2_AD5P_24
100	U1_XF.BH50 BH50	GND GND	0V	GND	GND
100	U1_XF.BH51 BH51	NC NC		IO_L9P_T1L_N4_AD12P_24	IO_L9P_T1L_N4_AD12P_24
100	U1_XF.BH52 BH52	NC NC		IO_L17P_T2U_N8_AD10P_24	IO_L17P_T2U_N8_AD10P_24
100	U1_XF.BH53 BH53	NC NC		IO_L18N_T2U_N11_AD2N_24	IO_L18N_T2U_N11_AD2N_24
100	U1_XF.BH54 BH54	NC NC		IO_L15N_T2L_N5_AD11N_24	IO_L15N_T2L_N5_AD11N_24
100	U1_XF.BH55 BH55	NC NC		VCCO_24	VCCO_24	1.8
100	U1_XF.BH56 BH56	NC NC		IO_L22P_T3U_N6_DBC_AD0P_24	IO_L22P_T3U_N6_DBC_AD0P_24
100	U1_XF.BH57 BH57	NC NC		IO_L21P_T3L_N4_AD8P_24	IO_L21P_T3L_N4_AD8P_24
100	U1_XF.BH58 BH58	NC NC		IO_L1P_T0L_N0_DBC_25	IO_L1P_T0L_N0_DBC_25
100	U1_XF.BH59 BH59	NC NC		IO_L1N_T0L_N1_DBC_25	IO_L1N_T0L_N1_DBC_25
100	U1_XF.BH60 BH60	NC NC		VCCO_25	VCCO_25	1.8
100	U1_XF.BH61 BH61	NC NC		IO_L2P_T0L_N2_25	IO_L2P_T0L_N2_25
100	U1_XF.BH62 BH62	NC NC		IO_L2N_T0L_N3_25	IO_L2N_T0L_N3_25
100	U1_XF.BH63 BH63	NC NC		IO_L4N_T0U_N7_DBC_AD7N_25	IO_L4N_T0U_N7_DBC_AD7N_25
95	U1_XF.BJ1 BJ1	OCL3_PER_N<1>_XF OCL3_PER_N<1>_XF		ocl3_per_n[1]	MGTYRXN1_223
95	U1_XF.BJ2 BJ2	OCL3_PER_P<1>_XF OCL3_PER_P<1>_XF		ocl3_per_p[1]	MGTYRXP1_223
100	U1_XF.BJ3 BJ3	GND GND	0V	GND	GND
100	U1_XF.BJ4 BJ4	GND GND	0V	GND	GND
95	U1_XF.BJ5 BJ5	OCL3_PER_N<0>_XF OCL3_PER_N<0>_XF		ocl3_per_n[0]	MGTYRXN0_223
95	U1_XF.BJ6 BJ6	OCL3_PER_P<0>_XF OCL3_PER_P<0>_XF		ocl3_per_p[0]	MGTYRXP0_223
100	U1_XF.BJ7 BJ7	GND GND	0V	GND	GND
100	U1_XF.BJ8 BJ8	GND GND	0V	GND	GND
23	U1_XF.BJ9 BJ9	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
92	U1_XF.BJ10 BJ10	AC_OCL3_PET_N<0>_XF AC_OCL3_PET_N<0>_XF		ocl3_pet_n[0]	MGTYTXN0_223
92	U1_XF.BJ11 BJ11	AC_OCL3_PET_P<0>_XF AC_OCL3_PET_P<0>_XF		ocl3_pet_p[0]	MGTYTXP0_223
100	U1_XF.BJ12 BJ12	GND GND	0V	GND	GND
18	U1_XF.BJ13 BJ13	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RS	MGTAVCC_RS	0.9
85	U1_XF.BJ14 BJ14	OCL3_FPGA_REFCLK_N_XF OCL3_FPGA_REFCLK_N_XF		ocl3_refclk_n	MGTREFCLK0N_223
85	U1_XF.BJ15 BJ15	OCL3_FPGA_REFCLK_P_XF OCL3_FPGA_REFCLK_P_XF		ocl3_refclk_p	MGTREFCLK0P_223
100	U1_XF.BJ16 BJ16	GND GND	0V	GND	GND
-	U1_XF.BJ17 BJ17	NC NC		ocl_3r3v_extra_io[8]	IO_L8P_HDGC_AD4P_83
100	U1_XF.BJ18 BJ18	GND GND	0V	GND	GND
34	U1_XF.BJ19 BJ19	OCL0_3R3V_CKEN_F<1>_XF OCL0_3R3V_CKEN_F<1>_XF		ocl_3r3v_cken1_f[0]	IO_L7N_HDGC_AD5N_83
83	U1_XF.BJ20 BJ20	OCL0_3R3V_BP_TYPE_XF OCL0_3R3V_BP_TYPE_XF	3.3V	ocl_3r3v_bp_type[0]	IO_L7P_HDGC_AD5P_83
35	U1_XF.BJ21 BJ21	C0_DDR4_DQ<53>_XF C0_DDR4_DQ<53>_XF		c0_ddr4_dq[37]	IO_L15N_T2L_N5_AD11N_61
35	U1_XF.BJ22 BJ22	C0_DDR4_DQ<54>_XF C0_DDR4_DQ<54>_XF		c0_ddr4_dq[36]	IO_L15P_T2L_N4_AD11P_61
-	U1_XF.BJ23 BJ23	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_61	VCCO_61	1.2
16	U1_XF.BJ24 BJ24	C0_RDIMM_DQS_C<15>_XF C0_RDIMM_DQS_C<15>_XF		c0_ddr4_dqs_c[9]	IO_L13N_T2L_N1_GC_QBC_61
16	U1_XF.BJ25 BJ25	C0_RDIMM_DQS_T<15>_XF C0_RDIMM_DQS_T<15>_XF		c0_ddr4_dqs_t[9]	IO_L13P_T2L_N0_GC_QBC_61
16	U1_XF.BJ26 BJ26	C0_RDIMM_DQS_C<7>_XF C0_RDIMM_DQS_C<7>_XF		c0_ddr4_dqs_c[16]	IO_L22N_T3U_N7_DBC_AD0N_61
16	U1_XF.BJ27 BJ27	C0_RDIMM_DQS_T<7>_XF C0_RDIMM_DQS_T<7>_XF		c0_ddr4_dqs_t[16]	IO_L22P_T3U_N6_DBC_AD0P_61
100	U1_XF.BJ28 BJ28	GND GND	0V	GND	GND
100	U1_XF.BJ29 BJ29	NC NC		IO_T3U_N12_61	IO_T3U_N12_61
100	U1_XF.BJ30 BJ30	NC NC		IO_L20N_T3L_N3_AD1N_D09_65	IO_L20N_T3L_N3_AD1N_D09_65
100	U1_XF.BJ31 BJ31	NC NC		IO_L20P_T3L_N2_AD1P_D08_65	IO_L20P_T3L_N2_AD1P_D08_65
100	U1_XF.BJ32 BJ32	NC NC		IO_L21N_T3L_N5_AD8N_D07_65	IO_L21N_T3L_N5_AD8N_D07_65
88	U1_XF.BJ33 BJ33	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCO_65	VCCO_65	1.8
100	U1_XF.BJ34 BJ34	NC NC		IO_L24N_T3U_N11_DOUT_CSO_B_65	IO_L24N_T3U_N11_DOUT_CSO_B_65
100	U1_XF.BJ35 BJ35	NC NC		IO_T3U_N12_67	IO_T3U_N12_67
100	U1_XF.BJ36 BJ36	NC NC		IO_L20P_T3L_N2_AD1P_67	IO_L20P_T3L_N2_AD1P_67
100	U1_XF.BJ37 BJ37	NC NC		IO_L20N_T3L_N3_AD1N_67	IO_L20N_T3L_N3_AD1N_67
100	U1_XF.BJ38 BJ38	NC NC		VCCO_67	VCCO_67	1.8
100	U1_XF.BJ39 BJ39	NC NC		IO_L24P_T3U_N10_67	IO_L24P_T3U_N10_67
100	U1_XF.BJ40 BJ40	NC NC		IO_L24N_T3U_N11_67	IO_L24N_T3U_N11_67
100	U1_XF.BJ41 BJ41	NC NC		IO_L24N_T3U_N11_19	IO_L24N_T3U_N11_19
100	U1_XF.BJ42 BJ42	NC NC		IO_L22N_T3U_N7_DBC_AD0N_19	IO_L22N_T3U_N7_DBC_AD0N_19
100	U1_XF.BJ43 BJ43	NC NC		VCCO_19	VCCO_19	1.8
100	U1_XF.BJ44 BJ44	NC NC		IO_L23P_T3U_N8_19	IO_L23P_T3U_N8_19
100	U1_XF.BJ45 BJ45	NC NC		IO_L14P_T2L_N2_GC_19	IO_L14P_T2L_N2_GC_19
100	U1_XF.BJ46 BJ46	NC NC		IO_L17P_T2U_N8_AD10P_19	IO_L17P_T2U_N8_AD10P_19
100	U1_XF.BJ47 BJ47	NC NC		IO_L17N_T2U_N9_AD10N_19	IO_L17N_T2U_N9_AD10N_19
100	U1_XF.BJ48 BJ48	GND GND	0V	GND	GND
100	U1_XF.BJ49 BJ49	NC NC		IO_L8N_T1L_N3_AD5N_24	IO_L8N_T1L_N3_AD5N_24
100	U1_XF.BJ50 BJ50	NC NC		IO_T1U_N12_24	IO_T1U_N12_24
100	U1_XF.BJ51 BJ51	NC NC		IO_L9N_T1L_N5_AD12N_24	IO_L9N_T1L_N5_AD12N_24
100	U1_XF.BJ52 BJ52	NC NC		IO_L17N_T2U_N9_AD10N_24	IO_L17N_T2U_N9_AD10N_24
100	U1_XF.BJ53 BJ53	GND GND	0V	GND	GND
100	U1_XF.BJ54 BJ54	NC NC		IO_T2U_N12_24	IO_T2U_N12_24
100	U1_XF.BJ55 BJ55	NC NC		IO_T3U_N12_24	IO_T3U_N12_24
100	U1_XF.BJ56 BJ56	NC NC		IO_L22N_T3U_N7_DBC_AD0N_24	IO_L22N_T3U_N7_DBC_AD0N_24
100	U1_XF.BJ57 BJ57	NC NC		IO_L21N_T3L_N5_AD8N_24	IO_L21N_T3L_N5_AD8N_24
100	U1_XF.BJ58 BJ58	GND GND	0V	GND	GND
100	U1_XF.BJ59 BJ59	NC NC		IO_L3P_T0L_N4_AD15P_25	IO_L3P_T0L_N4_AD15P_25
100	U1_XF.BJ60 BJ60	NC NC		IO_L3N_T0L_N5_AD15N_25	IO_L3N_T0L_N5_AD15N_25
100	U1_XF.BJ61 BJ61	NC NC		IO_L5P_T0U_N8_AD14P_25	IO_L5P_T0U_N8_AD14P_25
100	U1_XF.BJ62 BJ62	NC NC		IO_L5N_T0U_N9_AD14N_25	IO_L5N_T0U_N9_AD14N_25
100	U1_XF.BJ63 BJ63	GND GND	0V	GND	GND
100	U1_XF.BK1 BK1	GND GND	0V	GND	GND
100	U1_XF.BK2 BK2	GND GND	0V	GND	GND
95	U1_XF.BK3 BK3	OCL2_PER_N<3>_XF OCL2_PER_N<3>_XF		ocl2_per_n[3]	MGTYRXN3_222
95	U1_XF.BK4 BK4	OCL2_PER_P<3>_XF OCL2_PER_P<3>_XF		ocl2_per_p[3]	MGTYRXP3_222
100	U1_XF.BK5 BK5	GND GND	0V	GND	GND
100	U1_XF.BK6 BK6	GND GND	0V	GND	GND
100	U1_XF.BK7 BK7	GND GND	0V	GND	GND
92	U1_XF.BK8 BK8	AC_OCL2_PET_N<3>_XF AC_OCL2_PET_N<3>_XF		ocl2_pet_n[3]	MGTYTXN3_222
92	U1_XF.BK9 BK9	AC_OCL2_PET_P<3>_XF AC_OCL2_PET_P<3>_XF		ocl2_pet_p[3]	MGTYTXP3_222
100	U1_XF.BK10 BK10	GND GND	0V	GND	GND
23	U1_XF.BK11 BK11	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
100	U1_XF.BK12 BK12	NC NC		MGTREFCLK1N_222	MGTREFCLK1N_222
100	U1_XF.BK13 BK13	NC NC		MGTREFCLK1P_222	MGTREFCLK1P_222
100	U1_XF.BK14 BK14	GND GND	0V	GND	GND
80	U1_XF.BK15 BK15	PWR_RS_RLC_MGTVCCAUX_XF PWR_RS_RLC_MGTVCCAUX_XF	1.8	MGTVCCAUX_RS	MGTVCCAUX_RS	1.8
100	U1_XF.BK16 BK16	GND GND	0V	GND	GND
-	U1_XF.BK17 BK17	NC NC		ocl_3r3v_extra_io[9]	IO_L8N_HDGC_AD4N_83
18	U1_XF.BK18 BK18	OCL1_3R3V_BP_TYPE_XF OCL1_3R3V_BP_TYPE_XF	3.3V	ocl_3r3v_cwake_f[0]	IO_L6P_HDGC_AD6P_83
18	U1_XF.BK19 BK19	OCL1_3R3V_PERST_F_XF OCL1_3R3V_PERST_F_XF	3.3V	ocl_3r3v_scl[0]	IO_L5N_HDGC_AD7N_83
23	U1_XF.BK20 BK20	OCL1_3R3V_SCL_XF OCL1_3R3V_SCL_XF	3.3V	ocl_3r3v_perst_f[0]	IO_L5P_HDGC_AD7P_83
100	U1_XF.BK21 BK21	GND GND	0V	GND	GND
35	U1_XF.BK22 BK22	C0_DDR4_DQ<34>_XF C0_DDR4_DQ<34>_XF		c0_ddr4_dq[50]	IO_L12P_T1U_N10_GC_61
35	U1_XF.BK23 BK23	C0_DDR4_DQ<52>_XF C0_DDR4_DQ<52>_XF		c0_ddr4_dq[38]	IO_L14N_T2L_N3_GC_61
35	U1_XF.BK24 BK24	C0_DDR4_DQ<55>_XF C0_DDR4_DQ<55>_XF		c0_ddr4_dq[39]	IO_L14P_T2L_N2_GC_61
100	U1_XF.BK25 BK25	NC NC		IO_T2U_N12_61	IO_T2U_N12_61
100	U1_XF.BK26 BK26	GND GND	0V	GND	GND
35	U1_XF.BK27 BK27	C0_DDR4_DQ<60>_XF C0_DDR4_DQ<60>_XF		c0_ddr4_dq[70]	IO_L20N_T3L_N3_AD1N_61
35	U1_XF.BK28 BK28	C0_DDR4_DQ<61>_XF C0_DDR4_DQ<61>_XF		c0_ddr4_dq[71]	IO_L20P_T3L_N2_AD1P_61
100	U1_XF.BK29 BK29	NC NC		IO_L17N_T2U_N9_AD10N_D15_65	IO_L17N_T2U_N9_AD10N_D15_65
100	U1_XF.BK30 BK30	NC NC		IO_L17P_T2U_N8_AD10P_D14_65	IO_L17P_T2U_N8_AD10P_D14_65
100	U1_XF.BK31 BK31	GND GND	0V	GND	GND
100	U1_XF.BK32 BK32	NC NC		IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65	IO_L16P_T2U_N6_QBC_AD3P_A00_D16_65
100	U1_XF.BK33 BK33	NC NC		IO_L18P_T2U_N10_AD2P_D12_65	IO_L18P_T2U_N10_AD2P_D12_65
100	U1_XF.BK34 BK34	PCIE0_RST_F UNNAMED_11_RESISTOR_I769_B_XF ->R154_XF->PCIE0_RST_F ->R155_XF->GND		pcie0_rst_f	IO_T3U_N12_PERSTN0_65
100	U1_XF.BK35 BK35	NC NC		IO_T2U_N12_67	IO_T2U_N12_67
100	U1_XF.BK36 BK36	GND GND	0V	GND	GND
100	U1_XF.BK37 BK37	NC NC		IO_L14P_T2L_N2_GC_67	IO_L14P_T2L_N2_GC_67
100	U1_XF.BK38 BK38	NC NC		IO_L13P_T2L_N0_GC_QBC_67	IO_L13P_T2L_N0_GC_QBC_67
100	U1_XF.BK39 BK39	NC NC		IO_L15P_T2L_N4_AD11P_67	IO_L15P_T2L_N4_AD11P_67
100	U1_XF.BK40 BK40	NC NC		IO_L15N_T2L_N5_AD11N_67	IO_L15N_T2L_N5_AD11N_67
100	U1_XF.BK41 BK41	GND GND	0V	GND	GND
100	U1_XF.BK42 BK42	NC NC		IO_T3U_N12_19	IO_T3U_N12_19
100	U1_XF.BK43 BK43	NC NC		IO_L20P_T3L_N2_AD1P_19	IO_L20P_T3L_N2_AD1P_19
100	U1_XF.BK44 BK44	NC NC		IO_L23N_T3U_N9_19	IO_L23N_T3U_N9_19
100	U1_XF.BK45 BK45	NC NC		IO_L14N_T2L_N3_GC_19	IO_L14N_T2L_N3_GC_19
100	U1_XF.BK46 BK46	NC NC		VCCO_19	VCCO_19	1.8
100	U1_XF.BK47 BK47	NC NC		IO_L18P_T2U_N10_AD2P_19	IO_L18P_T2U_N10_AD2P_19
100	U1_XF.BK48 BK48	NC NC		IO_L16P_T2U_N6_QBC_AD3P_19	IO_L16P_T2U_N6_QBC_AD3P_19
-	U1_XF.BK49 BK49	UNNAMED_21_RESISTOR_I30_B_XF UNNAMED_21_RESISTOR_I30_B_XF ->R27_XF->GND		VREF_23	VREF_23
-	U1_XF.BK50 BK50	UNNAMED_21_RESISTOR_I31_B_XF UNNAMED_21_RESISTOR_I31_B_XF ->R24_XF->GND		IO_T0U_N12_VRP_23	IO_T0U_N12_VRP_23
100	U1_XF.BK51 BK51	GND GND	0V	GND	GND
35	U1_XF.BK52 BK52	C1_DDR4_DQ<62>_XF C1_DDR4_DQ<62>_XF		c1_ddr4_dq[38]	IO_L8P_T1L_N2_AD5P_23
35	U1_XF.BK53 BK53	C1_DDR4_DQ<61>_XF C1_DDR4_DQ<61>_XF		c1_ddr4_dq[37]	IO_L8N_T1L_N3_AD5N_23
16	U1_XF.BK54 BK54	C1_RDIMM_DQS_T<7>_XF C1_RDIMM_DQS_T<7>_XF		c1_ddr4_dqs_t[8]	IO_L10P_T1U_N6_QBC_AD4P_23
16	U1_XF.BK55 BK55	C1_RDIMM_DQS_C<7>_XF C1_RDIMM_DQS_C<7>_XF		c1_ddr4_dqs_c[8]	IO_L10N_T1U_N7_QBC_AD4N_23
100	U1_XF.BK56 BK56	GND GND	0V	GND	GND
100	U1_XF.BK57 BK57	NC NC		IO_T2U_N12_23	IO_T2U_N12_23
35	U1_XF.BK58 BK58	C1_DDR4_DQ<48>_XF C1_DDR4_DQ<48>_XF		c1_ddr4_dq[56]	IO_L17P_T2U_N8_AD10P_23
35	U1_XF.BK59 BK59	C1_DDR4_DQ<51>_XF C1_DDR4_DQ<51>_XF		c1_ddr4_dq[59]	IO_L17N_T2U_N9_AD10N_23
35	U1_XF.BK60 BK60	C1_DDR4_DQ<43>_XF C1_DDR4_DQ<43>_XF		c1_ddr4_dq[51]	IO_L24P_T3U_N10_23
100	U1_XF.BK61 BK61	GND GND	0V	GND	GND
35	U1_XF.BK62 BK62	C1_DDR4_DQ<41>_XF C1_DDR4_DQ<41>_XF		c1_ddr4_dq[49]	IO_L23P_T3U_N8_23
35	U1_XF.BK63 BK63	C1_DDR4_DQ<40>_XF C1_DDR4_DQ<40>_XF		c1_ddr4_dq[48]	IO_L23N_T3U_N9_23
95	U1_XF.BL1 BL1	OCL2_PER_N<2>_XF OCL2_PER_N<2>_XF		ocl2_per_n[2]	MGTYRXN2_222
95	U1_XF.BL2 BL2	OCL2_PER_P<2>_XF OCL2_PER_P<2>_XF		ocl2_per_p[2]	MGTYRXP2_222
100	U1_XF.BL3 BL3	GND GND	0V	GND	GND
100	U1_XF.BL4 BL4	GND GND	0V	GND	GND
95	U1_XF.BL5 BL5	OCL2_PER_N<1>_XF OCL2_PER_N<1>_XF		ocl2_per_n[1]	MGTYRXN1_222
95	U1_XF.BL6 BL6	OCL2_PER_P<1>_XF OCL2_PER_P<1>_XF		ocl2_per_p[1]	MGTYRXP1_222
100	U1_XF.BL7 BL7	GND GND	0V	GND	GND
100	U1_XF.BL8 BL8	GND GND	0V	GND	GND
23	U1_XF.BL9 BL9	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
92	U1_XF.BL10 BL10	AC_OCL2_PET_N<2>_XF AC_OCL2_PET_N<2>_XF		ocl2_pet_n[2]	MGTYTXN2_222
92	U1_XF.BL11 BL11	AC_OCL2_PET_P<2>_XF AC_OCL2_PET_P<2>_XF		ocl2_pet_p[2]	MGTYTXP2_222
100	U1_XF.BL12 BL12	GND GND	0V	GND	GND
18	U1_XF.BL13 BL13	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RS	MGTAVCC_RS	0.9
85	U1_XF.BL14 BL14	OCL2_FPGA_REFCLK_N_XF OCL2_FPGA_REFCLK_N_XF		ocl2_refclk_n	MGTREFCLK0N_222
85	U1_XF.BL15 BL15	OCL2_FPGA_REFCLK_P_XF OCL2_FPGA_REFCLK_P_XF		ocl2_refclk_p	MGTREFCLK0P_222
100	U1_XF.BL16 BL16	GND GND	0V	GND	GND
85	U1_XF.BL17 BL17	OCL0_3R3V_CPRSNT_F_XF OCL0_3R3V_CPRSNT_F_XF	3.3V	ocl_3r3v_cprsnt_f[0]	IO_L6N_HDGC_AD6N_83
85	U1_XF.BL18 BL18	OCL0_3R3V_SDA_XF OCL0_3R3V_SDA_XF	3.3V	ocl_3r3v_sda[0]	IO_L4P_AD8P_83
100	U1_XF.BL19 BL19	GND GND	0V	GND	GND
84	U1_XF.BL20 BL20	OCL1_3R3V_CKEN_F<1>_XF OCL1_3R3V_CKEN_F<1>_XF		ocl_3r3v_cken1_f[1]	IO_L3P_AD9P_83
16	U1_XF.BL21 BL21	C0_RDIMM_DQS_T<4>_XF C0_RDIMM_DQS_T<4>_XF		c0_ddr4_dqs_t[12]	IO_L10P_T1U_N6_QBC_AD4P_61
35	U1_XF.BL22 BL22	C0_DDR4_DQ<33>_XF C0_DDR4_DQ<33>_XF		c0_ddr4_dq[51]	IO_L12N_T1U_N11_GC_61
35	U1_XF.BL23 BL23	C0_DDR4_DQ<35>_XF C0_DDR4_DQ<35>_XF		c0_ddr4_dq[49]	IO_L11P_T1U_N8_GC_61
100	U1_XF.BL24 BL24	GND GND	0V	GND	GND
-	U1_XF.BL25 BL25	UNNAMED_22_RESISTOR_I42_B_XF UNNAMED_22_RESISTOR_I42_B_XF ->R61_XF->GND		VREF_61	VREF_61
-	U1_XF.BL26 BL26	UNNAMED_22_RESISTOR_I44_B_XF UNNAMED_22_RESISTOR_I44_B_XF ->R56_XF->GND		IO_T0U_N12_VRP_61	IO_T0U_N12_VRP_61
16	U1_XF.BL27 BL27	C0_RDIMM_DQS_C<14>_XF C0_RDIMM_DQS_C<14>_XF		c0_ddr4_dqs_c[11]	IO_L1N_T0L_N1_DBC_61
16	U1_XF.BL28 BL28	C0_RDIMM_DQS_T<14>_XF C0_RDIMM_DQS_T<14>_XF		c0_ddr4_dqs_t[11]	IO_L1P_T0L_N0_DBC_61
100	U1_XF.BL29 BL29	GND GND	0V	GND	GND
100	U1_XF.BL30 BL30	NC NC		IO_L13N_T2L_N1_GC_QBC_A07_D23_65	IO_L13N_T2L_N1_GC_QBC_A07_D23_65
96	U1_XF.BL31 BL31	CPLD_FPGA_DCLK_1 CPLD_FPGA_DCLK_1		cpld_fpga_dclk	IO_L13P_T2L_N0_GC_QBC_A06_D22_65
100	U1_XF.BL32 BL32	NC NC		IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65	IO_L16N_T2U_N7_QBC_AD3N_A01_D17_65
100	U1_XF.BL33 BL33	NC NC		IO_L18N_T2U_N11_AD2N_D13_65	IO_L18N_T2U_N11_AD2N_D13_65
100	U1_XF.BL34 BL34	GND GND	0V	GND	GND
100	U1_XF.BL35 BL35	NC NC		IO_L18P_T2U_N10_AD2P_67	IO_L18P_T2U_N10_AD2P_67
100	U1_XF.BL36 BL36	NC NC		IO_L16P_T2U_N6_QBC_AD3P_67	IO_L16P_T2U_N6_QBC_AD3P_67
100	U1_XF.BL37 BL37	NC NC		IO_L14N_T2L_N3_GC_67	IO_L14N_T2L_N3_GC_67
100	U1_XF.BL38 BL38	NC NC		IO_L13N_T2L_N1_GC_QBC_67	IO_L13N_T2L_N1_GC_QBC_67
100	U1_XF.BL39 BL39	GND GND	0V	GND	GND
100	U1_XF.BL40 BL40	NC NC		IO_L17P_T2U_N8_AD10P_67	IO_L17P_T2U_N8_AD10P_67
100	U1_XF.BL41 BL41	NC NC		IO_L5P_T0U_N8_AD14P_19	IO_L5P_T0U_N8_AD14P_19
100	U1_XF.BL42 BL42	NC NC		IO_L5N_T0U_N9_AD14N_19	IO_L5N_T0U_N9_AD14N_19
100	U1_XF.BL43 BL43	NC NC		IO_L20N_T3L_N3_AD1N_19	IO_L20N_T3L_N3_AD1N_19
100	U1_XF.BL44 BL44	GND GND	0V	GND	GND
100	U1_XF.BL45 BL45	NC NC		IO_L13P_T2L_N0_GC_QBC_19	IO_L13P_T2L_N0_GC_QBC_19
100	U1_XF.BL46 BL46	NC NC		IO_L13N_T2L_N1_GC_QBC_19	IO_L13N_T2L_N1_GC_QBC_19
100	U1_XF.BL47 BL47	NC NC		IO_L18N_T2U_N11_AD2N_19	IO_L18N_T2U_N11_AD2N_19
100	U1_XF.BL48 BL48	NC NC		IO_L16N_T2U_N7_QBC_AD3N_19	IO_L16N_T2U_N7_QBC_AD3N_19
100	U1_XF.BL49 BL49	GND GND	0V	GND	GND
37	U1_XF.BL50 BL50	C1_DDR4_DQ<6>_XF C1_DDR4_DQ<6>_XF		c1_ddr4_dq[70]	IO_L2P_T0L_N2_23
37	U1_XF.BL51 BL51	C1_DDR4_DQ<7>_XF C1_DDR4_DQ<7>_XF		c1_ddr4_dq[71]	IO_L2N_T0L_N3_23
35	U1_XF.BL52 BL52	C1_DDR4_DQ<63>_XF C1_DDR4_DQ<63>_XF		c1_ddr4_dq[39]	IO_L9P_T1L_N4_AD12P_23
35	U1_XF.BL53 BL53	C1_DDR4_DQ<60>_XF C1_DDR4_DQ<60>_XF		c1_ddr4_dq[36]	IO_L9N_T1L_N5_AD12N_23
100	U1_XF.BL54 BL54	GND GND	0V	GND	GND
35	U1_XF.BL55 BL55	C1_DDR4_DQ<57>_XF C1_DDR4_DQ<57>_XF		c1_ddr4_dq[34]	IO_L12P_T1U_N10_GC_23
35	U1_XF.BL56 BL56	C1_DDR4_DQ<55>_XF C1_DDR4_DQ<55>_XF		c1_ddr4_dq[61]	IO_L14P_T2L_N2_GC_23
54	U1_XF.BL57 BL57	C1_RDIMM_DQS_T<15>_XF C1_RDIMM_DQS_T<15>_XF		c1_ddr4_dqs_t[15]	IO_L13P_T2L_N0_GC_QBC_23
54	U1_XF.BL58 BL58	C1_RDIMM_DQS_C<15>_XF C1_RDIMM_DQS_C<15>_XF		c1_ddr4_dqs_c[15]	IO_L13N_T2L_N1_GC_QBC_23
100	U1_XF.BL59 BL59	GND GND	0V	GND	GND
35	U1_XF.BL60 BL60	C1_DDR4_DQ<42>_XF C1_DDR4_DQ<42>_XF		c1_ddr4_dq[50]	IO_L24N_T3U_N11_23
16	U1_XF.BL61 BL61	C1_RDIMM_DQS_T<5>_XF C1_RDIMM_DQS_T<5>_XF		c1_ddr4_dqs_t[12]	IO_L22P_T3U_N6_DBC_AD0P_23
35	U1_XF.BL62 BL62	C1_DDR4_DQ<47>_XF C1_DDR4_DQ<47>_XF		c1_ddr4_dq[55]	IO_L21P_T3L_N4_AD8P_23
35	U1_XF.BL63 BL63	C1_DDR4_DQ<46>_XF C1_DDR4_DQ<46>_XF		c1_ddr4_dq[54]	IO_L21N_T3L_N5_AD8N_23
100	U1_XF.BM1 BM1	GND GND	0V	GND	GND
100	U1_XF.BM2 BM2	GND GND	0V	GND	GND
95	U1_XF.BM3 BM3	OCL2_PER_N<0>_XF OCL2_PER_N<0>_XF		ocl2_per_n[0]	MGTYRXN0_222
95	U1_XF.BM4 BM4	OCL2_PER_P<0>_XF OCL2_PER_P<0>_XF		ocl2_per_p[0]	MGTYRXP0_222
100	U1_XF.BM5 BM5	GND GND	0V	GND	GND
100	U1_XF.BM6 BM6	GND GND	0V	GND	GND
100	U1_XF.BM7 BM7	GND GND	0V	GND	GND
92	U1_XF.BM8 BM8	AC_OCL2_PET_N<1>_XF AC_OCL2_PET_N<1>_XF		ocl2_pet_n[1]	MGTYTXN1_222
92	U1_XF.BM9 BM9	AC_OCL2_PET_P<1>_XF AC_OCL2_PET_P<1>_XF		ocl2_pet_p[1]	MGTYTXP1_222
100	U1_XF.BM10 BM10	GND GND	0V	GND	GND
23	U1_XF.BM11 BM11	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
100	U1_XF.BM12 BM12	NC NC		MGTREFCLK1N_221	MGTREFCLK1N_221
100	U1_XF.BM13 BM13	NC NC		MGTREFCLK1P_221	MGTREFCLK1P_221
100	U1_XF.BM14 BM14	GND GND	0V	GND	GND
18	U1_XF.BM15 BM15	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RS	MGTAVCC_RS	0.9
100	U1_XF.BM16 BM16	GND GND	0V	GND	GND
-	U1_XF.BM17 BM17	PWR_FPGA_3R3V PWR_FPGA_3R3V	3.3	VCCO_83	VCCO_83	3.3
18	U1_XF.BM18 BM18	OCL0_3R3V_CWAKE_F_XF OCL0_3R3V_CWAKE_F_XF	3.3V	ocl_3r3v_bp_type[1]	IO_L4N_AD8N_83
23	U1_XF.BM19 BM19	OCL0_3R3V_SCL_XF OCL0_3R3V_SCL_XF	3.3V	ocl_3r3v_cprsnt_f[1]	IO_L2P_AD10P_83
36	U1_XF.BM20 BM20	OCL0_3R3V_PERST_F_XF OCL0_3R3V_PERST_F_XF	3.3V	ocl_3r3v_cwake_f[1]	IO_L3N_AD9N_83
16	U1_XF.BM21 BM21	C0_RDIMM_DQS_C<4>_XF C0_RDIMM_DQS_C<4>_XF		c0_ddr4_dqs_c[12]	IO_L10N_T1U_N7_QBC_AD4N_61
-	U1_XF.BM22 BM22	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_61	VCCO_61	1.2
35	U1_XF.BM23 BM23	C0_DDR4_DQ<32>_XF C0_DDR4_DQ<32>_XF		c0_ddr4_dq[48]	IO_L11N_T1U_N9_GC_61
54	U1_XF.BM24 BM24	C0_RDIMM_DQS_T<13>_XF C0_RDIMM_DQS_T<13>_XF		c0_ddr4_dqs_t[13]	IO_L7P_T1L_N0_QBC_AD13P_61
95	U1_XF.BM25 BM25	C0_DDR4_DQ<47>_XF C0_DDR4_DQ<47>_XF		c0_ddr4_dq[47]	IO_L3N_T0L_N5_AD15N_61
95	U1_XF.BM26 BM26	C0_DDR4_DQ<46>_XF C0_DDR4_DQ<46>_XF		c0_ddr4_dq[46]	IO_L3P_T0L_N4_AD15P_61
100	U1_XF.BM27 BM27	GND GND	0V	GND	GND
35	U1_XF.BM28 BM28	C0_DDR4_DQ<43>_XF C0_DDR4_DQ<43>_XF		c0_ddr4_dq[41]	IO_L5P_T0U_N8_AD14P_61
96	U1_XF.BM29 BM29	FPGA_CPLD_DQ<1>_1 FPGA_CPLD_DQ<1>_1		fpga_cpld_dq[1]	IO_T2U_N12_CSI_ADV_B_65
100	U1_XF.BM30 BM30	NC NC		IO_L14N_T2L_N3_GC_A05_D21_65	IO_L14N_T2L_N3_GC_A05_D21_65
100	U1_XF.BM31 BM31	NC NC		IO_L14P_T2L_N2_GC_A04_D20_65	IO_L14P_T2L_N2_GC_A04_D20_65
88	U1_XF.BM32 BM32	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCO_65	VCCO_65	1.8
100	U1_XF.BM33 BM33	NC NC		IO_L15N_T2L_N5_AD11N_A03_D19_65	IO_L15N_T2L_N5_AD11N_A03_D19_65
100	U1_XF.BM34 BM34	NC NC		IO_L15P_T2L_N4_AD11P_A02_D18_65	IO_L15P_T2L_N4_AD11P_A02_D18_65
100	U1_XF.BM35 BM35	NC NC		IO_L18N_T2U_N11_AD2N_67	IO_L18N_T2U_N11_AD2N_67
100	U1_XF.BM36 BM36	NC NC		IO_L16N_T2U_N7_QBC_AD3N_67	IO_L16N_T2U_N7_QBC_AD3N_67
100	U1_XF.BM37 BM37	NC NC		VCCO_67	VCCO_67	1.8
100	U1_XF.BM38 BM38	NC NC		IO_L12P_T1U_N10_GC_67	IO_L12P_T1U_N10_GC_67
100	U1_XF.BM39 BM39	NC NC		IO_L11P_T1U_N8_GC_67	IO_L11P_T1U_N8_GC_67
100	U1_XF.BM40 BM40	NC NC		IO_L17N_T2U_N9_AD10N_67	IO_L17N_T2U_N9_AD10N_67
100	U1_XF.BM41 BM41	NC NC		IO_T0U_N12_VRP_19	IO_T0U_N12_VRP_19
100	U1_XF.BM42 BM42	GND GND	0V	GND	GND
100	U1_XF.BM43 BM43	NC NC		IO_L6P_T0U_N10_AD6P_19	IO_L6P_T0U_N10_AD6P_19
100	U1_XF.BM44 BM44	NC NC		IO_L6N_T0U_N11_AD6N_19	IO_L6N_T0U_N11_AD6N_19
100	U1_XF.BM45 BM45	NC NC		IO_L11P_T1U_N8_GC_19	IO_L11P_T1U_N8_GC_19
100	U1_XF.BM46 BM46	NC NC		IO_L11N_T1U_N9_GC_19	IO_L11N_T1U_N9_GC_19
100	U1_XF.BM47 BM47	GND GND	0V	GND	GND
100	U1_XF.BM48 BM48	NC NC		IO_L10P_T1U_N6_QBC_AD4P_19	IO_L10P_T1U_N6_QBC_AD4P_19
16	U1_XF.BM49 BM49	C1_RDIMM_DQS_T<0>_XF C1_RDIMM_DQS_T<0>_XF		c1_ddr4_dqs_t[16]	IO_L4P_T0U_N6_DBC_AD7P_23
16	U1_XF.BM50 BM50	C1_RDIMM_DQS_C<0>_XF C1_RDIMM_DQS_C<0>_XF		c1_ddr4_dqs_c[16]	IO_L4N_T0U_N7_DBC_AD7N_23
37	U1_XF.BM51 BM51	C1_DDR4_DQ<1>_XF C1_DDR4_DQ<1>_XF		c1_ddr4_dq[65]	IO_L6P_T0U_N10_AD6P_23
-	U1_XF.BM52 BM52	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_23	VCCO_23	1.2
16	U1_XF.BM53 BM53	C1_RDIMM_DQS_T<16>_XF C1_RDIMM_DQS_T<16>_XF		c1_ddr4_dqs_t[9]	IO_L7P_T1L_N0_QBC_AD13P_23
35	U1_XF.BM54 BM54	C1_DDR4_DQ<58>_XF C1_DDR4_DQ<58>_XF		c1_ddr4_dq[35]	IO_L11P_T1U_N8_GC_23
35	U1_XF.BM55 BM55	C1_DDR4_DQ<56>_XF C1_DDR4_DQ<56>_XF		c1_ddr4_dq[32]	IO_L12N_T1U_N11_GC_23
35	U1_XF.BM56 BM56	C1_DDR4_DQ<52>_XF C1_DDR4_DQ<52>_XF		c1_ddr4_dq[60]	IO_L14N_T2L_N3_GC_23
-	U1_XF.BM57 BM57	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_23	VCCO_23	1.2
35	U1_XF.BM58 BM58	C1_DDR4_DQ<49>_XF C1_DDR4_DQ<49>_XF		c1_ddr4_dq[57]	IO_L18P_T2U_N10_AD2P_23
35	U1_XF.BM59 BM59	C1_DDR4_DQ<53>_XF C1_DDR4_DQ<53>_XF		c1_ddr4_dq[63]	IO_L15P_T2L_N4_AD11P_23
100	U1_XF.BM60 BM60	NC NC		IO_T3U_N12_23	IO_T3U_N12_23
16	U1_XF.BM61 BM61	C1_RDIMM_DQS_C<5>_XF C1_RDIMM_DQS_C<5>_XF		c1_ddr4_dqs_c[12]	IO_L22N_T3U_N7_DBC_AD0N_23
100	U1_XF.BM62 BM62	GND GND	0V	GND	GND
16	U1_XF.BM63 BM63	C1_RDIMM_DQS_T<14>_XF C1_RDIMM_DQS_T<14>_XF		c1_ddr4_dqs_t[13]	IO_L19P_T3L_N0_DBC_AD9P_23
100	U1_XF.BN1 BN1	NC NC		MGTYRXN3_221	MGTYRXN3_221
100	U1_XF.BN2 BN2	NC NC		MGTYRXP3_221	MGTYRXP3_221
100	U1_XF.BN3 BN3	GND GND	0V	GND	GND
100	U1_XF.BN4 BN4	GND GND	0V	GND	GND
100	U1_XF.BN5 BN5	NC NC		MGTYRXN2_221	MGTYRXN2_221
100	U1_XF.BN6 BN6	NC NC		MGTYRXP2_221	MGTYRXP2_221
100	U1_XF.BN7 BN7	GND GND	0V	GND	GND
100	U1_XF.BN8 BN8	GND GND	0V	GND	GND
23	U1_XF.BN9 BN9	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
92	U1_XF.BN10 BN10	AC_OCL2_PET_N<0>_XF AC_OCL2_PET_N<0>_XF		ocl2_pet_n[0]	MGTYTXN0_222
92	U1_XF.BN11 BN11	AC_OCL2_PET_P<0>_XF AC_OCL2_PET_P<0>_XF		ocl2_pet_p[0]	MGTYTXP0_222
100	U1_XF.BN12 BN12	GND GND	0V	GND	GND
18	U1_XF.BN13 BN13	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RS	MGTAVCC_RS	0.9
100	U1_XF.BN14 BN14	NC NC		MGTREFCLK0N_221	MGTREFCLK0N_221
100	U1_XF.BN15 BN15	NC NC		MGTREFCLK0P_221	MGTREFCLK0P_221
100	U1_XF.BN16 BN16	GND GND	0V	GND	GND
85	U1_XF.BN17 BN17	OCL1_3R3V_SDA_XF OCL1_3R3V_SDA_XF	3.3V	ocl_3r3v_sda[1]	IO_L1N_AD11N_83
18	U1_XF.BN18 BN18	OCL1_3R3V_CWAKE_F_XF OCL1_3R3V_CWAKE_F_XF	3.3V	ocl_3r3v_scl[1]	IO_L1P_AD11P_83
36	U1_XF.BN19 BN19	OCL1_3R3V_CPRSNT_F_XF OCL1_3R3V_CPRSNT_F_XF	3.3V	ocl_3r3v_perst_f[1]	IO_L2N_AD10N_83
100	U1_XF.BN20 BN20	GND GND	0V	GND	GND
35	U1_XF.BN21 BN21	C0_DDR4_DQ<37>_XF C0_DDR4_DQ<37>_XF		c0_ddr4_dq[52]	IO_L9N_T1L_N5_AD12N_61
35	U1_XF.BN22 BN22	C0_DDR4_DQ<39>_XF C0_DDR4_DQ<39>_XF		c0_ddr4_dq[53]	IO_L9P_T1L_N4_AD12P_61
100	U1_XF.BN23 BN23	NC NC		IO_T1U_N12_61	IO_T1U_N12_61
54	U1_XF.BN24 BN24	C0_RDIMM_DQS_C<13>_XF C0_RDIMM_DQS_C<13>_XF		c0_ddr4_dqs_c[13]	IO_L7N_T1L_N1_QBC_AD13N_61
-	U1_XF.BN25 BN25	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_61	VCCO_61	1.2
35	U1_XF.BN26 BN26	C0_DDR4_DQ<41>_XF C0_DDR4_DQ<41>_XF		c0_ddr4_dq[42]	IO_L6N_T0U_N11_AD6N_61
35	U1_XF.BN27 BN27	C0_DDR4_DQ<40>_XF C0_DDR4_DQ<40>_XF		c0_ddr4_dq[43]	IO_L6P_T0U_N10_AD6P_61
35	U1_XF.BN28 BN28	C0_DDR4_DQ<42>_XF C0_DDR4_DQ<42>_XF		c0_ddr4_dq[40]	IO_L5N_T0U_N9_AD14N_61
96	U1_XF.BN29 BN29	FPGA_CPLD_DCLK_1 FPGA_CPLD_DCLK_1		fpga_cpld_dclk	IO_T1U_N12_SMBALERT_65
100	U1_XF.BN30 BN30	GND GND	0V	GND	GND
100	U1_XF.BN31 BN31	FPGA_REF_CLK_N FPGA_REF_CLK_N		fpga_ref_clk_n	IO_L11N_T1U_N9_GC_A11_D27_65
100	U1_XF.BN32 BN32	FPGA_REF_CLK_P FPGA_REF_CLK_P		fpga_ref_clk_p	IO_L11P_T1U_N8_GC_A10_D26_65
100	U1_XF.BN33 BN33	NC NC		IO_L9N_T1L_N5_AD12N_A15_D31_65	IO_L9N_T1L_N5_AD12N_A15_D31_65
100	U1_XF.BN34 BN34	NC NC		IO_L9P_T1L_N4_AD12P_A14_D30_65	IO_L9P_T1L_N4_AD12P_A14_D30_65
100	U1_XF.BN35 BN35	GND GND	0V	GND	GND
100	U1_XF.BN36 BN36	NC NC		IO_L10P_T1U_N6_QBC_AD4P_67	IO_L10P_T1U_N6_QBC_AD4P_67
100	U1_XF.BN37 BN37	NC NC		IO_L9P_T1L_N4_AD12P_67	IO_L9P_T1L_N4_AD12P_67
100	U1_XF.BN38 BN38	NC NC		IO_L12N_T1U_N11_GC_67	IO_L12N_T1U_N11_GC_67
100	U1_XF.BN39 BN39	NC NC		IO_L11N_T1U_N9_GC_67	IO_L11N_T1U_N9_GC_67
100	U1_XF.BN40 BN40	GND GND	0V	GND	GND
100	U1_XF.BN41 BN41	NC NC		IO_L3P_T0L_N4_AD15P_19	IO_L3P_T0L_N4_AD15P_19
100	U1_XF.BN42 BN42	NC NC		IO_L3N_T0L_N5_AD15N_19	IO_L3N_T0L_N5_AD15N_19
100	U1_XF.BN43 BN43	NC NC		IO_L4P_T0U_N6_DBC_AD7P_19	IO_L4P_T0U_N6_DBC_AD7P_19
100	U1_XF.BN44 BN44	NC NC		IO_L4N_T0U_N7_DBC_AD7N_19	IO_L4N_T0U_N7_DBC_AD7N_19
100	U1_XF.BN45 BN45	GND GND	0V	GND	GND
100	U1_XF.BN46 BN46	NC NC		IO_L12P_T1U_N10_GC_19	IO_L12P_T1U_N10_GC_19
100	U1_XF.BN47 BN47	NC NC		IO_L12N_T1U_N11_GC_19	IO_L12N_T1U_N11_GC_19
100	U1_XF.BN48 BN48	NC NC		IO_L10N_T1U_N7_QBC_AD4N_19	IO_L10N_T1U_N7_QBC_AD4N_19
37	U1_XF.BN49 BN49	C1_DDR4_DQ<5>_XF C1_DDR4_DQ<5>_XF		c1_ddr4_dq[69]	IO_L3P_T0L_N4_AD15P_23
100	U1_XF.BN50 BN50	GND GND	0V	GND	GND
37	U1_XF.BN51 BN51	C1_DDR4_DQ<0>_XF C1_DDR4_DQ<0>_XF		c1_ddr4_dq[64]	IO_L6N_T0U_N11_AD6N_23
37	U1_XF.BN52 BN52	C1_DDR4_DQ<3>_XF C1_DDR4_DQ<3>_XF		c1_ddr4_dq[67]	IO_L5P_T0U_N8_AD14P_23
16	U1_XF.BN53 BN53	C1_RDIMM_DQS_C<16>_XF C1_RDIMM_DQS_C<16>_XF		c1_ddr4_dqs_c[9]	IO_L7N_T1L_N1_QBC_AD13N_23
35	U1_XF.BN54 BN54	C1_DDR4_DQ<59>_XF C1_DDR4_DQ<59>_XF		c1_ddr4_dq[33]	IO_L11N_T1U_N9_GC_23
100	U1_XF.BN55 BN55	GND GND	0V	GND	GND
16	U1_XF.BN56 BN56	C1_RDIMM_DQS_T<6>_XF C1_RDIMM_DQS_T<6>_XF		c1_ddr4_dqs_t[14]	IO_L16P_T2U_N6_QBC_AD3P_23
16	U1_XF.BN57 BN57	C1_RDIMM_DQS_C<6>_XF C1_RDIMM_DQS_C<6>_XF		c1_ddr4_dqs_c[14]	IO_L16N_T2U_N7_QBC_AD3N_23
35	U1_XF.BN58 BN58	C1_DDR4_DQ<50>_XF C1_DDR4_DQ<50>_XF		c1_ddr4_dq[58]	IO_L18N_T2U_N11_AD2N_23
35	U1_XF.BN59 BN59	C1_DDR4_DQ<54>_XF C1_DDR4_DQ<54>_XF		c1_ddr4_dq[62]	IO_L15N_T2L_N5_AD11N_23
-	U1_XF.BN60 BN60	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_23	VCCO_23	1.2
35	U1_XF.BN61 BN61	C1_DDR4_DQ<44>_XF C1_DDR4_DQ<44>_XF		c1_ddr4_dq[52]	IO_L20P_T3L_N2_AD1P_23
35	U1_XF.BN62 BN62	C1_DDR4_DQ<45>_XF C1_DDR4_DQ<45>_XF		c1_ddr4_dq[53]	IO_L20N_T3L_N3_AD1N_23
16	U1_XF.BN63 BN63	C1_RDIMM_DQS_C<14>_XF C1_RDIMM_DQS_C<14>_XF		c1_ddr4_dqs_c[13]	IO_L19N_T3L_N1_DBC_AD9N_23
100	U1_XF.BP1 BP1	GND GND	0V	GND	GND
100	U1_XF.BP2 BP2	GND GND	0V	GND	GND
100	U1_XF.BP3 BP3	NC NC		MGTYRXN1_221	MGTYRXN1_221
100	U1_XF.BP4 BP4	NC NC		MGTYRXP1_221	MGTYRXP1_221
100	U1_XF.BP5 BP5	GND GND	0V	GND	GND
100	U1_XF.BP6 BP6	GND GND	0V	GND	GND
100	U1_XF.BP7 BP7	GND GND	0V	GND	GND
100	U1_XF.BP8 BP8	NC NC		MGTYTXN3_221	MGTYTXN3_221
100	U1_XF.BP9 BP9	NC NC		MGTYTXP3_221	MGTYTXP3_221
100	U1_XF.BP10 BP10	GND GND	0V	GND	GND
23	U1_XF.BP11 BP11	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
100	U1_XF.BP12 BP12	NC NC		MGTREFCLK1N_220	MGTREFCLK1N_220
100	U1_XF.BP13 BP13	NC NC		MGTREFCLK1P_220	MGTREFCLK1P_220
100	U1_XF.BP14 BP14	GND GND	0V	GND	GND
100	U1_XF.BP15 BP15	GND GND	0V	GND	GND
100	U1_XF.BP16 BP16	GND GND	0V	GND	GND
35	U1_XF.BP17 BP17	C0_DDR4_DQ<18>_XF C0_DDR4_DQ<18>_XF		c0_ddr4_dq[58]	IO_L24P_T3U_N10_60
100	U1_XF.BP18 BP18	GND GND	0V	GND	GND
100	U1_XF.BP19 BP19	NC NC		IO_L18P_T2U_N10_AD2P_60	IO_L18P_T2U_N10_AD2P_60
95	U1_XF.BP20 BP20	C0_DDR4_ALERT_N_XF C0_DDR4_ALERT_N_XF		c0_ddr4_alert_n	IO_T2U_N12_60
35	U1_XF.BP21 BP21	C0_DDR4_DQ<38>_XF C0_DDR4_DQ<38>_XF		c0_ddr4_dq[54]	IO_L8N_T1L_N3_AD5N_61
35	U1_XF.BP22 BP22	C0_DDR4_DQ<36>_XF C0_DDR4_DQ<36>_XF		c0_ddr4_dq[55]	IO_L8P_T1L_N2_AD5P_61
100	U1_XF.BP23 BP23	GND GND	0V	GND	GND
95	U1_XF.BP24 BP24	C0_DDR4_DQ<44>_XF C0_DDR4_DQ<44>_XF		c0_ddr4_dq[44]	IO_L2N_T0L_N3_61
95	U1_XF.BP25 BP25	C0_DDR4_DQ<45>_XF C0_DDR4_DQ<45>_XF		c0_ddr4_dq[45]	IO_L2P_T0L_N2_61
16	U1_XF.BP26 BP26	C0_RDIMM_DQS_C<5>_XF C0_RDIMM_DQS_C<5>_XF		c0_ddr4_dqs_c[10]	IO_L4N_T0U_N7_DBC_AD7N_61
16	U1_XF.BP27 BP27	C0_RDIMM_DQS_T<5>_XF C0_RDIMM_DQS_T<5>_XF		c0_ddr4_dqs_t[10]	IO_L4P_T0U_N6_DBC_AD7P_61
100	U1_XF.BP28 BP28	GND GND	0V	GND	GND
100	U1_XF.BP29 BP29	NC NC		IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65	IO_L10N_T1U_N7_QBC_AD4N_A13_D29_65
100	U1_XF.BP30 BP30	NC NC		IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65	IO_L10P_T1U_N6_QBC_AD4P_A12_D28_65
100	U1_XF.BP31 BP31	NC NC		IO_L12N_T1U_N11_GC_A09_D25_65	IO_L12N_T1U_N11_GC_A09_D25_65
100	U1_XF.BP32 BP32	NC NC		IO_L12P_T1U_N10_GC_A08_D24_65	IO_L12P_T1U_N10_GC_A08_D24_65
100	U1_XF.BP33 BP33	GND GND	0V	GND	GND
100	U1_XF.BP34 BP34	NC NC		IO_L7P_T1L_N0_QBC_AD13P_A18_65	IO_L7P_T1L_N0_QBC_AD13P_A18_65
100	U1_XF.BP35 BP35	NC NC		IO_L8P_T1L_N2_AD5P_67	IO_L8P_T1L_N2_AD5P_67
100	U1_XF.BP36 BP36	NC NC		IO_L10N_T1U_N7_QBC_AD4N_67	IO_L10N_T1U_N7_QBC_AD4N_67
100	U1_XF.BP37 BP37	NC NC		IO_L9N_T1L_N5_AD12N_67	IO_L9N_T1L_N5_AD12N_67
100	U1_XF.BP38 BP38	GND GND	0V	GND	GND
100	U1_XF.BP39 BP39	NC NC		IO_L7P_T1L_N0_QBC_AD13P_67	IO_L7P_T1L_N0_QBC_AD13P_67
100	U1_XF.BP40 BP40	NC NC		IO_L7N_T1L_N1_QBC_AD13N_67	IO_L7N_T1L_N1_QBC_AD13N_67
100	U1_XF.BP41 BP41	NC NC		IO_L2P_T0L_N2_19	IO_L2P_T0L_N2_19
100	U1_XF.BP42 BP42	NC NC		IO_L2N_T0L_N3_19	IO_L2N_T0L_N3_19
100	U1_XF.BP43 BP43	NC NC		VCCO_19	VCCO_19	1.8
100	U1_XF.BP44 BP44	NC NC		IO_L9P_T1L_N4_AD12P_19	IO_L9P_T1L_N4_AD12P_19
100	U1_XF.BP45 BP45	NC NC		IO_L9N_T1L_N5_AD12N_19	IO_L9N_T1L_N5_AD12N_19
100	U1_XF.BP46 BP46	NC NC		VREF_19	VREF_19
100	U1_XF.BP47 BP47	NC NC		IO_T1U_N12_19	IO_T1U_N12_19
100	U1_XF.BP48 BP48	GND GND	0V	GND	GND
37	U1_XF.BP49 BP49	C1_DDR4_DQ<4>_XF C1_DDR4_DQ<4>_XF		c1_ddr4_dq[68]	IO_L3N_T0L_N5_AD15N_23
16	U1_XF.BP50 BP50	C1_RDIMM_DQS_T<9>_XF C1_RDIMM_DQS_T<9>_XF		c1_ddr4_dqs_t[17]	IO_L1P_T0L_N0_DBC_23
16	U1_XF.BP51 BP51	C1_RDIMM_DQS_C<9>_XF C1_RDIMM_DQS_C<9>_XF		c1_ddr4_dqs_c[17]	IO_L1N_T0L_N1_DBC_23
37	U1_XF.BP52 BP52	C1_DDR4_DQ<2>_XF C1_DDR4_DQ<2>_XF		c1_ddr4_dq[66]	IO_L5N_T0U_N9_AD14N_23
100	U1_XF.BP53 BP53	GND GND	0V	GND	GND
100	U1_XF.BP54 BP54	NC NC		IO_T1U_N12_23	IO_T1U_N12_23
16	U1_XF.BP55 BP55	C1_RDIMM_DQS_T<11>_XF C1_RDIMM_DQS_T<11>_XF		c1_ddr4_dqs_t[5]	IO_L7P_T1L_N0_QBC_AD13P_22
35	U1_XF.BP56 BP56	C1_DDR4_DQ<22>_XF C1_DDR4_DQ<22>_XF		c1_ddr4_dq[21]	IO_L9P_T1L_N4_AD12P_22
35	U1_XF.BP57 BP57	C1_DDR4_DQ<23>_XF C1_DDR4_DQ<23>_XF		c1_ddr4_dq[20]	IO_L9N_T1L_N5_AD12N_22
100	U1_XF.BP58 BP58	GND GND	0V	GND	GND
35	U1_XF.BP59 BP59	C1_DDR4_DQ<67>_XF C1_DDR4_DQ<67>_XF		c1_ddr4_dq[11]	IO_L17P_T2U_N8_AD10P_22
100	U1_XF.BP60 BP60	NC NC		IO_T3U_N12_22	IO_T3U_N12_22
44	U1_XF.BP61 BP61	C1_DDR4_DQ<35>_XF C1_DDR4_DQ<35>_XF		c1_ddr4_dq[3]	IO_L23P_T3U_N8_22
36	U1_XF.BP62 BP62	C1_DDR4_DQ<34>_XF C1_DDR4_DQ<34>_XF		c1_ddr4_dq[2]	IO_L23N_T3U_N9_22
100	U1_XF.BP63 BP63	GND GND	0V	GND	GND
100	U1_XF.BR1 BR1	NC NC		MGTYRXN0_221	MGTYRXN0_221
100	U1_XF.BR2 BR2	NC NC		MGTYRXP0_221	MGTYRXP0_221
100	U1_XF.BR3 BR3	GND GND	0V	GND	GND
100	U1_XF.BR4 BR4	GND GND	0V	GND	GND
95	U1_XF.BR5 BR5	OCL1_PER_N<3>_XF OCL1_PER_N<3>_XF		ocl1_per_n[3]	MGTYRXN3_220
95	U1_XF.BR6 BR6	OCL1_PER_P<3>_XF OCL1_PER_P<3>_XF		ocl1_per_p[3]	MGTYRXP3_220
100	U1_XF.BR7 BR7	GND GND	0V	GND	GND
100	U1_XF.BR8 BR8	GND GND	0V	GND	GND
23	U1_XF.BR9 BR9	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
100	U1_XF.BR10 BR10	NC NC		MGTYTXN2_221	MGTYTXN2_221
100	U1_XF.BR11 BR11	NC NC		MGTYTXP2_221	MGTYTXP2_221
100	U1_XF.BR12 BR12	GND GND	0V	GND	GND
18	U1_XF.BR13 BR13	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RS	MGTAVCC_RS	0.9
100	U1_XF.BR14 BR14	GND GND	0V	GND	GND
16	U1_XF.BR15 BR15	C0_RDIMM_DQS_T<2>_XF C0_RDIMM_DQS_T<2>_XF		c0_ddr4_dqs_t[14]	IO_L22P_T3U_N6_DBC_AD0P_60
100	U1_XF.BR16 BR16	GND GND	0V	GND	GND
35	U1_XF.BR17 BR17	C0_DDR4_DQ<19>_XF C0_DDR4_DQ<19>_XF		c0_ddr4_dq[59]	IO_L24N_T3U_N11_60
35	U1_XF.BR18 BR18	C0_DDR4_DQ<20>_XF C0_DDR4_DQ<20>_XF		c0_ddr4_dq[60]	IO_L20P_T3L_N2_AD1P_60
100	U1_XF.BR19 BR19	NC NC		IO_L18N_T2U_N11_AD2N_60	IO_L18N_T2U_N11_AD2N_60
95	U1_XF.BR20 BR20	C0_DDR4_ADR<15>_XF C0_DDR4_ADR<15>_XF		c0_ddr4_adr[15]	IO_L16P_T2U_N6_QBC_AD3P_60
100	U1_XF.BR21 BR21	GND GND	0V	GND	GND
35	U1_XF.BR22 BR22	C0_DDR4_DQ<28>_XF C0_DDR4_DQ<28>_XF		c0_ddr4_dq[22]	IO_L2N_T0L_N3_62
35	U1_XF.BR23 BR23	C0_DDR4_DQ<30>_XF C0_DDR4_DQ<30>_XF		c0_ddr4_dq[23]	IO_L2P_T0L_N2_62
-	U1_XF.BR24 BR24	UNNAMED_22_RESISTOR_I41_B_XF UNNAMED_22_RESISTOR_I41_B_XF ->R54_XF->GND		IO_T0U_N12_VRP_62	IO_T0U_N12_VRP_62
-	U1_XF.BR25 BR25	UNNAMED_22_RESISTOR_I40_B_XF UNNAMED_22_RESISTOR_I40_B_XF ->R55_XF->GND		VREF_62	VREF_62
100	U1_XF.BR26 BR26	GND GND	0V	GND	GND
36	U1_XF.BR27 BR27	C0_DDR4_DQ<67>_XF C0_DDR4_DQ<67>_XF		c0_ddr4_dq[2]	IO_L23N_T3U_N9_62
36	U1_XF.BR28 BR28	C0_DDR4_DQ<66>_XF C0_DDR4_DQ<66>_XF		c0_ddr4_dq[3]	IO_L23P_T3U_N8_62
100	U1_XF.BR29 BR29	NC NC		IO_L8N_T1L_N3_AD5N_A17_65	IO_L8N_T1L_N3_AD5N_A17_65
100	U1_XF.BR30 BR30	NC NC		IO_L8P_T1L_N2_AD5P_A16_65	IO_L8P_T1L_N2_AD5P_A16_65
88	U1_XF.BR31 BR31	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCO_65	VCCO_65	1.8
100	U1_XF.BR32 BR32	NC NC		IO_L5N_T0U_N9_AD14N_A23_65	IO_L5N_T0U_N9_AD14N_A23_65
100	U1_XF.BR33 BR33	NC NC		IO_L5P_T0U_N8_AD14P_A22_65	IO_L5P_T0U_N8_AD14P_A22_65
100	U1_XF.BR34 BR34	NC NC		IO_L7N_T1L_N1_QBC_AD13N_A19_65	IO_L7N_T1L_N1_QBC_AD13N_A19_65
100	U1_XF.BR35 BR35	NC NC		IO_L8N_T1L_N3_AD5N_67	IO_L8N_T1L_N3_AD5N_67
100	U1_XF.BR36 BR36	NC NC		VCCO_67	VCCO_67	1.8
100	U1_XF.BR37 BR37	NC NC		IO_L5P_T0U_N8_AD14P_67	IO_L5P_T0U_N8_AD14P_67
100	U1_XF.BR38 BR38	NC NC		IO_L5N_T0U_N9_AD14N_67	IO_L5N_T0U_N9_AD14N_67
100	U1_XF.BR39 BR39	NC NC		IO_T0U_N12_VRP_67	IO_T0U_N12_VRP_67
100	U1_XF.BR40 BR40	NC NC		IO_T1U_N12_67	IO_T1U_N12_67
100	U1_XF.BR41 BR41	GND GND	0V	GND	GND
100	U1_XF.BR42 BR42	NC NC		IO_L1P_T0L_N0_DBC_19	IO_L1P_T0L_N0_DBC_19
100	U1_XF.BR43 BR43	NC NC		IO_L1N_T0L_N1_DBC_19	IO_L1N_T0L_N1_DBC_19
100	U1_XF.BR44 BR44	NC NC		IO_L7P_T1L_N0_QBC_AD13P_19	IO_L7P_T1L_N0_QBC_AD13P_19
100	U1_XF.BR45 BR45	NC NC		IO_L7N_T1L_N1_QBC_AD13N_19	IO_L7N_T1L_N1_QBC_AD13N_19
100	U1_XF.BR46 BR46	GND GND	0V	GND	GND
100	U1_XF.BR47 BR47	NC NC		IO_L8P_T1L_N2_AD5P_19	IO_L8P_T1L_N2_AD5P_19
100	U1_XF.BR48 BR48	NC NC		IO_L8N_T1L_N3_AD5N_19	IO_L8N_T1L_N3_AD5N_19
-	U1_XF.BR49 BR49	UNNAMED_21_RESISTOR_I32_B_XF UNNAMED_21_RESISTOR_I32_B_XF ->R30_XF->GND		VREF_22	VREF_22
-	U1_XF.BR50 BR50	UNNAMED_21_RESISTOR_I33_B_XF UNNAMED_21_RESISTOR_I33_B_XF ->R29_XF->GND		IO_T0U_N12_VRP_22	IO_T0U_N12_VRP_22
100	U1_XF.BR51 BR51	GND GND	0V	GND	GND
35	U1_XF.BR52 BR52	C1_DDR4_DQ<13>_XF C1_DDR4_DQ<13>_XF		c1_ddr4_dq[30]	IO_L2P_T0L_N2_22
35	U1_XF.BR53 BR53	C1_DDR4_DQ<12>_XF C1_DDR4_DQ<12>_XF		c1_ddr4_dq[31]	IO_L2N_T0L_N3_22
100	U1_XF.BR54 BR54	NC NC		IO_T1U_N12_22	IO_T1U_N12_22
16	U1_XF.BR55 BR55	C1_RDIMM_DQS_C<11>_XF C1_RDIMM_DQS_C<11>_XF		c1_ddr4_dqs_c[5]	IO_L7N_T1L_N1_QBC_AD13N_22
-	U1_XF.BR56 BR56	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_22	VCCO_22	1.2
16	U1_XF.BR57 BR57	C1_RDIMM_DQS_T<17>_XF C1_RDIMM_DQS_T<17>_XF		c1_ddr4_dqs_t[3]	IO_L13P_T2L_N0_GC_QBC_22
16	U1_XF.BR58 BR58	C1_RDIMM_DQS_C<17>_XF C1_RDIMM_DQS_C<17>_XF		c1_ddr4_dqs_c[3]	IO_L13N_T2L_N1_GC_QBC_22
36	U1_XF.BR59 BR59	C1_DDR4_DQ<64>_XF C1_DDR4_DQ<64>_XF		c1_ddr4_dq[8]	IO_L17N_T2U_N9_AD10N_22
100	U1_XF.BR60 BR60	NC NC		IO_T2U_N12_22	IO_T2U_N12_22
100	U1_XF.BR61 BR61	GND GND	0V	GND	GND
36	U1_XF.BR62 BR62	C1_DDR4_DQ<32>_XF C1_DDR4_DQ<32>_XF		c1_ddr4_dq[0]	IO_L24P_T3U_N10_22
36	U1_XF.BR63 BR63	C1_DDR4_DQ<33>_XF C1_DDR4_DQ<33>_XF		c1_ddr4_dq[1]	IO_L24N_T3U_N11_22
100	U1_XF.BT1 BT1	GND GND	0V	GND	GND
100	U1_XF.BT2 BT2	GND GND	0V	GND	GND
95	U1_XF.BT3 BT3	OCL1_PER_N<2>_XF OCL1_PER_N<2>_XF		ocl1_per_n[2]	MGTYRXN2_220
95	U1_XF.BT4 BT4	OCL1_PER_P<2>_XF OCL1_PER_P<2>_XF		ocl1_per_p[2]	MGTYRXP2_220
100	U1_XF.BT5 BT5	GND GND	0V	GND	GND
100	U1_XF.BT6 BT6	GND GND	0V	GND	GND
100	U1_XF.BT7 BT7	GND GND	0V	GND	GND
100	U1_XF.BT8 BT8	NC NC		MGTYTXN1_221	MGTYTXN1_221
100	U1_XF.BT9 BT9	NC NC		MGTYTXP1_221	MGTYTXP1_221
100	U1_XF.BT10 BT10	GND GND	0V	GND	GND
23	U1_XF.BT11 BT11	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
85	U1_XF.BT12 BT12	OCL1_FPGA_REFCLK_N_XF OCL1_FPGA_REFCLK_N_XF		ocl1_refclk_n	MGTREFCLK0N_220
85	U1_XF.BT13 BT13	OCL1_FPGA_REFCLK_P_XF OCL1_FPGA_REFCLK_P_XF		ocl1_refclk_p	MGTREFCLK0P_220
100	U1_XF.BT14 BT14	GND GND	0V	GND	GND
16	U1_XF.BT15 BT15	C0_RDIMM_DQS_C<2>_XF C0_RDIMM_DQS_C<2>_XF		c0_ddr4_dqs_c[14]	IO_L22N_T3U_N7_DBC_AD0N_60
35	U1_XF.BT16 BT16	C0_DDR4_DQ<17>_XF C0_DDR4_DQ<17>_XF		c0_ddr4_dq[57]	IO_L23N_T3U_N9_60
35	U1_XF.BT17 BT17	C0_DDR4_DQ<16>_XF C0_DDR4_DQ<16>_XF		c0_ddr4_dq[56]	IO_L23P_T3U_N8_60
35	U1_XF.BT18 BT18	C0_DDR4_DQ<21>_XF C0_DDR4_DQ<21>_XF		c0_ddr4_dq[61]	IO_L20N_T3L_N3_AD1N_60
100	U1_XF.BT19 BT19	GND GND	0V	GND	GND
95	U1_XF.BT20 BT20	C0_DDR4_CKE<1>_XF C0_DDR4_CKE<1>_XF		c0_ddr4_cke[1]	IO_L16N_T2U_N7_QBC_AD3N_60
-	U1_XF.BT21 BT21	UNNAMED_22_RESISTOR_I43_B_XF UNNAMED_22_RESISTOR_I43_B_XF ->R58_XF->GND		VREF_60	VREF_60
16	U1_XF.BT22 BT22	C0_RDIMM_DQS_C<3>_XF C0_RDIMM_DQS_C<3>_XF		c0_ddr4_dqs_c[4]	IO_L4N_T0U_N7_DBC_AD7N_62
16	U1_XF.BT23 BT23	C0_RDIMM_DQS_T<3>_XF C0_RDIMM_DQS_T<3>_XF		c0_ddr4_dqs_t[4]	IO_L4P_T0U_N6_DBC_AD7P_62
100	U1_XF.BT24 BT24	GND GND	0V	GND	GND
35	U1_XF.BT25 BT25	C0_DDR4_DQ<26>_XF C0_DDR4_DQ<26>_XF		c0_ddr4_dq[19]	IO_L6P_T0U_N10_AD6P_62
36	U1_XF.BT26 BT26	C0_DDR4_DQ<71>_XF C0_DDR4_DQ<71>_XF		c0_ddr4_dq[4]	IO_L21P_T3L_N4_AD8P_62
36	U1_XF.BT27 BT27	C0_DDR4_DQ<64>_XF C0_DDR4_DQ<64>_XF		c0_ddr4_dq[1]	IO_L24N_T3U_N11_62
36	U1_XF.BT28 BT28	C0_DDR4_DQ<65>_XF C0_DDR4_DQ<65>_XF		c0_ddr4_dq[0]	IO_L24P_T3U_N10_62
100	U1_XF.BT29 BT29	GND GND	0V	GND	GND
96	U1_XF.BT30 BT30	FPGA_CPLD_RSVD<0>_1 FPGA_CPLD_RSVD<0>_1		fpga_cpld_rsvd[0]	IO_L4N_T0U_N7_DBC_AD7N_A25_65
100	U1_XF.BT31 BT31	NC NC		IO_L4P_T0U_N6_DBC_AD7P_A24_65	IO_L4P_T0U_N6_DBC_AD7P_A24_65
96	U1_XF.BT32 BT32	FPGA_CPLD_RSVD<2>_1 FPGA_CPLD_RSVD<2>_1		fpga_cpld_rsvd[2]	IO_L3N_T0L_N5_AD15N_A27_65
96	U1_XF.BT33 BT33	FPGA_CPLD_RSVD<1>_1 FPGA_CPLD_RSVD<1>_1		fpga_cpld_rsvd[1]	IO_L3P_T0L_N4_AD15P_A26_65
100	U1_XF.BT34 BT34	GND GND	0V	GND	GND
100	U1_XF.BT35 BT35	NC NC		IO_L6P_T0U_N10_AD6P_67	IO_L6P_T0U_N10_AD6P_67
100	U1_XF.BT36 BT36	NC NC		IO_L6N_T0U_N11_AD6N_67	IO_L6N_T0U_N11_AD6N_67
100	U1_XF.BT37 BT37	NC NC		IO_L3P_T0L_N4_AD15P_67	IO_L3P_T0L_N4_AD15P_67
100	U1_XF.BT38 BT38	NC NC		IO_L3N_T0L_N5_AD15N_67	IO_L3N_T0L_N5_AD15N_67
100	U1_XF.BT39 BT39	GND GND	0V	GND	GND
100	U1_XF.BT40 BT40	NC NC		IO_L1P_T0L_N0_DBC_67	IO_L1P_T0L_N0_DBC_67
100	U1_XF.BT41 BT41	NC NC		IO_L7P_T1L_N0_QBC_AD13P_20	IO_L7P_T1L_N0_QBC_AD13P_20
100	U1_XF.BT42 BT42	NC NC		IO_L7N_T1L_N1_QBC_AD13N_20	IO_L7N_T1L_N1_QBC_AD13N_20
100	U1_XF.BT43 BT43	NC NC		IO_T1U_N12_20	IO_T1U_N12_20
100	U1_XF.BT44 BT44	GND GND	0V	GND	GND
100	U1_XF.BT45 BT45	NC NC		IO_L1P_T0L_N0_DBC_20	IO_L1P_T0L_N0_DBC_20
100	U1_XF.BT46 BT46	NC NC		VREF_20	VREF_20
100	U1_XF.BT47 BT47	NC NC		IO_L5P_T0U_N8_AD14P_20	IO_L5P_T0U_N8_AD14P_20
100	U1_XF.BT48 BT48	NC NC		IO_L5N_T0U_N9_AD14N_20	IO_L5N_T0U_N9_AD14N_20
100	U1_XF.BT49 BT49	GND GND	0V	GND	GND
16	U1_XF.BT50 BT50	C1_RDIMM_DQS_T<1>_XF C1_RDIMM_DQS_T<1>_XF		c1_ddr4_dqs_t[6]	IO_L4P_T0U_N6_DBC_AD7P_22
54	U1_XF.BT51 BT51	C1_RDIMM_DQS_C<1>_XF C1_RDIMM_DQS_C<1>_XF		c1_ddr4_dqs_c[6]	IO_L4N_T0U_N7_DBC_AD7N_22
37	U1_XF.BT52 BT52	C1_DDR4_DQ<8>_XF C1_DDR4_DQ<8>_XF		c1_ddr4_dq[24]	IO_L6P_T0U_N10_AD6P_22
37	U1_XF.BT53 BT53	C1_DDR4_DQ<9>_XF C1_DDR4_DQ<9>_XF		c1_ddr4_dq[25]	IO_L6N_T0U_N11_AD6N_22
100	U1_XF.BT54 BT54	GND GND	0V	GND	GND
95	U1_XF.BT55 BT55	C1_DDR4_DQ<17>_XF C1_DDR4_DQ<17>_XF		c1_ddr4_dq[17]	IO_L12P_T1U_N10_GC_22
95	U1_XF.BT56 BT56	C1_DDR4_DQ<16>_XF C1_DDR4_DQ<16>_XF		c1_ddr4_dq[16]	IO_L11P_T1U_N8_GC_22
35	U1_XF.BT57 BT57	C1_DDR4_DQ<71>_XF C1_DDR4_DQ<71>_XF		c1_ddr4_dq[15]	IO_L14P_T2L_N2_GC_22
35	U1_XF.BT58 BT58	C1_DDR4_DQ<70>_XF C1_DDR4_DQ<70>_XF		c1_ddr4_dq[14]	IO_L14N_T2L_N3_GC_22
-	U1_XF.BT59 BT59	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_22	VCCO_22	1.2
35	U1_XF.BT60 BT60	C1_DDR4_DQ<66>_XF C1_DDR4_DQ<66>_XF		c1_ddr4_dq[10]	IO_L18P_T2U_N10_AD2P_22
36	U1_XF.BT61 BT61	C1_DDR4_DQ<38>_XF C1_DDR4_DQ<38>_XF		c1_ddr4_dq[6]	IO_L20P_T3L_N2_AD1P_22
16	U1_XF.BT62 BT62	C1_RDIMM_DQS_T<4>_XF C1_RDIMM_DQS_T<4>_XF		c1_ddr4_dqs_t[0]	IO_L22P_T3U_N6_DBC_AD0P_22
16	U1_XF.BT63 BT63	C1_RDIMM_DQS_C<4>_XF C1_RDIMM_DQS_C<4>_XF		c1_ddr4_dqs_c[0]	IO_L22N_T3U_N7_DBC_AD0N_22
95	U1_XF.BU1 BU1	OCL1_PER_N<1>_XF OCL1_PER_N<1>_XF		ocl1_per_n[1]	MGTYRXN1_220
95	U1_XF.BU2 BU2	OCL1_PER_P<1>_XF OCL1_PER_P<1>_XF		ocl1_per_p[1]	MGTYRXP1_220
100	U1_XF.BU3 BU3	GND GND	0V	GND	GND
100	U1_XF.BU4 BU4	GND GND	0V	GND	GND
95	U1_XF.BU5 BU5	OCL1_PER_N<0>_XF OCL1_PER_N<0>_XF		ocl1_per_n[0]	MGTYRXN0_220
95	U1_XF.BU6 BU6	OCL1_PER_P<0>_XF OCL1_PER_P<0>_XF		ocl1_per_p[0]	MGTYRXP0_220
100	U1_XF.BU7 BU7	GND GND	0V	GND	GND
100	U1_XF.BU8 BU8	GND GND	0V	GND	GND
23	U1_XF.BU9 BU9	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
100	U1_XF.BU10 BU10	NC NC		MGTYTXN0_221	MGTYTXN0_221
100	U1_XF.BU11 BU11	NC NC		MGTYTXP0_221	MGTYTXP0_221
100	U1_XF.BU12 BU12	GND GND	0V	GND	GND
18	U1_XF.BU13 BU13	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RS	MGTAVCC_RS	0.9
100	U1_XF.BU14 BU14	GND GND	0V	GND	GND
35	U1_XF.BU15 BU15	C0_DDR4_DQ<23>_XF C0_DDR4_DQ<23>_XF		c0_ddr4_dq[63]	IO_L21N_T3L_N5_AD8N_60
35	U1_XF.BU16 BU16	C0_DDR4_DQ<22>_XF C0_DDR4_DQ<22>_XF		c0_ddr4_dq[62]	IO_L21P_T3L_N4_AD8P_60
-	U1_XF.BU17 BU17	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_60	VCCO_60	1.2
16	U1_XF.BU18 BU18	C0_RDIMM_DQS_T<11>_XF C0_RDIMM_DQS_T<11>_XF		c0_ddr4_dqs_t[15]	IO_L19P_T3L_N0_DBC_AD9P_60
95	U1_XF.BU19 BU19	C0_DDR4_ADR<12>_XF C0_DDR4_ADR<12>_XF		c0_ddr4_adr[12]	IO_L14P_T2L_N2_GC_60
95	U1_XF.BU20 BU20	C0_DDR4_ACT_N_XF C0_DDR4_ACT_N_XF		c0_ddr4_act_n	IO_L17N_T2U_N9_AD10N_60
20	U1_XF.BU21 BU21	C0_DDR4_CKE<0>_XF C0_DDR4_CKE<0>_XF		c0_ddr4_adr[8]	IO_L17P_T2U_N8_AD10P_60
100	U1_XF.BU22 BU22	GND GND	0V	GND	GND
16	U1_XF.BU23 BU23	C0_RDIMM_DQS_C<12>_XF C0_RDIMM_DQS_C<12>_XF		c0_ddr4_dqs_c[5]	IO_L1N_T0L_N1_DBC_62
16	U1_XF.BU24 BU24	C0_RDIMM_DQS_T<12>_XF C0_RDIMM_DQS_T<12>_XF		c0_ddr4_dqs_t[5]	IO_L1P_T0L_N0_DBC_62
35	U1_XF.BU25 BU25	C0_DDR4_DQ<27>_XF C0_DDR4_DQ<27>_XF		c0_ddr4_dq[18]	IO_L6N_T0U_N11_AD6N_62
36	U1_XF.BU26 BU26	C0_DDR4_DQ<69>_XF C0_DDR4_DQ<69>_XF		c0_ddr4_dq[5]	IO_L21N_T3L_N5_AD8N_62
-	U1_XF.BU27 BU27	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_62	VCCO_62	1.2
16	U1_XF.BU28 BU28	C0_RDIMM_DQS_T<8>_XF C0_RDIMM_DQS_T<8>_XF		c0_ddr4_dqs_t[0]	IO_L22P_T3U_N6_DBC_AD0P_62
100	U1_XF.BU29 BU29	NC NC		IO_L2N_T0L_N3_FWE_FCS2_B_65	IO_L2N_T0L_N3_FWE_FCS2_B_65
96	U1_XF.BU30 BU30	FPGA_CPLD_RSVD<3>_1 FPGA_CPLD_RSVD<3>_1		fpga_cpld_rsvd[3]	IO_L2P_T0L_N2_FOE_B_65
100	U1_XF.BU31 BU31	NC NC		IO_L6P_T0U_N10_AD6P_A20_65	IO_L6P_T0U_N10_AD6P_A20_65
100	U1_XF.BU32 BU32	GND GND	0V	GND	GND
96	U1_XF.BU33 BU33	FPGA_CPLD_DQ<0>_1 FPGA_CPLD_DQ<0>_1		fpga_cpld_dq[0]	IO_L1N_T0L_N1_DBC_RS1_65
96	U1_XF.BU34 BU34	FPGA_CPLD_DVAL_1 FPGA_CPLD_DVAL_1		fpga_cpld_dval	IO_L1P_T0L_N0_DBC_RS0_65
100	U1_XF.BU35 BU35	NC NC		IO_L2P_T0L_N2_67	IO_L2P_T0L_N2_67
100	U1_XF.BU36 BU36	NC NC		IO_L2N_T0L_N3_67	IO_L2N_T0L_N3_67
100	U1_XF.BU37 BU37	GND GND	0V	GND	GND
100	U1_XF.BU38 BU38	NC NC		IO_L4P_T0U_N6_DBC_AD7P_67	IO_L4P_T0U_N6_DBC_AD7P_67
100	U1_XF.BU39 BU39	NC NC		IO_L4N_T0U_N7_DBC_AD7N_67	IO_L4N_T0U_N7_DBC_AD7N_67
100	U1_XF.BU40 BU40	NC NC		IO_L1N_T0L_N1_DBC_67	IO_L1N_T0L_N1_DBC_67
100	U1_XF.BU41 BU41	NC NC		IO_L8P_T1L_N2_AD5P_20	IO_L8P_T1L_N2_AD5P_20
100	U1_XF.BU42 BU42	NC NC		VCCO_20	VCCO_20	1.8
100	U1_XF.BU43 BU43	NC NC		IO_L9P_T1L_N4_AD12P_20	IO_L9P_T1L_N4_AD12P_20
100	U1_XF.BU44 BU44	NC NC		IO_L9N_T1L_N5_AD12N_20	IO_L9N_T1L_N5_AD12N_20
100	U1_XF.BU45 BU45	NC NC		IO_L1N_T0L_N1_DBC_20	IO_L1N_T0L_N1_DBC_20
100	U1_XF.BU46 BU46	NC NC		IO_L3P_T0L_N4_AD15P_20	IO_L3P_T0L_N4_AD15P_20
100	U1_XF.BU47 BU47	GND GND	0V	GND	GND
100	U1_XF.BU48 BU48	NC NC		IO_L2P_T0L_N2_20	IO_L2P_T0L_N2_20
100	U1_XF.BU49 BU49	NC NC		IO_L2N_T0L_N3_20	IO_L2N_T0L_N3_20
16	U1_XF.BU50 BU50	C1_RDIMM_DQS_T<10>_XF C1_RDIMM_DQS_T<10>_XF		c1_ddr4_dqs_t[7]	IO_L1P_T0L_N0_DBC_22
16	U1_XF.BU51 BU51	C1_RDIMM_DQS_C<10>_XF C1_RDIMM_DQS_C<10>_XF		c1_ddr4_dqs_c[7]	IO_L1N_T0L_N1_DBC_22
-	U1_XF.BU52 BU52	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_22	VCCO_22	1.2
35	U1_XF.BU53 BU53	C1_DDR4_DQ<11>_XF C1_DDR4_DQ<11>_XF		c1_ddr4_dq[27]	IO_L5P_T0U_N8_AD14P_22
35	U1_XF.BU54 BU54	C1_DDR4_DQ<20>_XF C1_DDR4_DQ<20>_XF		c1_ddr4_dq[23]	IO_L8P_T1L_N2_AD5P_22
95	U1_XF.BU55 BU55	C1_DDR4_DQ<18>_XF C1_DDR4_DQ<18>_XF		c1_ddr4_dq[18]	IO_L12N_T1U_N11_GC_22
95	U1_XF.BU56 BU56	C1_DDR4_DQ<19>_XF C1_DDR4_DQ<19>_XF		c1_ddr4_dq[19]	IO_L11N_T1U_N9_GC_22
100	U1_XF.BU57 BU57	GND GND	0V	GND	GND
35	U1_XF.BU58 BU58	C1_DDR4_DQ<68>_XF C1_DDR4_DQ<68>_XF		c1_ddr4_dq[12]	IO_L15P_T2L_N4_AD11P_22
16	U1_XF.BU59 BU59	C1_RDIMM_DQS_T<8>_XF C1_RDIMM_DQS_T<8>_XF		c1_ddr4_dqs_t[2]	IO_L16P_T2U_N6_QBC_AD3P_22
36	U1_XF.BU60 BU60	C1_DDR4_DQ<65>_XF C1_DDR4_DQ<65>_XF		c1_ddr4_dq[9]	IO_L18N_T2U_N11_AD2N_22
36	U1_XF.BU61 BU61	C1_DDR4_DQ<39>_XF C1_DDR4_DQ<39>_XF		c1_ddr4_dq[7]	IO_L20N_T3L_N3_AD1N_22
100	U1_XF.BU62 BU62	GND GND	0V	GND	GND
36	U1_XF.BU63 BU63	C1_DDR4_DQ<37>_XF C1_DDR4_DQ<37>_XF		c1_ddr4_dq[5]	IO_L21P_T3L_N4_AD8P_22
100	U1_XF.BV1 BV1	GND GND	0V	GND	GND
100	U1_XF.BV2 BV2	GND GND	0V	GND	GND
95	U1_XF.BV3 BV3	OCL0_PER_N<3>_XF OCL0_PER_N<3>_XF		ocl0_per_n[3]	MGTYRXN3_219
95	U1_XF.BV4 BV4	OCL0_PER_P<3>_XF OCL0_PER_P<3>_XF		ocl0_per_p[3]	MGTYRXP3_219
100	U1_XF.BV5 BV5	GND GND	0V	GND	GND
100	U1_XF.BV6 BV6	GND GND	0V	GND	GND
100	U1_XF.BV7 BV7	GND GND	0V	GND	GND
92	U1_XF.BV8 BV8	AC_OCL1_PET_N<3>_XF AC_OCL1_PET_N<3>_XF		ocl1_pet_n[3]	MGTYTXN3_220
92	U1_XF.BV9 BV9	AC_OCL1_PET_P<3>_XF AC_OCL1_PET_P<3>_XF		ocl1_pet_p[3]	MGTYTXP3_220
100	U1_XF.BV10 BV10	GND GND	0V	GND	GND
23	U1_XF.BV11 BV11	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
95	U1_XF.BV12 BV12	MGTRREF_RS_XF MGTRREF_RS_XF		MGTRREF_RS	MGTRREF_RS
23	U1_XF.BV13 BV13	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTTRCAL_RS	MGTAVTTRCAL_RS	1.2
100	U1_XF.BV14 BV14	GND GND	0V	GND	GND
100	U1_XF.BV15 BV15	GND GND	0V	GND	GND
95	U1_XF.BV16 BV16	C0_DDR4_CK_T<0>_XF C0_DDR4_CK_T<0>_XF		c0_ddr4_ck_t[0]	IO_L4P_T0U_N6_DBC_AD7P_60
95	U1_XF.BV17 BV17	C0_DDR4_RESET_N_XF C0_DDR4_RESET_N_XF		c0_ddr4_reset_n	IO_T3U_N12_60
16	U1_XF.BV18 BV18	C0_RDIMM_DQS_C<11>_XF C0_RDIMM_DQS_C<11>_XF		c0_ddr4_dqs_c[15]	IO_L19N_T3L_N1_DBC_AD9N_60
95	U1_XF.BV19 BV19	C0_DDR4_ADR<9>_XF C0_DDR4_ADR<9>_XF		c0_ddr4_adr[9]	IO_L14N_T2L_N3_GC_60
100	U1_XF.BV20 BV20	GND GND	0V	GND	GND
20	U1_XF.BV21 BV21	C0_DDR4_BG<1>_XF C0_DDR4_BG<1>_XF		c0_ddr4_cke[0]	IO_L15P_T2L_N4_AD11P_60
35	U1_XF.BV22 BV22	C0_DDR4_DQ<25>_XF C0_DDR4_DQ<25>_XF		c0_ddr4_dq[17]	IO_L5P_T0U_N8_AD14P_62
35	U1_XF.BV23 BV23	C0_DDR4_DQ<29>_XF C0_DDR4_DQ<29>_XF		c0_ddr4_dq[21]	IO_L3N_T0L_N5_AD15N_62
35	U1_XF.BV24 BV24	C0_DDR4_DQ<31>_XF C0_DDR4_DQ<31>_XF		c0_ddr4_dq[20]	IO_L3P_T0L_N4_AD15P_62
100	U1_XF.BV25 BV25	GND GND	0V	GND	GND
36	U1_XF.BV26 BV26	C0_DDR4_DQ<68>_XF C0_DDR4_DQ<68>_XF		c0_ddr4_dq[7]	IO_L20N_T3L_N3_AD1N_62
36	U1_XF.BV27 BV27	C0_DDR4_DQ<70>_XF C0_DDR4_DQ<70>_XF		c0_ddr4_dq[6]	IO_L20P_T3L_N2_AD1P_62
24	U1_XF.BV28 BV28	C0_RDIMM_DQS_C<8>_XF C0_RDIMM_DQS_C<8>_XF		c0_ddr4_dqs_c[0]	IO_L22N_T3U_N7_DBC_AD0N_62
-	U1_XF.BV29 BV29	UNNAMED_22_RESISTOR_I48_B_XF UNNAMED_22_RESISTOR_I48_B_XF ->R57_XF->GND		IO_T0U_N12_VRP_A28_65	IO_T0U_N12_VRP_A28_65
100	U1_XF.BV30 BV30	GND GND	0V	GND	GND
100	U1_XF.BV31 BV31	NC NC		IO_L6N_T0U_N11_AD6N_A21_65	IO_L6N_T0U_N11_AD6N_A21_65
-	U1_XF.BV32 BV32	UNNAMED_22_RESISTOR_I60_B_XF UNNAMED_22_RESISTOR_I60_B_XF ->R159_XF->GND		VREF_66	VREF_66
98	U1_XF.BV33 BV33	CPLD_FPGA_DQ<1> CPLD_FPGA_DQ<1>		cpld_fpga_dq[1]	IO_L9P_T1L_N4_AD12P_66
98	U1_XF.BV34 BV34	CPLD_FPGA_DQ<0> CPLD_FPGA_DQ<0>		cpld_fpga_dq[0]	IO_L9N_T1L_N5_AD12N_66
100	U1_XF.BV35 BV35	GND GND	0V	GND	GND
-	U1_XF.BV36 BV36	UNNAMED_17_BYPASSCAPNPOL_I58_A_XF UNNAMED_17_BYPASSCAPNPOL_I58_A_XF ->C146_XF->UNNAMED_17_BYPASSCAPNPOL_I58_B_XF ->R97_XF->UNNAMED_17_RESISTOR_I61_A_XF		vaux_p[3]	IO_L16P_T2U_N6_QBC_AD3P_66
100	U1_XF.BV37 BV37	FPGA_CPLD_SSTAT_CLK FPGA_CPLD_SSTAT_CLK		fpga_cpld_sstat_clk	IO_L17P_T2U_N8_AD10P_66
100	U1_XF.BV38 BV38	NC NC		IO_L23P_T3U_N8_66	IO_L23P_T3U_N8_66
93	U1_XF.BV39 BV39	FPGA_DCM_LOCK_F FPGA_DCM_LOCK_F		dcm_lock_f	IO_L23N_T3U_N9_66
100	U1_XF.BV40 BV40	GND GND	0V	GND	GND
100	U1_XF.BV41 BV41	NC NC		IO_L8N_T1L_N3_AD5N_20	IO_L8N_T1L_N3_AD5N_20
100	U1_XF.BV42 BV42	NC NC		IO_L11P_T1U_N8_GC_20	IO_L11P_T1U_N8_GC_20
100	U1_XF.BV43 BV43	NC NC		IO_L11N_T1U_N9_GC_20	IO_L11N_T1U_N9_GC_20
100	U1_XF.BV44 BV44	NC NC		IO_L12P_T1U_N10_GC_20	IO_L12P_T1U_N10_GC_20
100	U1_XF.BV45 BV45	NC NC		VCCO_20	VCCO_20	1.8
100	U1_XF.BV46 BV46	NC NC		IO_L3N_T0L_N5_AD15N_20	IO_L3N_T0L_N5_AD15N_20
100	U1_XF.BV47 BV47	NC NC		IO_L4P_T0U_N6_DBC_AD7P_20	IO_L4P_T0U_N6_DBC_AD7P_20
100	U1_XF.BV48 BV48	NC NC		IO_L4N_T0U_N7_DBC_AD7N_20	IO_L4N_T0U_N7_DBC_AD7N_20
-	U1_XF.BV49 BV49	UNNAMED_21_RESISTOR_I39_B_XF UNNAMED_21_RESISTOR_I39_B_XF ->R32_XF->GND		VREF_21	VREF_21
100	U1_XF.BV50 BV50	GND GND	0V	GND	GND
35	U1_XF.BV51 BV51	C1_DDR4_DQ<15>_XF C1_DDR4_DQ<15>_XF		c1_ddr4_dq[28]	IO_L3P_T0L_N4_AD15P_22
35	U1_XF.BV52 BV52	C1_DDR4_DQ<14>_XF C1_DDR4_DQ<14>_XF		c1_ddr4_dq[29]	IO_L3N_T0L_N5_AD15N_22
35	U1_XF.BV53 BV53	C1_DDR4_DQ<10>_XF C1_DDR4_DQ<10>_XF		c1_ddr4_dq[26]	IO_L5N_T0U_N9_AD14N_22
35	U1_XF.BV54 BV54	C1_DDR4_DQ<21>_XF C1_DDR4_DQ<21>_XF		c1_ddr4_dq[22]	IO_L8N_T1L_N3_AD5N_22
100	U1_XF.BV55 BV55	GND GND	0V	GND	GND
16	U1_XF.BV56 BV56	C1_RDIMM_DQS_T<2>_XF C1_RDIMM_DQS_T<2>_XF		c1_ddr4_dqs_t[4]	IO_L10P_T1U_N6_QBC_AD4P_22
16	U1_XF.BV57 BV57	C1_RDIMM_DQS_C<2>_XF C1_RDIMM_DQS_C<2>_XF		c1_ddr4_dqs_c[4]	IO_L10N_T1U_N7_QBC_AD4N_22
35	U1_XF.BV58 BV58	C1_DDR4_DQ<69>_XF C1_DDR4_DQ<69>_XF		c1_ddr4_dq[13]	IO_L15N_T2L_N5_AD11N_22
16	U1_XF.BV59 BV59	C1_RDIMM_DQS_C<8>_XF C1_RDIMM_DQS_C<8>_XF		c1_ddr4_dqs_c[2]	IO_L16N_T2U_N7_QBC_AD3N_22
100	U1_XF.BV60 BV60	GND GND	0V	GND	GND
16	U1_XF.BV61 BV61	C1_RDIMM_DQS_T<13>_XF C1_RDIMM_DQS_T<13>_XF		c1_ddr4_dqs_t[1]	IO_L19P_T3L_N0_DBC_AD9P_22
24	U1_XF.BV62 BV62	C1_RDIMM_DQS_C<13>_XF C1_RDIMM_DQS_C<13>_XF		c1_ddr4_dqs_c[1]	IO_L19N_T3L_N1_DBC_AD9N_22
36	U1_XF.BV63 BV63	C1_DDR4_DQ<36>_XF C1_DDR4_DQ<36>_XF		c1_ddr4_dq[4]	IO_L21N_T3L_N5_AD8N_22
95	U1_XF.BW1 BW1	OCL0_PER_N<2>_XF OCL0_PER_N<2>_XF		ocl0_per_n[2]	MGTYRXN2_219
95	U1_XF.BW2 BW2	OCL0_PER_P<2>_XF OCL0_PER_P<2>_XF		ocl0_per_p[2]	MGTYRXP2_219
100	U1_XF.BW3 BW3	GND GND	0V	GND	GND
100	U1_XF.BW4 BW4	GND GND	0V	GND	GND
95	U1_XF.BW5 BW5	OCL0_PER_N<1>_XF OCL0_PER_N<1>_XF		ocl0_per_n[1]	MGTYRXN1_219
95	U1_XF.BW6 BW6	OCL0_PER_P<1>_XF OCL0_PER_P<1>_XF		ocl0_per_p[1]	MGTYRXP1_219
100	U1_XF.BW7 BW7	GND GND	0V	GND	GND
100	U1_XF.BW8 BW8	GND GND	0V	GND	GND
23	U1_XF.BW9 BW9	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
92	U1_XF.BW10 BW10	AC_OCL1_PET_N<2>_XF AC_OCL1_PET_N<2>_XF		ocl1_pet_n[2]	MGTYTXN2_220
92	U1_XF.BW11 BW11	AC_OCL1_PET_P<2>_XF AC_OCL1_PET_P<2>_XF		ocl1_pet_p[2]	MGTYTXP2_220
100	U1_XF.BW12 BW12	GND GND	0V	GND	GND
18	U1_XF.BW13 BW13	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RS	MGTAVCC_RS	0.9
100	U1_XF.BW14 BW14	GND GND	0V	GND	GND
44	U1_XF.BW15 BW15	C0_DDR4_ADR<13>_XF C0_DDR4_ADR<13>_XF		c0_ddr4_adr[1]	IO_L2P_T0L_N2_60
89	U1_XF.BW16 BW16	C0_DDR4_CK_C<0>_XF C0_DDR4_CK_C<0>_XF		c0_ddr4_ck_c[0]	IO_L4N_T0U_N7_DBC_AD7N_60
95	U1_XF.BW17 BW17	C0_DDR4_ADR<5>_XF C0_DDR4_ADR<5>_XF		c0_ddr4_adr[5]	IO_L6P_T0U_N10_AD6P_60
100	U1_XF.BW18 BW18	GND GND	0V	GND	GND
20	U1_XF.BW19 BW19	C0_DDR4_ADR<6>_XF C0_DDR4_ADR<6>_XF		c0_ddr4_odt[1]	IO_L13N_T2L_N1_GC_QBC_60
20	U1_XF.BW20 BW20	C0_DDR4_ADR<8>_XF C0_DDR4_ADR<8>_XF		c0_ddr4_bg[1]	IO_L13P_T2L_N0_GC_QBC_60
95	U1_XF.BW21 BW21	C0_DDR4_BG<0>_XF C0_DDR4_BG<0>_XF		c0_ddr4_bg[0]	IO_L15N_T2L_N5_AD11N_60
35	U1_XF.BW22 BW22	C0_DDR4_DQ<24>_XF C0_DDR4_DQ<24>_XF		c0_ddr4_dq[16]	IO_L5N_T0U_N9_AD14N_62
-	U1_XF.BW23 BW23	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_62	VCCO_62	1.2
37	U1_XF.BW24 BW24	C0_DDR4_DQ<0>_XF C0_DDR4_DQ<0>_XF		c0_ddr4_dq[24]	IO_L12N_T1U_N11_GC_62
37	U1_XF.BW25 BW25	C0_DDR4_DQ<1>_XF C0_DDR4_DQ<1>_XF		c0_ddr4_dq[25]	IO_L12P_T1U_N10_GC_62
16	U1_XF.BW26 BW26	C0_RDIMM_DQS_C<17>_XF C0_RDIMM_DQS_C<17>_XF		c0_ddr4_dqs_c[1]	IO_L19N_T3L_N1_DBC_AD9N_62
16	U1_XF.BW27 BW27	C0_RDIMM_DQS_T<17>_XF C0_RDIMM_DQS_T<17>_XF		c0_ddr4_dqs_t[1]	IO_L19P_T3L_N0_DBC_AD9P_62
100	U1_XF.BW28 BW28	GND GND	0V	GND	GND
23	U1_XF.BW29 BW29	FPGA_1R8V_SDA FPGA_1R8V_SDA	1.8V	mst_slv_i2c_sda	IO_L2P_T0L_N2_66
23	U1_XF.BW30 BW30	FPGA_1R8V_SCL FPGA_1R8V_SCL	1.8V	mst_slv_i2c_scl	IO_L2N_T0L_N3_66
-	U1_XF.BW31 BW31	UNNAMED_17_BYPASSCAPNPOL_I116_A_XF UNNAMED_17_BYPASSCAPNPOL_I116_A_XF ->R129_XF->UNNAMED_17_RESISTOR_I110_A_XF ->C268_XF->UNNAMED_17_BYPASSCAPNPOL_I116_B_XF		vaux_p[6]	IO_L6P_T0U_N10_AD6P_66
-	U1_XF.BW32 BW32	UNNAMED_17_BYPASSCAPNPOL_I116_B_XF UNNAMED_17_BYPASSCAPNPOL_I116_B_XF ->R130_XF->UNNAMED_17_RESISTOR_I113_A_XF ->C268_XF->UNNAMED_17_BYPASSCAPNPOL_I116_A_XF		vaux_n[6]	IO_L6N_T0U_N11_AD6N_66
100	U1_XF.BW33 BW33	GND GND	0V	GND	GND
100	U1_XF.BW34 BW34	CPLD_FPGA_SSTAT_CLK CPLD_FPGA_SSTAT_CLK		cpld_fpga_sstat_clk	IO_L12P_T1U_N10_GC_66
62	U1_XF.BW35 BW35	CLK125M_FROM_CPLD CLK125M_FROM_CPLD		clk125_from_cpld	IO_L11P_T1U_N8_GC_66
-	U1_XF.BW36 BW36	UNNAMED_17_BYPASSCAPNPOL_I58_B_XF UNNAMED_17_BYPASSCAPNPOL_I58_B_XF ->C146_XF->UNNAMED_17_BYPASSCAPNPOL_I58_A_XF ->R98_XF->UNNAMED_17_RESISTOR_I95_B_XF		vaux_n[3]	IO_L16N_T2U_N7_QBC_AD3N_66
100	U1_XF.BW37 BW37	NC NC		IO_L17N_T2U_N9_AD10N_66	IO_L17N_T2U_N9_AD10N_66
88	U1_XF.BW38 BW38	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCO_66	VCCO_66	1.8
-	U1_XF.BW39 BW39	UNNAMED_17_BYPASSCAPNPOL_I198_A_XF UNNAMED_17_BYPASSCAPNPOL_I198_A_XF ->R25_XF->UNNAMED_17_RESISTOR_I196_A_XF ->C315_XF->UNNAMED_17_BYPASSCAPNPOL_I198_B_XF		vaux_p[8]	IO_L21P_T3L_N4_AD8P_66
-	U1_XF.BW40 BW40	UNNAMED_17_BYPASSCAPNPOL_I198_B_XF UNNAMED_17_BYPASSCAPNPOL_I198_B_XF ->C315_XF->UNNAMED_17_BYPASSCAPNPOL_I198_A_XF ->R26_XF->UNNAMED_17_RESISTOR_I199_A_XF		vaux_n[8]	IO_L21N_T3L_N5_AD8N_66
100	U1_XF.BW41 BW41	NC NC		IO_L10P_T1U_N6_QBC_AD4P_20	IO_L10P_T1U_N6_QBC_AD4P_20
100	U1_XF.BW42 BW42	NC NC		IO_L10N_T1U_N7_QBC_AD4N_20	IO_L10N_T1U_N7_QBC_AD4N_20
100	U1_XF.BW43 BW43	GND GND	0V	GND	GND
100	U1_XF.BW44 BW44	NC NC		IO_L12N_T1U_N11_GC_20	IO_L12N_T1U_N11_GC_20
100	U1_XF.BW45 BW45	NC NC		IO_T0U_N12_VRP_20	IO_T0U_N12_VRP_20
100	U1_XF.BW46 BW46	NC NC		IO_L6P_T0U_N10_AD6P_20	IO_L6P_T0U_N10_AD6P_20
100	U1_XF.BW47 BW47	NC NC		IO_L6N_T0U_N11_AD6N_20	IO_L6N_T0U_N11_AD6N_20
100	U1_XF.BW48 BW48	GND GND	0V	GND	GND
95	U1_XF.BW49 BW49	C1_DDR4_ADR<6>_XF C1_DDR4_ADR<6>_XF		c1_ddr4_adr[6]	IO_L2P_T0L_N2_21
95	U1_XF.BW50 BW50	C1_DDR4_ADR<16>_XF C1_DDR4_ADR<16>_XF		c1_ddr4_adr[16]	IO_L6P_T0U_N10_AD6P_21
-	U1_XF.BW51 BW51	UNNAMED_21_RESISTOR_I40_B_XF UNNAMED_21_RESISTOR_I40_B_XF ->R31_XF->GND		IO_T0U_N12_VRP_21	IO_T0U_N12_VRP_21
95	U1_XF.BW52 BW52	C1_DDR4_ADR<15>_XF C1_DDR4_ADR<15>_XF		c1_ddr4_adr[15]	IO_L8P_T1L_N2_AD5P_21
100	U1_XF.BW53 BW53	GND GND	0V	GND	GND
95	U1_XF.BW54 BW54	C1_DDR4_ADR<4>_XF C1_DDR4_ADR<4>_XF		c1_ddr4_adr[4]	IO_L9P_T1L_N4_AD12P_21
95	U1_XF.BW55 BW55	C1_DDR4_ADR<2>_XF C1_DDR4_ADR<2>_XF		c1_ddr4_adr[2]	IO_L9N_T1L_N5_AD12N_21
100	U1_XF.BW56 BW56	NC NC		IO_L18P_T2U_N10_AD2P_21	IO_L18P_T2U_N10_AD2P_21
100	U1_XF.BW57 BW57	NC NC		IO_L18N_T2U_N11_AD2N_21	IO_L18N_T2U_N11_AD2N_21
100	U1_XF.BW58 BW58	GND GND	0V	GND	GND
35	U1_XF.BW59 BW59	C1_DDR4_DQ<31>_XF C1_DDR4_DQ<31>_XF		c1_ddr4_dq[45]	IO_L21P_T3L_N4_AD8P_21
35	U1_XF.BW60 BW60	C1_DDR4_DQ<30>_XF C1_DDR4_DQ<30>_XF		c1_ddr4_dq[44]	IO_L21N_T3L_N5_AD8N_21
35	U1_XF.BW61 BW61	C1_DDR4_DQ<24>_XF C1_DDR4_DQ<24>_XF		c1_ddr4_dq[40]	IO_L23P_T3U_N8_21
35	U1_XF.BW62 BW62	C1_DDR4_DQ<26>_XF C1_DDR4_DQ<26>_XF		c1_ddr4_dq[42]	IO_L23N_T3U_N9_21
100	U1_XF.BW63 BW63	GND GND	0V	GND	GND
100	U1_XF.BY1 BY1	GND GND	0V	GND	GND
100	U1_XF.BY2 BY2	GND GND	0V	GND	GND
95	U1_XF.BY3 BY3	OCL0_PER_N<0>_XF OCL0_PER_N<0>_XF		ocl0_per_n[0]	MGTYRXN0_219
95	U1_XF.BY4 BY4	OCL0_PER_P<0>_XF OCL0_PER_P<0>_XF		ocl0_per_p[0]	MGTYRXP0_219
100	U1_XF.BY5 BY5	GND GND	0V	GND	GND
100	U1_XF.BY6 BY6	GND GND	0V	GND	GND
100	U1_XF.BY7 BY7	GND GND	0V	GND	GND
92	U1_XF.BY8 BY8	AC_OCL1_PET_N<1>_XF AC_OCL1_PET_N<1>_XF		ocl1_pet_n[1]	MGTYTXN1_220
92	U1_XF.BY9 BY9	AC_OCL1_PET_P<1>_XF AC_OCL1_PET_P<1>_XF		ocl1_pet_p[1]	MGTYTXP1_220
100	U1_XF.BY10 BY10	GND GND	0V	GND	GND
23	U1_XF.BY11 BY11	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
100	U1_XF.BY12 BY12	NC NC		MGTREFCLK1N_219	MGTREFCLK1N_219
100	U1_XF.BY13 BY13	NC NC		MGTREFCLK1P_219	MGTREFCLK1P_219
100	U1_XF.BY14 BY14	GND GND	0V	GND	GND
36	U1_XF.BY15 BY15	C0_DDR4_ADR<0>_XF C0_DDR4_ADR<0>_XF		c0_ddr4_adr[13]	IO_L2N_T0L_N3_60
-	U1_XF.BY16 BY16	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_60	VCCO_60	1.2
20	U1_XF.BY17 BY17	C0_DDR4_ODT<1>_XF C0_DDR4_ODT<1>_XF		c0_ddr4_adr[4]	IO_L6N_T0U_N11_AD6N_60
20	U1_XF.BY18 BY18	C0_DDR4_ODT<0>_XF C0_DDR4_ODT<0>_XF		c0_ddr4_adr[6]	IO_L12P_T1U_N10_GC_60
95	U1_XF.BY19 BY19	C0_SYS_CLK_N_XF C0_SYS_CLK_N_XF		c0_sys_clk_n	IO_L11N_T1U_N9_GC_60
95	U1_XF.BY20 BY20	C0_SYS_CLK_P_XF C0_SYS_CLK_P_XF		c0_sys_clk_p	IO_L11P_T1U_N8_GC_60
100	U1_XF.BY21 BY21	GND GND	0V	GND	GND
37	U1_XF.BY22 BY22	C0_DDR4_DQ<6>_XF C0_DDR4_DQ<6>_XF		c0_ddr4_dq[30]	IO_L8N_T1L_N3_AD5N_62
37	U1_XF.BY23 BY23	C0_DDR4_DQ<7>_XF C0_DDR4_DQ<7>_XF		c0_ddr4_dq[31]	IO_L8P_T1L_N2_AD5P_62
37	U1_XF.BY24 BY24	C0_DDR4_DQ<3>_XF C0_DDR4_DQ<3>_XF		c0_ddr4_dq[27]	IO_L11N_T1U_N9_GC_62
37	U1_XF.BY25 BY25	C0_DDR4_DQ<2>_XF C0_DDR4_DQ<2>_XF		c0_ddr4_dq[26]	IO_L11P_T1U_N8_GC_62
-	U1_XF.BY26 BY26	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_62	VCCO_62	1.2
16	U1_XF.BY27 BY27	C0_RDIMM_DQS_T<1>_XF C0_RDIMM_DQS_T<1>_XF		c0_ddr4_dqs_t[2]	IO_L16P_T2U_N6_QBC_AD3P_62
100	U1_XF.BY28 BY28	NC NC		IO_T3U_N12_62	IO_T3U_N12_62
-	U1_XF.BY29 BY29	UNNAMED_17_RESISTOR_I121_A_XF UNNAMED_17_RESISTOR_I121_A_XF ->R131_XF->UNNAMED_17_RESISTOR_I119_A_XF ->C269_XF->UNNAMED_17_RESISTOR_I124_A_XF		vaux_p[7]	IO_L4P_T0U_N6_DBC_AD7P_66
-	U1_XF.BY30 BY30	UNNAMED_17_RESISTOR_I124_A_XF UNNAMED_17_RESISTOR_I124_A_XF ->R132_XF->UNNAMED_17_RESISTOR_I122_A_XF ->C269_XF->UNNAMED_17_RESISTOR_I121_A_XF		vaux_n[7]	IO_L4N_T0U_N7_DBC_AD7N_66
88	U1_XF.BY31 BY31	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCO_66	VCCO_66	1.8
95	U1_XF.BY32 BY32	JTAG_CTL_TDI JTAG_CTL_TDI		jtag_ctl_tdi[0]	IO_L5P_T0U_N8_AD14P_66
-	U1_XF.BY33 BY33	UNNAMED_17_BYPASSCAPNPOL_I46_A_XF UNNAMED_17_BYPASSCAPNPOL_I46_A_XF ->R99_XF->UNNAMED_17_RESISTOR_I40_A_XF ->C147_XF->UNNAMED_17_BYPASSCAPNPOL_I46_B_XF		vaux_p[4]	IO_L10P_T1U_N6_QBC_AD4P_66
100	U1_XF.BY34 BY34	CPLD_FPGA_SSTAT CPLD_FPGA_SSTAT		cpld_fpga_sstat	IO_L12N_T1U_N11_GC_66
98	U1_XF.BY35 BY35	BOARD_CFG_SW<2> BOARD_CFG_SW<2>		board_cfg_sw[2]	IO_L11N_T1U_N9_GC_66
100	U1_XF.BY36 BY36	GND GND	0V	GND	GND
100	U1_XF.BY37 BY37	NC NC		IO_L15P_T2L_N4_AD11P_66	IO_L15P_T2L_N4_AD11P_66
-	U1_XF.BY38 BY38	UNNAMED_17_BYPASSCAPNPOL_I49_A_XF UNNAMED_17_BYPASSCAPNPOL_I49_A_XF ->C141_XF->UNNAMED_17_BYPASSCAPNPOL_I49_B_XF ->R82_XF->UNNAMED_17_RESISTOR_I53_A_XF		vaux_p[0]	IO_L22P_T3U_N6_DBC_AD0P_66
100	U1_XF.BY39 BY39	NC NC		IO_L24P_T3U_N10_66	IO_L24P_T3U_N10_66
100	U1_XF.BY40 BY40	NC NC		IO_L24N_T3U_N11_66	IO_L24N_T3U_N11_66
100	U1_XF.BY41 BY41	GND GND	0V	GND	GND
100	U1_XF.BY42 BY42	NC NC		IO_T2U_N12_20	IO_T2U_N12_20
100	U1_XF.BY43 BY43	NC NC		IO_L13P_T2L_N0_GC_QBC_20	IO_L13P_T2L_N0_GC_QBC_20
100	U1_XF.BY44 BY44	NC NC		IO_L13N_T2L_N1_GC_QBC_20	IO_L13N_T2L_N1_GC_QBC_20
100	U1_XF.BY45 BY45	NC NC		IO_T3U_N12_20	IO_T3U_N12_20
100	U1_XF.BY46 BY46	GND GND	0V	GND	GND
100	U1_XF.BY47 BY47	NC NC		IO_L19P_T3L_N0_DBC_AD9P_20	IO_L19P_T3L_N0_DBC_AD9P_20
100	U1_XF.BY48 BY48	NC NC		IO_L19N_T3L_N1_DBC_AD9N_20	IO_L19N_T3L_N1_DBC_AD9N_20
95	U1_XF.BY49 BY49	C1_DDR4_ADR<5>_XF C1_DDR4_ADR<5>_XF		c1_ddr4_adr[5]	IO_L2N_T0L_N3_21
95	U1_XF.BY50 BY50	C1_DDR4_BA<0>_XF C1_DDR4_BA<0>_XF		c1_ddr4_ba[0]	IO_L6N_T0U_N11_AD6N_21
-	U1_XF.BY51 BY51	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_21	VCCO_21	1.2
95	U1_XF.BY52 BY52	C1_DDR4_CS_N<0>_XF C1_DDR4_CS_N<0>_XF		c1_ddr4_cs_n[0]	IO_L8N_T1L_N3_AD5N_21
95	U1_XF.BY53 BY53	C1_DDR4_ACT_N_XF C1_DDR4_ACT_N_XF		c1_ddr4_act_n	IO_L12P_T1U_N10_GC_21
95	U1_XF.BY54 BY54	C1_SYS_CLK_P_XF C1_SYS_CLK_P_XF		c1_sys_clk_p	IO_L11P_T1U_N8_GC_21
95	U1_XF.BY55 BY55	C1_SYS_CLK_N_XF C1_SYS_CLK_N_XF		c1_sys_clk_n	IO_L11N_T1U_N9_GC_21
100	U1_XF.BY56 BY56	GND GND	0V	GND	GND
95	U1_XF.BY57 BY57	C1_DDR4_ADR<14>_XF C1_DDR4_ADR<14>_XF		c1_ddr4_adr[14]	IO_L17P_T2U_N8_AD10P_21
35	U1_XF.BY58 BY58	C1_DDR4_ADR<13>_XF C1_DDR4_ADR<13>_XF		c1_ddr4_adr[10]	IO_L17N_T2U_N9_AD10N_21
35	U1_XF.BY59 BY59	C1_DDR4_DQ<25>_XF C1_DDR4_DQ<25>_XF		c1_ddr4_dq[41]	IO_L24P_T3U_N10_21
35	U1_XF.BY60 BY60	C1_DDR4_DQ<27>_XF C1_DDR4_DQ<27>_XF		c1_ddr4_dq[43]	IO_L24N_T3U_N11_21
100	U1_XF.BY61 BY61	GND GND	0V	GND	GND
95	U1_XF.BY62 BY62	C1_DDR4_CS_N<3>_XF C1_DDR4_CS_N<3>_XF		c1_ddr4_cs_n[3]	IO_T3U_N12_21
100	U1_XF.BY63 BY63	GND GND	0V	GND	GND
100	U1_XF.C2 C2	GND GND	0V	GND	GND
100	U1_XF.C3 C3	GND GND	0V	GND	GND
100	U1_XF.C4 C4	GND GND	0V	GND	GND
100	U1_XF.C5 C5	GND GND	0V	GND	GND
92	U1_XF.C6 C6	AC_E1S0_PET_N<0>_XF AC_E1S0_PET_N<0>_XF		e1s0_pet_n[0]	MGTYTXN0_238
92	U1_XF.C7 C7	AC_E1S0_PET_P<0>_XF AC_E1S0_PET_P<0>_XF		e1s0_pet_p[0]	MGTYTXP0_238
100	U1_XF.C8 C8	GND GND	0V	GND	GND
23	U1_XF.C9 C9	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
92	U1_XF.C10 C10	AC_E1S0_PET_N<7>_XF AC_E1S0_PET_N<7>_XF		e1s0_pet_n[7]	MGTYTXN3_237
92	U1_XF.C11 C11	AC_E1S0_PET_P<7>_XF AC_E1S0_PET_P<7>_XF		e1s0_pet_p[7]	MGTYTXP3_237
100	U1_XF.C12 C12	GND GND	0V	GND	GND
23	U1_XF.C13 C13	PWR_AVCC_RN_XF PWR_AVCC_RN_XF	0.9	MGTAVCC_RN	MGTAVCC_RN	0.9
100	U1_XF.C14 C14	GND GND	0V	GND	GND
100	U1_XF.C15 C15	GND GND	0V	GND	GND
16	U1_XF.C16 C16	C3_RDIMM_DQS_C<6>_XF C3_RDIMM_DQS_C<6>_XF		c3_ddr4_dqs_c[12]	IO_L16N_T2U_N7_QBC_AD3N_77
100	U1_XF.C17 C17	NC NC		IO_T3U_N12_77	IO_T3U_N12_77
35	U1_XF.C18 C18	C3_DDR4_DQ<58>_XF C3_DDR4_DQ<58>_XF		c3_ddr4_dq[66]	IO_L23N_T3U_N9_77
35	U1_XF.C19 C19	C3_DDR4_DQ<59>_XF C3_DDR4_DQ<59>_XF		c3_ddr4_dq[67]	IO_L23P_T3U_N8_77
100	U1_XF.C20 C20	GND GND	0V	GND	GND
100	U1_XF.C21 C21	NC NC		IO_T1U_N12_76	IO_T1U_N12_76
35	U1_XF.C22 C22	C3_DDR4_DQ<42>_XF C3_DDR4_DQ<42>_XF		c3_ddr4_dq[16]	IO_L11N_T1U_N9_GC_76
35	U1_XF.C23 C23	C3_DDR4_DQ<43>_XF C3_DDR4_DQ<43>_XF		c3_ddr4_dq[18]	IO_L11P_T1U_N8_GC_76
35	U1_XF.C24 C24	C3_DDR4_DQ<40>_XF C3_DDR4_DQ<40>_XF		c3_ddr4_dq[19]	IO_L12N_T1U_N11_GC_76
-	U1_XF.C25 C25	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_76	VCCO_76	1.2
16	U1_XF.C26 C26	C3_RDIMM_DQS_C<4>_XF C3_RDIMM_DQS_C<4>_XF		c3_ddr4_dqs_c[2]	IO_L4N_T0U_N7_DBC_AD7N_76
16	U1_XF.C27 C27	C3_RDIMM_DQS_T<4>_XF C3_RDIMM_DQS_T<4>_XF		c3_ddr4_dqs_t[2]	IO_L4P_T0U_N6_DBC_AD7P_76
16	U1_XF.C28 C28	C3_RDIMM_DQS_T<13>_XF C3_RDIMM_DQS_T<13>_XF		c3_ddr4_dqs_t[3]	IO_L1P_T0L_N0_DBC_76
100	U1_XF.C29 C29	NC NC		IO_L22P_T3U_N6_DBC_AD0P_71	IO_L22P_T3U_N6_DBC_AD0P_71
100	U1_XF.C30 C30	NC NC		VCCO_71	VCCO_71	1.8
100	U1_XF.C31 C31	NC NC		IO_L23N_T3U_N9_71	IO_L23N_T3U_N9_71
100	U1_XF.C32 C32	NC NC		IO_L17N_T2U_N9_AD10N_71	IO_L17N_T2U_N9_AD10N_71
100	U1_XF.C33 C33	NC NC		IO_L13P_T2L_N0_GC_QBC_71	IO_L13P_T2L_N0_GC_QBC_71
100	U1_XF.C34 C34	NC NC		IO_L13N_T2L_N1_GC_QBC_71	IO_L13N_T2L_N1_GC_QBC_71
100	U1_XF.C35 C35	GND GND	0V	GND	GND
100	U1_XF.C36 C36	NC NC		IO_L11N_T1U_N9_GC_71	IO_L11N_T1U_N9_GC_71
100	U1_XF.C37 C37	NC NC		IO_L5N_T0U_N9_AD14N_71	IO_L5N_T0U_N9_AD14N_71
100	U1_XF.C38 C38	NC NC		IO_L2P_T0L_N2_71	IO_L2P_T0L_N2_71
100	U1_XF.C39 C39	NC NC		IO_L2N_T0L_N3_71	IO_L2N_T0L_N3_71
100	U1_XF.C40 C40	GND GND	0V	GND	GND
100	U1_XF.C41 C41	NC NC		IO_L19P_T3L_N0_DBC_AD9P_37	IO_L19P_T3L_N0_DBC_AD9P_37
100	U1_XF.C42 C42	NC NC		IO_L19N_T3L_N1_DBC_AD9N_37	IO_L19N_T3L_N1_DBC_AD9N_37
100	U1_XF.C43 C43	NC NC		IO_L18P_T2U_N10_AD2P_37	IO_L18P_T2U_N10_AD2P_37
100	U1_XF.C44 C44	NC NC		IO_L15P_T2L_N4_AD11P_37	IO_L15P_T2L_N4_AD11P_37
100	U1_XF.C45 C45	GND GND	0V	GND	GND
100	U1_XF.C46 C46	NC NC		IO_L14P_T2L_N2_GC_37	IO_L14P_T2L_N2_GC_37
100	U1_XF.C47 C47	NC NC		IO_L12P_T1U_N10_GC_37	IO_L12P_T1U_N10_GC_37
100	U1_XF.C48 C48	NC NC		IO_L12N_T1U_N11_GC_37	IO_L12N_T1U_N11_GC_37
100	U1_XF.C49 C49	NC NC		IO_T0U_N12_VRP_37	IO_T0U_N12_VRP_37
100	U1_XF.C50 C50	NC NC		VCCO_37	VCCO_37	1.8
100	U1_XF.C51 C51	NC NC		IO_L2N_T0L_N3_37	IO_L2N_T0L_N3_37
100	U1_XF.C52 C52	NC NC		IO_T3U_N12_35	IO_T3U_N12_35
35	U1_XF.C53 C53	C2_DDR4_DQ<47>_XF C2_DDR4_DQ<47>_XF		c2_ddr4_dq[52]	IO_L21P_T3L_N4_AD8P_35
35	U1_XF.C54 C54	C2_DDR4_DQ<46>_XF C2_DDR4_DQ<46>_XF		c2_ddr4_dq[53]	IO_L21N_T3L_N5_AD8N_35
-	U1_XF.C55 C55	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_35	VCCO_35	1.2
35	U1_XF.C56 C56	C2_DDR4_DQ<37>_XF C2_DDR4_DQ<37>_XF		c2_ddr4_dq[69]	IO_L14N_T2L_N3_GC_35
35	U1_XF.C57 C57	C2_DDR4_DQ<67>_XF C2_DDR4_DQ<67>_XF		c2_ddr4_dq[58]	IO_L11N_T1U_N9_GC_35
35	U1_XF.C58 C58	C2_DDR4_DQ<66>_XF C2_DDR4_DQ<66>_XF		c2_ddr4_dq[56]	IO_L12P_T1U_N10_GC_35
35	U1_XF.C59 C59	C2_DDR4_DQ<64>_XF C2_DDR4_DQ<64>_XF		c2_ddr4_dq[57]	IO_L12N_T1U_N11_GC_35
100	U1_XF.C60 C60	GND GND	0V	GND	GND
100	U1_XF.C61 C61	NC NC		IO_T1U_N12_35	IO_T1U_N12_35
100	U1_XF.C62 C62	GND GND	0V	GND	GND
100	U1_XF.CA2 CA2	GND GND	0V	GND	GND
100	U1_XF.CA3 CA3	GND GND	0V	GND	GND
100	U1_XF.CA4 CA4	GND GND	0V	GND	GND
100	U1_XF.CA5 CA5	GND GND	0V	GND	GND
92	U1_XF.CA6 CA6	AC_OCL1_PET_N<0>_XF AC_OCL1_PET_N<0>_XF		ocl1_pet_n[0]	MGTYTXN0_220
92	U1_XF.CA7 CA7	AC_OCL1_PET_P<0>_XF AC_OCL1_PET_P<0>_XF		ocl1_pet_p[0]	MGTYTXP0_220
100	U1_XF.CA8 CA8	GND GND	0V	GND	GND
23	U1_XF.CA9 CA9	PWR_AVTT_RS_XF PWR_AVTT_RS_XF	1.2	MGTAVTT_RS	MGTAVTT_RS	1.2
92	U1_XF.CA10 CA10	AC_OCL0_PET_N<3>_XF AC_OCL0_PET_N<3>_XF		ocl0_pet_n[3]	MGTYTXN3_219
92	U1_XF.CA11 CA11	AC_OCL0_PET_P<3>_XF AC_OCL0_PET_P<3>_XF		ocl0_pet_p[3]	MGTYTXP3_219
100	U1_XF.CA12 CA12	GND GND	0V	GND	GND
18	U1_XF.CA13 CA13	PWR_AVCC_RS_RLC_XF PWR_AVCC_RS_RLC_XF	0.9	MGTAVCC_RS	MGTAVCC_RS	0.9
100	U1_XF.CA14 CA14	GND GND	0V	GND	GND
95	U1_XF.CA15 CA15	C0_DDR4_BA<1>_XF C0_DDR4_BA<1>_XF		c0_ddr4_ba[1]	IO_L5N_T0U_N9_AD14N_60
37	U1_XF.CA16 CA16	C0_DDR4_ADR<1>_XF C0_DDR4_ADR<1>_XF		c0_ddr4_adr[0]	IO_L5P_T0U_N8_AD14P_60
-	U1_XF.CA17 CA17	UNNAMED_22_RESISTOR_I46_B_XF UNNAMED_22_RESISTOR_I46_B_XF ->R59_XF->GND		IO_T0U_N12_VRP_60	IO_T0U_N12_VRP_60
95	U1_XF.CA18 CA18	C0_DDR4_CS_N<1>_XF C0_DDR4_CS_N<1>_XF		c0_ddr4_cs_n[1]	IO_L12N_T1U_N11_GC_60
-	U1_XF.CA19 CA19	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_60	VCCO_60	1.2
20	U1_XF.CA20 CA20	C0_DDR4_ADR<4>_XF C0_DDR4_ADR<4>_XF		c0_ddr4_odt[0]	IO_L10P_T1U_N6_QBC_AD4P_60
20	U1_XF.CA21 CA21	C0_DDR4_ADR<11>_XF C0_DDR4_ADR<11>_XF		c0_ddr4_parity	IO_L8P_T1L_N2_AD5P_60
54	U1_XF.CA22 CA22	C0_RDIMM_DQS_C<0>_XF C0_RDIMM_DQS_C<0>_XF		c0_ddr4_dqs_c[6]	IO_L10N_T1U_N7_QBC_AD4N_62
16	U1_XF.CA23 CA23	C0_RDIMM_DQS_T<0>_XF C0_RDIMM_DQS_T<0>_XF		c0_ddr4_dqs_t[6]	IO_L10P_T1U_N6_QBC_AD4P_62
100	U1_XF.CA24 CA24	GND GND	0V	GND	GND
35	U1_XF.CA25 CA25	C0_DDR4_DQ<13>_XF C0_DDR4_DQ<13>_XF		c0_ddr4_dq[15]	IO_L14N_T2L_N3_GC_62
95	U1_XF.CA26 CA26	C0_DDR4_DQ<14>_XF C0_DDR4_DQ<14>_XF		c0_ddr4_dq[14]	IO_L14P_T2L_N2_GC_62
16	U1_XF.CA27 CA27	C0_RDIMM_DQS_C<1>_XF C0_RDIMM_DQS_C<1>_XF		c0_ddr4_dqs_c[2]	IO_L16N_T2U_N7_QBC_AD3N_62
37	U1_XF.CA28 CA28	C0_DDR4_DQ<9>_XF C0_DDR4_DQ<9>_XF		c0_ddr4_dq[8]	IO_L18P_T2U_N10_AD2P_62
100	U1_XF.CA29 CA29	GND GND	0V	GND	GND
95	U1_XF.CA30 CA30	CLK_O_VIS_P_XF CLK_O_VIS_P_XF		clk_o_vis_p	IO_L1P_T0L_N0_DBC_66
95	U1_XF.CA31 CA31	JTAG_CTL_TMS JTAG_CTL_TMS		jtag_ctl_tms[0]	IO_L3P_T0L_N4_AD15P_66
95	U1_XF.CA32 CA32	JTAG_CTL_TCK JTAG_CTL_TCK		jtag_ctl_tck[0]	IO_L5N_T0U_N9_AD14N_66
-	U1_XF.CA33 CA33	UNNAMED_17_BYPASSCAPNPOL_I46_B_XF UNNAMED_17_BYPASSCAPNPOL_I46_B_XF ->R100_XF->UNNAMED_17_RESISTOR_I41_A_XF ->C147_XF->UNNAMED_17_BYPASSCAPNPOL_I46_A_XF		vaux_n[4]	IO_L10N_T1U_N7_QBC_AD4N_66
88	U1_XF.CA34 CA34	FPGA_VCCAUX_P1R8V FPGA_VCCAUX_P1R8V	1.8	VCCO_66	VCCO_66	1.8
100	U1_XF.CA35 CA35	PSU_1R8V_SCL PSU_1R8V_SCL	1.8V	psu_1r8v_scl	IO_L14P_T2L_N2_GC_66
98	U1_XF.CA36 CA36	BOARD_CFG_SW<1> BOARD_CFG_SW<1>		board_cfg_sw[1]	IO_L13P_T2L_N0_GC_QBC_66
100	U1_XF.CA37 CA37	PSU_1R8V_SDA PSU_1R8V_SDA	1.8V	psu_1r8v_sda	IO_L15N_T2L_N5_AD11N_66
-	U1_XF.CA38 CA38	UNNAMED_17_BYPASSCAPNPOL_I49_B_XF UNNAMED_17_BYPASSCAPNPOL_I49_B_XF ->C141_XF->UNNAMED_17_BYPASSCAPNPOL_I49_A_XF ->R83_XF->UNNAMED_17_RESISTOR_I54_A_XF		vaux_n[0]	IO_L22N_T3U_N7_DBC_AD0N_66
100	U1_XF.CA39 CA39	GND GND	0V	GND	GND
-	U1_XF.CA40 CA40	UNNAMED_17_BYPASSCAPNPOL_I216_A_XF UNNAMED_17_BYPASSCAPNPOL_I216_A_XF ->R68_XF->UNNAMED_17_RESISTOR_I214_B_XF ->C316_XF->UNNAMED_17_BYPASSCAPNPOL_I216_B_XF		vaux_p[9]	IO_L19P_T3L_N0_DBC_AD9P_66
100	U1_XF.CA41 CA41	NC NC		IO_L15P_T2L_N4_AD11P_20	IO_L15P_T2L_N4_AD11P_20
100	U1_XF.CA42 CA42	NC NC		IO_L14P_T2L_N2_GC_20	IO_L14P_T2L_N2_GC_20
100	U1_XF.CA43 CA43	NC NC		IO_L14N_T2L_N3_GC_20	IO_L14N_T2L_N3_GC_20
100	U1_XF.CA44 CA44	NC NC		VCCO_20	VCCO_20	1.8
100	U1_XF.CA45 CA45	NC NC		IO_L21P_T3L_N4_AD8P_20	IO_L21P_T3L_N4_AD8P_20
100	U1_XF.CA46 CA46	NC NC		IO_L21N_T3L_N5_AD8N_20	IO_L21N_T3L_N5_AD8N_20
100	U1_XF.CA47 CA47	NC NC		IO_L20P_T3L_N2_AD1P_20	IO_L20P_T3L_N2_AD1P_20
100	U1_XF.CA48 CA48	NC NC		IO_L20N_T3L_N3_AD1N_20	IO_L20N_T3L_N3_AD1N_20
100	U1_XF.CA49 CA49	GND GND	0V	GND	GND
95	U1_XF.CA50 CA50	C1_DDR4_ADR<3>_XF C1_DDR4_ADR<3>_XF		c1_ddr4_adr[3]	IO_L1P_T0L_N0_DBC_21
95	U1_XF.CA51 CA51	C1_DDR4_PARITY_XF C1_DDR4_PARITY_XF		c1_ddr4_parity	IO_L5P_T0U_N8_AD14P_21
37	U1_XF.CA52 CA52	C1_DDR4_ADR<0>_XF C1_DDR4_ADR<0>_XF		c1_ddr4_adr[8]	IO_T1U_N12_21
95	U1_XF.CA53 CA53	C1_DDR4_ADR<12>_XF C1_DDR4_ADR<12>_XF		c1_ddr4_adr[12]	IO_L12N_T1U_N11_GC_21
-	U1_XF.CA54 CA54	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_21	VCCO_21	1.2
95	U1_XF.CA55 CA55	C1_DDR4_RESET_N_XF C1_DDR4_RESET_N_XF		c1_ddr4_reset_n	IO_L14P_T2L_N2_GC_21
95	U1_XF.CA56 CA56	C1_DDR4_BG<0>_XF C1_DDR4_BG<0>_XF		c1_ddr4_bg[0]	IO_L13P_T2L_N0_GC_QBC_21
16	U1_XF.CA57 CA57	C1_DDR4_CS_N<2>_XF C1_DDR4_CS_N<2>_XF		c1_ddr4_adr[13]	IO_L16P_T2U_N6_QBC_AD3P_21
95	U1_XF.CA58 CA58	C1_DDR4_BA<1>_XF C1_DDR4_BA<1>_XF		c1_ddr4_ba[1]	IO_L16N_T2U_N7_QBC_AD3N_21
-	U1_XF.CA59 CA59	PWR_SDIMM_VDD_XF PWR_SDIMM_VDD_XF	1.2	VCCO_21	VCCO_21	1.2
16	U1_XF.CA60 CA60	C1_RDIMM_DQS_T<3>_XF C1_RDIMM_DQS_T<3>_XF		c1_ddr4_dqs_t[10]	IO_L22P_T3U_N6_DBC_AD0P_21
16	U1_XF.CA61 CA61	C1_RDIMM_DQS_C<3>_XF C1_RDIMM_DQS_C<3>_XF		c1_ddr4_dqs_c[10]	IO_L22N_T3U_N7_DBC_AD0N_21
100	U1_XF.CA62 CA62	GND GND	0V	GND	GND
100	U1_XF.CB3 CB3	GND GND	0V	GND	GND
100	U1_XF.CB4 CB4	GND GND	0V	GND	GND
100	U1_XF.CB5 CB5	GND GND	0V	GND	GND
100	U1_XF.CB6 CB6	GND GND	0V	GND	GND
100	U1_XF.CB7 CB7	GND GND	0V	GND	GND
92	U1_XF.CB8 CB8	AC_OCL0_PET_N<2>_XF AC_OCL0_PET_N<2>_XF		ocl0_pet_n[2]	MGTYTXN2_219
92	U1_XF.CB9 CB9	AC_OCL0_PET_P<2>_XF AC_OCL0_PET_P<2>_XF		ocl0_pet_p[2]	MGTYTXP2_219
100	U1_XF.CB10 CB10	GND GND	0V	GND	GND
100	U1_XF.CB11 CB11	GND GND	0V	GND	GND
85	U1_XF.CB12 CB12	OCL0_FPGA_REFCLK_N_XF OCL0_FPGA_REFCLK_N_XF		ocl0_refclk_n	MGTREFCLK0N_219
85	U1_XF.CB13 CB13	OCL0_FPGA_REFCLK_P_XF OCL0_FPGA_REFCLK_P_XF		ocl0_refclk_p	MGTREFCLK0P_219
100	U1_XF.CB14 CB14	GND GND	0V	GND	GND
95	U1_XF.CB15 CB15	C0_DDR4_ADR<3>_XF C0_DDR4_ADR<3>_XF		c0_ddr4_adr[3]	IO_L3N_T0L_N5_AD15N_60
16	U1_XF.CB16 CB16	C0_DDR4_CS_N<2>_XF C0_DDR4_CS_N<2>_XF		c0_ddr4_adr[2]	IO_L3P_T0L_N4_AD15P_60
100	U1_XF.CB17 CB17	GND GND	0V	GND	GND
16	U1_XF.CB18 CB18	C0_DDR4_CS_N<0>_XF C0_DDR4_CS_N<0>_XF		c0_ddr4_adr[7]	IO_L9N_T1L_N5_AD12N_60
20	U1_XF.CB19 CB19	C0_DDR4_BA<0>_XF C0_DDR4_BA<0>_XF		c0_ddr4_adr[11]	IO_L9P_T1L_N4_AD12P_60
46	U1_XF.CB20 CB20	C0_DDR4_PARITY_XF C0_DDR4_PARITY_XF		c0_ddr4_cs_n[2]	IO_L10N_T1U_N7_QBC_AD4N_60
20	U1_XF.CB21 CB21	C0_DDR4_ADR<2>_XF C0_DDR4_ADR<2>_XF		c0_ddr4_cs_n[0]	IO_L8N_T1L_N3_AD5N_60
100	U1_XF.CB22 CB22	GND GND	0V	GND	GND
16	U1_XF.CB23 CB23	C0_RDIMM_DQS_T<9>_XF C0_RDIMM_DQS_T<9>_XF		c0_ddr4_dqs_t[7]	IO_L7P_T1L_N0_QBC_AD13P_62
37	U1_XF.CB24 CB24	C0_DDR4_DQ<4>_XF C0_DDR4_DQ<4>_XF		c0_ddr4_dq[28]	IO_L9P_T1L_N4_AD12P_62
16	U1_XF.CB25 CB25	C0_RDIMM_DQS_C<10>_XF C0_RDIMM_DQS_C<10>_XF		c0_ddr4_dqs_c[3]	IO_L13N_T2L_N1_GC_QBC_62
16	U1_XF.CB26 CB26	C0_RDIMM_DQS_T<10>_XF C0_RDIMM_DQS_T<10>_XF		c0_ddr4_dqs_t[3]	IO_L13P_T2L_N0_GC_QBC_62
100	U1_XF.CB27 CB27	GND GND	0V	GND	GND
35	U1_XF.CB28 CB28	C0_DDR4_DQ<11>_XF C0_DDR4_DQ<11>_XF		c0_ddr4_dq[10]	IO_L18N_T2U_N11_AD2N_62
100	U1_XF.CB29 CB29	NC NC		IO_T2U_N12_62	IO_T2U_N12_62
95	U1_XF.CB30 CB30	CLK_O_VIS_N_XF CLK_O_VIS_N_XF		clk_o_vis_n	IO_L1N_T0L_N1_DBC_66
95	U1_XF.CB31 CB31	TDO_JTAG_CTL TDO_JTAG_CTL		tdo_jtag_ctl[0]	IO_L3N_T0L_N5_AD15N_66
100	U1_XF.CB32 CB32	GND GND	0V	GND	GND
-	U1_XF.CB33 CB33	UNNAMED_17_BYPASSCAPNPOL_I107_A_XF UNNAMED_17_BYPASSCAPNPOL_I107_A_XF ->R127_XF->UNNAMED_17_RESISTOR_I101_A_XF ->C267_XF->UNNAMED_17_BYPASSCAPNPOL_I107_B_XF		vaux_p[5]	IO_L8P_T1L_N2_AD5P_66
98	U1_XF.CB34 CB34	BOARD_CFG_SW<3> BOARD_CFG_SW<3>		board_cfg_sw[3]	IO_L7P_T1L_N0_QBC_AD13P_66
98	U1_XF.CB35 CB35	BOARD_CFG_SW<0> BOARD_CFG_SW<0>		board_cfg_sw[0]	IO_L14N_T2L_N3_GC_66
96	U1_XF.CB36 CB36	CPLD_FPGA_DVAL_1 CPLD_FPGA_DVAL_1		cpld_fpga_dval	IO_L13N_T2L_N1_GC_QBC_66
100	U1_XF.CB37 CB37	GND GND	0V	GND	GND
-	U1_XF.CB38 CB38	UNNAMED_17_BYPASSCAPNPOL_I50_A_XF UNNAMED_17_BYPASSCAPNPOL_I50_A_XF ->C139_XF->UNNAMED_17_BYPASSCAPNPOL_I50_B_XF ->R78_XF->UNNAMED_17_RESISTOR_I55_A_XF		vaux_p[1]	IO_L20P_T3L_N2_AD1P_66
-	U1_XF.CB39 CB39	UNNAMED_17_BYPASSCAPNPOL_I50_B_XF UNNAMED_17_BYPASSCAPNPOL_I50_B_XF ->C139_XF->UNNAMED_17_BYPASSCAPNPOL_I50_A_XF ->R79_XF->UNNAMED_17_RESISTOR_I56_A_XF		vaux_n[1]	IO_L20N_T3L_N3_AD1N_66
-	U1_XF.CB40 CB40	UNNAMED_17_BYPASSCAPNPOL_I216_B_XF UNNAMED_17_BYPASSCAPNPOL_I216_B_XF ->R69_XF->UNNAMED_17_RESISTOR_I215_B_XF ->C316_XF->UNNAMED_17_BYPASSCAPNPOL_I216_A_XF		vaux_n[9]	IO_L19N_T3L_N1_DBC_AD9N_66
100	U1_XF.CB41 CB41	NC NC		IO_L15N_T2L_N5_AD11N_20	IO_L15N_T2L_N5_AD11N_20
100	U1_XF.CB42 CB42	GND GND	0V	GND	GND
100	U1_XF.CB43 CB43	NC NC		IO_L17P_T2U_N8_AD10P_20	IO_L17P_T2U_N8_AD10P_20
100	U1_XF.CB44 CB44	NC NC		IO_L17N_T2U_N9_AD10N_20	IO_L17N_T2U_N9_AD10N_20
100	U1_XF.CB45 CB45	NC NC		IO_L23P_T3U_N8_20	IO_L23P_T3U_N8_20
100	U1_XF.CB46 CB46	NC NC		IO_L23N_T3U_N9_20	IO_L23N_T3U_N9_20
100	U1_XF.CB47 CB47	GND GND	0V	GND	GND
100	U1_XF.CB48 CB48	NC NC		IO_L24P_T3U_N10_20	IO_L24P_T3U_N10_20
95	U1_XF.CB49 CB49	C1_DDR4_CK_T<0>_XF C1_DDR4_CK_T<0>_XF		c1_ddr4_ck_t[0]	IO_L4P_T0U_N6_DBC_AD7P_21
20	U1_XF.CB50 CB50	C1_DDR4_CKE<0>_XF C1_DDR4_CKE<0>_XF		c1_ddr4_adr[1]	IO_L1N_T0L_N1_DBC_21
36	U1_XF.CB51 CB51	C1_DDR4_ADR<11>_XF C1_DDR4_ADR<11>_XF		c1_ddr4_adr[0]	IO_L5N_T0U_N9_AD14N_21
100	U1_XF.CB52 CB52	GND GND	0V	GND	GND
20	U1_XF.CB53 CB53	C1_DDR4_ADR<7>_XF C1_DDR4_ADR<7>_XF		c1_ddr4_bg[1]	IO_L10P_T1U_N6_QBC_AD4P_21
20	U1_XF.CB54 CB54	C1_DDR4_ADR<1>_XF C1_DDR4_ADR<1>_XF		c1_ddr4_cs_n[1]	IO_L7P_T1L_N0_QBC_AD13P_21
20	U1_XF.CB55 CB55	C1_DDR4_ADR<10>_XF C1_DDR4_ADR<10>_XF		c1_ddr4_cke[1]	IO_L14N_T2L_N3_GC_21
16	U1_XF.CB56 CB56	C1_DDR4_CS_N<1>_XF C1_DDR4_CS_N<1>_XF		c1_ddr4_cke[0]	IO_L13N_T2L_N1_GC_QBC_21
100	U1_XF.CB57 CB57	GND GND	0V	GND	GND
95	U1_XF.CB58 CB58	C1_DDR4_ALERT_N_XF C1_DDR4_ALERT_N_XF		c1_ddr4_alert_n	IO_T2U_N12_21
35	U1_XF.CB59 CB59	C1_DDR4_DQ<29>_XF C1_DDR4_DQ<29>_XF		c1_ddr4_dq[46]	IO_L20P_T3L_N2_AD1P_21
35	U1_XF.CB60 CB60	C1_DDR4_DQ<28>_XF C1_DDR4_DQ<28>_XF		c1_ddr4_dq[47]	IO_L20N_T3L_N3_AD1N_21
100	U1_XF.CB61 CB61	GND GND	0V	GND	GND
100	U1_XF.CC4 CC4	GND GND	0V	GND	GND
100	U1_XF.CC5 CC5	GND GND	0V	GND	GND
92	U1_XF.CC6 CC6	AC_OCL0_PET_N<1>_XF AC_OCL0_PET_N<1>_XF		ocl0_pet_n[1]	MGTYTXN1_219
92	U1_XF.CC7 CC7	AC_OCL0_PET_P<1>_XF AC_OCL0_PET_P<1>_XF		ocl0_pet_p[1]	MGTYTXP1_219
100	U1_XF.CC8 CC8	GND GND	0V	GND	GND
100	U1_XF.CC9 CC9	GND GND	0V	GND	GND
92	U1_XF.CC10 CC10	AC_OCL0_PET_N<0>_XF AC_OCL0_PET_N<0>_XF		ocl0_pet_n[0]	MGTYTXN0_219
92	U1_XF.CC11 CC11	AC_OCL0_PET_P<0>_XF AC_OCL0_PET_P<0>_XF		ocl0_pet_p[0]	MGTYTXP0_219
100	U1_XF.CC12 CC12	GND GND	0V	GND	GND
100	U1_XF.CC13 CC13	GND GND	0V	GND	GND
100	U1_XF.CC14 CC14	GND GND	0V	GND	GND
100	U1_XF.CC15 CC15	GND GND	0V	GND	GND
95	U1_XF.CC16 CC16	C0_DDR4_CS_N<3>_XF C0_DDR4_CS_N<3>_XF		c0_ddr4_cs_n[3]	IO_L1N_T0L_N1_DBC_60
95	U1_XF.CC17 CC17	C0_DDR4_ADR<14>_XF C0_DDR4_ADR<14>_XF		c0_ddr4_adr[14]	IO_L1P_T0L_N0_DBC_60
20	U1_XF.CC18 CC18	C0_DDR4_ADR<16>_XF C0_DDR4_ADR<16>_XF		c0_ddr4_ba[0]	IO_L7N_T1L_N1_QBC_AD13N_60
95	U1_XF.CC19 CC19	C0_DDR4_ADR<10>_XF C0_DDR4_ADR<10>_XF		c0_ddr4_adr[10]	IO_L7P_T1L_N0_QBC_AD13P_60
100	U1_XF.CC20 CC20	GND GND	0V	GND	GND
36	U1_XF.CC21 CC21	C0_DDR4_ADR<7>_XF C0_DDR4_ADR<7>_XF		c0_ddr4_adr[16]	IO_T1U_N12_60
100	U1_XF.CC22 CC22	NC NC		IO_T1U_N12_62	IO_T1U_N12_62
16	U1_XF.CC23 CC23	C0_RDIMM_DQS_C<9>_XF C0_RDIMM_DQS_C<9>_XF		c0_ddr4_dqs_c[7]	IO_L7N_T1L_N1_QBC_AD13N_62
37	U1_XF.CC24 CC24	C0_DDR4_DQ<5>_XF C0_DDR4_DQ<5>_XF		c0_ddr4_dq[29]	IO_L9N_T1L_N5_AD12N_62
100	U1_XF.CC25 CC25	GND GND	0V	GND	GND
95	U1_XF.CC26 CC26	C0_DDR4_DQ<12>_XF C0_DDR4_DQ<12>_XF		c0_ddr4_dq[12]	IO_L15N_T2L_N5_AD11N_62
35	U1_XF.CC27 CC27	C0_DDR4_DQ<15>_XF C0_DDR4_DQ<15>_XF		c0_ddr4_dq[13]	IO_L15P_T2L_N4_AD11P_62
37	U1_XF.CC28 CC28	C0_DDR4_DQ<8>_XF C0_DDR4_DQ<8>_XF		c0_ddr4_dq[9]	IO_L17N_T2U_N9_AD10N_62
35	U1_XF.CC29 CC29	C0_DDR4_DQ<10>_XF C0_DDR4_DQ<10>_XF		c0_ddr4_dq[11]	IO_L17P_T2U_N8_AD10P_62
100	U1_XF.CC30 CC30	GND GND	0V	GND	GND
-	U1_XF.CC31 CC31	UNNAMED_22_RESISTOR_I61_B_XF UNNAMED_22_RESISTOR_I61_B_XF ->R160_XF->GND		IO_T0U_N12_VRP_66	IO_T0U_N12_VRP_66
100	U1_XF.CC32 CC32	FPGA_CPLD_SSTAT FPGA_CPLD_SSTAT		fpga_cpld_sstat	IO_T1U_N12_66
-	U1_XF.CC33 CC33	UNNAMED_17_BYPASSCAPNPOL_I107_B_XF UNNAMED_17_BYPASSCAPNPOL_I107_B_XF ->R128_XF->UNNAMED_17_RESISTOR_I104_A_XF ->C267_XF->UNNAMED_17_BYPASSCAPNPOL_I107_A_XF		vaux_n[5]	IO_L8N_T1L_N3_AD5N_66
96	U1_XF.CC34 CC34	FPGA_ERR_VIS<0>_1 FPGA_ERR_VIS<0>_1		fpga_err_vis[0]	IO_L7N_T1L_N1_QBC_AD13N_66
100	U1_XF.CC35 CC35	GND GND	0V	GND	GND
-	U1_XF.CC36 CC36	UNNAMED_17_BYPASSCAPNPOL_I57_A_XF UNNAMED_17_BYPASSCAPNPOL_I57_A_XF ->C140_XF->UNNAMED_17_BYPASSCAPNPOL_I57_B_XF ->R80_XF->UNNAMED_17_RESISTOR_I59_A_XF		vaux_p[2]	IO_L18P_T2U_N10_AD2P_66
-	U1_XF.CC37 CC37	UNNAMED_17_BYPASSCAPNPOL_I57_B_XF UNNAMED_17_BYPASSCAPNPOL_I57_B_XF ->C140_XF->UNNAMED_17_BYPASSCAPNPOL_I57_A_XF ->R81_XF->UNNAMED_17_RESISTOR_I60_A_XF		vaux_n[2]	IO_L18N_T2U_N11_AD2N_66
96	U1_XF.CC38 CC38	FPGA_ERR_VIS<2>_1 FPGA_ERR_VIS<2>_1		fpga_err_vis[2]	IO_T2U_N12_66
96	U1_XF.CC39 CC39	FPGA_ERR_VIS<1>_1 FPGA_ERR_VIS<1>_1		fpga_err_vis[1]	IO_T3U_N12_66
100	U1_XF.CC40 CC40	GND GND	0V	GND	GND
100	U1_XF.CC41 CC41	NC NC		IO_L16P_T2U_N6_QBC_AD3P_20	IO_L16P_T2U_N6_QBC_AD3P_20
100	U1_XF.CC42 CC42	NC NC		IO_L16N_T2U_N7_QBC_AD3N_20	IO_L16N_T2U_N7_QBC_AD3N_20
100	U1_XF.CC43 CC43	NC NC		IO_L18P_T2U_N10_AD2P_20	IO_L18P_T2U_N10_AD2P_20
100	U1_XF.CC44 CC44	NC NC		IO_L18N_T2U_N11_AD2N_20	IO_L18N_T2U_N11_AD2N_20
100	U1_XF.CC45 CC45	GND GND	0V	GND	GND
100	U1_XF.CC46 CC46	NC NC		IO_L22P_T3U_N6_DBC_AD0P_20	IO_L22P_T3U_N6_DBC_AD0P_20
100	U1_XF.CC47 CC47	NC NC		IO_L22N_T3U_N7_DBC_AD0N_20	IO_L22N_T3U_N7_DBC_AD0N_20
100	U1_XF.CC48 CC48	NC NC		IO_L24N_T3U_N11_20	IO_L24N_T3U_N11_20
95	U1_XF.CC49 CC49	C1_DDR4_CK_C<0>_XF C1_DDR4_CK_C<0>_XF		c1_ddr4_ck_c[0]	IO_L4N_T0U_N7_DBC_AD7N_21
100	U1_XF.CC50 CC50	GND GND	0V	GND	GND
20	U1_XF.CC51 CC51	C1_DDR4_CKE<1>_XF C1_DDR4_CKE<1>_XF		c1_ddr4_adr[11]	IO_L3P_T0L_N4_AD15P_21
20	U1_XF.CC52 CC52	C1_DDR4_BG<1>_XF C1_DDR4_BG<1>_XF		c1_ddr4_adr[7]	IO_L3N_T0L_N5_AD15N_21
95	U1_XF.CC53 CC53	C1_DDR4_ADR<9>_XF C1_DDR4_ADR<9>_XF		c1_ddr4_adr[9]	IO_L10N_T1U_N7_QBC_AD4N_21
20	U1_XF.CC54 CC54	C1_DDR4_ADR<8>_XF C1_DDR4_ADR<8>_XF		c1_ddr4_odt[0]	IO_L7N_T1L_N1_QBC_AD13N_21
100	U1_XF.CC55 CC55	GND GND	0V	GND	GND
20	U1_XF.CC56 CC56	C1_DDR4_ODT<0>_XF C1_DDR4_ODT<0>_XF		c1_ddr4_cs_n[2]	IO_L15P_T2L_N4_AD11P_21
95	U1_XF.CC57 CC57	C1_DDR4_ODT<1>_XF C1_DDR4_ODT<1>_XF		c1_ddr4_odt[1]	IO_L15N_T2L_N5_AD11N_21
16	U1_XF.CC58 CC58	C1_RDIMM_DQS_T<12>_XF C1_RDIMM_DQS_T<12>_XF		c1_ddr4_dqs_t[11]	IO_L19P_T3L_N0_DBC_AD9P_21
16	U1_XF.CC59 CC59	C1_RDIMM_DQS_C<12>_XF C1_RDIMM_DQS_C<12>_XF		c1_ddr4_dqs_c[11]	IO_L19N_T3L_N1_DBC_AD9N_21
100	U1_XF.CC60 CC60	GND GND	0V	GND	GND
100	U1_XF.D1 D1	GND GND	0V	GND	GND
100	U1_XF.D2 D2	GND GND	0V	GND	GND
95	U1_XF.D3 D3	E1S0_PER_N<3>_XF E1S0_PER_N<3>_XF		e1s0_per_n[3]	MGTYRXN3_238
95	U1_XF.D4 D4	E1S0_PER_P<3>_XF E1S0_PER_P<3>_XF		e1s0_per_p[3]	MGTYRXP3_238
100	U1_XF.D5 D5	GND GND	0V	GND	GND
100	U1_XF.D6 D6	GND GND	0V	GND	GND
100	U1_XF.D7 D7	GND GND	0V	GND	GND
92	U1_XF.D8 D8	AC_E1S0_PET_N<6>_XF AC_E1S0_PET_N<6>_XF		e1s0_pet_n[6]	MGTYTXN2_237
92	U1_XF.D9 D9	AC_E1S0_PET_P<6>_XF AC_E1S0_PET_P<6>_XF		e1s0_pet_p[6]	MGTYTXP2_237
100	U1_XF.D10 D10	GND GND	0V	GND	GND
23	U1_XF.D11 D11	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
85	U1_XF.D12 D12	E1S0_FPGA_REFCLK_N<0>_XF E1S0_FPGA_REFCLK_N<0>_XF		e1s0_refclk_n[0]	MGTREFCLK0N_238
85	U1_XF.D13 D13	E1S0_FPGA_REFCLK_P<0>_XF E1S0_FPGA_REFCLK_P<0>_XF		e1s0_refclk_p[0]	MGTREFCLK0P_238
100	U1_XF.D14 D14	GND GND	0V	GND	GND
95	U1_XF.D15 D15	C3_DDR4_DQ<50>_XF C3_DDR4_DQ<50>_XF		c3_ddr4_dq[50]	IO_L17N_T2U_N9_AD10N_77
16	U1_XF.D16 D16	C3_RDIMM_DQS_T<6>_XF C3_RDIMM_DQS_T<6>_XF		c3_ddr4_dqs_t[12]	IO_L16P_T2U_N6_QBC_AD3P_77
95	U1_XF.D17 D17	C3_DDR4_DQ<54>_XF C3_DDR4_DQ<54>_XF		c3_ddr4_dq[54]	IO_L14N_T2L_N3_GC_77
-	U1_XF.D18 D18	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_77	VCCO_77	1.2
95	U1_XF.D19 D19	C3_DDR4_DQ<48>_XF C3_DDR4_DQ<48>_XF		c3_ddr4_dq[48]	IO_L18N_T2U_N11_AD2N_77
95	U1_XF.D20 D20	C3_DDR4_DQ<49>_XF C3_DDR4_DQ<49>_XF		c3_ddr4_dq[49]	IO_L18P_T2U_N10_AD2P_77
16	U1_XF.D21 D21	C3_RDIMM_DQS_C<5>_XF C3_RDIMM_DQS_C<5>_XF		c3_ddr4_dqs_c[4]	IO_L10N_T1U_N7_QBC_AD4N_76
16	U1_XF.D22 D22	C3_RDIMM_DQS_T<5>_XF C3_RDIMM_DQS_T<5>_XF		c3_ddr4_dqs_t[4]	IO_L10P_T1U_N6_QBC_AD4P_76
100	U1_XF.D23 D23	GND GND	0V	GND	GND
35	U1_XF.D24 D24	C3_DDR4_DQ<41>_XF C3_DDR4_DQ<41>_XF		c3_ddr4_dq[17]	IO_L12P_T1U_N10_GC_76
35	U1_XF.D25 D25	C3_DDR4_DQ<35>_XF C3_DDR4_DQ<35>_XF		c3_ddr4_dq[11]	IO_L6N_T0U_N11_AD6N_76
35	U1_XF.D26 D26	C3_DDR4_DQ<34>_XF C3_DDR4_DQ<34>_XF		c3_ddr4_dq[10]	IO_L6P_T0U_N10_AD6P_76
-	U1_XF.D27 D27	UNNAMED_22_RESISTOR_I36_B_XF UNNAMED_22_RESISTOR_I36_B_XF ->R50_XF->GND		IO_T0U_N12_VRP_76	IO_T0U_N12_VRP_76
100	U1_XF.D28 D28	GND GND	0V	GND	GND
100	U1_XF.D29 D29	NC NC		IO_L24N_T3U_N11_71	IO_L24N_T3U_N11_71
100	U1_XF.D30 D30	NC NC		IO_L20N_T3L_N3_AD1N_71	IO_L20N_T3L_N3_AD1N_71
100	U1_XF.D31 D31	NC NC		IO_L23P_T3U_N8_71	IO_L23P_T3U_N8_71
100	U1_XF.D32 D32	NC NC		IO_L17P_T2U_N8_AD10P_71	IO_L17P_T2U_N8_AD10P_71
100	U1_XF.D33 D33	NC NC		VCCO_71	VCCO_71	1.8
100	U1_XF.D34 D34	NC NC		IO_L14N_T2L_N3_GC_71	IO_L14N_T2L_N3_GC_71
100	U1_XF.D35 D35	NC NC		IO_L12N_T1U_N11_GC_71	IO_L12N_T1U_N11_GC_71
100	U1_XF.D36 D36	NC NC		IO_L11P_T1U_N8_GC_71	IO_L11P_T1U_N8_GC_71
100	U1_XF.D37 D37	NC NC		IO_L5P_T0U_N8_AD14P_71	IO_L5P_T0U_N8_AD14P_71
100	U1_XF.D38 D38	GND GND	0V	GND	GND
100	U1_XF.D39 D39	NC NC		IO_L1N_T0L_N1_DBC_71	IO_L1N_T0L_N1_DBC_71
100	U1_XF.D40 D40	NC NC		IO_L21P_T3L_N4_AD8P_37	IO_L21P_T3L_N4_AD8P_37
100	U1_XF.D41 D41	NC NC		IO_L21N_T3L_N5_AD8N_37	IO_L21N_T3L_N5_AD8N_37
100	U1_XF.D42 D42	NC NC		IO_T3U_N12_37	IO_T3U_N12_37
100	U1_XF.D43 D43	NC NC		VCCO_37	VCCO_37	1.8
100	U1_XF.D44 D44	NC NC		IO_L13P_T2L_N0_GC_QBC_37	IO_L13P_T2L_N0_GC_QBC_37
100	U1_XF.D45 D45	NC NC		IO_L13N_T2L_N1_GC_QBC_37	IO_L13N_T2L_N1_GC_QBC_37
100	U1_XF.D46 D46	NC NC		IO_L11P_T1U_N8_GC_37	IO_L11P_T1U_N8_GC_37
100	U1_XF.D47 D47	NC NC		IO_L11N_T1U_N9_GC_37	IO_L11N_T1U_N9_GC_37
100	U1_XF.D48 D48	GND GND	0V	GND	GND
100	U1_XF.D49 D49	NC NC		IO_L5P_T0U_N8_AD14P_37	IO_L5P_T0U_N8_AD14P_37
100	U1_XF.D50 D50	NC NC		IO_L5N_T0U_N9_AD14N_37	IO_L5N_T0U_N9_AD14N_37
100	U1_XF.D51 D51	NC NC		IO_L2P_T0L_N2_37	IO_L2P_T0L_N2_37
16	U1_XF.D52 D52	C2_RDIMM_DQS_C<5>_XF C2_RDIMM_DQS_C<5>_XF		c2_ddr4_dqs_c[12]	IO_L22N_T3U_N7_DBC_AD0N_35
100	U1_XF.D53 D53	GND GND	0V	GND	GND
35	U1_XF.D54 D54	C2_DDR4_DQ<45>_XF C2_DDR4_DQ<45>_XF		c2_ddr4_dq[54]	IO_L20N_T3L_N3_AD1N_35
16	U1_XF.D55 D55	C2_RDIMM_DQS_C<13>_XF C2_RDIMM_DQS_C<13>_XF		c2_ddr4_dqs_c[17]	IO_L13N_T2L_N1_GC_QBC_35
35	U1_XF.D56 D56	C2_DDR4_DQ<36>_XF C2_DDR4_DQ<36>_XF		c2_ddr4_dq[68]	IO_L14P_T2L_N2_GC_35
35	U1_XF.D57 D57	C2_DDR4_DQ<65>_XF C2_DDR4_DQ<65>_XF		c2_ddr4_dq[59]	IO_L11P_T1U_N8_GC_35
-	U1_XF.D58 D58	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_35	VCCO_35	1.2
35	U1_XF.D59 D59	C2_DDR4_DQ<68>_XF C2_DDR4_DQ<68>_XF		c2_ddr4_dq[61]	IO_L8N_T1L_N3_AD5N_35
-	U1_XF.D60 D60	UNNAMED_21_RESISTOR_I26_B_XF UNNAMED_21_RESISTOR_I26_B_XF ->R44_XF->GND		IO_T0U_N12_VRP_35	IO_T0U_N12_VRP_35
35	U1_XF.D61 D61	C2_DDR4_DQ<19>_XF C2_DDR4_DQ<19>_XF		c2_ddr4_dq[35]	IO_L5P_T0U_N8_AD14P_35
35	U1_XF.D62 D62	C2_DDR4_DQ<18>_XF C2_DDR4_DQ<18>_XF		c2_ddr4_dq[34]	IO_L5N_T0U_N9_AD14N_35
100	U1_XF.D63 D63	GND GND	0V	GND	GND
95	U1_XF.E1 E1	E1S0_PER_N<2>_XF E1S0_PER_N<2>_XF		e1s0_per_n[2]	MGTYRXN2_238
95	U1_XF.E2 E2	E1S0_PER_P<2>_XF E1S0_PER_P<2>_XF		e1s0_per_p[2]	MGTYRXP2_238
100	U1_XF.E3 E3	GND GND	0V	GND	GND
100	U1_XF.E4 E4	GND GND	0V	GND	GND
95	U1_XF.E5 E5	E1S0_PER_N<1>_XF E1S0_PER_N<1>_XF		e1s0_per_n[1]	MGTYRXN1_238
95	U1_XF.E6 E6	E1S0_PER_P<1>_XF E1S0_PER_P<1>_XF		e1s0_per_p[1]	MGTYRXP1_238
100	U1_XF.E7 E7	GND GND	0V	GND	GND
100	U1_XF.E8 E8	GND GND	0V	GND	GND
23	U1_XF.E9 E9	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
92	U1_XF.E10 E10	AC_E1S0_PET_N<5>_XF AC_E1S0_PET_N<5>_XF		e1s0_pet_n[5]	MGTYTXN1_237
92	U1_XF.E11 E11	AC_E1S0_PET_P<5>_XF AC_E1S0_PET_P<5>_XF		e1s0_pet_p[5]	MGTYTXP1_237
100	U1_XF.E12 E12	GND GND	0V	GND	GND
23	U1_XF.E13 E13	PWR_AVCC_RN_XF PWR_AVCC_RN_XF	0.9	MGTAVCC_RN	MGTAVCC_RN	0.9
100	U1_XF.E14 E14	GND GND	0V	GND	GND
95	U1_XF.E15 E15	C3_DDR4_DQ<51>_XF C3_DDR4_DQ<51>_XF		c3_ddr4_dq[51]	IO_L17P_T2U_N8_AD10P_77
100	U1_XF.E16 E16	GND GND	0V	GND	GND
35	U1_XF.E17 E17	C3_DDR4_DQ<55>_XF C3_DDR4_DQ<55>_XF		c3_ddr4_dq[52]	IO_L14P_T2L_N2_GC_77
16	U1_XF.E18 E18	C3_RDIMM_DQS_C<15>_XF C3_RDIMM_DQS_C<15>_XF		c3_ddr4_dqs_c[13]	IO_L13N_T2L_N1_GC_QBC_77
35	U1_XF.E19 E19	C3_DDR4_DQ<52>_XF C3_DDR4_DQ<52>_XF		c3_ddr4_dq[55]	IO_L15N_T2L_N5_AD11N_77
95	U1_XF.E20 E20	C3_DDR4_DQ<53>_XF C3_DDR4_DQ<53>_XF		c3_ddr4_dq[53]	IO_L15P_T2L_N4_AD11P_77
100	U1_XF.E21 E21	GND GND	0V	GND	GND
100	U1_XF.E22 E22	NC NC		IO_T2U_N12_76	IO_T2U_N12_76
35	U1_XF.E23 E23	C3_DDR4_DQ<28>_XF C3_DDR4_DQ<28>_XF		c3_ddr4_dq[31]	IO_L14N_T2L_N3_GC_76
95	U1_XF.E24 E24	C3_DDR4_DQ<29>_XF C3_DDR4_DQ<29>_XF		c3_ddr4_dq[29]	IO_L14P_T2L_N2_GC_76
35	U1_XF.E25 E25	C3_DDR4_DQ<18>_XF C3_DDR4_DQ<18>_XF		c3_ddr4_dq[40]	IO_L23N_T3U_N9_76
100	U1_XF.E26 E26	GND GND	0V	GND	GND
54	U1_XF.E27 E27	C3_RDIMM_DQS_C<11>_XF C3_RDIMM_DQS_C<11>_XF		c3_ddr4_dqs_c[11]	IO_L19N_T3L_N1_DBC_AD9N_76
54	U1_XF.E28 E28	C3_RDIMM_DQS_T<11>_XF C3_RDIMM_DQS_T<11>_XF		c3_ddr4_dqs_t[11]	IO_L19P_T3L_N0_DBC_AD9P_76
100	U1_XF.E29 E29	NC NC		IO_L24P_T3U_N10_71	IO_L24P_T3U_N10_71
100	U1_XF.E30 E30	NC NC		IO_L20P_T3L_N2_AD1P_71	IO_L20P_T3L_N2_AD1P_71
100	U1_XF.E31 E31	GND GND	0V	GND	GND
100	U1_XF.E32 E32	NC NC		IO_L18N_T2U_N11_AD2N_71	IO_L18N_T2U_N11_AD2N_71
100	U1_XF.E33 E33	NC NC		IO_L16N_T2U_N7_QBC_AD3N_71	IO_L16N_T2U_N7_QBC_AD3N_71
100	U1_XF.E34 E34	NC NC		IO_L14P_T2L_N2_GC_71	IO_L14P_T2L_N2_GC_71
100	U1_XF.E35 E35	NC NC		IO_L12P_T1U_N10_GC_71	IO_L12P_T1U_N10_GC_71
100	U1_XF.E36 E36	NC NC		VCCO_71	VCCO_71	1.8
100	U1_XF.E37 E37	NC NC		IO_L7N_T1L_N1_QBC_AD13N_71	IO_L7N_T1L_N1_QBC_AD13N_71
100	U1_XF.E38 E38	NC NC		IO_L3N_T0L_N5_AD15N_71	IO_L3N_T0L_N5_AD15N_71
100	U1_XF.E39 E39	NC NC		IO_L1P_T0L_N0_DBC_71	IO_L1P_T0L_N0_DBC_71
100	U1_XF.E40 E40	NC NC		VREF_37	VREF_37
100	U1_XF.E41 E41	GND GND	0V	GND	GND
100	U1_XF.E42 E42	NC NC		IO_L23P_T3U_N8_37	IO_L23P_T3U_N8_37
100	U1_XF.E43 E43	NC NC		IO_L23N_T3U_N9_37	IO_L23N_T3U_N9_37
100	U1_XF.E44 E44	NC NC		IO_L17P_T2U_N8_AD10P_37	IO_L17P_T2U_N8_AD10P_37
100	U1_XF.E45 E45	NC NC		IO_L17N_T2U_N9_AD10N_37	IO_L17N_T2U_N9_AD10N_37
100	U1_XF.E46 E46	NC NC		VCCO_37	VCCO_37	1.8
100	U1_XF.E47 E47	NC NC		IO_L9P_T1L_N4_AD12P_37	IO_L9P_T1L_N4_AD12P_37
100	U1_XF.E48 E48	NC NC		IO_L9N_T1L_N5_AD12N_37	IO_L9N_T1L_N5_AD12N_37
100	U1_XF.E49 E49	NC NC		IO_L4P_T0U_N6_DBC_AD7P_37	IO_L4P_T0U_N6_DBC_AD7P_37
100	U1_XF.E50 E50	NC NC		IO_L4N_T0U_N7_DBC_AD7N_37	IO_L4N_T0U_N7_DBC_AD7N_37
100	U1_XF.E51 E51	GND GND	0V	GND	GND
16	U1_XF.E52 E52	C2_RDIMM_DQS_T<5>_XF C2_RDIMM_DQS_T<5>_XF		c2_ddr4_dqs_t[12]	IO_L22P_T3U_N6_DBC_AD0P_35
16	U1_XF.E53 E53	C2_RDIMM_DQS_C<14>_XF C2_RDIMM_DQS_C<14>_XF		c2_ddr4_dqs_c[13]	IO_L19N_T3L_N1_DBC_AD9N_35
35	U1_XF.E54 E54	C2_DDR4_DQ<44>_XF C2_DDR4_DQ<44>_XF		c2_ddr4_dq[55]	IO_L20P_T3L_N2_AD1P_35
16	U1_XF.E55 E55	C2_RDIMM_DQS_T<13>_XF C2_RDIMM_DQS_T<13>_XF		c2_ddr4_dqs_t[17]	IO_L13P_T2L_N0_GC_QBC_35
100	U1_XF.E56 E56	GND GND	0V	GND	GND
16	U1_XF.E57 E57	C2_RDIMM_DQS_C<4>_XF C2_RDIMM_DQS_C<4>_XF		c2_ddr4_dqs_c[16]	IO_L16N_T2U_N7_QBC_AD3N_35
16	U1_XF.E58 E58	C2_RDIMM_DQS_C<17>_XF C2_RDIMM_DQS_C<17>_XF		c2_ddr4_dqs_c[15]	IO_L7N_T1L_N1_QBC_AD13N_35
35	U1_XF.E59 E59	C2_DDR4_DQ<69>_XF C2_DDR4_DQ<69>_XF		c2_ddr4_dq[60]	IO_L8P_T1L_N2_AD5P_35
35	U1_XF.E60 E60	C2_DDR4_DQ<21>_XF C2_DDR4_DQ<21>_XF		c2_ddr4_dq[38]	IO_L3N_T0L_N5_AD15N_35
-	U1_XF.E61 E61	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_35	VCCO_35	1.2
35	U1_XF.E62 E62	C2_DDR4_DQ<17>_XF C2_DDR4_DQ<17>_XF		c2_ddr4_dq[33]	IO_L6P_T0U_N10_AD6P_35
35	U1_XF.E63 E63	C2_DDR4_DQ<16>_XF C2_DDR4_DQ<16>_XF		c2_ddr4_dq[32]	IO_L6N_T0U_N11_AD6N_35
100	U1_XF.F1 F1	GND GND	0V	GND	GND
100	U1_XF.F2 F2	GND GND	0V	GND	GND
95	U1_XF.F3 F3	E1S0_PER_N<0>_XF E1S0_PER_N<0>_XF		e1s0_per_n[0]	MGTYRXN0_238
95	U1_XF.F4 F4	E1S0_PER_P<0>_XF E1S0_PER_P<0>_XF		e1s0_per_p[0]	MGTYRXP0_238
100	U1_XF.F5 F5	GND GND	0V	GND	GND
100	U1_XF.F6 F6	GND GND	0V	GND	GND
100	U1_XF.F7 F7	GND GND	0V	GND	GND
92	U1_XF.F8 F8	AC_E1S0_PET_N<4>_XF AC_E1S0_PET_N<4>_XF		e1s0_pet_n[4]	MGTYTXN0_237
92	U1_XF.F9 F9	AC_E1S0_PET_P<4>_XF AC_E1S0_PET_P<4>_XF		e1s0_pet_p[4]	MGTYTXP0_237
100	U1_XF.F10 F10	GND GND	0V	GND	GND
23	U1_XF.F11 F11	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
100	U1_XF.F12 F12	NC NC		MGTREFCLK1N_237	MGTREFCLK1N_237
100	U1_XF.F13 F13	NC NC		MGTREFCLK1P_237	MGTREFCLK1P_237
100	U1_XF.F14 F14	GND GND	0V	GND	GND
35	U1_XF.F15 F15	C3_DDR4_DQ<69>_XF C3_DDR4_DQ<69>_XF		c3_ddr4_dq[61]	IO_L8N_T1L_N3_AD5N_77
35	U1_XF.F16 F16	C3_DDR4_DQ<64>_XF C3_DDR4_DQ<64>_XF		c3_ddr4_dq[56]	IO_L12N_T1U_N11_GC_77
35	U1_XF.F17 F17	C3_DDR4_DQ<65>_XF C3_DDR4_DQ<65>_XF		c3_ddr4_dq[57]	IO_L12P_T1U_N10_GC_77
16	U1_XF.F18 F18	C3_RDIMM_DQS_T<15>_XF C3_RDIMM_DQS_T<15>_XF		c3_ddr4_dqs_t[13]	IO_L13P_T2L_N0_GC_QBC_77
100	U1_XF.F19 F19	GND GND	0V	GND	GND
100	U1_XF.F20 F20	NC NC		IO_T2U_N12_77	IO_T2U_N12_77
35	U1_XF.F21 F21	C3_DDR4_DQ<27>_XF C3_DDR4_DQ<27>_XF		c3_ddr4_dq[25]	IO_L18N_T2U_N11_AD2N_76
35	U1_XF.F22 F22	C3_DDR4_DQ<26>_XF C3_DDR4_DQ<26>_XF		c3_ddr4_dq[24]	IO_L18P_T2U_N10_AD2P_76
16	U1_XF.F23 F23	C3_RDIMM_DQS_C<12>_XF C3_RDIMM_DQS_C<12>_XF		c3_ddr4_dqs_c[7]	IO_L13N_T2L_N1_GC_QBC_76
-	U1_XF.F24 F24	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_76	VCCO_76	1.2
35	U1_XF.F25 F25	C3_DDR4_DQ<19>_XF C3_DDR4_DQ<19>_XF		c3_ddr4_dq[41]	IO_L23P_T3U_N8_76
35	U1_XF.F26 F26	C3_DDR4_DQ<22>_XF C3_DDR4_DQ<22>_XF		c3_ddr4_dq[46]	IO_L20N_T3L_N3_AD1N_76
35	U1_XF.F27 F27	C3_DDR4_DQ<23>_XF C3_DDR4_DQ<23>_XF		c3_ddr4_dq[44]	IO_L21N_T3L_N5_AD8N_76
35	U1_XF.F28 F28	C3_DDR4_DQ<20>_XF C3_DDR4_DQ<20>_XF		c3_ddr4_dq[45]	IO_L21P_T3L_N4_AD8P_76
100	U1_XF.F29 F29	GND GND	0V	GND	GND
100	U1_XF.F30 F30	NC NC		VREF_71	VREF_71
100	U1_XF.F31 F31	NC NC		IO_T3U_N12_71	IO_T3U_N12_71
100	U1_XF.F32 F32	NC NC		IO_L18P_T2U_N10_AD2P_71	IO_L18P_T2U_N10_AD2P_71
100	U1_XF.F33 F33	NC NC		IO_L16P_T2U_N6_QBC_AD3P_71	IO_L16P_T2U_N6_QBC_AD3P_71
100	U1_XF.F34 F34	GND GND	0V	GND	GND
100	U1_XF.F35 F35	NC NC		IO_L9P_T1L_N4_AD12P_71	IO_L9P_T1L_N4_AD12P_71
100	U1_XF.F36 F36	NC NC		IO_L9N_T1L_N5_AD12N_71	IO_L9N_T1L_N5_AD12N_71
100	U1_XF.F37 F37	NC NC		IO_L7P_T1L_N0_QBC_AD13P_71	IO_L7P_T1L_N0_QBC_AD13P_71
100	U1_XF.F38 F38	NC NC		IO_L3P_T0L_N4_AD15P_71	IO_L3P_T0L_N4_AD15P_71
100	U1_XF.F39 F39	GND GND	0V	GND	GND
100	U1_XF.F40 F40	NC NC		IO_T0U_N12_VRP_71	IO_T0U_N12_VRP_71
100	U1_XF.F41 F41	NC NC		IO_L22N_T3U_N7_DBC_AD0N_38	IO_L22N_T3U_N7_DBC_AD0N_38
100	U1_XF.F42 F42	NC NC		IO_L24P_T3U_N10_38	IO_L24P_T3U_N10_38
100	U1_XF.F43 F43	NC NC		IO_L24N_T3U_N11_38	IO_L24N_T3U_N11_38
100	U1_XF.F44 F44	GND GND	0V	GND	GND
100	U1_XF.F45 F45	NC NC		IO_T3U_N12_38	IO_T3U_N12_38
100	U1_XF.F46 F46	NC NC		IO_T2U_N12_37	IO_T2U_N12_37
100	U1_XF.F47 F47	NC NC		IO_L7P_T1L_N0_QBC_AD13P_37	IO_L7P_T1L_N0_QBC_AD13P_37
100	U1_XF.F48 F48	NC NC		IO_L7N_T1L_N1_QBC_AD13N_37	IO_L7N_T1L_N1_QBC_AD13N_37
100	U1_XF.F49 F49	GND GND	0V	GND	GND
100	U1_XF.F50 F50	NC NC		IO_L6P_T0U_N10_AD6P_37	IO_L6P_T0U_N10_AD6P_37
100	U1_XF.F51 F51	NC NC		IO_L6N_T0U_N11_AD6N_37	IO_L6N_T0U_N11_AD6N_37
-	U1_XF.F52 F52	UNNAMED_21_RESISTOR_I27_B_XF UNNAMED_21_RESISTOR_I27_B_XF ->R45_XF->GND		VREF_35	VREF_35
16	U1_XF.F53 F53	C2_RDIMM_DQS_T<14>_XF C2_RDIMM_DQS_T<14>_XF		c2_ddr4_dqs_t[13]	IO_L19P_T3L_N0_DBC_AD9P_35
100	U1_XF.F54 F54	GND GND	0V	GND	GND
35	U1_XF.F55 F55	C2_DDR4_DQ<35>_XF C2_DDR4_DQ<35>_XF		c2_ddr4_dq[64]	IO_L18P_T2U_N10_AD2P_35
35	U1_XF.F56 F56	C2_DDR4_DQ<34>_XF C2_DDR4_DQ<34>_XF		c2_ddr4_dq[65]	IO_L18N_T2U_N11_AD2N_35
16	U1_XF.F57 F57	C2_RDIMM_DQS_T<4>_XF C2_RDIMM_DQS_T<4>_XF		c2_ddr4_dqs_t[16]	IO_L16P_T2U_N6_QBC_AD3P_35
16	U1_XF.F58 F58	C2_RDIMM_DQS_T<17>_XF C2_RDIMM_DQS_T<17>_XF		c2_ddr4_dqs_t[15]	IO_L7P_T1L_N0_QBC_AD13P_35
100	U1_XF.F59 F59	GND GND	0V	GND	GND
35	U1_XF.F60 F60	C2_DDR4_DQ<23>_XF C2_DDR4_DQ<23>_XF		c2_ddr4_dq[39]	IO_L3P_T0L_N4_AD15P_35
16	U1_XF.F61 F61	C2_RDIMM_DQS_T<11>_XF C2_RDIMM_DQS_T<11>_XF		c2_ddr4_dqs_t[9]	IO_L1P_T0L_N0_DBC_35
16	U1_XF.F62 F62	C2_RDIMM_DQS_C<11>_XF C2_RDIMM_DQS_C<11>_XF		c2_ddr4_dqs_c[9]	IO_L1N_T0L_N1_DBC_35
54	U1_XF.F63 F63	C2_RDIMM_DQS_C<2>_XF C2_RDIMM_DQS_C<2>_XF		c2_ddr4_dqs_c[8]	IO_L4N_T0U_N7_DBC_AD7N_35
95	U1_XF.G1 G1	E1S0_PER_N<7>_XF E1S0_PER_N<7>_XF		e1s0_per_n[7]	MGTYRXN3_237
95	U1_XF.G2 G2	E1S0_PER_P<7>_XF E1S0_PER_P<7>_XF		e1s0_per_p[7]	MGTYRXP3_237
100	U1_XF.G3 G3	GND GND	0V	GND	GND
100	U1_XF.G4 G4	GND GND	0V	GND	GND
95	U1_XF.G5 G5	E1S0_PER_N<6>_XF E1S0_PER_N<6>_XF		e1s0_per_n[6]	MGTYRXN2_237
95	U1_XF.G6 G6	E1S0_PER_P<6>_XF E1S0_PER_P<6>_XF		e1s0_per_p[6]	MGTYRXP2_237
100	U1_XF.G7 G7	GND GND	0V	GND	GND
100	U1_XF.G8 G8	GND GND	0V	GND	GND
23	U1_XF.G9 G9	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
100	U1_XF.G10 G10	NC NC		MGTYTXN3_236	MGTYTXN3_236
100	U1_XF.G11 G11	NC NC		MGTYTXP3_236	MGTYTXP3_236
100	U1_XF.G12 G12	GND GND	0V	GND	GND
23	U1_XF.G13 G13	PWR_AVCC_RN_XF PWR_AVCC_RN_XF	0.9	MGTAVCC_RN	MGTAVCC_RN	0.9
100	U1_XF.G14 G14	GND GND	0V	GND	GND
35	U1_XF.G15 G15	C3_DDR4_DQ<68>_XF C3_DDR4_DQ<68>_XF		c3_ddr4_dq[60]	IO_L8P_T1L_N2_AD5P_77
35	U1_XF.G16 G16	C3_DDR4_DQ<70>_XF C3_DDR4_DQ<70>_XF		c3_ddr4_dq[62]	IO_L9N_T1L_N5_AD12N_77
100	U1_XF.G17 G17	GND GND	0V	GND	GND
35	U1_XF.G18 G18	C3_DDR4_DQ<66>_XF C3_DDR4_DQ<66>_XF		c3_ddr4_dq[59]	IO_L11N_T1U_N9_GC_77
35	U1_XF.G19 G19	C3_DDR4_DQ<67>_XF C3_DDR4_DQ<67>_XF		c3_ddr4_dq[58]	IO_L11P_T1U_N8_GC_77
100	U1_XF.G20 G20	NC NC		IO_T1U_N12_77	IO_T1U_N12_77
54	U1_XF.G21 G21	C3_RDIMM_DQS_C<3>_XF C3_RDIMM_DQS_C<3>_XF		c3_ddr4_dqs_c[6]	IO_L16N_T2U_N7_QBC_AD3N_76
100	U1_XF.G22 G22	GND GND	0V	GND	GND
16	U1_XF.G23 G23	C3_RDIMM_DQS_T<12>_XF C3_RDIMM_DQS_T<12>_XF		c3_ddr4_dqs_t[7]	IO_L13P_T2L_N0_GC_QBC_76
35	U1_XF.G24 G24	C3_DDR4_DQ<31>_XF C3_DDR4_DQ<31>_XF		c3_ddr4_dq[30]	IO_L15N_T2L_N5_AD11N_76
100	U1_XF.G25 G25	NC NC		IO_T3U_N12_76	IO_T3U_N12_76
35	U1_XF.G26 G26	C3_DDR4_DQ<21>_XF C3_DDR4_DQ<21>_XF		c3_ddr4_dq[47]	IO_L20P_T3L_N2_AD1P_76
-	U1_XF.G27 G27	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_76	VCCO_76	1.2
16	U1_XF.G28 G28	C3_RDIMM_DQS_C<2>_XF C3_RDIMM_DQS_C<2>_XF		c3_ddr4_dqs_c[10]	IO_L22N_T3U_N7_DBC_AD0N_76
100	U1_XF.G29 G29	NC NC		IO_L24N_T3U_N11_72	IO_L24N_T3U_N11_72
100	U1_XF.G30 G30	NC NC		IO_L22N_T3U_N7_DBC_AD0N_72	IO_L22N_T3U_N7_DBC_AD0N_72
100	U1_XF.G31 G31	NC NC		IO_L22P_T3U_N6_DBC_AD0P_72	IO_L22P_T3U_N6_DBC_AD0P_72
100	U1_XF.G32 G32	GND GND	0V	GND	GND
100	U1_XF.G33 G33	NC NC		IO_L20N_T3L_N3_AD1N_72	IO_L20N_T3L_N3_AD1N_72
100	U1_XF.G34 G34	NC NC		IO_T3U_N12_72	IO_T3U_N12_72
100	U1_XF.G35 G35	NC NC		IO_L19P_T3L_N0_DBC_AD9P_70	IO_L19P_T3L_N0_DBC_AD9P_70
100	U1_XF.G36 G36	NC NC		IO_L19N_T3L_N1_DBC_AD9N_70	IO_L19N_T3L_N1_DBC_AD9N_70
100	U1_XF.G37 G37	GND GND	0V	GND	GND
100	U1_XF.G38 G38	NC NC		IO_L24N_T3U_N11_70	IO_L24N_T3U_N11_70
100	U1_XF.G39 G39	NC NC		IO_L22P_T3U_N6_DBC_AD0P_70	IO_L22P_T3U_N6_DBC_AD0P_70
100	U1_XF.G40 G40	NC NC		IO_L22N_T3U_N7_DBC_AD0N_70	IO_L22N_T3U_N7_DBC_AD0N_70
100	U1_XF.G41 G41	NC NC		IO_L22P_T3U_N6_DBC_AD0P_38	IO_L22P_T3U_N6_DBC_AD0P_38
100	U1_XF.G42 G42	GND GND	0V	GND	GND
100	U1_XF.G43 G43	NC NC		IO_L20P_T3L_N2_AD1P_38	IO_L20P_T3L_N2_AD1P_38
100	U1_XF.G44 G44	NC NC		IO_L20N_T3L_N3_AD1N_38	IO_L20N_T3L_N3_AD1N_38
100	U1_XF.G45 G45	NC NC		IO_L19P_T3L_N0_DBC_AD9P_38	IO_L19P_T3L_N0_DBC_AD9P_38
100	U1_XF.G46 G46	NC NC		IO_L19N_T3L_N1_DBC_AD9N_38	IO_L19N_T3L_N1_DBC_AD9N_38
100	U1_XF.G47 G47	GND GND	0V	GND	GND
16	U1_XF.G48 G48	C2_RDIMM_DQS_T<15>_XF C2_RDIMM_DQS_T<15>_XF		c2_ddr4_dqs_t[7]	IO_L19P_T3L_N0_DBC_AD9P_36
16	U1_XF.G49 G49	C2_RDIMM_DQS_C<15>_XF C2_RDIMM_DQS_C<15>_XF		c2_ddr4_dqs_c[7]	IO_L19N_T3L_N1_DBC_AD9N_36
35	U1_XF.G50 G50	C2_DDR4_DQ<49>_XF C2_DDR4_DQ<49>_XF		c2_ddr4_dq[27]	IO_L24P_T3U_N10_36
35	U1_XF.G51 G51	C2_DDR4_DQ<48>_XF C2_DDR4_DQ<48>_XF		c2_ddr4_dq[26]	IO_L24N_T3U_N11_36
100	U1_XF.G52 G52	GND GND	0V	GND	GND
36	U1_XF.G53 G53	C2_DDR4_DQ<31>_XF C2_DDR4_DQ<31>_XF		c2_ddr4_dq[4]	IO_L20P_T3L_N2_AD1P_34
36	U1_XF.G54 G54	C2_DDR4_DQ<30>_XF C2_DDR4_DQ<30>_XF		c2_ddr4_dq[6]	IO_L20N_T3L_N3_AD1N_34
100	U1_XF.G55 G55	NC NC		IO_L18P_T2U_N10_AD2P_34	IO_L18P_T2U_N10_AD2P_34
100	U1_XF.G56 G56	NC NC		IO_L18N_T2U_N11_AD2N_34	IO_L18N_T2U_N11_AD2N_34
100	U1_XF.G57 G57	GND GND	0V	GND	GND
95	U1_XF.G58 G58	C2_DDR4_ADR<13>_XF C2_DDR4_ADR<13>_XF		c2_ddr4_adr[13]	IO_L7P_T1L_N0_QBC_AD13P_34
20	U1_XF.G59 G59	C2_DDR4_ADR<15>_XF C2_DDR4_ADR<15>_XF		c2_ddr4_cs_n[2]	IO_L7N_T1L_N1_QBC_AD13N_34
35	U1_XF.G60 G60	C2_DDR4_DQ<22>_XF C2_DDR4_DQ<22>_XF		c2_ddr4_dq[37]	IO_L2P_T0L_N2_35
35	U1_XF.G61 G61	C2_DDR4_DQ<20>_XF C2_DDR4_DQ<20>_XF		c2_ddr4_dq[36]	IO_L2N_T0L_N3_35
100	U1_XF.G62 G62	GND GND	0V	GND	GND
16	U1_XF.G63 G63	C2_RDIMM_DQS_T<2>_XF C2_RDIMM_DQS_T<2>_XF		c2_ddr4_dqs_t[8]	IO_L4P_T0U_N6_DBC_AD7P_35
100	U1_XF.H1 H1	GND GND	0V	GND	GND
100	U1_XF.H2 H2	GND GND	0V	GND	GND
95	U1_XF.H3 H3	E1S0_PER_N<5>_XF E1S0_PER_N<5>_XF		e1s0_per_n[5]	MGTYRXN1_237
95	U1_XF.H4 H4	E1S0_PER_P<5>_XF E1S0_PER_P<5>_XF		e1s0_per_p[5]	MGTYRXP1_237
100	U1_XF.H5 H5	GND GND	0V	GND	GND
100	U1_XF.H6 H6	GND GND	0V	GND	GND
100	U1_XF.H7 H7	GND GND	0V	GND	GND
100	U1_XF.H8 H8	NC NC		MGTYTXN2_236	MGTYTXN2_236
100	U1_XF.H9 H9	NC NC		MGTYTXP2_236	MGTYTXP2_236
100	U1_XF.H10 H10	GND GND	0V	GND	GND
23	U1_XF.H11 H11	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
85	U1_XF.H12 H12	E1S0_FPGA_REFCLK_N<1>_XF E1S0_FPGA_REFCLK_N<1>_XF		e1s0_refclk_n[1]	MGTREFCLK0N_237
85	U1_XF.H13 H13	E1S0_FPGA_REFCLK_P<1>_XF E1S0_FPGA_REFCLK_P<1>_XF		e1s0_refclk_p[1]	MGTREFCLK0P_237
100	U1_XF.H14 H14	GND GND	0V	GND	GND
-	U1_XF.H15 H15	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_77	VCCO_77	1.2
35	U1_XF.H16 H16	C3_DDR4_DQ<71>_XF C3_DDR4_DQ<71>_XF		c3_ddr4_dq[63]	IO_L9P_T1L_N4_AD12P_77
16	U1_XF.H17 H17	C3_RDIMM_DQS_C<8>_XF C3_RDIMM_DQS_C<8>_XF		c3_ddr4_dqs_c[14]	IO_L10N_T1U_N7_QBC_AD4N_77
16	U1_XF.H18 H18	C3_RDIMM_DQS_T<8>_XF C3_RDIMM_DQS_T<8>_XF		c3_ddr4_dqs_t[14]	IO_L10P_T1U_N6_QBC_AD4P_77
16	U1_XF.H19 H19	C3_RDIMM_DQS_C<17>_XF C3_RDIMM_DQS_C<17>_XF		c3_ddr4_dqs_c[15]	IO_L7N_T1L_N1_QBC_AD13N_77
100	U1_XF.H20 H20	GND GND	0V	GND	GND
16	U1_XF.H21 H21	C3_RDIMM_DQS_T<3>_XF C3_RDIMM_DQS_T<3>_XF		c3_ddr4_dqs_t[6]	IO_L16P_T2U_N6_QBC_AD3P_76
35	U1_XF.H22 H22	C3_DDR4_DQ<25>_XF C3_DDR4_DQ<25>_XF		c3_ddr4_dq[26]	IO_L17N_T2U_N9_AD10N_76
35	U1_XF.H23 H23	C3_DDR4_DQ<24>_XF C3_DDR4_DQ<24>_XF		c3_ddr4_dq[27]	IO_L17P_T2U_N8_AD10P_76
35	U1_XF.H24 H24	C3_DDR4_DQ<30>_XF C3_DDR4_DQ<30>_XF		c3_ddr4_dq[28]	IO_L15P_T2L_N4_AD11P_76
100	U1_XF.H25 H25	GND GND	0V	GND	GND
35	U1_XF.H26 H26	C3_DDR4_DQ<17>_XF C3_DDR4_DQ<17>_XF		c3_ddr4_dq[42]	IO_L24N_T3U_N11_76
35	U1_XF.H27 H27	C3_DDR4_DQ<16>_XF C3_DDR4_DQ<16>_XF		c3_ddr4_dq[43]	IO_L24P_T3U_N10_76
16	U1_XF.H28 H28	C3_RDIMM_DQS_T<2>_XF C3_RDIMM_DQS_T<2>_XF		c3_ddr4_dqs_t[10]	IO_L22P_T3U_N6_DBC_AD0P_76
100	U1_XF.H29 H29	NC NC		IO_L24P_T3U_N10_72	IO_L24P_T3U_N10_72
100	U1_XF.H30 H30	NC NC		VCCO_72	VCCO_72	1.8
100	U1_XF.H31 H31	NC NC		IO_L23N_T3U_N9_72	IO_L23N_T3U_N9_72
100	U1_XF.H32 H32	NC NC		IO_L23P_T3U_N8_72	IO_L23P_T3U_N8_72
100	U1_XF.H33 H33	NC NC		IO_L20P_T3L_N2_AD1P_72	IO_L20P_T3L_N2_AD1P_72
100	U1_XF.H34 H34	NC NC		IO_L19N_T3L_N1_DBC_AD9N_72	IO_L19N_T3L_N1_DBC_AD9N_72
100	U1_XF.H35 H35	GND GND	0V	GND	GND
100	U1_XF.H36 H36	NC NC		IO_L23N_T3U_N9_70	IO_L23N_T3U_N9_70
100	U1_XF.H37 H37	NC NC		IO_L21N_T3L_N5_AD8N_70	IO_L21N_T3L_N5_AD8N_70
100	U1_XF.H38 H38	NC NC		IO_L24P_T3U_N10_70	IO_L24P_T3U_N10_70
100	U1_XF.H39 H39	NC NC		IO_T3U_N12_70	IO_T3U_N12_70
100	U1_XF.H40 H40	GND GND	0V	GND	GND
100	U1_XF.H41 H41	NC NC		IO_L23P_T3U_N8_38	IO_L23P_T3U_N8_38
100	U1_XF.H42 H42	NC NC		IO_L23N_T3U_N9_38	IO_L23N_T3U_N9_38
100	U1_XF.H43 H43	NC NC		IO_L21P_T3L_N4_AD8P_38	IO_L21P_T3L_N4_AD8P_38
100	U1_XF.H44 H44	NC NC		IO_L21N_T3L_N5_AD8N_38	IO_L21N_T3L_N5_AD8N_38
100	U1_XF.H45 H45	GND GND	0V	GND	GND
100	U1_XF.H46 H46	NC NC		IO_L18N_T2U_N11_AD2N_38	IO_L18N_T2U_N11_AD2N_38
35	U1_XF.H47 H47	C2_DDR4_DQ<51>_XF C2_DDR4_DQ<51>_XF		c2_ddr4_dq[25]	IO_L23N_T3U_N9_36
35	U1_XF.H48 H48	C2_DDR4_DQ<54>_XF C2_DDR4_DQ<54>_XF		c2_ddr4_dq[30]	IO_L21P_T3L_N4_AD8P_36
35	U1_XF.H49 H49	C2_DDR4_DQ<55>_XF C2_DDR4_DQ<55>_XF		c2_ddr4_dq[31]	IO_L21N_T3L_N5_AD8N_36
-	U1_XF.H50 H50	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_36	VCCO_36	1.2
54	U1_XF.H51 H51	C2_RDIMM_DQS_C<6>_XF C2_RDIMM_DQS_C<6>_XF		c2_ddr4_dqs_c[6]	IO_L22N_T3U_N7_DBC_AD0N_36
36	U1_XF.H52 H52	C2_DDR4_DQ<26>_XF C2_DDR4_DQ<26>_XF		c2_ddr4_dq[3]	IO_L24P_T3U_N10_34
36	U1_XF.H53 H53	C2_DDR4_DQ<27>_XF C2_DDR4_DQ<27>_XF		c2_ddr4_dq[1]	IO_L24N_T3U_N11_34
16	U1_XF.H54 H54	C2_RDIMM_DQS_C<3>_XF C2_RDIMM_DQS_C<3>_XF		c2_ddr4_dqs_c[0]	IO_L22N_T3U_N7_DBC_AD0N_34
100	U1_XF.H55 H55	GND GND	0V	GND	GND
20	U1_XF.H56 H56	C2_DDR4_ODT<1>_XF C2_DDR4_ODT<1>_XF		c2_ddr4_adr[11]	IO_L14N_T2L_N3_GC_34
95	U1_XF.H57 H57	C2_DDR4_ALERT_N_XF C2_DDR4_ALERT_N_XF		c2_ddr4_alert_n	IO_T2U_N12_34
37	U1_XF.H58 H58	C2_DDR4_ODT<0>_XF C2_DDR4_ODT<0>_XF		c2_ddr4_odt[1]	IO_L9P_T1L_N4_AD12P_34
37	U1_XF.H59 H59	C2_DDR4_CS_N<0>_XF C2_DDR4_CS_N<0>_XF		c2_ddr4_cs_n[1]	IO_L9N_T1L_N5_AD12N_34
100	U1_XF.H60 H60	GND GND	0V	GND	GND
-	U1_XF.H61 H61	UNNAMED_21_RESISTOR_I28_B_XF UNNAMED_21_RESISTOR_I28_B_XF ->R46_XF->GND		IO_T0U_N12_VRP_34	IO_T0U_N12_VRP_34
35	U1_XF.H62 H62	C2_DDR4_ADR<10>_XF C2_DDR4_ADR<10>_XF		c2_ddr4_adr[14]	IO_L1P_T0L_N0_DBC_34
20	U1_XF.H63 H63	C2_DDR4_BA<0>_XF C2_DDR4_BA<0>_XF		c2_ddr4_parity	IO_L1N_T0L_N1_DBC_34
95	U1_XF.J1 J1	E1S0_PER_N<4>_XF E1S0_PER_N<4>_XF		e1s0_per_n[4]	MGTYRXN0_237
95	U1_XF.J2 J2	E1S0_PER_P<4>_XF E1S0_PER_P<4>_XF		e1s0_per_p[4]	MGTYRXP0_237
100	U1_XF.J3 J3	GND GND	0V	GND	GND
100	U1_XF.J4 J4	GND GND	0V	GND	GND
100	U1_XF.J5 J5	NC NC		MGTYRXN3_236	MGTYRXN3_236
100	U1_XF.J6 J6	NC NC		MGTYRXP3_236	MGTYRXP3_236
100	U1_XF.J7 J7	GND GND	0V	GND	GND
100	U1_XF.J8 J8	GND GND	0V	GND	GND
23	U1_XF.J9 J9	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
100	U1_XF.J10 J10	NC NC		MGTYTXN1_236	MGTYTXN1_236
100	U1_XF.J11 J11	NC NC		MGTYTXP1_236	MGTYTXP1_236
100	U1_XF.J12 J12	GND GND	0V	GND	GND
23	U1_XF.J13 J13	PWR_AVCC_RN_XF PWR_AVCC_RN_XF	0.9	MGTAVCC_RN	MGTAVCC_RN	0.9
100	U1_XF.J14 J14	GND GND	0V	GND	GND
95	U1_XF.J15 J15	C3_DDR4_DQ<4>_XF C3_DDR4_DQ<4>_XF		c3_ddr4_dq[4]	IO_L3N_T0L_N5_AD15N_77
95	U1_XF.J16 J16	C3_DDR4_DQ<5>_XF C3_DDR4_DQ<5>_XF		c3_ddr4_dq[5]	IO_L3P_T0L_N4_AD15P_77
37	U1_XF.J17 J17	C3_DDR4_DQ<6>_XF C3_DDR4_DQ<6>_XF		c3_ddr4_dq[7]	IO_L2N_T0L_N3_77
-	U1_XF.J18 J18	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_77	VCCO_77	1.2
-	U1_XF.J19 J19	UNNAMED_22_RESISTOR_I35_B_XF UNNAMED_22_RESISTOR_I35_B_XF ->R48_XF->GND		IO_T0U_N12_VRP_77	IO_T0U_N12_VRP_77
16	U1_XF.J20 J20	C3_RDIMM_DQS_T<17>_XF C3_RDIMM_DQS_T<17>_XF		c3_ddr4_dqs_t[15]	IO_L7P_T1L_N0_QBC_AD13P_77
16	U1_XF.J21 J21	C3_DDR4_CS_N<3>_XF C3_DDR4_CS_N<3>_XF		c3_ddr4_adr[15]	IO_L17N_T2U_N9_AD10N_75
16	U1_XF.J22 J22	C3_DDR4_CS_N<2>_XF C3_DDR4_CS_N<2>_XF		c3_ddr4_adr[14]	IO_L17P_T2U_N8_AD10P_75
100	U1_XF.J23 J23	GND GND	0V	GND	GND
20	U1_XF.J24 J24	C3_DDR4_ODT<0>_XF C3_DDR4_ODT<0>_XF		c3_ddr4_cs_n[2]	IO_T3U_N12_75
35	U1_XF.J25 J25	C3_DDR4_DQ<11>_XF C3_DDR4_DQ<11>_XF		c3_ddr4_dq[35]	IO_L23N_T3U_N9_75
35	U1_XF.J26 J26	C3_DDR4_DQ<10>_XF C3_DDR4_DQ<10>_XF		c3_ddr4_dq[34]	IO_L23P_T3U_N8_75
-	U1_XF.J27 J27	UNNAMED_22_RESISTOR_I37_B_XF UNNAMED_22_RESISTOR_I37_B_XF ->R53_XF->GND		VREF_76	VREF_76
100	U1_XF.J28 J28	GND GND	0V	GND	GND
100	U1_XF.J29 J29	NC NC		IO_L18N_T2U_N11_AD2N_72	IO_L18N_T2U_N11_AD2N_72
100	U1_XF.J30 J30	NC NC		IO_L18P_T2U_N10_AD2P_72	IO_L18P_T2U_N10_AD2P_72
100	U1_XF.J31 J31	NC NC		IO_L21N_T3L_N5_AD8N_72	IO_L21N_T3L_N5_AD8N_72
100	U1_XF.J32 J32	NC NC		IO_L21P_T3L_N4_AD8P_72	IO_L21P_T3L_N4_AD8P_72
100	U1_XF.J33 J33	GND GND	0V	GND	GND
100	U1_XF.J34 J34	NC NC		IO_L19P_T3L_N0_DBC_AD9P_72	IO_L19P_T3L_N0_DBC_AD9P_72
100	U1_XF.J35 J35	NC NC		IO_L17N_T2U_N9_AD10N_70	IO_L17N_T2U_N9_AD10N_70
100	U1_XF.J36 J36	NC NC		IO_L23P_T3U_N8_70	IO_L23P_T3U_N8_70
100	U1_XF.J37 J37	NC NC		IO_L21P_T3L_N4_AD8P_70	IO_L21P_T3L_N4_AD8P_70
100	U1_XF.J38 J38	NC NC		VCCO_70	VCCO_70	1.8
100	U1_XF.J39 J39	NC NC		IO_L20P_T3L_N2_AD1P_70	IO_L20P_T3L_N2_AD1P_70
100	U1_XF.J40 J40	NC NC		IO_L20N_T3L_N3_AD1N_70	IO_L20N_T3L_N3_AD1N_70
100	U1_XF.J41 J41	NC NC		IO_T2U_N12_38	IO_T2U_N12_38
100	U1_XF.J42 J42	NC NC		IO_L17N_T2U_N9_AD10N_38	IO_L17N_T2U_N9_AD10N_38
100	U1_XF.J43 J43	NC NC		VCCO_38	VCCO_38	1.8
100	U1_XF.J44 J44	NC NC		IO_L16P_T2U_N6_QBC_AD3P_38	IO_L16P_T2U_N6_QBC_AD3P_38
100	U1_XF.J45 J45	NC NC		IO_L16N_T2U_N7_QBC_AD3N_38	IO_L16N_T2U_N7_QBC_AD3N_38
100	U1_XF.J46 J46	NC NC		IO_L18P_T2U_N10_AD2P_38	IO_L18P_T2U_N10_AD2P_38
35	U1_XF.J47 J47	C2_DDR4_DQ<50>_XF C2_DDR4_DQ<50>_XF		c2_ddr4_dq[24]	IO_L23P_T3U_N8_36
100	U1_XF.J48 J48	GND GND	0V	GND	GND
100	U1_XF.J49 J49	NC NC		IO_T3U_N12_36	IO_T3U_N12_36
35	U1_XF.J50 J50	C2_DDR4_DQ<53>_XF C2_DDR4_DQ<53>_XF		c2_ddr4_dq[29]	IO_L20N_T3L_N3_AD1N_36
54	U1_XF.J51 J51	C2_RDIMM_DQS_T<6>_XF C2_RDIMM_DQS_T<6>_XF		c2_ddr4_dqs_t[6]	IO_L22P_T3U_N6_DBC_AD0P_36
36	U1_XF.J52 J52	C2_DDR4_DQ<29>_XF C2_DDR4_DQ<29>_XF		c2_ddr4_dq[5]	IO_L21N_T3L_N5_AD8N_34
-	U1_XF.J53 J53	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_34	VCCO_34	1.2
16	U1_XF.J54 J54	C2_RDIMM_DQS_T<3>_XF C2_RDIMM_DQS_T<3>_XF		c2_ddr4_dqs_t[0]	IO_L22P_T3U_N6_DBC_AD0P_34
16	U1_XF.J55 J55	C2_DDR4_CS_N<2>_XF C2_DDR4_CS_N<2>_XF		c2_ddr4_reset_n	IO_L15N_T2L_N5_AD11N_34
16	U1_XF.J56 J56	C2_DDR4_CS_N<3>_XF C2_DDR4_CS_N<3>_XF		c2_ddr4_adr[12]	IO_L14P_T2L_N2_GC_34
16	U1_XF.J57 J57	C2_DDR4_CS_N<1>_XF C2_DDR4_CS_N<1>_XF		c2_ddr4_adr[6]	IO_L13N_T2L_N1_GC_QBC_34
100	U1_XF.J58 J58	GND GND	0V	GND	GND
95	U1_XF.J59 J59	C2_SYS_CLK_P_XF C2_SYS_CLK_P_XF		c2_sys_clk_p	IO_L11P_T1U_N8_GC_34
95	U1_XF.J60 J60	C2_SYS_CLK_N_XF C2_SYS_CLK_N_XF		c2_sys_clk_n	IO_L11N_T1U_N9_GC_34
36	U1_XF.J61 J61	C2_DDR4_ADR<16>_XF C2_DDR4_ADR<16>_XF		c2_ddr4_adr[5]	IO_L5P_T0U_N8_AD14P_34
20	U1_XF.J62 J62	C2_DDR4_BA<1>_XF C2_DDR4_BA<1>_XF		c2_ddr4_adr[4]	IO_L5N_T0U_N9_AD14N_34
100	U1_XF.J63 J63	GND GND	0V	GND	GND
100	U1_XF.K1 K1	GND GND	0V	GND	GND
100	U1_XF.K2 K2	GND GND	0V	GND	GND
100	U1_XF.K3 K3	NC NC		MGTYRXN2_236	MGTYRXN2_236
100	U1_XF.K4 K4	NC NC		MGTYRXP2_236	MGTYRXP2_236
100	U1_XF.K5 K5	GND GND	0V	GND	GND
100	U1_XF.K6 K6	GND GND	0V	GND	GND
100	U1_XF.K7 K7	GND GND	0V	GND	GND
100	U1_XF.K8 K8	NC NC		MGTYTXN0_236	MGTYTXN0_236
100	U1_XF.K9 K9	NC NC		MGTYTXP0_236	MGTYTXP0_236
100	U1_XF.K10 K10	GND GND	0V	GND	GND
23	U1_XF.K11 K11	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
100	U1_XF.K12 K12	NC NC		MGTREFCLK1N_236	MGTREFCLK1N_236
100	U1_XF.K13 K13	NC NC		MGTREFCLK1P_236	MGTREFCLK1P_236
100	U1_XF.K14 K14	GND GND	0V	GND	GND
16	U1_XF.K15 K15	C3_RDIMM_DQS_C<9>_XF C3_RDIMM_DQS_C<9>_XF		c3_ddr4_dqs_c[1]	IO_L1N_T0L_N1_DBC_77
100	U1_XF.K16 K16	GND GND	0V	GND	GND
37	U1_XF.K17 K17	C3_DDR4_DQ<7>_XF C3_DDR4_DQ<7>_XF		c3_ddr4_dq[6]	IO_L2P_T0L_N2_77
54	U1_XF.K18 K18	C3_RDIMM_DQS_C<0>_XF C3_RDIMM_DQS_C<0>_XF		c3_ddr4_dqs_c[0]	IO_L4N_T0U_N7_DBC_AD7N_77
95	U1_XF.K19 K19	C3_DDR4_DQ<3>_XF C3_DDR4_DQ<3>_XF		c3_ddr4_dq[3]	IO_L6N_T0U_N11_AD6N_77
95	U1_XF.K20 K20	C3_DDR4_DQ<2>_XF C3_DDR4_DQ<2>_XF		c3_ddr4_dq[2]	IO_L6P_T0U_N10_AD6P_77
100	U1_XF.K21 K21	GND GND	0V	GND	GND
20	U1_XF.K22 K22	C3_DDR4_ODT<1>_XF C3_DDR4_ODT<1>_XF		c3_ddr4_adr[10]	IO_L15N_T2L_N5_AD11N_75
95	U1_XF.K23 K23	C3_DDR4_ALERT_N_XF C3_DDR4_ALERT_N_XF		c3_ddr4_alert_n	IO_T2U_N12_75
35	U1_XF.K24 K24	C3_DDR4_DQ<14>_XF C3_DDR4_DQ<14>_XF		c3_ddr4_dq[36]	IO_L21N_T3L_N5_AD8N_75
35	U1_XF.K25 K25	C3_DDR4_DQ<15>_XF C3_DDR4_DQ<15>_XF		c3_ddr4_dq[38]	IO_L21P_T3L_N4_AD8P_75
100	U1_XF.K26 K26	GND GND	0V	GND	GND
16	U1_XF.K27 K27	C3_RDIMM_DQS_C<10>_XF C3_RDIMM_DQS_C<10>_XF		c3_ddr4_dqs_c[9]	IO_L19N_T3L_N1_DBC_AD9N_75
16	U1_XF.K28 K28	C3_RDIMM_DQS_T<10>_XF C3_RDIMM_DQS_T<10>_XF		c3_ddr4_dqs_t[9]	IO_L19P_T3L_N0_DBC_AD9P_75
100	U1_XF.K29 K29	NC NC		IO_L16N_T2U_N7_QBC_AD3N_72	IO_L16N_T2U_N7_QBC_AD3N_72
100	U1_XF.K30 K30	NC NC		IO_L16P_T2U_N6_QBC_AD3P_72	IO_L16P_T2U_N6_QBC_AD3P_72
100	U1_XF.K31 K31	GND GND	0V	GND	GND
100	U1_XF.K32 K32	NC NC		IO_L13N_T2L_N1_GC_QBC_72	IO_L13N_T2L_N1_GC_QBC_72
100	U1_XF.K33 K33	NC NC		IO_L17N_T2U_N9_AD10N_72	IO_L17N_T2U_N9_AD10N_72
100	U1_XF.K34 K34	NC NC		IO_T2U_N12_72	IO_T2U_N12_72
100	U1_XF.K35 K35	NC NC		IO_L17P_T2U_N8_AD10P_70	IO_L17P_T2U_N8_AD10P_70
100	U1_XF.K36 K36	GND GND	0V	GND	GND
100	U1_XF.K37 K37	NC NC		IO_L13P_T2L_N0_GC_QBC_70	IO_L13P_T2L_N0_GC_QBC_70
100	U1_XF.K38 K38	NC NC		IO_L13N_T2L_N1_GC_QBC_70	IO_L13N_T2L_N1_GC_QBC_70
100	U1_XF.K39 K39	NC NC		IO_L18P_T2U_N10_AD2P_70	IO_L18P_T2U_N10_AD2P_70
100	U1_XF.K40 K40	NC NC		IO_L18N_T2U_N11_AD2N_70	IO_L18N_T2U_N11_AD2N_70
100	U1_XF.K41 K41	GND GND	0V	GND	GND
100	U1_XF.K42 K42	NC NC		IO_L17P_T2U_N8_AD10P_38	IO_L17P_T2U_N8_AD10P_38
100	U1_XF.K43 K43	NC NC		IO_L14P_T2L_N2_GC_38	IO_L14P_T2L_N2_GC_38
100	U1_XF.K44 K44	NC NC		IO_L14N_T2L_N3_GC_38	IO_L14N_T2L_N3_GC_38
100	U1_XF.K45 K45	NC NC		VREF_38	VREF_38
100	U1_XF.K46 K46	GND GND	0V	GND	GND
35	U1_XF.K47 K47	C2_DDR4_DQ<59>_XF C2_DDR4_DQ<59>_XF		c2_ddr4_dq[40]	IO_L17P_T2U_N8_AD10P_36
35	U1_XF.K48 K48	C2_DDR4_DQ<58>_XF C2_DDR4_DQ<58>_XF		c2_ddr4_dq[41]	IO_L17N_T2U_N9_AD10N_36
100	U1_XF.K49 K49	NC NC		IO_T2U_N12_36	IO_T2U_N12_36
35	U1_XF.K50 K50	C2_DDR4_DQ<52>_XF C2_DDR4_DQ<52>_XF		c2_ddr4_dq[28]	IO_L20P_T3L_N2_AD1P_36
100	U1_XF.K51 K51	GND GND	0V	GND	GND
36	U1_XF.K52 K52	C2_DDR4_DQ<28>_XF C2_DDR4_DQ<28>_XF		c2_ddr4_dq[7]	IO_L21P_T3L_N4_AD8P_34
16	U1_XF.K53 K53	C2_RDIMM_DQS_T<12>_XF C2_RDIMM_DQS_T<12>_XF		c2_ddr4_dqs_t[1]	IO_L19P_T3L_N0_DBC_AD9P_34
16	U1_XF.K54 K54	C2_RDIMM_DQS_C<12>_XF C2_RDIMM_DQS_C<12>_XF		c2_ddr4_dqs_c[1]	IO_L19N_T3L_N1_DBC_AD9N_34
36	U1_XF.K55 K55	C2_DDR4_RESET_N_XF C2_DDR4_RESET_N_XF		c2_ddr4_adr[9]	IO_L15P_T2L_N4_AD11P_34
-	U1_XF.K56 K56	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_34	VCCO_34	1.2
20	U1_XF.K57 K57	C2_DDR4_BG<0>_XF C2_DDR4_BG<0>_XF		c2_ddr4_adr[8]	IO_L13P_T2L_N0_GC_QBC_34
37	U1_XF.K58 K58	C2_DDR4_ADR<4>_XF C2_DDR4_ADR<4>_XF		c2_ddr4_adr[1]	IO_L12P_T1U_N10_GC_34
20	U1_XF.K59 K59	C2_DDR4_ADR<9>_XF C2_DDR4_ADR<9>_XF		c2_ddr4_cs_n[0]	IO_L12N_T1U_N11_GC_34
36	U1_XF.K60 K60	C2_DDR4_ADR<14>_XF C2_DDR4_ADR<14>_XF		c2_ddr4_adr[3]	IO_L10N_T1U_N7_QBC_AD4N_34
100	U1_XF.K61 K61	GND GND	0V	GND	GND
46	U1_XF.K62 K62	C2_DDR4_PARITY_XF C2_DDR4_PARITY_XF		c2_ddr4_adr[2]	IO_L3P_T0L_N4_AD15P_34
36	U1_XF.K63 K63	C2_DDR4_ADR<0>_XF C2_DDR4_ADR<0>_XF		c2_ddr4_adr[10]	IO_L3N_T0L_N5_AD15N_34
100	U1_XF.L1 L1	NC NC		MGTYRXN1_236	MGTYRXN1_236
100	U1_XF.L2 L2	NC NC		MGTYRXP1_236	MGTYRXP1_236
100	U1_XF.L3 L3	GND GND	0V	GND	GND
100	U1_XF.L4 L4	GND GND	0V	GND	GND
100	U1_XF.L5 L5	NC NC		MGTYRXN0_236	MGTYRXN0_236
100	U1_XF.L6 L6	NC NC		MGTYRXP0_236	MGTYRXP0_236
100	U1_XF.L7 L7	GND GND	0V	GND	GND
100	U1_XF.L8 L8	GND GND	0V	GND	GND
23	U1_XF.L9 L9	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
92	U1_XF.L10 L10	AC_E1S1_PET_N<3>_XF AC_E1S1_PET_N<3>_XF		e1s1_pet_n[3]	MGTYTXN3_235
92	U1_XF.L11 L11	AC_E1S1_PET_P<3>_XF AC_E1S1_PET_P<3>_XF		e1s1_pet_p[3]	MGTYTXP3_235
100	U1_XF.L12 L12	GND GND	0V	GND	GND
23	U1_XF.L13 L13	PWR_AVCC_RN_XF PWR_AVCC_RN_XF	0.9	MGTAVCC_RN	MGTAVCC_RN	0.9
100	U1_XF.L14 L14	GND GND	0V	GND	GND
16	U1_XF.L15 L15	C3_RDIMM_DQS_T<9>_XF C3_RDIMM_DQS_T<9>_XF		c3_ddr4_dqs_t[1]	IO_L1P_T0L_N0_DBC_77
95	U1_XF.L16 L16	C3_DDR4_DQ<1>_XF C3_DDR4_DQ<1>_XF		c3_ddr4_dq[1]	IO_L5N_T0U_N9_AD14N_77
95	U1_XF.L17 L17	C3_DDR4_DQ<0>_XF C3_DDR4_DQ<0>_XF		c3_ddr4_dq[0]	IO_L5P_T0U_N8_AD14P_77
54	U1_XF.L18 L18	C3_RDIMM_DQS_T<0>_XF C3_RDIMM_DQS_T<0>_XF		c3_ddr4_dqs_t[0]	IO_L4P_T0U_N6_DBC_AD7P_77
100	U1_XF.L19 L19	GND GND	0V	GND	GND
-	U1_XF.L20 L20	UNNAMED_22_RESISTOR_I34_B_XF UNNAMED_22_RESISTOR_I34_B_XF ->R49_XF->GND		VREF_77	VREF_77
100	U1_XF.L21 L21	NC NC		IO_L18N_T2U_N11_AD2N_75	IO_L18N_T2U_N11_AD2N_75
20	U1_XF.L22 L22	C3_DDR4_ADR<13>_XF C3_DDR4_ADR<13>_XF		c3_ddr4_parity	IO_L15P_T2L_N4_AD11P_75
20	U1_XF.L23 L23	C3_DDR4_ADR<10>_XF C3_DDR4_ADR<10>_XF		c3_ddr4_ba[0]	IO_L13N_T2L_N1_GC_QBC_75
-	U1_XF.L24 L24	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_75	VCCO_75	1.2
16	U1_XF.L25 L25	C3_RDIMM_DQS_C<1>_XF C3_RDIMM_DQS_C<1>_XF		c3_ddr4_dqs_c[8]	IO_L22N_T3U_N7_DBC_AD0N_75
16	U1_XF.L26 L26	C3_RDIMM_DQS_T<1>_XF C3_RDIMM_DQS_T<1>_XF		c3_ddr4_dqs_t[8]	IO_L22P_T3U_N6_DBC_AD0P_75
37	U1_XF.L27 L27	C3_DDR4_DQ<8>_XF C3_DDR4_DQ<8>_XF		c3_ddr4_dq[32]	IO_L24N_T3U_N11_75
37	U1_XF.L28 L28	C3_DDR4_DQ<9>_XF C3_DDR4_DQ<9>_XF		c3_ddr4_dq[33]	IO_L24P_T3U_N10_75
100	U1_XF.L29 L29	GND GND	0V	GND	GND
100	U1_XF.L30 L30	NC NC		IO_L14N_T2L_N3_GC_72	IO_L14N_T2L_N3_GC_72
100	U1_XF.L31 L31	NC NC		IO_L14P_T2L_N2_GC_72	IO_L14P_T2L_N2_GC_72
100	U1_XF.L32 L32	NC NC		IO_L13P_T2L_N0_GC_QBC_72	IO_L13P_T2L_N0_GC_QBC_72
100	U1_XF.L33 L33	NC NC		IO_L17P_T2U_N8_AD10P_72	IO_L17P_T2U_N8_AD10P_72
100	U1_XF.L34 L34	GND GND	0V	GND	GND
100	U1_XF.L35 L35	NC NC		IO_L15P_T2L_N4_AD11P_70	IO_L15P_T2L_N4_AD11P_70
100	U1_XF.L36 L36	NC NC		IO_L15N_T2L_N5_AD11N_70	IO_L15N_T2L_N5_AD11N_70
100	U1_XF.L37 L37	NC NC		IO_L14P_T2L_N2_GC_70	IO_L14P_T2L_N2_GC_70
100	U1_XF.L38 L38	NC NC		IO_L14N_T2L_N3_GC_70	IO_L14N_T2L_N3_GC_70
100	U1_XF.L39 L39	GND GND	0V	GND	GND
100	U1_XF.L40 L40	NC NC		IO_T2U_N12_70	IO_T2U_N12_70
100	U1_XF.L41 L41	NC NC		IO_L10N_T1U_N7_QBC_AD4N_38	IO_L10N_T1U_N7_QBC_AD4N_38
100	U1_XF.L42 L42	NC NC		IO_L13P_T2L_N0_GC_QBC_38	IO_L13P_T2L_N0_GC_QBC_38
100	U1_XF.L43 L43	NC NC		IO_L13N_T2L_N1_GC_QBC_38	IO_L13N_T2L_N1_GC_QBC_38
100	U1_XF.L44 L44	GND GND	0V	GND	GND
100	U1_XF.L45 L45	NC NC		IO_L15P_T2L_N4_AD11P_38	IO_L15P_T2L_N4_AD11P_38
100	U1_XF.L46 L46	NC NC		IO_L15N_T2L_N5_AD11N_38	IO_L15N_T2L_N5_AD11N_38
35	U1_XF.L47 L47	C2_DDR4_DQ<61>_XF C2_DDR4_DQ<61>_XF		c2_ddr4_dq[46]	IO_L15P_T2L_N4_AD11P_36
35	U1_XF.L48 L48	C2_DDR4_DQ<60>_XF C2_DDR4_DQ<60>_XF		c2_ddr4_dq[47]	IO_L15N_T2L_N5_AD11N_36
-	U1_XF.L49 L49	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_36	VCCO_36	1.2
35	U1_XF.L50 L50	C2_DDR4_DQ<57>_XF C2_DDR4_DQ<57>_XF		c2_ddr4_dq[43]	IO_L18P_T2U_N10_AD2P_36
35	U1_XF.L51 L51	C2_DDR4_DQ<56>_XF C2_DDR4_DQ<56>_XF		c2_ddr4_dq[42]	IO_L18N_T2U_N11_AD2N_36
36	U1_XF.L52 L52	C2_DDR4_DQ<24>_XF C2_DDR4_DQ<24>_XF		c2_ddr4_dq[0]	IO_L23P_T3U_N8_34
44	U1_XF.L53 L53	C2_DDR4_DQ<25>_XF C2_DDR4_DQ<25>_XF		c2_ddr4_dq[2]	IO_L23N_T3U_N9_34
100	U1_XF.L54 L54	GND GND	0V	GND	GND
20	U1_XF.L55 L55	C2_DDR4_CKE<0>_XF C2_DDR4_CKE<0>_XF		c2_ddr4_bg[1]	IO_L17N_T2U_N9_AD10N_34
20	U1_XF.L56 L56	C2_DDR4_ADR<11>_XF C2_DDR4_ADR<11>_XF		c2_ddr4_cke[1]	IO_L16N_T2U_N7_QBC_AD3N_34
36	U1_XF.L57 L57	C2_DDR4_ACT_N_XF C2_DDR4_ACT_N_XF		c2_ddr4_adr[16]	IO_L8P_T1L_N2_AD5P_34
37	U1_XF.L58 L58	C2_DDR4_ADR<5>_XF C2_DDR4_ADR<5>_XF		c2_ddr4_adr[0]	IO_L8N_T1L_N3_AD5N_34
-	U1_XF.L59 L59	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_34	VCCO_34	1.2
36	U1_XF.L60 L60	C2_DDR4_ADR<8>_XF C2_DDR4_ADR<8>_XF		c2_ddr4_adr[15]	IO_L10P_T1U_N6_QBC_AD4P_34
37	U1_XF.L61 L61	C2_DDR4_ADR<3>_XF C2_DDR4_ADR<3>_XF		c2_ddr4_adr[7]	IO_L6P_T0U_N10_AD6P_34
20	U1_XF.L62 L62	C2_DDR4_ADR<1>_XF C2_DDR4_ADR<1>_XF		c2_ddr4_cs_n[3]	IO_L6N_T0U_N11_AD6N_34
95	U1_XF.L63 L63	C2_DDR4_CK_C<0>_XF C2_DDR4_CK_C<0>_XF		c2_ddr4_ck_c[0]	IO_L4N_T0U_N7_DBC_AD7N_34
100	U1_XF.M1 M1	GND GND	0V	GND	GND
100	U1_XF.M2 M2	GND GND	0V	GND	GND
95	U1_XF.M3 M3	E1S1_PER_N<3>_XF E1S1_PER_N<3>_XF		e1s1_per_n[3]	MGTYRXN3_235
95	U1_XF.M4 M4	E1S1_PER_P<3>_XF E1S1_PER_P<3>_XF		e1s1_per_p[3]	MGTYRXP3_235
100	U1_XF.M5 M5	GND GND	0V	GND	GND
100	U1_XF.M6 M6	GND GND	0V	GND	GND
100	U1_XF.M7 M7	GND GND	0V	GND	GND
92	U1_XF.M8 M8	AC_E1S1_PET_N<2>_XF AC_E1S1_PET_N<2>_XF		e1s1_pet_n[2]	MGTYTXN2_235
92	U1_XF.M9 M9	AC_E1S1_PET_P<2>_XF AC_E1S1_PET_P<2>_XF		e1s1_pet_p[2]	MGTYTXP2_235
100	U1_XF.M10 M10	GND GND	0V	GND	GND
23	U1_XF.M11 M11	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
100	U1_XF.M12 M12	NC NC		MGTREFCLK0N_236	MGTREFCLK0N_236
100	U1_XF.M13 M13	NC NC		MGTREFCLK0P_236	MGTREFCLK0P_236
100	U1_XF.M14 M14	GND GND	0V	GND	GND
100	U1_XF.M15 M15	GND GND	0V	GND	GND
100	U1_XF.M16 M16	GND GND	0V	GND	GND
-	U1_XF.M17 M17	PWR_FPGA_3R3V PWR_FPGA_3R3V	3.3	VCCO_98	VCCO_98	3.3
33	U1_XF.M18 M18	E1S2_3R3V_CKEN_F<0>_XF E1S2_3R3V_CKEN_F<0>_XF		e1s_3r3v_cken0_f[2]	IO_L12N_AD0N_98
34	U1_XF.M19 M19	E1S2_3R3V_PRSNT_F<0>_XF E1S2_3R3V_PRSNT_F<0>_XF	3.3V	e1s_3r3v_prsnt0_f[2]	IO_L11N_AD1N_98
34	U1_XF.M20 M20	E1S2_3R3V_PRSNT_F<1>_XF E1S2_3R3V_PRSNT_F<1>_XF	3.3V	e1s_3r3v_prsnt1_f[2]	IO_L11P_AD1P_98
100	U1_XF.M21 M21	NC NC		IO_L18P_T2U_N10_AD2P_75	IO_L18P_T2U_N10_AD2P_75
100	U1_XF.M22 M22	GND GND	0V	GND	GND
36	U1_XF.M23 M23	C3_DDR4_ADR<14>_XF C3_DDR4_ADR<14>_XF		c3_ddr4_adr[2]	IO_L13P_T2L_N0_GC_QBC_75
35	U1_XF.M24 M24	C3_DDR4_DQ<12>_XF C3_DDR4_DQ<12>_XF		c3_ddr4_dq[39]	IO_L20N_T3L_N3_AD1N_75
35	U1_XF.M25 M25	C3_DDR4_DQ<13>_XF C3_DDR4_DQ<13>_XF		c3_ddr4_dq[37]	IO_L20P_T3L_N2_AD1P_75
-	U1_XF.M26 M26	UNNAMED_22_RESISTOR_I39_B_XF UNNAMED_22_RESISTOR_I39_B_XF ->R51_XF->GND		IO_T0U_N12_VRP_75	IO_T0U_N12_VRP_75
100	U1_XF.M27 M27	GND GND	0V	GND	GND
37	U1_XF.M28 M28	C3_DDR4_ADR<2>_XF C3_DDR4_ADR<2>_XF		c3_ddr4_adr[1]	IO_L6N_T0U_N11_AD6N_75
100	U1_XF.M29 M29	NC NC		IO_L10N_T1U_N7_QBC_AD4N_72	IO_L10N_T1U_N7_QBC_AD4N_72
100	U1_XF.M30 M30	NC NC		IO_L12N_T1U_N11_GC_72	IO_L12N_T1U_N11_GC_72
100	U1_XF.M31 M31	NC NC		IO_L12P_T1U_N10_GC_72	IO_L12P_T1U_N10_GC_72
100	U1_XF.M32 M32	NC NC		VCCO_72	VCCO_72	1.8
100	U1_XF.M33 M33	NC NC		IO_L15N_T2L_N5_AD11N_72	IO_L15N_T2L_N5_AD11N_72
100	U1_XF.M34 M34	NC NC		IO_L15P_T2L_N4_AD11P_72	IO_L15P_T2L_N4_AD11P_72
100	U1_XF.M35 M35	NC NC		IO_L7P_T1L_N0_QBC_AD13P_70	IO_L7P_T1L_N0_QBC_AD13P_70
100	U1_XF.M36 M36	NC NC		IO_L7N_T1L_N1_QBC_AD13N_70	IO_L7N_T1L_N1_QBC_AD13N_70
100	U1_XF.M37 M37	NC NC		VCCO_70	VCCO_70	1.8
100	U1_XF.M38 M38	NC NC		IO_L12N_T1U_N11_GC_70	IO_L12N_T1U_N11_GC_70
100	U1_XF.M39 M39	NC NC		IO_L16P_T2U_N6_QBC_AD3P_70	IO_L16P_T2U_N6_QBC_AD3P_70
100	U1_XF.M40 M40	NC NC		IO_L16N_T2U_N7_QBC_AD3N_70	IO_L16N_T2U_N7_QBC_AD3N_70
100	U1_XF.M41 M41	NC NC		IO_L10P_T1U_N6_QBC_AD4P_38	IO_L10P_T1U_N6_QBC_AD4P_38
100	U1_XF.M42 M42	NC NC		VCCO_38	VCCO_38	1.8
100	U1_XF.M43 M43	NC NC		IO_L12P_T1U_N10_GC_38	IO_L12P_T1U_N10_GC_38
100	U1_XF.M44 M44	NC NC		IO_L12N_T1U_N11_GC_38	IO_L12N_T1U_N11_GC_38
100	U1_XF.M45 M45	NC NC		IO_L7P_T1L_N0_QBC_AD13P_38	IO_L7P_T1L_N0_QBC_AD13P_38
100	U1_XF.M46 M46	NC NC		IO_L7N_T1L_N1_QBC_AD13N_38	IO_L7N_T1L_N1_QBC_AD13N_38
100	U1_XF.M47 M47	GND GND	0V	GND	GND
35	U1_XF.M48 M48	C2_DDR4_DQ<62>_XF C2_DDR4_DQ<62>_XF		c2_ddr4_dq[45]	IO_L14N_T2L_N3_GC_36
16	U1_XF.M49 M49	C2_RDIMM_DQS_C<16>_XF C2_RDIMM_DQS_C<16>_XF		c2_ddr4_dqs_c[11]	IO_L13N_T2L_N1_GC_QBC_36
16	U1_XF.M50 M50	C2_RDIMM_DQS_T<7>_XF C2_RDIMM_DQS_T<7>_XF		c2_ddr4_dqs_t[10]	IO_L16P_T2U_N6_QBC_AD3P_36
16	U1_XF.M51 M51	C2_RDIMM_DQS_C<7>_XF C2_RDIMM_DQS_C<7>_XF		c2_ddr4_dqs_c[10]	IO_L16N_T2U_N7_QBC_AD3N_36
100	U1_XF.M52 M52	GND GND	0V	GND	GND
-	U1_XF.M53 M53	UNNAMED_21_RESISTOR_I29_B_XF UNNAMED_21_RESISTOR_I29_B_XF ->R47_XF->GND		VREF_34	VREF_34
20	U1_XF.M54 M54	C2_DDR4_CKE<1>_XF C2_DDR4_CKE<1>_XF		c2_ddr4_bg[0]	IO_T3U_N12_34
20	U1_XF.M55 M55	C2_DDR4_BG<1>_XF C2_DDR4_BG<1>_XF		c2_ddr4_act_n	IO_L17P_T2U_N8_AD10P_34
20	U1_XF.M56 M56	C2_DDR4_ADR<7>_XF C2_DDR4_ADR<7>_XF		c2_ddr4_cke[0]	IO_L16P_T2U_N6_QBC_AD3P_34
100	U1_XF.M57 M57	GND GND	0V	GND	GND
100	U1_XF.M58 M58	NC NC		IO_L9N_T1L_N5_AD12N_33	IO_L9N_T1L_N5_AD12N_33
20	U1_XF.M59 M59	C2_DDR4_ADR<12>_XF C2_DDR4_ADR<12>_XF		c2_ddr4_odt[0]	IO_T1U_N12_34
20	U1_XF.M60 M60	C2_DDR4_ADR<2>_XF C2_DDR4_ADR<2>_XF		c2_ddr4_ba[1]	IO_L2P_T0L_N2_34
20	U1_XF.M61 M61	C2_DDR4_ADR<6>_XF C2_DDR4_ADR<6>_XF		c2_ddr4_ba[0]	IO_L2N_T0L_N3_34
100	U1_XF.M62 M62	GND GND	0V	GND	GND
95	U1_XF.M63 M63	C2_DDR4_CK_T<0>_XF C2_DDR4_CK_T<0>_XF		c2_ddr4_ck_t[0]	IO_L4P_T0U_N6_DBC_AD7P_34
95	U1_XF.N1 N1	E1S1_PER_N<2>_XF E1S1_PER_N<2>_XF		e1s1_per_n[2]	MGTYRXN2_235
95	U1_XF.N2 N2	E1S1_PER_P<2>_XF E1S1_PER_P<2>_XF		e1s1_per_p[2]	MGTYRXP2_235
100	U1_XF.N3 N3	GND GND	0V	GND	GND
100	U1_XF.N4 N4	GND GND	0V	GND	GND
95	U1_XF.N5 N5	E1S1_PER_N<1>_XF E1S1_PER_N<1>_XF		e1s1_per_n[1]	MGTYRXN1_235
95	U1_XF.N6 N6	E1S1_PER_P<1>_XF E1S1_PER_P<1>_XF		e1s1_per_p[1]	MGTYRXP1_235
100	U1_XF.N7 N7	GND GND	0V	GND	GND
100	U1_XF.N8 N8	GND GND	0V	GND	GND
23	U1_XF.N9 N9	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
92	U1_XF.N10 N10	AC_E1S1_PET_N<1>_XF AC_E1S1_PET_N<1>_XF		e1s1_pet_n[1]	MGTYTXN1_235
92	U1_XF.N11 N11	AC_E1S1_PET_P<1>_XF AC_E1S1_PET_P<1>_XF		e1s1_pet_p[1]	MGTYTXP1_235
100	U1_XF.N12 N12	GND GND	0V	GND	GND
23	U1_XF.N13 N13	PWR_AVCC_RN_XF PWR_AVCC_RN_XF	0.9	MGTAVCC_RN	MGTAVCC_RN	0.9
100	U1_XF.N14 N14	NC NC		MGTREFCLK1N_235	MGTREFCLK1N_235
100	U1_XF.N15 N15	NC NC		MGTREFCLK1P_235	MGTREFCLK1P_235
100	U1_XF.N16 N16	GND GND	0V	GND	GND
33	U1_XF.N17 N17	E1S2_3R3V_PERST_F<0>_XF E1S2_3R3V_PERST_F<0>_XF	3.3V	e1s_3r3v_perst0_f[2]	IO_L10N_AD2N_98
33	U1_XF.N18 N18	E1S2_3R3V_CKEN_F<1>_XF E1S2_3R3V_CKEN_F<1>_XF		e1s_3r3v_cken1_f[2]	IO_L12P_AD0P_98
84	U1_XF.N19 N19	E1S2_3R3V_LED_XF E1S2_3R3V_LED_XF	3.3V	e1s_3r3v_led[2]	IO_L9N_AD3N_98
100	U1_XF.N20 N20	GND GND	0V	GND	GND
16	U1_XF.N21 N21	C3_DDR4_CS_N<1>_XF C3_DDR4_CS_N<1>_XF		c3_ddr4_odt[1]	IO_L16N_T2U_N7_QBC_AD3N_75
37	U1_XF.N22 N22	C3_DDR4_CS_N<0>_XF C3_DDR4_CS_N<0>_XF		c3_ddr4_cs_n[3]	IO_L16P_T2U_N6_QBC_AD3P_75
20	U1_XF.N23 N23	C3_DDR4_ADR<16>_XF C3_DDR4_ADR<16>_XF		c3_ddr4_cs_n[0]	IO_L14N_T2L_N3_GC_75
20	U1_XF.N24 N24	C3_DDR4_BA<1>_XF C3_DDR4_BA<1>_XF		c3_ddr4_adr[16]	IO_L14P_T2L_N2_GC_75
100	U1_XF.N25 N25	GND GND	0V	GND	GND
95	U1_XF.N26 N26	C3_DDR4_CK_C<0>_XF C3_DDR4_CK_C<0>_XF		c3_ddr4_ck_c[0]	IO_L4N_T0U_N7_DBC_AD7N_75
95	U1_XF.N27 N27	C3_DDR4_CK_T<0>_XF C3_DDR4_CK_T<0>_XF		c3_ddr4_ck_t[0]	IO_L4P_T0U_N6_DBC_AD7P_75
95	U1_XF.N28 N28	C3_DDR4_ADR<3>_XF C3_DDR4_ADR<3>_XF		c3_ddr4_adr[3]	IO_L6P_T0U_N10_AD6P_75
100	U1_XF.N29 N29	NC NC		IO_L10P_T1U_N6_QBC_AD4P_72	IO_L10P_T1U_N6_QBC_AD4P_72
100	U1_XF.N30 N30	GND GND	0V	GND	GND
100	U1_XF.N31 N31	NC NC		IO_L11N_T1U_N9_GC_72	IO_L11N_T1U_N9_GC_72
100	U1_XF.N32 N32	NC NC		IO_L11P_T1U_N8_GC_72	IO_L11P_T1U_N8_GC_72
100	U1_XF.N33 N33	NC NC		IO_T1U_N12_72	IO_T1U_N12_72
100	U1_XF.N34 N34	NC NC		IO_L7N_T1L_N1_QBC_AD13N_72	IO_L7N_T1L_N1_QBC_AD13N_72
100	U1_XF.N35 N35	GND GND	0V	GND	GND
100	U1_XF.N36 N36	NC NC		IO_L9N_T1L_N5_AD12N_70	IO_L9N_T1L_N5_AD12N_70
100	U1_XF.N37 N37	NC NC		IO_L11N_T1U_N9_GC_70	IO_L11N_T1U_N9_GC_70
100	U1_XF.N38 N38	NC NC		IO_L12P_T1U_N10_GC_70	IO_L12P_T1U_N10_GC_70
100	U1_XF.N39 N39	NC NC		IO_L10N_T1U_N7_QBC_AD4N_70	IO_L10N_T1U_N7_QBC_AD4N_70
100	U1_XF.N40 N40	GND GND	0V	GND	GND
100	U1_XF.N41 N41	NC NC		IO_L8P_T1L_N2_AD5P_38	IO_L8P_T1L_N2_AD5P_38
100	U1_XF.N42 N42	NC NC		IO_L8N_T1L_N3_AD5N_38	IO_L8N_T1L_N3_AD5N_38
100	U1_XF.N43 N43	NC NC		IO_L11P_T1U_N8_GC_38	IO_L11P_T1U_N8_GC_38
100	U1_XF.N44 N44	NC NC		IO_L11N_T1U_N9_GC_38	IO_L11N_T1U_N9_GC_38
100	U1_XF.N45 N45	GND GND	0V	GND	GND
16	U1_XF.N46 N46	C2_RDIMM_DQS_C<1>_XF C2_RDIMM_DQS_C<1>_XF		c2_ddr4_dqs_c[4]	IO_L10N_T1U_N7_QBC_AD4N_36
35	U1_XF.N47 N47	C2_DDR4_DQ<14>_XF C2_DDR4_DQ<14>_XF		c2_ddr4_dq[23]	IO_L9N_T1L_N5_AD12N_36
35	U1_XF.N48 N48	C2_DDR4_DQ<63>_XF C2_DDR4_DQ<63>_XF		c2_ddr4_dq[44]	IO_L14P_T2L_N2_GC_36
16	U1_XF.N49 N49	C2_RDIMM_DQS_T<16>_XF C2_RDIMM_DQS_T<16>_XF		c2_ddr4_dqs_t[11]	IO_L13P_T2L_N0_GC_QBC_36
100	U1_XF.N50 N50	GND GND	0V	GND	GND
16	U1_XF.N51 N51	C2_RDIMM_DQS_C<10>_XF C2_RDIMM_DQS_C<10>_XF		c2_ddr4_dqs_c[5]	IO_L7N_T1L_N1_QBC_AD13N_36
100	U1_XF.N52 N52	NC NC		IO_L24N_T3U_N11_33	IO_L24N_T3U_N11_33
100	U1_XF.N53 N53	NC NC		IO_L22P_T3U_N6_DBC_AD0P_33	IO_L22P_T3U_N6_DBC_AD0P_33
100	U1_XF.N54 N54	NC NC		IO_L22N_T3U_N7_DBC_AD0N_33	IO_L22N_T3U_N7_DBC_AD0N_33
100	U1_XF.N55 N55	GND GND	0V	GND	GND
100	U1_XF.N56 N56	NC NC		IO_L16P_T2U_N6_QBC_AD3P_33	IO_L16P_T2U_N6_QBC_AD3P_33
100	U1_XF.N57 N57	NC NC		IO_L16N_T2U_N7_QBC_AD3N_33	IO_L16N_T2U_N7_QBC_AD3N_33
100	U1_XF.N58 N58	NC NC		IO_L9P_T1L_N4_AD12P_33	IO_L9P_T1L_N4_AD12P_33
100	U1_XF.N59 N59	NC NC		IO_L7N_T1L_N1_QBC_AD13N_33	IO_L7N_T1L_N1_QBC_AD13N_33
100	U1_XF.N60 N60	GND GND	0V	GND	GND
100	U1_XF.N61 N61	NC NC		IO_T0U_N12_VRP_33	IO_T0U_N12_VRP_33
100	U1_XF.N62 N62	NC NC		IO_L3P_T0L_N4_AD15P_33	IO_L3P_T0L_N4_AD15P_33
100	U1_XF.N63 N63	NC NC		IO_L3N_T0L_N5_AD15N_33	IO_L3N_T0L_N5_AD15N_33
100	U1_XF.P1 P1	GND GND	0V	GND	GND
100	U1_XF.P2 P2	GND GND	0V	GND	GND
95	U1_XF.P3 P3	E1S1_PER_N<0>_XF E1S1_PER_N<0>_XF		e1s1_per_n[0]	MGTYRXN0_235
95	U1_XF.P4 P4	E1S1_PER_P<0>_XF E1S1_PER_P<0>_XF		e1s1_per_p[0]	MGTYRXP0_235
100	U1_XF.P5 P5	GND GND	0V	GND	GND
100	U1_XF.P6 P6	GND GND	0V	GND	GND
100	U1_XF.P7 P7	GND GND	0V	GND	GND
92	U1_XF.P8 P8	AC_E1S1_PET_N<0>_XF AC_E1S1_PET_N<0>_XF		e1s1_pet_n[0]	MGTYTXN0_235
92	U1_XF.P9 P9	AC_E1S1_PET_P<0>_XF AC_E1S1_PET_P<0>_XF		e1s1_pet_p[0]	MGTYTXP0_235
100	U1_XF.P10 P10	GND GND	0V	GND	GND
23	U1_XF.P11 P11	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
85	U1_XF.P12 P12	E1S1_FPGA_REFCLK_N<0>_XF E1S1_FPGA_REFCLK_N<0>_XF		e1s1_refclk_n[0]	MGTREFCLK0N_235
85	U1_XF.P13 P13	E1S1_FPGA_REFCLK_P<0>_XF E1S1_FPGA_REFCLK_P<0>_XF		e1s1_refclk_p[0]	MGTREFCLK0P_235
100	U1_XF.P14 P14	GND GND	0V	GND	GND
80	U1_XF.P15 P15	PWR_RN_RUC_MGTVCCAUX_XF PWR_RN_RUC_MGTVCCAUX_XF	1.8	MGTVCCAUX_RN	MGTVCCAUX_RN	1.8
100	U1_XF.P16 P16	GND GND	0V	GND	GND
31	U1_XF.P17 P17	E1S2_3R3V_PERST_CLKREQ_F<1>_XF E1S2_3R3V_PERST_CLKREQ_F<1>_XF	3.3V	e1s_3r3v_perst1_clkreq_f[2]	IO_L10P_AD2P_98
100	U1_XF.P18 P18	GND GND	0V	GND	GND
84	U1_XF.P19 P19	E1S2_3R3V_PWRDIS_XF E1S2_3R3V_PWRDIS_XF	3.3V	e1s_3r3v_pwrdis[2]	IO_L9P_AD3P_98
84	U1_XF.P20 P20	E1S2_3R3V_SDA_XF E1S2_3R3V_SDA_XF	3.3V	e1s_3r3v_sda[2]	IO_L7N_HDGC_AD5N_98
85	U1_XF.P21 P21	E1S2_3R3V_SCL_XF E1S2_3R3V_SCL_XF	3.3V	e1s_3r3v_scl[2]	IO_L7P_HDGC_AD5P_98
36	U1_XF.P22 P22	C3_DDR4_ADR<15>_XF C3_DDR4_ADR<15>_XF		c3_ddr4_adr[7]	IO_L7N_T1L_N1_QBC_AD13N_75
-	U1_XF.P23 P23	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_75	VCCO_75	1.2
95	U1_XF.P24 P24	C3_SYS_CLK_N_XF C3_SYS_CLK_N_XF		c3_sys_clk_n	IO_L11N_T1U_N9_GC_75
95	U1_XF.P25 P25	C3_SYS_CLK_P_XF C3_SYS_CLK_P_XF		c3_sys_clk_p	IO_L11P_T1U_N8_GC_75
20	U1_XF.P26 P26	C3_DDR4_ADR<1>_XF C3_DDR4_ADR<1>_XF		c3_ddr4_bg[1]	IO_L2N_T0L_N3_75
20	U1_XF.P27 P27	C3_DDR4_ADR<4>_XF C3_DDR4_ADR<4>_XF		c3_ddr4_cke[0]	IO_L2P_T0L_N2_75
100	U1_XF.P28 P28	GND GND	0V	GND	GND
100	U1_XF.P29 P29	NC NC		IO_L9N_T1L_N5_AD12N_72	IO_L9N_T1L_N5_AD12N_72
100	U1_XF.P30 P30	NC NC		IO_L9P_T1L_N4_AD12P_72	IO_L9P_T1L_N4_AD12P_72
100	U1_XF.P31 P31	NC NC		IO_L8N_T1L_N3_AD5N_72	IO_L8N_T1L_N3_AD5N_72
100	U1_XF.P32 P32	NC NC		IO_L8P_T1L_N2_AD5P_72	IO_L8P_T1L_N2_AD5P_72
100	U1_XF.P33 P33	GND GND	0V	GND	GND
100	U1_XF.P34 P34	NC NC		IO_L7P_T1L_N0_QBC_AD13P_72	IO_L7P_T1L_N0_QBC_AD13P_72
100	U1_XF.P35 P35	NC NC		IO_T1U_N12_70	IO_T1U_N12_70
100	U1_XF.P36 P36	NC NC		IO_L9P_T1L_N4_AD12P_70	IO_L9P_T1L_N4_AD12P_70
100	U1_XF.P37 P37	NC NC		IO_L11P_T1U_N8_GC_70	IO_L11P_T1U_N8_GC_70
100	U1_XF.P38 P38	GND GND	0V	GND	GND
100	U1_XF.P39 P39	NC NC		IO_L10P_T1U_N6_QBC_AD4P_70	IO_L10P_T1U_N6_QBC_AD4P_70
100	U1_XF.P40 P40	NC NC		IO_L8N_T1L_N3_AD5N_70	IO_L8N_T1L_N3_AD5N_70
100	U1_XF.P41 P41	NC NC		IO_L9P_T1L_N4_AD12P_38	IO_L9P_T1L_N4_AD12P_38
100	U1_XF.P42 P42	NC NC		IO_L9N_T1L_N5_AD12N_38	IO_L9N_T1L_N5_AD12N_38
100	U1_XF.P43 P43	GND GND	0V	GND	GND
100	U1_XF.P44 P44	NC NC		IO_T1U_N12_38	IO_T1U_N12_38
100	U1_XF.P45 P45	NC NC		IO_L1N_T0L_N1_DBC_38	IO_L1N_T0L_N1_DBC_38
16	U1_XF.P46 P46	C2_RDIMM_DQS_T<1>_XF C2_RDIMM_DQS_T<1>_XF		c2_ddr4_dqs_t[4]	IO_L10P_T1U_N6_QBC_AD4P_36
35	U1_XF.P47 P47	C2_DDR4_DQ<15>_XF C2_DDR4_DQ<15>_XF		c2_ddr4_dq[22]	IO_L9P_T1L_N4_AD12P_36
100	U1_XF.P48 P48	GND GND	0V	GND	GND
35	U1_XF.P49 P49	C2_DDR4_DQ<11>_XF C2_DDR4_DQ<11>_XF		c2_ddr4_dq[17]	IO_L11P_T1U_N8_GC_36
37	U1_XF.P50 P50	C2_DDR4_DQ<8>_XF C2_DDR4_DQ<8>_XF		c2_ddr4_dq[16]	IO_L11N_T1U_N9_GC_36
16	U1_XF.P51 P51	C2_RDIMM_DQS_T<10>_XF C2_RDIMM_DQS_T<10>_XF		c2_ddr4_dqs_t[5]	IO_L7P_T1L_N0_QBC_AD13P_36
100	U1_XF.P52 P52	NC NC		IO_L24P_T3U_N10_33	IO_L24P_T3U_N10_33
100	U1_XF.P53 P53	GND GND	0V	GND	GND
100	U1_XF.P54 P54	NC NC		IO_T3U_N12_33	IO_T3U_N12_33
100	U1_XF.P55 P55	NC NC		IO_L13P_T2L_N0_GC_QBC_33	IO_L13P_T2L_N0_GC_QBC_33
100	U1_XF.P56 P56	NC NC		IO_L13N_T2L_N1_GC_QBC_33	IO_L13N_T2L_N1_GC_QBC_33
100	U1_XF.P57 P57	NC NC		IO_L14N_T2L_N3_GC_33	IO_L14N_T2L_N3_GC_33
100	U1_XF.P58 P58	NC NC		VCCO_33	VCCO_33	1.8
100	U1_XF.P59 P59	NC NC		IO_L7P_T1L_N0_QBC_AD13P_33	IO_L7P_T1L_N0_QBC_AD13P_33
100	U1_XF.P60 P60	NC NC		IO_L10N_T1U_N7_QBC_AD4N_33	IO_L10N_T1U_N7_QBC_AD4N_33
100	U1_XF.P61 P61	NC NC		IO_L5P_T0U_N8_AD14P_33	IO_L5P_T0U_N8_AD14P_33
100	U1_XF.P62 P62	NC NC		IO_L5N_T0U_N9_AD14N_33	IO_L5N_T0U_N9_AD14N_33
100	U1_XF.P63 P63	GND GND	0V	GND	GND
95	U1_XF.R1 R1	E1S1_PER_N<7>_XF E1S1_PER_N<7>_XF		e1s1_per_n[7]	MGTYRXN3_234
95	U1_XF.R2 R2	E1S1_PER_P<7>_XF E1S1_PER_P<7>_XF		e1s1_per_p[7]	MGTYRXP3_234
100	U1_XF.R3 R3	GND GND	0V	GND	GND
100	U1_XF.R4 R4	GND GND	0V	GND	GND
100	U1_XF.R5 R5	GND GND	0V	GND	GND
92	U1_XF.R6 R6	AC_E1S1_PET_N<7>_XF AC_E1S1_PET_N<7>_XF		e1s1_pet_n[7]	MGTYTXN3_234
92	U1_XF.R7 R7	AC_E1S1_PET_P<7>_XF AC_E1S1_PET_P<7>_XF		e1s1_pet_p[7]	MGTYTXP3_234
100	U1_XF.R8 R8	GND GND	0V	GND	GND
23	U1_XF.R9 R9	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
92	U1_XF.R10 R10	AC_E1S1_PET_N<6>_XF AC_E1S1_PET_N<6>_XF		e1s1_pet_n[6]	MGTYTXN2_234
92	U1_XF.R11 R11	AC_E1S1_PET_P<6>_XF AC_E1S1_PET_P<6>_XF		e1s1_pet_p[6]	MGTYTXP2_234
100	U1_XF.R12 R12	GND GND	0V	GND	GND
23	U1_XF.R13 R13	PWR_AVCC_RN_XF PWR_AVCC_RN_XF	0.9	MGTAVCC_RN	MGTAVCC_RN	0.9
95	U1_XF.R14 R14	MGTRREF_RN_XF MGTRREF_RN_XF		MGTRREF_RN	MGTRREF_RN
23	U1_XF.R15 R15	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTTRCAL_RN	MGTAVTTRCAL_RN	1.2
100	U1_XF.R16 R16	GND GND	0V	GND	GND
33	U1_XF.R17 R17	E1S3_3R3V_CKEN_F<0>_XF E1S3_3R3V_CKEN_F<0>_XF		e1s_3r3v_cken0_f[3]	IO_L6N_HDGC_AD6N_98
33	U1_XF.R18 R18	E1S3_3R3V_CKEN_F<1>_XF E1S3_3R3V_CKEN_F<1>_XF		e1s_3r3v_cken1_f[3]	IO_L6P_HDGC_AD6P_98
83	U1_XF.R19 R19	E1S2_3R3V_SMB_RST_F_XF E1S2_3R3V_SMB_RST_F_XF	3.3V	e1s_3r3v_smb_rst_f[2]	IO_L8N_HDGC_AD4N_98
80	U1_XF.R20 R20	E1S2_3R3V_DUALPORTEN_F_XF E1S2_3R3V_DUALPORTEN_F_XF		e1s_3r3v_dualporten_f[2]	IO_L8P_HDGC_AD4P_98
100	U1_XF.R21 R21	GND GND	0V	GND	GND
20	U1_XF.R22 R22	C3_DDR4_BA<0>_XF C3_DDR4_BA<0>_XF		c3_ddr4_adr[9]	IO_L7P_T1L_N0_QBC_AD13P_75
95	U1_XF.R23 R23	C3_DDR4_ADR<0>_XF C3_DDR4_ADR<0>_XF		c3_ddr4_adr[0]	IO_L12N_T1U_N11_GC_75
46	U1_XF.R24 R24	C3_DDR4_PARITY_XF C3_DDR4_PARITY_XF		c3_ddr4_odt[0]	IO_L12P_T1U_N10_GC_75
37	U1_XF.R25 R25	C3_DDR4_ADR<8>_XF C3_DDR4_ADR<8>_XF		c3_ddr4_adr[4]	IO_L9N_T1L_N5_AD12N_75
-	U1_XF.R26 R26	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_75	VCCO_75	1.2
20	U1_XF.R27 R27	C3_DDR4_ADR<5>_XF C3_DDR4_ADR<5>_XF		c3_ddr4_act_n	IO_L3N_T0L_N5_AD15N_75
20	U1_XF.R28 R28	C3_DDR4_ADR<6>_XF C3_DDR4_ADR<6>_XF		c3_ddr4_reset_n	IO_L3P_T0L_N4_AD15P_75
100	U1_XF.R29 R29	NC NC		IO_L6N_T0U_N11_AD6N_72	IO_L6N_T0U_N11_AD6N_72
100	U1_XF.R30 R30	NC NC		IO_L6P_T0U_N10_AD6P_72	IO_L6P_T0U_N10_AD6P_72
100	U1_XF.R31 R31	NC NC		VCCO_72	VCCO_72	1.8
100	U1_XF.R32 R32	NC NC		IO_T0U_N12_VRP_72	IO_T0U_N12_VRP_72
100	U1_XF.R33 R33	NC NC		IO_L2N_T0L_N3_72	IO_L2N_T0L_N3_72
100	U1_XF.R34 R34	NC NC		IO_L2P_T0L_N2_72	IO_L2P_T0L_N2_72
100	U1_XF.R35 R35	NC NC		IO_L3N_T0L_N5_AD15N_70	IO_L3N_T0L_N5_AD15N_70
100	U1_XF.R36 R36	NC NC		VCCO_70	VCCO_70	1.8
100	U1_XF.R37 R37	NC NC		IO_L5N_T0U_N9_AD14N_70	IO_L5N_T0U_N9_AD14N_70
100	U1_XF.R38 R38	NC NC		IO_L4P_T0U_N6_DBC_AD7P_70	IO_L4P_T0U_N6_DBC_AD7P_70
100	U1_XF.R39 R39	NC NC		IO_L4N_T0U_N7_DBC_AD7N_70	IO_L4N_T0U_N7_DBC_AD7N_70
100	U1_XF.R40 R40	NC NC		IO_L8P_T1L_N2_AD5P_70	IO_L8P_T1L_N2_AD5P_70
100	U1_XF.R41 R41	GND GND	0V	GND	GND
100	U1_XF.R42 R42	NC NC		IO_L6P_T0U_N10_AD6P_38	IO_L6P_T0U_N10_AD6P_38
100	U1_XF.R43 R43	NC NC		IO_L6N_T0U_N11_AD6N_38	IO_L6N_T0U_N11_AD6N_38
100	U1_XF.R44 R44	NC NC		IO_T0U_N12_VRP_38	IO_T0U_N12_VRP_38
100	U1_XF.R45 R45	NC NC		IO_L1P_T0L_N0_DBC_38	IO_L1P_T0L_N0_DBC_38
100	U1_XF.R46 R46	GND GND	0V	GND	GND
100	U1_XF.R47 R47	NC NC		IO_T1U_N12_36	IO_T1U_N12_36
35	U1_XF.R48 R48	C2_DDR4_DQ<10>_XF C2_DDR4_DQ<10>_XF		c2_ddr4_dq[18]	IO_L12P_T1U_N10_GC_36
37	U1_XF.R49 R49	C2_DDR4_DQ<9>_XF C2_DDR4_DQ<9>_XF		c2_ddr4_dq[19]	IO_L12N_T1U_N11_GC_36
35	U1_XF.R50 R50	C2_DDR4_DQ<12>_XF C2_DDR4_DQ<12>_XF		c2_ddr4_dq[21]	IO_L8N_T1L_N3_AD5N_36
100	U1_XF.R51 R51	GND GND	0V	GND	GND
100	U1_XF.R52 R52	NC NC		IO_L20P_T3L_N2_AD1P_33	IO_L20P_T3L_N2_AD1P_33
100	U1_XF.R53 R53	NC NC		IO_L20N_T3L_N3_AD1N_33	IO_L20N_T3L_N3_AD1N_33
100	U1_XF.R54 R54	NC NC		IO_L18P_T2U_N10_AD2P_33	IO_L18P_T2U_N10_AD2P_33
100	U1_XF.R55 R55	NC NC		IO_L18N_T2U_N11_AD2N_33	IO_L18N_T2U_N11_AD2N_33
100	U1_XF.R56 R56	GND GND	0V	GND	GND
100	U1_XF.R57 R57	NC NC		IO_L14P_T2L_N2_GC_33	IO_L14P_T2L_N2_GC_33
100	U1_XF.R58 R58	NC NC		IO_L11P_T1U_N8_GC_33	IO_L11P_T1U_N8_GC_33
100	U1_XF.R59 R59	NC NC		IO_L11N_T1U_N9_GC_33	IO_L11N_T1U_N9_GC_33
100	U1_XF.R60 R60	NC NC		IO_L10P_T1U_N6_QBC_AD4P_33	IO_L10P_T1U_N6_QBC_AD4P_33
100	U1_XF.R61 R61	NC NC		VCCO_33	VCCO_33	1.8
100	U1_XF.R62 R62	NC NC		IO_L1P_T0L_N0_DBC_33	IO_L1P_T0L_N0_DBC_33
100	U1_XF.R63 R63	NC NC		IO_L1N_T0L_N1_DBC_33	IO_L1N_T0L_N1_DBC_33
100	U1_XF.T1 T1	GND GND	0V	GND	GND
100	U1_XF.T2 T2	GND GND	0V	GND	GND
95	U1_XF.T3 T3	E1S1_PER_N<6>_XF E1S1_PER_N<6>_XF		e1s1_per_n[6]	MGTYRXN2_234
95	U1_XF.T4 T4	E1S1_PER_P<6>_XF E1S1_PER_P<6>_XF		e1s1_per_p[6]	MGTYRXP2_234
100	U1_XF.T5 T5	GND GND	0V	GND	GND
100	U1_XF.T6 T6	GND GND	0V	GND	GND
100	U1_XF.T7 T7	GND GND	0V	GND	GND
92	U1_XF.T8 T8	AC_E1S1_PET_N<5>_XF AC_E1S1_PET_N<5>_XF		e1s1_pet_n[5]	MGTYTXN1_234
92	U1_XF.T9 T9	AC_E1S1_PET_P<5>_XF AC_E1S1_PET_P<5>_XF		e1s1_pet_p[5]	MGTYTXP1_234
100	U1_XF.T10 T10	GND GND	0V	GND	GND
23	U1_XF.T11 T11	PWR_AVTT_RN_XF PWR_AVTT_RN_XF	1.2	MGTAVTT_RN	MGTAVTT_RN	1.2
100	U1_XF.T12 T12	NC NC		MGTREFCLK1N_234	MGTREFCLK1N_234
100	U1_XF.T13 T13	NC NC		MGTREFCLK1P_234	MGTREFCLK1P_234
100	U1_XF.T14 T14	GND GND	0V	GND	GND
80	U1_XF.T15 T15	PWR_RN_RUC_MGTVCCAUX_XF PWR_RN_RUC_MGTVCCAUX_XF	1.8	MGTVCCAUX_RN	MGTVCCAUX_RN	1.8
100	U1_XF.T16 T16	GND GND	0V	GND	GND
34	U1_XF.T17 T17	E1S3_3R3V_PRSNT_F<0>_XF E1S3_3R3V_PRSNT_F<0>_XF	3.3V	e1s_3r3v_prsnt0_f[3]	IO_L5N_HDGC_AD7N_98
34	U1_XF.T18 T18	E1S3_3R3V_PRSNT_F<1>_XF E1S3_3R3V_PRSNT_F<1>_XF	3.3V	e1s_3r3v_prsnt1_f[3]	IO_L5P_HDGC_AD7P_98
100	U1_XF.T19 T19	GND GND	0V	GND	GND
33	U1_XF.T20 T20	E1S3_3R3V_PERST_F<0>_XF E1S3_3R3V_PERST_F<0>_XF	3.3V	e1s_3r3v_perst0_f[3]	IO_L4N_AD8N_98
31	U1_XF.T21 T21	E1S3_3R3V_PERST_CLKREQ_F<1>_XF E1S3_3R3V_PERST_CLKREQ_F<1>_XF	3.3V	e1s_3r3v_perst1_clkreq_f[3]	IO_L4P_AD8P_98
54	U1_XF.T22 T22	C3_DDR4_RESET_N_XF C3_DDR4_RESET_N_XF		c3_ddr4_cs_n[1]	IO_L10N_T1U_N7_QBC_AD4N_75
20	U1_XF.T23 T23	C3_DDR4_CKE<0>_XF C3_DDR4_CKE<0>_XF		c3_ddr4_adr[13]	IO_L10P_T1U_N6_QBC_AD4P_75
100	U1_XF.T24 T24	GND GND	0V	GND	GND
20	U1_XF.T25 T25	C3_DDR4_BG<1>_XF C3_DDR4_BG<1>_XF		c3_ddr4_adr[5]	IO_L9P_T1L_N4_AD12P_75
35	U1_XF.T26 T26	C3_DDR4_ADR<12>_XF C3_DDR4_ADR<12>_XF		c3_ddr4_adr[11]	IO_L5N_T0U_N9_AD14N_75
35	U1_XF.T27 T27	C3_DDR4_ADR<11>_XF C3_DDR4_ADR<11>_XF		c3_ddr4_adr[12]	IO_L5P_T0U_N8_AD14P_75
20	U1_XF.T28 T28	C3_DDR4_ADR<7>_XF C3_DDR4_ADR<7>_XF		c3_ddr4_bg[0]	IO_L1N_T0L_N1_DBC_75
100	U1_XF.T29 T29	GND GND	0V	GND	GND
100	U1_XF.T30 T30	NC NC		IO_L4N_T0U_N7_DBC_AD7N_72	IO_L4N_T0U_N7_DBC_AD7N_72
100	U1_XF.T31 T31	NC NC		IO_L5N_T0U_N9_AD14N_72	IO_L5N_T0U_N9_AD14N_72
100	U1_XF.T32 T32	NC NC		IO_L3N_T0L_N5_AD15N_72	IO_L3N_T0L_N5_AD15N_72
100	U1_XF.T33 T33	NC NC		IO_L3P_T0L_N4_AD15P_72	IO_L3P_T0L_N4_AD15P_72
100	U1_XF.T34 T34	GND GND	0V	GND	GND
100	U1_XF.T35 T35	NC NC		IO_L3P_T0L_N4_AD15P_70	IO_L3P_T0L_N4_AD15P_70
100	U1_XF.T36 T36	NC NC		IO_L1N_T0L_N1_DBC_70	IO_L1N_T0L_N1_DBC_70
100	U1_XF.T37 T37	NC NC		IO_L5P_T0U_N8_AD14P_70	IO_L5P_T0U_N8_AD14P_70
100	U1_XF.T38 T38	NC NC		IO_T0U_N12_VRP_70	IO_T0U_N12_VRP_70
100	U1_XF.T39 T39	GND GND	0V	GND	GND
100	U1_XF.T40 T40	NC NC		IO_L2N_T0L_N3_70	IO_L2N_T0L_N3_70
100	U1_XF.T41 T41	NC NC		IO_L4N_T0U_N7_DBC_AD7N_38	IO_L4N_T0U_N7_DBC_AD7N_38
100	U1_XF.T42 T42	NC NC		IO_L2P_T0L_N2_38	IO_L2P_T0L_N2_38
100	U1_XF.T43 T43	NC NC		IO_L2N_T0L_N3_38	IO_L2N_T0L_N3_38
100	U1_XF.T44 T44	NC NC		VCCO_38	VCCO_38	1.8
100	U1_XF.T45 T45	NC NC		IO_L3N_T0L_N5_AD15N_38	IO_L3N_T0L_N5_AD15N_38
-	U1_XF.T46 T46	UNNAMED_21_RESISTOR_I24_B_XF UNNAMED_21_RESISTOR_I24_B_XF ->R43_XF->GND		VREF_36	VREF_36
-	U1_XF.T47 T47	UNNAMED_21_RESISTOR_I25_B_XF UNNAMED_21_RESISTOR_I25_B_XF ->R115_XF->GND		IO_T0U_N12_VRP_36	IO_T0U_N12_VRP_36
37	U1_XF.T48 T48	C2_DDR4_DQ<3>_XF C2_DDR4_DQ<3>_XF		c2_ddr4_dq[10]	IO_L6N_T0U_N11_AD6N_36
-	U1_XF.T49 T49	PWR_NDIMM_VDD_XF PWR_NDIMM_VDD_XF	1.2	VCCO_36	VCCO_36	1.2
35	U1_XF.T50 T50	C2_DDR4_DQ<13>_XF C2_DDR4_DQ<13>_XF		c2_ddr4_dq[20]	IO_L8P_T1L_N2_AD5P_36
37	U1_XF.T51 T51	C2_DDR4_DQ<6>_XF C2_DDR4_DQ<6>_XF		c2_ddr4_dq[15]	IO_L3N_T0L_N5_AD15N_36
100	U1_XF.T52 T52	NC NC		IO_L19P_T3L_N0_DBC_AD9P_33	IO_L19P_T3L_N0_DBC_AD9P_33
100	U1_XF.T53 T53	NC NC		IO_L19N_T3L_N1_DBC_AD9N_33	IO_L19N_T3L_N1_DBC_AD9N_33
100	U1_XF.T54 T54	NC NC		VCCO_33	VCCO_33	1.8
100	U1_XF.T55 T55	NC NC		IO_L15P_T2L_N4_AD11P_33	IO_L15P_T2L_N4_AD11P_33
100	U1_XF.T56 T56	NC NC		IO_L15N_T2L_N5_AD11N_33	IO_L15N_T2L_N5_AD11N_33
100	U1_XF.T57 T57	NC NC		IO_L12P_T1U_N10_GC_33	IO_L12P_T1U_N10_GC_33
100	U1_XF.T58 T58	NC NC		IO_L12N_T1U_N11_GC_33	IO_L12N_T1U_N11_GC_33
100	U1_XF.T59 T59	GND GND	0V	GND	GND
100	U1_XF.T60 T60	NC NC		IO_T1U_N12_33	IO_T1U_N12_33
100	U1_XF.T61 T61	NC NC		IO_L6P_T0U_N10_AD6P_33	IO_L6P_T0U_N10_AD6P_33
100	U1_XF.T62 T62	NC NC		IO_L6N_T0U_N11_AD6N_33	IO_L6N_T0U_N11_AD6N_33
100	U1_XF.T63 T63	NC NC		IO_L2N_T0L_N3_33	IO_L2N_T0L_N3_33
95	U1_XF.U1 U1	E1S1_PER_N<5>_XF E1S1_PER_N<5>_XF		e1s1_per_n[5]	MGTYRXN1_234
95	U1_XF.U2 U2	E1S1_PER_P<5>_XF E1S1_PER_P<5>_XF		e1s1_per_p[5]	MGTYRXP1_234
100	U1_XF.U3 U3	GND GND	0V	GND	GND
100	U1_XF.U4 U4	GND GND	0V	GND	GND
100	U1_XF.U5 U5	GND GND	0V	GND	GND
92	U1_XF.U6 U6	AC_E1S1_PET_N<4>_XF AC_E1S1_PET_N<4>_XF		e1s1_pet_n[4]	MGTYTXN0_234
92	U1_XF.U7 U7	AC_E1S1_PET_P<4>_XF AC_E1S1_PET_P<4>_XF		e1s1_pet_p[4]	MGTYTXP0_234
100	U1_XF.U8 U8	GND GND	0V	GND	GND
23	U1_XF.U9 U9	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
92	U1_XF.U10 U10	AC_E1S2_PET_N<3>_XF AC_E1S2_PET_N<3>_XF		e1s2_pet_n[3]	MGTYTXN3_233
92	U1_XF.U11 U11	AC_E1S2_PET_P<3>_XF AC_E1S2_PET_P<3>_XF		e1s2_pet_p[3]	MGTYTXP3_233
100	U1_XF.U12 U12	GND GND	0V	GND	GND
23	U1_XF.U13 U13	PWR_AVCC_RN_XF PWR_AVCC_RN_XF	0.9	MGTAVCC_RN	MGTAVCC_RN	0.9
85	U1_XF.U14 U14	E1S1_FPGA_REFCLK_N<1>_XF E1S1_FPGA_REFCLK_N<1>_XF		e1s1_refclk_n[1]	MGTREFCLK0N_234
85	U1_XF.U15 U15	E1S1_FPGA_REFCLK_P<1>_XF E1S1_FPGA_REFCLK_P<1>_XF		e1s1_refclk_p[1]	MGTREFCLK0P_234
100	U1_XF.U16 U16	GND GND	0V	GND	GND
-	U1_XF.U17 U17	PWR_FPGA_3R3V PWR_FPGA_3R3V	3.3	VCCO_98	VCCO_98	3.3
84	U1_XF.U18 U18	E1S3_3R3V_LED_XF E1S3_3R3V_LED_XF	3.3V	e1s_3r3v_led[3]	IO_L3N_AD9N_98
83	U1_XF.U19 U19	E1S3_3R3V_SMB_RST_F_XF E1S3_3R3V_SMB_RST_F_XF	3.3V	e1s_3r3v_smb_rst_f[3]	IO_L2N_AD10N_98
84	U1_XF.U20 U20	E1S3_3R3V_SDA_XF E1S3_3R3V_SDA_XF	3.3V	e1s_3r3v_sda[3]	IO_L1N_AD11N_98
85	U1_XF.U21 U21	E1S3_3R3V_SCL_XF E1S3_3R3V_SCL_XF	3.3V	e1s_3r3v_scl[3]	IO_L1P_AD11P_98
100	U1_XF.U22 U22	GND GND	0V	GND	GND
20	U1_XF.U23 U23	C3_DDR4_CKE<1>_XF C3_DDR4_CKE<1>_XF		c3_ddr4_adr[6]	IO_L8N_T1L_N3_AD5N_75
36	U1_XF.U24 U24	C3_DDR4_ACT_N_XF C3_DDR4_ACT_N_XF		c3_ddr4_ba[1]	IO_L8P_T1L_N2_AD5P_75
20	U1_XF.U25 U25	C3_DDR4_BG<0>_XF C3_DDR4_BG<0>_XF		c3_ddr4_adr[8]	IO_T1U_N12_75
-	U1_XF.U26 U26	UNNAMED_22_RESISTOR_I38_B_XF UNNAMED_22_RESISTOR_I38_B_XF ->R52_XF->GND		VREF_75	VREF_75
100	U1_XF.U27 U27	GND GND	0V	GND	GND
20	U1_XF.U28 U28	C3_DDR4_ADR<9>_XF C3_DDR4_ADR<9>_XF		c3_ddr4_cke[1]	IO_L1P_T0L_N0_DBC_75
100	U1_XF.U29 U29	NC NC		VREF_72	VREF_72
100	U1_XF.U30 U30	NC NC		IO_L4P_T0U_N6_DBC_AD7P_72	IO_L4P_T0U_N6_DBC_AD7P_72
100	U1_XF.U31 U31	NC NC		IO_L5P_T0U_N8_AD14P_72	IO_L5P_T0U_N8_AD14P_72
100	U1_XF.U32 U32	GND GND	0V	GND	GND
100	U1_XF.U33 U33	NC NC		IO_L1N_T0L_N1_DBC_72	IO_L1N_T0L_N1_DBC_72
100	U1_XF.U34 U34	NC NC		IO_L1P_T0L_N0_DBC_72	IO_L1P_T0L_N0_DBC_72
100	U1_XF.U35 U35	NC NC		IO_L1P_T0L_N0_DBC_70	IO_L1P_T0L_N0_DBC_70
100	U1_XF.U36 U36	NC NC		VREF_70	VREF_70
100	U1_XF.U37 U37	GND GND	0V	GND	GND
100	U1_XF.U38 U38	NC NC		IO_L6P_T0U_N10_AD6P_70	IO_L6P_T0U_N10_AD6P_70
100	U1_XF.U39 U39	NC NC		IO_L6N_T0U_N11_AD6N_70	IO_L6N_T0U_N11_AD6N_70
100	U1_XF.U40 U40	NC NC		IO_L2P_T0L_N2_70	IO_L2P_T0L_N2_70
100	U1_XF.U41 U41	NC NC		IO_L4P_T0U_N6_DBC_AD7P_38	IO_L4P_T0U_N6_DBC_AD7P_38
100	U1_XF.U42 U42	GND GND	0V	GND	GND
100	U1_XF.U43 U43	NC NC		IO_L5P_T0U_N8_AD14P_38	IO_L5P_T0U_N8_AD14P_38
100	U1_XF.U44 U44	NC NC		IO_L5N_T0U_N9_AD14N_38	IO_L5N_T0U_N9_AD14N_38
100	U1_XF.U45 U45	NC NC		IO_L3P_T0L_N4_AD15P_38	IO_L3P_T0L_N4_AD15P_38
37	U1_XF.U46 U46	C2_DDR4_DQ<5>_XF C2_DDR4_DQ<5>_XF		c2_ddr4_dq[14]	IO_L2N_T0L_N3_36
100	U1_XF.U47 U47	GND GND	0V	GND	GND
37	U1_XF.U48 U48	C2_DDR4_DQ<1>_XF C2_DDR4_DQ<1>_XF		c2_ddr4_dq[11]	IO_L6P_T0U_N10_AD6P_36
37	U1_XF.U49 U49	C2_DDR4_DQ<2>_XF C2_DDR4_DQ<2>_XF		c2_ddr4_dq[8]	IO_L5N_T0U_N9_AD14N_36
37	U1_XF.U50 U50	C2_DDR4_DQ<7>_XF C2_DDR4_DQ<7>_XF		c2_ddr4_dq[12]	IO_L3P_T0L_N4_AD15P_36
16	U1_XF.U51 U51	C2_RDIMM_DQS_C<9>_XF C2_RDIMM_DQS_C<9>_XF		c2_ddr4_dqs_c[3]	IO_L1N_T0L_N1_DBC_36
100	U1_XF.U52 U52	GND GND	0V	GND	GND
100	U1_XF.U53 U53	NC NC		IO_L21P_T3L_N4_AD8P_33	IO_L21P_T3L_N4_AD8P_33
100	U1_XF.U54 U54	NC NC		IO_L21N_T3L_N5_AD8N_33	IO_L21N_T3L_N5_AD8N_33
100	U1_XF.U55 U55	NC NC		IO_L17P_T2U_N8_AD10P_33	IO_L17P_T2U_N8_AD10P_33
100	U1_XF.U56 U56	NC NC		IO_L17N_T2U_N9_AD10N_33	IO_L17N_T2U_N9_AD10N_33
100	U1_XF.U57 U57	GND GND	0V	GND	GND
100	U1_XF.U58 U58	NC NC		IO_L8P_T1L_N2_AD5P_33	IO_L8P_T1L_N2_AD5P_33
100	U1_XF.U59 U59	NC NC		IO_L8N_T1L_N3_AD5N_33	IO_L8N_T1L_N3_AD5N_33
100	U1_XF.U60 U60	NC NC		IO_L4P_T0U_N6_DBC_AD7P_33	IO_L4P_T0U_N6_DBC_AD7P_33
100	U1_XF.U61 U61	NC NC		IO_L4N_T0U_N7_DBC_AD7N_33	IO_L4N_T0U_N7_DBC_AD7N_33
100	U1_XF.U62 U62	GND GND	0V	GND	GND
100	U1_XF.U63 U63	NC NC		IO_L2P_T0L_N2_33	IO_L2P_T0L_N2_33
100	U1_XF.V1 V1	GND GND	0V	GND	GND
100	U1_XF.V2 V2	GND GND	0V	GND	GND
95	U1_XF.V3 V3	E1S1_PER_N<4>_XF E1S1_PER_N<4>_XF		e1s1_per_n[4]	MGTYRXN0_234
95	U1_XF.V4 V4	E1S1_PER_P<4>_XF E1S1_PER_P<4>_XF		e1s1_per_p[4]	MGTYRXP0_234
100	U1_XF.V5 V5	GND GND	0V	GND	GND
100	U1_XF.V6 V6	GND GND	0V	GND	GND
100	U1_XF.V7 V7	GND GND	0V	GND	GND
92	U1_XF.V8 V8	AC_E1S2_PET_N<2>_XF AC_E1S2_PET_N<2>_XF		e1s2_pet_n[2]	MGTYTXN2_233
92	U1_XF.V9 V9	AC_E1S2_PET_P<2>_XF AC_E1S2_PET_P<2>_XF		e1s2_pet_p[2]	MGTYTXP2_233
100	U1_XF.V10 V10	GND GND	0V	GND	GND
23	U1_XF.V11 V11	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
100	U1_XF.V12 V12	NC NC		MGTREFCLK1N_233	MGTREFCLK1N_233
100	U1_XF.V13 V13	NC NC		MGTREFCLK1P_233	MGTREFCLK1P_233
100	U1_XF.V14 V14	GND GND	0V	GND	GND
23	U1_XF.V15 V15	PWR_AVCC_RUC_XF PWR_AVCC_RUC_XF	0.9	MGTAVCC_RUC	MGTAVCC_RUC	0.9
100	U1_XF.V16 V16	GND GND	0V	GND	GND
83	U1_XF.V17 V17	E1S0_3R3V_CKEN_F<0>_XF E1S0_3R3V_CKEN_F<0>_XF		e1s_3r3v_cken0_f[0]	IO_L12N_AD0N_93
84	U1_XF.V18 V18	E1S3_3R3V_PWRDIS_XF E1S3_3R3V_PWRDIS_XF	3.3V	e1s_3r3v_pwrdis[3]	IO_L3P_AD9P_98
80	U1_XF.V19 V19	E1S3_3R3V_DUALPORTEN_F_XF E1S3_3R3V_DUALPORTEN_F_XF		e1s_3r3v_dualporten_f[3]	IO_L2P_AD10P_98
100	U1_XF.V20 V20	GND GND	0V	GND	GND
91	U1_XF.V21 V21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.V22 V22	GND GND	0V	GND	GND
91	U1_XF.V23 V23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.V24 V24	GND GND	0V	GND	GND
91	U1_XF.V25 V25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.V26 V26	GND GND	0V	GND	GND
91	U1_XF.V27 V27	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.V28 V28	GND GND	0V	GND	GND
91	U1_XF.V29 V29	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.V30 V30	GND GND	0V	GND	GND
91	U1_XF.V31 V31	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.V32 V32	GND GND	0V	GND	GND
91	U1_XF.V33 V33	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.V34 V34	GND GND	0V	GND	GND
91	U1_XF.V35 V35	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.V36 V36	GND GND	0V	GND	GND
91	U1_XF.V37 V37	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.V38 V38	GND GND	0V	GND	GND
91	U1_XF.V39 V39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.V40 V40	GND GND	0V	GND	GND
91	U1_XF.V41 V41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.V42 V42	GND GND	0V	GND	GND
91	U1_XF.V43 V43	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.V44 V44	GND GND	0V	GND	GND
100	U1_XF.V45 V45	GND GND	0V	GND	GND
37	U1_XF.V46 V46	C2_DDR4_DQ<4>_XF C2_DDR4_DQ<4>_XF		c2_ddr4_dq[13]	IO_L2P_T0L_N2_36
16	U1_XF.V47 V47	C2_RDIMM_DQS_T<0>_XF C2_RDIMM_DQS_T<0>_XF		c2_ddr4_dqs_t[2]	IO_L4P_T0U_N6_DBC_AD7P_36
24	U1_XF.V48 V48	C2_RDIMM_DQS_C<0>_XF C2_RDIMM_DQS_C<0>_XF		c2_ddr4_dqs_c[2]	IO_L4N_T0U_N7_DBC_AD7N_36
37	U1_XF.V49 V49	C2_DDR4_DQ<0>_XF C2_DDR4_DQ<0>_XF		c2_ddr4_dq[9]	IO_L5P_T0U_N8_AD14P_36
100	U1_XF.V50 V50	GND GND	0V	GND	GND
16	U1_XF.V51 V51	C2_RDIMM_DQS_T<9>_XF C2_RDIMM_DQS_T<9>_XF		c2_ddr4_dqs_t[3]	IO_L1P_T0L_N0_DBC_36
100	U1_XF.V52 V52	NC NC		VREF_33	VREF_33
100	U1_XF.V53 V53	NC NC		IO_L23P_T3U_N8_33	IO_L23P_T3U_N8_33
100	U1_XF.V54 V54	NC NC		IO_L23N_T3U_N9_33	IO_L23N_T3U_N9_33
100	U1_XF.V55 V55	GND GND	0V	GND	GND
100	U1_XF.V56 V56	NC NC		IO_T2U_N12_33	IO_T2U_N12_33
100	U1_XF.V57 V57	NC NC		IO_T0U_N12_VRP_32	IO_T0U_N12_VRP_32
100	U1_XF.V58 V58	NC NC		IO_L24P_T3U_N10_31	IO_L24P_T3U_N10_31
100	U1_XF.V59 V59	NC NC		IO_L24N_T3U_N11_31	IO_L24N_T3U_N11_31
100	U1_XF.V60 V60	NC NC		VCCO_31	VCCO_31	1.8
100	U1_XF.V61 V61	NC NC		IO_L22P_T3U_N6_DBC_AD0P_31	IO_L22P_T3U_N6_DBC_AD0P_31
100	U1_XF.V62 V62	NC NC		IO_L22N_T3U_N7_DBC_AD0N_31	IO_L22N_T3U_N7_DBC_AD0N_31
100	U1_XF.V63 V63	NC NC		IO_T3U_N12_31	IO_T3U_N12_31
95	U1_XF.W1 W1	E1S2_PER_N<3>_XF E1S2_PER_N<3>_XF		e1s2_per_n[3]	MGTYRXN3_233
95	U1_XF.W2 W2	E1S2_PER_P<3>_XF E1S2_PER_P<3>_XF		e1s2_per_p[3]	MGTYRXP3_233
100	U1_XF.W3 W3	GND GND	0V	GND	GND
100	U1_XF.W4 W4	GND GND	0V	GND	GND
100	U1_XF.W5 W5	GND GND	0V	GND	GND
92	U1_XF.W6 W6	AC_E1S2_PET_N<1>_XF AC_E1S2_PET_N<1>_XF		e1s2_pet_n[1]	MGTYTXN1_233
92	U1_XF.W7 W7	AC_E1S2_PET_P<1>_XF AC_E1S2_PET_P<1>_XF		e1s2_pet_p[1]	MGTYTXP1_233
100	U1_XF.W8 W8	GND GND	0V	GND	GND
23	U1_XF.W9 W9	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
92	U1_XF.W10 W10	AC_E1S2_PET_N<0>_XF AC_E1S2_PET_N<0>_XF		e1s2_pet_n[0]	MGTYTXN0_233
92	U1_XF.W11 W11	AC_E1S2_PET_P<0>_XF AC_E1S2_PET_P<0>_XF		e1s2_pet_p[0]	MGTYTXP0_233
100	U1_XF.W12 W12	GND GND	0V	GND	GND
23	U1_XF.W13 W13	PWR_AVCC_RUC_XF PWR_AVCC_RUC_XF	0.9	MGTAVCC_RUC	MGTAVCC_RUC	0.9
85	U1_XF.W14 W14	E1S2_FPGA_REFCLK_N<0>_XF E1S2_FPGA_REFCLK_N<0>_XF		e1s2_refclk_n[0]	MGTREFCLK0N_233
85	U1_XF.W15 W15	E1S2_FPGA_REFCLK_P<0>_XF E1S2_FPGA_REFCLK_P<0>_XF		e1s2_refclk_p[0]	MGTREFCLK0P_233
100	U1_XF.W16 W16	GND GND	0V	GND	GND
33	U1_XF.W17 W17	E1S0_3R3V_CKEN_F<1>_XF E1S0_3R3V_CKEN_F<1>_XF		e1s_3r3v_cken1_f[0]	IO_L12P_AD0P_93
100	U1_XF.W18 W18	GND GND	0V	GND	GND
84	U1_XF.W19 W19	E1S0_3R3V_PRSNT_F<0>_XF E1S0_3R3V_PRSNT_F<0>_XF	3.3V	e1s_3r3v_prsnt0_f[0]	IO_L11N_AD1N_93
91	U1_XF.W20 W20	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.W21 W21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.W22 W22	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.W23 W23	GND GND	0V	GND	GND
91	U1_XF.W24 W24	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.W25 W25	GND GND	0V	GND	GND
91	U1_XF.W26 W26	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.W27 W27	GND GND	0V	GND	GND
91	U1_XF.W28 W28	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.W29 W29	GND GND	0V	GND	GND
91	U1_XF.W30 W30	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.W31 W31	GND GND	0V	GND	GND
91	U1_XF.W32 W32	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.W33 W33	GND GND	0V	GND	GND
91	U1_XF.W34 W34	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.W35 W35	GND GND	0V	GND	GND
91	U1_XF.W36 W36	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.W37 W37	GND GND	0V	GND	GND
91	U1_XF.W38 W38	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.W39 W39	GND GND	0V	GND	GND
91	U1_XF.W40 W40	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.W41 W41	GND GND	0V	GND	GND
91	U1_XF.W42 W42	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.W43 W43	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
91	U1_XF.W44 W44	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.W45 W45	NC NC		IO_L21P_T3L_N4_AD8P_32	IO_L21P_T3L_N4_AD8P_32
100	U1_XF.W46 W46	NC NC		IO_L21N_T3L_N5_AD8N_32	IO_L21N_T3L_N5_AD8N_32
100	U1_XF.W47 W47	NC NC		IO_L19N_T3L_N1_DBC_AD9N_32	IO_L19N_T3L_N1_DBC_AD9N_32
100	U1_XF.W48 W48	GND GND	0V	GND	GND
100	U1_XF.W49 W49	NC NC		IO_L15N_T2L_N5_AD11N_32	IO_L15N_T2L_N5_AD11N_32
100	U1_XF.W50 W50	NC NC		IO_L17N_T2U_N9_AD10N_32	IO_L17N_T2U_N9_AD10N_32
100	U1_XF.W51 W51	NC NC		IO_L10P_T1U_N6_QBC_AD4P_32	IO_L10P_T1U_N6_QBC_AD4P_32
100	U1_XF.W52 W52	NC NC		IO_L10N_T1U_N7_QBC_AD4N_32	IO_L10N_T1U_N7_QBC_AD4N_32
100	U1_XF.W53 W53	GND GND	0V	GND	GND
100	U1_XF.W54 W54	NC NC		IO_L8N_T1L_N3_AD5N_32	IO_L8N_T1L_N3_AD5N_32
100	U1_XF.W55 W55	NC NC		IO_L6N_T0U_N11_AD6N_32	IO_L6N_T0U_N11_AD6N_32
100	U1_XF.W56 W56	NC NC		IO_L4P_T0U_N6_DBC_AD7P_32	IO_L4P_T0U_N6_DBC_AD7P_32
100	U1_XF.W57 W57	NC NC		IO_L4N_T0U_N7_DBC_AD7N_32	IO_L4N_T0U_N7_DBC_AD7N_32
100	U1_XF.W58 W58	GND GND	0V	GND	GND
100	U1_XF.W59 W59	NC NC		IO_L20P_T3L_N2_AD1P_31	IO_L20P_T3L_N2_AD1P_31
100	U1_XF.W60 W60	NC NC		IO_L20N_T3L_N3_AD1N_31	IO_L20N_T3L_N3_AD1N_31
100	U1_XF.W61 W61	NC NC		IO_L23P_T3U_N8_31	IO_L23P_T3U_N8_31
100	U1_XF.W62 W62	NC NC		IO_L23N_T3U_N9_31	IO_L23N_T3U_N9_31
100	U1_XF.W63 W63	GND GND	0V	GND	GND
100	U1_XF.Y1 Y1	GND GND	0V	GND	GND
100	U1_XF.Y2 Y2	GND GND	0V	GND	GND
95	U1_XF.Y3 Y3	E1S2_PER_N<2>_XF E1S2_PER_N<2>_XF		e1s2_per_n[2]	MGTYRXN2_233
95	U1_XF.Y4 Y4	E1S2_PER_P<2>_XF E1S2_PER_P<2>_XF		e1s2_per_p[2]	MGTYRXP2_233
100	U1_XF.Y5 Y5	GND GND	0V	GND	GND
100	U1_XF.Y6 Y6	GND GND	0V	GND	GND
100	U1_XF.Y7 Y7	GND GND	0V	GND	GND
92	U1_XF.Y8 Y8	AC_E1S2_PET_N<7>_XF AC_E1S2_PET_N<7>_XF		e1s2_pet_n[7]	MGTYTXN3_232
92	U1_XF.Y9 Y9	AC_E1S2_PET_P<7>_XF AC_E1S2_PET_P<7>_XF		e1s2_pet_p[7]	MGTYTXP3_232
100	U1_XF.Y10 Y10	GND GND	0V	GND	GND
23	U1_XF.Y11 Y11	PWR_AVTT_RUC_XF PWR_AVTT_RUC_XF	1.2	MGTAVTT_RUC	MGTAVTT_RUC	1.2
100	U1_XF.Y12 Y12	NC NC		MGTREFCLK1N_232	MGTREFCLK1N_232
100	U1_XF.Y13 Y13	NC NC		MGTREFCLK1P_232	MGTREFCLK1P_232
100	U1_XF.Y14 Y14	GND GND	0V	GND	GND
23	U1_XF.Y15 Y15	PWR_AVCC_RUC_XF PWR_AVCC_RUC_XF	0.9	MGTAVCC_RUC	MGTAVCC_RUC	0.9
100	U1_XF.Y16 Y16	GND GND	0V	GND	GND
83	U1_XF.Y17 Y17	E1S0_3R3V_PERST_F<0>_XF E1S0_3R3V_PERST_F<0>_XF	3.3V	e1s_3r3v_perst0_f[0]	IO_L10N_AD2N_93
31	U1_XF.Y18 Y18	E1S0_3R3V_PERST_CLKREQ_F<1>_XF E1S0_3R3V_PERST_CLKREQ_F<1>_XF	3.3V	e1s_3r3v_perst1_clkreq_f[0]	IO_L10P_AD2P_93
34	U1_XF.Y19 Y19	E1S0_3R3V_PRSNT_F<1>_XF E1S0_3R3V_PRSNT_F<1>_XF	3.3V	e1s_3r3v_prsnt1_f[0]	IO_L11P_AD1P_93
100	U1_XF.Y20 Y20	GND GND	0V	GND	GND
91	U1_XF.Y21 Y21	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.Y22 Y22	GND GND	0V	GND	GND
91	U1_XF.Y23 Y23	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.Y24 Y24	GND GND	0V	GND	GND
91	U1_XF.Y25 Y25	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.Y26 Y26	GND GND	0V	GND	GND
91	U1_XF.Y27 Y27	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.Y28 Y28	GND GND	0V	GND	GND
91	U1_XF.Y29 Y29	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.Y30 Y30	GND GND	0V	GND	GND
91	U1_XF.Y31 Y31	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.Y32 Y32	GND GND	0V	GND	GND
91	U1_XF.Y33 Y33	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.Y34 Y34	GND GND	0V	GND	GND
91	U1_XF.Y35 Y35	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.Y36 Y36	GND GND	0V	GND	GND
91	U1_XF.Y37 Y37	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.Y38 Y38	GND GND	0V	GND	GND
91	U1_XF.Y39 Y39	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.Y40 Y40	GND GND	0V	GND	GND
91	U1_XF.Y41 Y41	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.Y42 Y42	GND GND	0V	GND	GND
91	U1_XF.Y43 Y43	PWR_VCCINT_XF PWR_VCCINT_XF	0.85	VCCINT	VCCINT	0.85
100	U1_XF.Y44 Y44	GND GND	0V	GND	GND
100	U1_XF.Y45 Y45	NC NC		IO_L23N_T3U_N9_32	IO_L23N_T3U_N9_32
100	U1_XF.Y46 Y46	GND GND	0V	GND	GND
100	U1_XF.Y47 Y47	NC NC		IO_L19P_T3L_N0_DBC_AD9P_32	IO_L19P_T3L_N0_DBC_AD9P_32
100	U1_XF.Y48 Y48	NC NC		IO_L18N_T2U_N11_AD2N_32	IO_L18N_T2U_N11_AD2N_32
100	U1_XF.Y49 Y49	NC NC		IO_L15P_T2L_N4_AD11P_32	IO_L15P_T2L_N4_AD11P_32
100	U1_XF.Y50 Y50	NC NC		IO_L17P_T2U_N8_AD10P_32	IO_L17P_T2U_N8_AD10P_32
100	U1_XF.Y51 Y51	GND GND	0V	GND	GND
100	U1_XF.Y52 Y52	NC NC		IO_L12N_T1U_N11_GC_32	IO_L12N_T1U_N11_GC_32
100	U1_XF.Y53 Y53	NC NC		IO_L11N_T1U_N9_GC_32	IO_L11N_T1U_N9_GC_32
100	U1_XF.Y54 Y54	NC NC		IO_L8P_T1L_N2_AD5P_32	IO_L8P_T1L_N2_AD5P_32
100	U1_XF.Y55 Y55	NC NC		IO_L6P_T0U_N10_AD6P_32	IO_L6P_T0U_N10_AD6P_32
100	U1_XF.Y56 Y56	NC NC		VCCO_32	VCCO_32	1.8
100	U1_XF.Y57 Y57	NC NC		IO_L2N_T0L_N3_32	IO_L2N_T0L_N3_32
100	U1_XF.Y58 Y58	NC NC		IO_L18N_T2U_N11_AD2N_31	IO_L18N_T2U_N11_AD2N_31
100	U1_XF.Y59 Y59	NC NC		IO_L21P_T3L_N4_AD8P_31	IO_L21P_T3L_N4_AD8P_31
100	U1_XF.Y60 Y60	NC NC		IO_L21N_T3L_N5_AD8N_31	IO_L21N_T3L_N5_AD8N_31
100	U1_XF.Y61 Y61	GND GND	0V	GND	GND
100	U1_XF.Y62 Y62	NC NC		IO_L19P_T3L_N0_DBC_AD9P_31	IO_L19P_T3L_N0_DBC_AD9P_31
100	U1_XF.Y63 Y63	NC NC		IO_L19N_T3L_N1_DBC_AD9N_31	IO_L19N_T3L_N1_DBC_AD9N_31

* NetName = NC, SigName = PinName
** Voltage Inferred From Net Name

Name	Value	Description
BOM_NO_POP_PROP	DNI	This Setting is used to pick a list of properties that excludes a reference designators from installation, but keeps the part in the BOM for purchasing When the BOM is generated by the netlist convert routine, any parts with this property found to be true will be printed on a separate row.
BOM_NO_POP_TRUE_VALS	TRUE,YES,1	This Setting is used to pick a property and value that excludes reference designators from installation, but keeps the part in the BOM for purchasing When the BOM is generated by the netlist convert routine, any parts with this property enabled will be printed on a separate row. ###This was recently renamed from BOM_NO_PROP_TRUE_VALS and this setting is not yet Used
CAPACITANCE_DERATING	90	Capacitance derating value (percentage). Used as the default derating value for capacitors in the power rail report. Capacitors are multiplied by this value to determine the real capacitance value.
CAP_VOLTAGE_DERATING	33	Capacitance voltage derating setpoint (percentage). Used as pass/fail limit for calculated voltage derating The calculated voltage derating shown in the rail capacitance tables is 100*(1-netVoltage/CapVoltage) If the calculated voltage derating is less than this setpoint, the capacitor on that rail will be flagged and added to overvoltage capacitor report
DNI_TRUE_VALS	NM,1,TRUE,YES	This is a list of the values that make the DO_NOT_INSTALL_PROP true (comma seperated vals like:TRUE,1,YES)
DO_NOT_INSTALL_PROP	Statut,BOM_IGNORE,DNI	This is a comma seperated list of properties that will be used to determine if a part is not included in a BOM Could look like BOM_IGNORE,DNI. Any part with this Property found True will not be included in the BOM (unlike the BOM_NO_POP_PROP)
EP_VERIFY_CONFIG	TEST_DATA/netlists/CET-1009-NetBom_FPGA_Endpoint_Verify/test_case_1_xilinx_lattice/endpoint_verify_config.txt	EP_VERIFY_CONFIG is the path to the endpoint config file. In order to edit an existing configuration file, select the path to your desired file and then press the Create button to the right of the field. To create a new configuration file, leave this field blank and press the Create button. If no configuration controls are appearing (the GUI is nearly blank), make sure the VERIFY_ENDPOINT_PARTLIST field is populated with your endpoints. This configuration file contains information such as the pin report type, file path, optional package file, and match score override information. The file and field is required for successful endpoint verification operation.
IGNORE_NET_PROP_DIFFS	0	Property names listed in this comma separated list will be ignored when properties for the same NET_NAME in the 2 netLists are compared The following properties are never compared so they should not need to be added NET_NAME NET_CONNS NET_ID_FROM_PINS NET_ID_XCHECKED NL_INDEX NODE_LIST HIER_NET_NAME LOGICAL_PATH C_SIGNAL The user can look at the net_prop difference report and add any properties to this list that they do not want to include in the comparison
IS_BOM_COMPARE	0	If set, NetBom will only Compare PartLists, and the Netlist compare operation will be skipped. NetBom will help detect this for the user on the first pass of a diff or convert opeartion if one of the NETLIST files is a BOM spreadsheet. If this is not set, the user will be asked if they want to set it when the operation is run.
KEY_PROP_IGNORE_LIST	Verify_	The BOM_DIFF engine will filter any of these props out of the KEY_PROP_LIST before comparing part properties it is entered as a single PropName or comma separated list of Propertieeslike: MY_LIB,Validate_,GEOMETRY.HEIGHT
KEY_PROP_LIST	ALT_SYMBOLS,BODY_NAME,BOM_IGNORE,CDS_LIB,CDS_PART_NAME,CLASS,COLOR,CURRENT,C_PATH,C_TEMPERATURE,DCR,DESC,DIELECTRIC,DOCUMENT,DRAWING,EXC_MNG_MATCHING,FREQ,HEIGHT,INSTANCE,JEDEC_TYPE,J_TEMPERATURE,LIB_INFO,LOCATION,MAX_CASE_DISS_LIMIT,MAX_POWER_DISS,MGTOL_VAR1,MGTOL_VAR2,MGTOL_VAR3,MULT_QTY,NAME,NOT_FEEDTHRU,OC_LIBRARY,ORIENTATION,PACK_TYPE,PAGE,PARENT_PART_TYPE,PARENT_PPT,PARENT_PPT_PART,PART_IN_LIB,PART_LIB_MODIFIER,PART_NAME,PART_NUMBER,PATH,PHYS_DES_PREFIX,PHYS_PAGE,PHY_DES_PREFIX,PN,POWER,PRIMITIVE,PRIM_FILE,P_PATH,REF_DES,REMOTE,REMOVE,REUSE_INSTANCE,REUSE_NAME,REUSE_PID,REVISION,ROOM,ROT,R_FREQ,SCH_MODIFIED_PART,SEC,SECTION_NUM,SECTION_PAGE_INFO,SEC_TYPE,SPEED,SUBDESIGN_NAME,SUBDESIGN_SUFFIX,SYMBOL_NAME,TECH,TEMP,TH_JA_RES,TH_JC_RES,TOL,TYPE,TYP_POWER_DISS,VALUE,VARIANT,VENDOR,VENDOR_PN,VER,VIN,VOLT,VOLTAGE,VOUT,WX2_FPGA_VARIANT,XC2_FPGA_VARIANT,XY	The BOM_DIFF engine will compare these properties for each refdes in the 2 bom revisions and report if they are different... it can be entered as a single propName or as a comma separated list like: JEDEC_TYPE,VALUE,TYPE If you leave this blank(New Default), NetBom will gather all the part properties it detects and create the list for you (while excluding any props in the KEY_PROP_IGNORE_LIST)
NET_PROP_RENAME_RULES	0	Comma Separated List of Was:Is rules to change Net Property Names in an existing netlist. This Example: ^_(.*):$1 This will remove a leading '_' from a property _WebLink:WebLink will rename the _WebLink property to WebLink
NET_TRACE_COMPONENT_STOP	CONNECTOR,IC	This comma-separated list of reference designator prefixes tells NetBom which nodes should stop the net trace when encountered. By default it is assumed that connector/ic parts start with a J or U and when the trace encounters nodes that start with those letters it will stop the trace.
NET_TRACE_NET_NODE_LIMIT	6	This setting governs the max number of pins that a net can have in a net trace before the trace stops. A higher number represents more pins that the net trace will tolerate before it stops tracing. Higher numbers means more complex traces, which can be desireable in some cases and undeseriable in other cases.
NET_TRACE_PIN_LIMIT	3	This setting governs the max number of pins that a node can have in a net trace before the net trace stops. The higher the pin limit, the further the net trace will go. Along with this, the higher the limit, the exponentially longer time the net trace will take. If a net trace is taking too long, it may be because this number is too high.
NET_TRACE_PWR_RAIL_NODE_LIMIT	15	This number is the upper limit for how many nodes are on a power rail in order for NetBom to trace it. With the default value of 15, all nets that we identify as power rails that have 15 or less nodes will be traced and available to view in the net trace utilities. All power rails with more than 15 nodes will not be traced and will not be included in our tracing utilities. Using a lower value may speed up the netlist processing for designs that have many power rails. Set to 0 to not trace any suspected power rails.
NEW_NETLIST	TEST_DATA/netlists/CET-1009-NetBom_FPGA_Endpoint_Verify/test_case_1_xilinx_lattice/packaged_20210921_02/pstxnet.dat	NEW_NETLIST use for diffing and converting netlists. For Orcad/AllegroHDL You choose the pstxnet.dat file and netBom will find the matching pstxprt.dat and pstchip.dat files For Mentor, you can choose the .kyn or nets.fwd file For EDIF netlists, you choose the .edf file
NODE_PROP_RENAME_RULES	0	Comma Separated List of Was:Is rules to change Node Property Names in an existing netlist. This Example: ^_(.*):$1 This will remove a leading '_' from a property _WebLink:WebLink will rename the _WebLink property to WebLink
OLD_NETLIST	0	OLD_NETLIST for diffing BOMs and NETLISTS. For Orcad/AllegroHDL You choose the pstxnet.dat file and netBom will find the matching pstxprt.dat and pstchip.dat files For Mentor, you can choose the .kyn or nets.fwd file For EDIF netlists, you choose the .edf file
PART_NUMBER_PROPS	zetec_no,PART_NUMBER,PART_NAME	The BOM_DIFF engine and NETLIST Creators will use this comma separated list of properties to search for the device part-number, It will use the first one it finds in this list The property name is case insensitive.
PART_PROPVAL_RENAME_RULES	^_:	Comma Separated List of Was:Is rules to change Part Property Values in an existing netlist. This Example: ^_(.*):$1 This will remove a leading '_' from a property _WebLink:WebLink will rename the _WebLink property to WebLink
PART_PROP_RENAME_RULES	Reference_:Reference	Comma Separated List of Was:Is rules to change Part Property Names in an existing netlist. This Example: ^_(.*):$1 This will remove a leading '_' from a property _WebLink:WebLink will rename the _WebLink property to WebLink
POWER_RAIL_CAP_VALUE_MIN	50	Minimum value (in pF) that a capacitor needs in order to be included in the power rail report. Set to zero in order to have no minimum. Example: A rail is identified with three caps. Capacitor 1: 1uf Capacitor 2: 2.5uF Capacitor 3: 45pF If the minimum value is set to 50pF, then capacitor 3 will not be included in the report. Furthermore, if POWER_RAIL_MIN_CAP_COUNT is set to 3 or more (the default is 3), then this will be excluded from the report entirely because it does not have enough capacitors.
POWER_RAIL_MIN_CAP_COUNT	3	Minimum number of capacitors that a net needs in order to be considered a power rail. This number is combined with net name voltage matching to determine which nets are power rails. The voltage matching system can be configured through the VOLTAGE_MATCH_OVERRIDE CSET.
POWER_RAIL_RESISTOR_OHM_LIMIT	10	This is the maximum value (in OHMs) that a resistor can have in order for it to be traced through when determining power rails. When we are evaluating a potential power net, we check the number of caps that are connected to the net. We trace through small components, including resistors, to find the capacitors, and this settings governs if we stop at a given resistor based on its OHM value.
POWER_RAIL_TOTAL_CAP_VALUE_MIN	1	Minimum value (in uF) that the caps on a rail should have in order for the rail to be considered a power rail and to be included in the power rail report. For example, with the default miniumum of 1uF, if there is a power rail with five 0.1uF caps and no other caps, the total cap value for the rail will be 0.5uF and will be excluded from the power rail report.
REFDES_RENAME_RULES	0	Comma Separated List of Was:Is rules to change reference designators in an existing netlist. This can be used when the user knows they are changing many refdes in the new NetList and they don't want them to show up in the difference reports Example: _57$:_S5_S7,_46$:_S4_S6,_02$:_S0_S2,_13$:_S1_S3 this will replace any location ending in _57 with _S5_S7, _46 with S4_S6, _02 with S2_S2, _13 with S1_S3,
SINGLE_NODE_NET_FILTERS	NC_,_NC,NC,^$UN	This Comma Separated List is used to validate SINGLE NODE NETS. If a NET_NAME contains any of these matches, and it only contains a single node, it will be counted as filtered, but not included in the SINGLE_NODE_NET report table
USE_PSTCMDB_PROPS	1	If enabled, this setting will make NetBom merge all net and part properties found in the PSTCMDB.dat file into the netlist and partlist databases.
VERIFY_ENDPOINT_PARTLIST	U1_XF,U1_CPLD	NO DESCRIPTION
VOLTAGE_MATCH_OVERRIDE	0	This will allow the user to have custom voltage matching algorithms beyond what is available in NetBom by default. VOLTAGE_MATCH_OVERRIDE holds a file path to a txt file. If this field is populated, NetBom will attempt to parse and use it instead of the default matching algorithms. If the file is not found or is unable to be parsed, NetBom will use the default matching as a fall-back.

NetBom: EP Verify

Version 0.99.99 | Thu Sep 01 2022 05:47:38

New Design: TEST_DATA/netlists/CET-1009-NetBom_FPGA_Endpoint_Verify/test_case_1_xilinx_lattice/packaged_20210921_02/pstxnet.dat

NetBom: EP Verify

Version 0.99.99 | Thu Sep 01 2022 05:47:38

New Design: TEST_DATA/netlists/CET-1009-NetBom_FPGA_Endpoint_Verify/test_case_1_xilinx_lattice/packaged_20210921_02/pstxnet.dat

Build Information

CSETs