var pl_nl_db_new = { "net_tracing" : { "UNNAMED_29_PI6CB33401_I63_SCLK_XF" : { "U5_XF.9" : {}, "R126_XF.2" : { "R126_XF.1" : { "PWR_FPGA_3R3V" : {} } } }, "C3_DDR4_ADR<1>_XF" : { "U1_XF.P26" : {}, "J4_XF.72" : {} }, "C2_RDIMM_DQS_T<15>_XF" : { "J3_XF.121" : {}, "U1_XF.G48" : {} }, "AC_OCL0_PET_N<2>_XF" : { "U1_XF.CB8" : {}, "C259_XF.1" : { "C259_XF.2" : { "OCL0_PET_N<2>_XF" : { "J1_O0_XF.B16" : {} } } } }, "AC_E1S3_PET_P<1>_XF" : { "C341_XF.1" : { "C341_XF.2" : { "E1S3_PET_P<1>_XF" : { "J1_E3_XF.B21" : {} } } }, "U1_XF.AH9" : {} }, "C1_DDR4_DQ<34>_XF" : { "J2_XF.104" : {}, "U1_XF.BP62" : {} }, "PCIE0_TXP<2>_XF" : { "J1_P0_XF.B15" : {}, "C39_XF.2" : { "C39_XF.1" : { "AC_PCIE0_TXP<2>_XF" : { "U1_XF.AV13" : {} } } } }, "UNNAMED_21_RESISTOR_I28_B_XF" : { "R46_XF.2" : { "R46_XF.1" : { "GND" : {} } }, "U1_XF.H61" : {} }, "POK_OD_VCCINT_TRSW_P<1>" : { "U1_CPLD.P12" : {}, "R92_SP_XF.2" : { "R92_SP_XF.1" : { "UNNAMED_5_LTM4650FIXED_I78_PGOOD2_SP" : { "PM5_SP_XF.G8" : { "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "PM4_SP_XF.E6" : { "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K5" : { "GND" : {} } } } } } }, "RGB_LED_RED<2>_CPLD" : { "U1_CPLD.D9" : {}, "R4_CPLD.2" : { "R4_CPLD.1" : { "UNNAMED_9_LUMEXRGBLED_I90_REDK_CPLD" : { "D2_CPLD.2" : { "D2_CPLD.4" : { "UNNAMED_9_LUMEXRGBLED_I90_GREENK_CPLD" : { "R5_CPLD.1" : { "R5_CPLD.2" : { "RGB_LED_GREEN<2>_CPLD" : { "U1_CPLD.A8" : {} } } } } }, "D2_CPLD.3" : { "UNNAMED_9_LUMEXRGBLED_I90_BLUEK_CPLD" : { "R20_CPLD.1" : { "R20_CPLD.2" : { "RGB_LED_BLUE<2>_CPLD" : { "U1_CPLD.B7" : {} } } } } }, "D2_CPLD.1" : { "CPLD_P3R3V" : {} } } } } } }, "E1S0_PET_P<1>_XF" : { "C108_XF.2" : { "C108_XF.1" : { "AC_E1S0_PET_P<1>_XF" : { "U1_XF.B9" : {} } } }, "J1_E0_XF.B21" : {} }, "C1_DDR4_DQ<50>_XF" : { "J2_XF.126" : {}, "U1_XF.BN58" : {} }, "C3_DDR4_DQ<19>_XF" : { "U1_XF.F25" : {}, "J4_XF.179" : {} }, "P12V_FUSED_4675_ND" : { "PM4_ND_XF.J9" : {}, "PM4_ND_XF.A9" : {}, "PM4_ND_XF.D9" : {}, "PM4_ND_XF.B9" : {}, "F7_ND_XF.2" : { "F7_ND_XF.1" : { "P12V_MAIN" : {} } }, "C10_ND_XF.1" : { "C10_ND_XF.2" : { "GND" : {} } }, "C2_ND_XF.1" : { "C2_ND_XF.2" : { "GND" : {} } }, "C67_ND_XF.2" : { "C67_ND_XF.1" : { "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF" : {} } }, "C66_ND_XF.1" : { "C66_ND_XF.2" : { "GND" : {} } }, "C7_ND_XF.1" : { "C7_ND_XF.2" : { "GND" : {} } }, "PM4_ND_XF.L9" : {}, "PM4_ND_XF.M9" : {}, "PM4_ND_XF.K9" : {}, "PM4_ND_XF.F9" : {}, "C68_ND_XF.2" : { "C68_ND_XF.1" : { "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF" : {} } }, "PM4_ND_XF.C9" : {} }, "E1S2_PER_N<1>_XF" : { "U1_XF.AA1" : {}, "J1_E2_XF.A20" : {} }, "UNNAMED_7_NMOSFETVMT3_I2_D" : { "Q13.4" : { "Q13.6" : { "PWR_FPGA_3R3V" : {} }, "Q13.5" : { "PWR_FPGA_3R3V" : {} }, "Q13.1" : { "P3R3V" : {} }, "Q13.3" : { "P3R3V" : {} }, "Q13.2" : { "P3R3V" : {} }, "Q13.8" : { "PWR_FPGA_3R3V" : {} }, "Q13.7" : { "PWR_FPGA_3R3V" : {} } }, "Q12.3" : { "Q12.1" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "PM2_SP_XF.J8" : { "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : {} } } } }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} } }, "U1_CPLD.N16" : {} } }, "Q12.2" : { "GND" : {} } } }, "FSET_4650_BR_SP" : { "R89_SP_XF.2" : { "R89_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "PM7_SP_XF.C6" : { "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} } } }, "VMON_AVTT_RS_LIN_XF" : { "R137_XF.2" : { "R137_XF.1" : { "UNNAMED_17_RESISTOR_I110_A_XF" : { "R129_XF.2" : { "R129_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I116_A_XF" : { "U1_XF.BW31" : {}, "C268_XF.1" : { "C268_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I116_B_XF" : { "R130_XF.1" : { "R130_XF.2" : { "UNNAMED_17_RESISTOR_I113_A_XF" : { "R141_XF.1" : { "R141_XF.2" : { "GND" : {} } }, "R139_XF.1" : { "R139_XF.2" : { "GND" : {} } } } } }, "U1_XF.BW32" : {} } } } } } }, "R138_XF.1" : { "R138_XF.2" : { "GND" : {} } } } } }, "R4_FL_XF.2" : { "R4_FL_XF.1" : { "VS_AVTT_RS_LIN_FL" : { "NS5_FL_XF.2" : { "NS5_FL_XF.1" : { "PWR_AVTT_RS_XF" : {} } }, "U2_FL_XF.19" : {} } } }, "R93_XF.2" : { "R93_XF.1" : { "UNNAMED_17_RESISTOR_I40_A_XF" : { "R99_XF.2" : { "R99_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I46_A_XF" : { "U1_XF.BY33" : {}, "C147_XF.1" : { "C147_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I46_B_XF" : { "U1_XF.CA33" : {}, "R100_XF.1" : { "R100_XF.2" : { "UNNAMED_17_RESISTOR_I41_A_XF" : { "R96_XF.1" : { "R96_XF.2" : { "GND" : {} } }, "R95_XF.1" : { "R95_XF.2" : { "GND" : {} } } } } } } } } } } }, "R94_XF.1" : { "R94_XF.2" : { "GND" : {} } } } } } }, "C3_DDR4_DQ<26>_XF" : { "U1_XF.F22" : {}, "J4_XF.45" : {} }, "C0_DDR4_DQ<58>_XF" : { "J1_XF.137" : {}, "U1_XF.BG29" : {} }, "C0_DDR4_BA<0>_XF" : { "U1_XF.CB19" : {}, "J1_XF.81" : {} }, "E1S1_FPGA_REFCLK_P<0>_XF" : { "C19_E1_XF.2" : { "C19_E1_XF.1" : { "AC_FPGA_CLK_REF_P<0>" : { "U1_E1_XF.22" : {} } } }, "U1_XF.P13" : {}, "R180_XF.1" : { "R180_XF.2" : { "E1S1_FPGA_REFCLK_N<0>_XF" : {} } }, "R168_XF.2" : { "R168_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R179_XF.1" : { "R179_XF.2" : { "GND" : {} } } }, "CLKIN_P_E0" : { "R16_E0_XF.1" : { "R16_E0_XF.2" : { "GND" : {} } }, "C16_E0_XF.2" : { "C16_E0_XF.1" : { "E1S_REF_CLK_P<0>" : { "U1.28" : {} } } }, "R17_E0_XF.1" : { "R17_E0_XF.2" : { "CLKIN_N_E0" : {} } }, "R14_E0_XF.2" : { "R14_E0_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E0_XF.5" : {} }, "C1_DDR4_DQ<64>_XF" : { "U1_XF.BR59" : {}, "J2_XF.49" : {} }, "AC_E1S2_PET_N<2>_XF" : { "C171_XF.1" : { "C171_XF.2" : { "E1S2_PET_N<2>_XF" : { "J1_E2_XF.B23" : {} } } }, "U1_XF.V8" : {} }, "UNNAMED_29_PI6CB33401_I89_SADRTRI_XF" : { "R148_XF.2" : { "R148_XF.1" : { "GND" : {} } }, "U7_XF.32" : {} }, "C2_RDIMM_DQS_C<5>_XF" : { "U1_XF.D52" : {}, "J3_XF.255" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I107_B_XF" : { "R128_XF.1" : { "R128_XF.2" : { "UNNAMED_17_RESISTOR_I104_A_XF" : { "R136_XF.1" : { "R136_XF.2" : { "UNNAMED_17_RESISTOR_I105_B_XF" : { "R121_XF.1" : { "R121_XF.2" : { "GND" : {} } } } } }, "R135_XF.1" : { "R135_XF.2" : { "GND" : {} } } } } }, "U1_XF.CC33" : {}, "C267_XF.2" : { "C267_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I107_A_XF" : { "U1_XF.CB33" : {}, "R127_XF.1" : { "R127_XF.2" : { "UNNAMED_17_RESISTOR_I101_A_XF" : { "R134_XF.1" : { "R134_XF.2" : { "UNNAMED_17_RESISTOR_I101_B_XF" : { "R120_XF.1" : { "R120_XF.2" : { "GND" : {} } } } } }, "R133_XF.1" : { "R133_XF.2" : { "IMON_AVTT_LIN_XF" : { "R25_FL_XF.2" : { "R25_FL_XF.1" : { "UNNAMED_6_LT3071_I30_IMON_FL" : { "U2_FL_XF.21" : {} } } }, "R82_FL_XF.2" : { "R82_FL_XF.1" : { "UNNAMED_8_LT3071_I30_IMON_FL" : { "R26_FL_XF.2" : { "R26_FL_XF.1" : { "GND" : {} } }, "U5_FL_XF.21" : {} } } }, "R64_FL_XF.2" : { "R64_FL_XF.1" : { "UNNAMED_7_LT3071_I30_IMON_FL" : { "U4_FL_XF.21" : {} } } }, "R24_FL_XF.2" : { "R24_FL_XF.1" : { "UNNAMED_5_LT3071_I30_IMON_FL" : { "U1_FL_XF.21" : {} } } } } } } } } } } } } }, "UNNAMED_3_LTM4675_I40_COMP0A_ND" : { "R108_ND_XF.2" : { "R108_ND_XF.1" : { "UNNAMED_3_LTM4675_I40_COMP0B_ND" : {} } }, "PM4_ND_XF.E6" : { "PM4_ND_XF.J6" : { "UNNAMED_3_LTM4675_I40_COMP0B_ND" : {} }, "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.D6" : { "UNNAMED_3_LTM4675_I40_COMP0B_ND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } } } } } }, "SDA_P0" : { "J1_P0_XF.A10" : {} }, "C1_DDR4_ODT<1>_XF" : { "J2_XF.91" : {}, "U1_XF.CC57" : {} }, "RGB_LED_GREEN<1>_CPLD" : { "U1_CPLD.F7" : {}, "R22_CPLD.2" : { "R22_CPLD.1" : { "UNNAMED_9_LUMEXRGBLED_I91_GREENK_CPLD" : { "D3_CPLD.4" : { "D3_CPLD.1" : { "CPLD_P3R3V" : {} }, "D3_CPLD.3" : { "UNNAMED_9_LUMEXRGBLED_I91_BLUEK_CPLD" : { "R23_CPLD.1" : { "R23_CPLD.2" : { "RGB_LED_BLUE<1>_CPLD" : { "U1_CPLD.C7" : {} } } } } }, "D3_CPLD.2" : { "UNNAMED_9_LUMEXRGBLED_I91_REDK_CPLD" : { "R21_CPLD.1" : { "R21_CPLD.2" : { "RGB_LED_RED<1>_CPLD" : { "U1_CPLD.D8" : {} } } } } } } } } } }, "C0_DDR4_CS_N<1>_XF" : { "J1_XF.89" : {}, "U1_XF.CA18" : {} }, "UNNAMED_4_RESISTOR_I8_A_MP" : { "U2_MP.6" : {}, "R13_MP.1" : { "R13_MP.2" : { "CPLD_P3R3V" : {} } }, "R12_MP.2" : { "R12_MP.1" : { "GND" : {} } } }, "C0_DDR4_DQ<23>_XF" : { "J1_XF.177" : {}, "U1_XF.BU15" : {} }, "PCIE1_TXN<0>_XF" : { "C49_XF.2" : { "C49_XF.1" : { "AC_PCIE1_TXN<0>_XF" : { "U1_XF.AM8" : {} } } }, "J1_P1_XF.B4" : {} }, "UNNAMED_9_LT3071_I66_V01_FL" : { "R110_FL_XF.2" : { "R110_FL_XF.1" : { "GND" : {} } }, "U11_FL_XF.24" : {}, "R106_FL_XF.1" : { "R106_FL_XF.2" : { "P3R3V" : {} } } }, "C0_DDR4_ADR<14>_XF" : { "J1_XF.228" : {}, "U1_XF.CC17" : {} }, "IMON_AVCC_LIN_XF" : { "R7_FL_XF.2" : { "R7_FL_XF.1" : { "UNNAMED_3_LT3071_I32_IMON_FL" : { "U3_FL_XF.21" : {} } } }, "R72_XF.1" : { "R72_XF.2" : { "UNNAMED_17_RESISTOR_I53_A_XF" : { "R73_XF.2" : { "R73_XF.1" : { "UNNAMED_17_RESISTOR_I188_B_XF" : { "R118_XF.2" : { "R118_XF.1" : { "GND" : {} } } } } }, "R82_XF.1" : { "R82_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_A_XF" : { "U1_XF.BY38" : {}, "C141_XF.1" : { "C141_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_B_XF" : { "R83_XF.2" : { "R83_XF.1" : { "UNNAMED_17_RESISTOR_I54_A_XF" : { "R74_XF.2" : { "R74_XF.1" : { "GND" : {} } }, "R75_XF.2" : { "R75_XF.1" : { "UNNAMED_17_RESISTOR_I187_B_XF" : { "R119_XF.2" : { "R119_XF.1" : { "GND" : {} } } } } } } } }, "U1_XF.CA38" : {} } } } } } } } } }, "R91_FL_XF.2" : { "R91_FL_XF.1" : { "UNNAMED_12_LT3071_I30_IMON_FL" : { "U10_FL_XF.21" : {} } } }, "R15_FL_XF.2" : { "R15_FL_XF.1" : { "UNNAMED_4_LT3071_I30_IMON_FL" : { "U6_FL_XF.21" : {} } } } }, "IMON_VCCAUX_LIN_XF" : { "R113_FL_XF.1" : { "R113_FL_XF.2" : { "UNNAMED_9_LT3071_I66_IMON_FL" : { "U11_FL_XF.21" : {}, "IMON_VCCAUX_B_TP_FL_XF.1" : {} } } }, "IMON_VCCAUX_TP_FL_XF.1" : {}, "R14_XF.1" : { "R14_XF.2" : { "UNNAMED_17_RESISTOR_I196_A_XF" : { "R25_XF.1" : { "R25_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I198_A_XF" : { "U1_XF.BW39" : {}, "C315_XF.1" : { "C315_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I198_B_XF" : { "R26_XF.2" : { "R26_XF.1" : { "UNNAMED_17_RESISTOR_I199_A_XF" : { "R21_XF.2" : { "R21_XF.1" : { "GND" : {} } }, "R23_XF.2" : { "R23_XF.1" : { "UNNAMED_17_RESISTOR_I202_A_XF" : { "R13_XF.2" : { "R13_XF.1" : { "GND" : {} } } } } } } } }, "U1_XF.BW40" : {} } } } } } }, "R17_XF.2" : { "R17_XF.1" : { "UNNAMED_17_RESISTOR_I201_A_XF" : { "R10_XF.2" : { "R10_XF.1" : { "GND" : {} } } } } } } } }, "R90_FL_XF.1" : { "R90_FL_XF.2" : { "UNNAMED_9_LT3071_I30_IMON_FL" : { "IMON_VCCAUX_A_TP_FL_XF.1" : {}, "U7_FL_XF.21" : {} } } } }, "UNNAMED_3_LTC2975_I168_WP_SP" : { "R37_SP_XF.2" : { "R37_SP_XF.1" : { "P3R3V" : {} } }, "U1_SP_XF.28" : {}, "R38_SP_XF.2" : { "R38_SP_XF.1" : { "GND" : {} } } }, "AVTT_RS_BNC_XF" : { "J10_XF.C" : {}, "R147_XF.2" : { "R147_XF.1" : { "PWR_AVTT_RS_XF" : {} } } }, "E1S0_PER_P<4>_XF" : { "U1_XF.J2" : {}, "J1_E0_XF.A31" : {} }, "CFGBVS_0_XF" : { "R36_XF.2" : { "R36_XF.1" : { "GND" : {} } }, "U1_XF.AM20" : {} }, "UNNAMED_3_LT3071_I32_V00_FL" : { "R72_FL_XF.2" : { "R72_FL_XF.1" : { "GND" : {} } }, "U3_FL_XF.23" : {}, "R13_FL_XF.1" : { "R13_FL_XF.2" : { "P3R3V" : {} } } }, "UNNAMED_9_598BICOLORLED_I16_L1A_CPLD" : { "D1_CPLD.3" : { "D1_CPLD.2" : { "STAT_LED_ON_F<0>_CPLD" : { "U1_CPLD.A3" : {} } }, "D1_CPLD.4" : { "STAT_LED_ON_F<1>_CPLD" : { "U1_CPLD.E7" : {} } }, "D1_CPLD.1" : { "UNNAMED_9_598BICOLORLED_I16_L2A_CPLD" : { "R119_CPLD.1" : { "R119_CPLD.2" : { "CPLD_P3R3V" : {} } } } } }, "R118_CPLD.1" : { "R118_CPLD.2" : { "CPLD_P3R3V" : {} } } }, "E1S2_PET_N<4>_XF" : { "C169_XF.2" : { "C169_XF.1" : { "AC_E1S2_PET_N<4>_XF" : { "U1_XF.AC10" : {} } } }, "J1_E2_XF.B30" : {} }, "C0_DDR4_DQ<17>_XF" : { "U1_XF.BT16" : {}, "J1_XF.172" : {} }, "UNNAMED_10_LTM4650FIXED_I151_PGOOD2_SP" : { "R31_SP_XF.1" : { "R31_SP_XF.2" : { "POK_OD_VCCINT_BLSW_P<1>" : { "U1_CPLD.T11" : {} } } }, "PM3_SP_XF.G8" : { "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } } } }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G3" : { "GND" : {} } } }, "C0_DDR4_CS_N<0>_XF" : { "J1_XF.84" : {}, "U1_XF.CB18" : {} }, "UNNAMED_3_DIODESOD923F_I70_A_ND" : { "PM4_ND_XF.E2" : { "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } } } }, "NC_TR_2_SP" : {}, "OCL3_PER_P<0>_XF" : { "J1_O3_XF.A3" : {}, "U1_XF.BJ6" : {} }, "AC_OCL1_PET_P<1>_XF" : { "U1_XF.BY9" : {}, "C183_XF.1" : { "C183_XF.2" : { "OCL1_PET_P<1>_XF" : { "J1_O1_XF.B6" : {} } } } }, "UNNAMED_3_BYPASSCAPNPOL_I7_B_MP" : { "U1_MP.11" : {}, "U1_MP.12" : {}, "C3_MP.2" : { "C3_MP.1" : { "UNNAMED_3_BYPASSCAPNPOL_I7_A_MP" : { "U1_MP.13" : {} } } }, "U1_MP.10" : {}, "L1_MP.1" : { "L1_MP.2" : { "CPLD_P1R8V_1" : {} } } }, "VDDO9" : { "U1.57" : {}, "R17.2" : { "R17.1" : { "CPLD_P1R8V_1" : {} } }, "C19.1" : { "C19.2" : { "GND" : {} } } }, "UNNAMED_3_LED_I24_A_MP" : { "R2_MP.2" : { "R2_MP.1" : { "P5VSB" : {} } }, "CPLD_P1R8V_FLT_MP.2" : { "CPLD_P1R8V_FLT_MP.1" : { "UNNAMED_3_LED_I24_C_MP" : { "U1_MP.14" : {} } } } }, "VS_AVCC_LIN_P_XF" : { "U3_FL_XF.19" : {}, "R34_SP_XF.2" : { "R34_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I152_A_SP" : { "U1_SP_XF.61" : {}, "C17_SP_XF.1" : { "C17_SP_XF.2" : { "GND" : {} } } } } }, "NS2_FL_XF.2" : { "NS2_FL_XF.1" : { "PWR_AVCC_RS_RLC_XF" : {} } } }, "UNNAMED_9_LT3071_I66_VIOC_FL" : { "C101_FL_XF.1" : { "C101_FL_XF.2" : { "GND" : {} } }, "U11_FL_XF.1" : {} }, "C1_DDR4_DQ<70>_XF" : { "J2_XF.54" : {}, "U1_XF.BT58" : {} }, "UNNAMED_4_PI6CB33401_I37_SADRTRI_E0" : { "R12_E0_XF.2" : { "R12_E0_XF.1" : { "GND" : {} } }, "U1_E0_XF.32" : {} }, "E1S1_PER_N<0>_XF" : { "J1_E1_XF.A17" : {}, "U1_XF.P3" : {} }, "UNNAMED_6_LTM4671_I456_PHMODE3_SP" : { "R88_SP_XF.1" : { "R88_SP_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I402_B_SP" : { "R94_SP_XF.2" : { "R94_SP_XF.1" : { "UNNAMED_6_LTM4671_I456_MODECLKIN3_SP" : { "PM2_SP_XF.R8" : { "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.R6" : { "UNNAMED_6_LTM4671_I456_PHMODE3_SP" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.R11" : { "UNNAMED_6_BYPASSCAPNPOL_I402_B_SP" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} } } } } }, "C83_SP_XF.2" : { "C83_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } } }, "C0_DDR4_DQ<30>_XF" : { "U1_XF.BR23" : {}, "J1_XF.43" : {} }, "E1S2_PET_N<0>_XF" : { "C173_XF.2" : { "C173_XF.1" : { "AC_E1S2_PET_N<0>_XF" : { "U1_XF.W10" : {} } } }, "J1_E2_XF.B17" : {} }, "C2_RDIMM_DQS_T<1>_XF" : { "J3_XF.164" : {}, "U1_XF.P46" : {} }, "C1_DDR4_DQ<38>_XF" : { "J2_XF.102" : {}, "U1_XF.BT61" : {} }, "SCL_P0" : { "J1_P0_XF.A9" : {} }, "UNNAMED_4_MAX116XXQSOP16_I97_AIN0" : { "U11.5" : {}, "R48.1" : { "R48.2" : { "VMON_VCCAUX_SW" : { "R121_SP_XF.2" : { "R121_SP_XF.1" : { "PWR_VCCAUX_SW_XF" : {} } } } } }, "C49.1" : { "C49.2" : { "GND" : {} } }, "R36.1" : { "R36.2" : { "GND" : {} } } }, "CFG_FLASH_D03_0_XF" : { "U3_XF.D4" : {}, "U1_XF.AP19" : {}, "R64_XF.2" : { "R64_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U2_XF.D4" : {} }, "FPGA_CPLD_RSVD<1>_1" : { "U1_CPLD.A10" : {}, "U1_XF.BT33" : {} }, "UNNAMED_6_LTM4671_I456_MODECLKIN3_SP" : { "R94_SP_XF.1" : { "R94_SP_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I402_B_SP" : { "R85_SP_XF.2" : { "R85_SP_XF.1" : { "UNNAMED_6_RESISTOR_I441_A_SP" : { "PM2_SP_XF.P8" : { "PM2_SP_XF.E10" : { "UNNAMED_6_LTM4671_I456_MODECLKIN3_SP" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R8" : { "UNNAMED_6_LTM4671_I456_MODECLKIN3_SP" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R11" : { "UNNAMED_6_BYPASSCAPNPOL_I402_B_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} } }, "R83_SP_XF.2" : { "R83_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "C83_SP_XF.2" : { "C83_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } } }, "UNNAMED_10_CAPACITOR_I11_A_SP" : { "R10_SP_XF.1" : { "R10_SP_XF.2" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} } } } } } }, "E1S2_3R3V_SMB_RST_F_XF" : { "U1_XF.R19" : {}, "J1_E2_XF.A9" : {}, "R5_E2_XF.2" : { "R5_E2_XF.1" : { "P3R3V" : {} } } }, "NC" : {}, "E1S1_PER_N<4>_XF" : { "U1_XF.V3" : {}, "J1_E1_XF.A30" : {} }, "AC_PCIE_X1_TXP_XF" : { "C290_XF.1" : { "C290_XF.2" : { "PCIE_X1_TXP_XF" : { "J1_PX1_XF.A16" : {} } } }, "U1_XF.BF9" : {} }, "UNNAMED_29_PI6CB33401_I63_BWSELTRI_XF" : { "R90_XF.2" : { "R90_XF.1" : { "GND" : {} } }, "U5_XF.1" : {} }, "JT_CPLD_TDI" : { "U3_CPLD.1" : {}, "R67.2" : { "R67.1" : { "GND" : {} } }, "J5.15" : {} }, "UNNAMED_4_LTM4650FIXED_I78_RUN1_SP" : { "PM4_SP_XF.F5" : { "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} } } }, "UNNAMED_20_FERRITEBEAD_I59_B" : { "FB1.2" : { "FB1.1" : { "P12V_MAIN" : {} } }, "P1.2" : {} }, "CONN_CLK_REFP<0>_E2" : { "J1_E2_XF.B15" : {}, "C21_E2_XF.2" : { "C21_E2_XF.1" : { "AC_CONN_CLK_REFP<0>_3" : { "U1_E2_XF.13" : {} } } } }, "AC_E1S2_PET_N<4>_XF" : { "C169_XF.1" : { "C169_XF.2" : { "E1S2_PET_N<4>_XF" : { "J1_E2_XF.B30" : {} } } }, "U1_XF.AC10" : {} }, "C0_DDR4_DQ<54>_XF" : { "J1_XF.124" : {}, "U1_XF.BJ22" : {} }, "FPGA_CPLD_RSVD<0>_1" : { "U1_XF.BT30" : {}, "U1_CPLD.F8" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I51_B_SP" : { "U1_SP_XF.40" : {}, "C64_SP_XF.2" : { "C64_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I51_A_SP" : { "U1_SP_XF.38" : {} } } } }, "PCIE1_RXN<4>_XF" : { "U1_XF.AR5" : {}, "J2_P1_XF.A4" : {} }, "C1_DDR4_DQ<68>_XF" : { "U1_XF.BU58" : {}, "J2_XF.47" : {} }, "UNNAMED_3_LT3071_I32_MARGA_FL" : { "U3_FL_XF.22" : {}, "R12_FL_XF.2" : { "R12_FL_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I31_B_FL" : { "R11_FL_XF.2" : { "R11_FL_XF.1" : { "DAC_AVCC_LIN_XF" : { "R93_FL_XF.1" : { "R93_FL_XF.2" : { "UNNAMED_12_BYPASSCAPNPOL_I23_B_FL" : { "C94_FL_XF.2" : { "C94_FL_XF.1" : { "GND" : {} } }, "R94_FL_XF.1" : { "R94_FL_XF.2" : { "UNNAMED_12_LT3071_I30_MARGA_FL" : { "U10_FL_XF.22" : {} } } } } } }, "U1_SP_XF.57" : {}, "R21_FL_XF.1" : { "R21_FL_XF.2" : { "UNNAMED_4_BYPASSCAPNPOL_I23_B_FL" : { "C5_FL_XF.2" : { "C5_FL_XF.1" : { "GND" : {} } }, "R22_FL_XF.1" : { "R22_FL_XF.2" : { "UNNAMED_4_LT3071_I30_MARGA_FL" : { "U6_FL_XF.22" : {} } } } } } } } } }, "C66_FL_XF.2" : { "C66_FL_XF.1" : { "GND" : {} } } } } } }, "AC_CONN_CLK_REFN<0>_2" : { "C25_E3_XF.1" : { "C25_E3_XF.2" : { "CONN_CLK_REFN<0>_E3" : { "J1_E3_XF.B14" : {} } } }, "U1_E3_XF.14" : {} }, "UNNAMED_13_NMOSFETVMT3_I33_G" : { "Q3.1" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.3" : { "BASE_3R3V_SCL_2" : { "Q1.3" : { "Q1.2" : { "FPGA_1R8V_SCL" : { "R33.1" : { "R33.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q1.1" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "R32.2" : { "R32.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R31.1" : { "R31.2" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "Q2.1" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "U1_XF.BW29" : {}, "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.3" : { "BASE_3R3V_SDA_2" : { "J1_XF.285" : {}, "J4_XF.285" : {}, "U1_CPLD.C9" : {}, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "Q4.3" : { "Q4.1" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "R5.2" : { "R5.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R3.1" : { "R3.2" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : {} } }, "R6.2" : { "R6.1" : { "CPLD_P1R8V_1" : {} } } } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R120.1" : { "R120.2" : { "CPLD_P1R8V_1" : {} } }, "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } }, "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "J5.6" : {}, "J3_XF.285" : {}, "PM4_ND_XF.D4" : { "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.C1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.D9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : {} }, "PM4_ND_XF.J9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.D8" : { "NC" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.B1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.A1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.F9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.H5" : { "NC" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.M9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.F7" : { "NC" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.E5" : { "CKI_LTM4675_ND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.L9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.E3" : { "NDIMM_LTM4675_ALERT_OD_F_1" : { "U1_CPLD.M6" : {} } }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.G7" : { "NC" : {} }, "PM4_ND_XF.E8" : { "NC" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.G2" : { "NDIMM_I2C_ASEL_RESISTOR_XF" : {} }, "PM4_ND_XF.K1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.B8" : { "SW0_NODE_ND" : {} }, "PM4_ND_XF.D1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.J5" : { "NC" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.J1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.J4" : { "NC" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.H7" : { "NC" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.L1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.M1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.B9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} } }, "J2_XF.285" : {} } } } } } } } } } } } }, "R34.2" : { "R34.1" : { "P3R3V" : {} } }, "U11.13" : {}, "U12.6" : {}, "U1_CPLD.A9" : {} } } } }, "OCL1_FPGA_REFCLK_P_XF" : { "R221_XF.1" : { "R221_XF.2" : { "GND" : {} } }, "R212_XF.2" : { "R212_XF.1" : { "P3R3V" : {} } }, "R222_XF.1" : { "R222_XF.2" : { "OCL1_FPGA_REFCLK_N_XF" : {} } }, "C353_XF.2" : { "C353_XF.1" : { "AC_OCL1_FPGA_REFCLK_P_XF" : { "U7_XF.27" : {} } } }, "U1_XF.BT13" : {} }, "C0_DDR4_ADR<5>_XF" : { "U1_XF.BW17" : {}, "J1_XF.213" : {} }, "C2_RDIMM_DQS_T<0>_XF" : { "U1_XF.V47" : {}, "J3_XF.153" : {} }, "STAT_LED_ON_F<1>_CPLD" : { "U1_CPLD.E7" : {}, "D1_CPLD.4" : { "D1_CPLD.2" : { "STAT_LED_ON_F<0>_CPLD" : { "U1_CPLD.A3" : {} } }, "D1_CPLD.3" : { "UNNAMED_9_598BICOLORLED_I16_L1A_CPLD" : { "R118_CPLD.1" : { "R118_CPLD.2" : { "CPLD_P3R3V" : {} } } } }, "D1_CPLD.1" : { "UNNAMED_9_598BICOLORLED_I16_L2A_CPLD" : { "R119_CPLD.1" : { "R119_CPLD.2" : { "CPLD_P3R3V" : {} } } } } } }, "C1_RDIMM_DQS_T<17>_XF" : { "J2_XF.51" : {}, "U1_XF.BR57" : {} }, "C0_DDR4_DQ<60>_XF" : { "J1_XF.128" : {}, "U1_XF.BK27" : {} }, "E1S0_PER_P<0>_XF" : { "J1_E0_XF.A18" : {}, "U1_XF.F4" : {} }, "CONN_CLK_REFP<0>_E0" : { "C21_E0_XF.2" : { "C21_E0_XF.1" : { "AC_CONN_CLK_REFP<0>_1" : { "U1_E0_XF.13" : {} } } }, "J1_E0_XF.B15" : {} }, "E1S2_3R3V_PRSNT_F<1>_XF" : { "U1_XF.M20" : {}, "J1_E2_XF.B42" : {} }, "CONN_CLK_REFP<1>_E1" : { "J1_E1_XF.A15" : {}, "C20_E1_XF.2" : { "C20_E1_XF.1" : { "AC_CONN_CLK_REFP<1>" : { "U1_E1_XF.17" : {} } } } }, "PCIE1_REFN_XF" : { "R2_P1_XF.2" : { "R2_P1_XF.1" : { "UNNAMED_3_OCULINKX4CONN_I86_REFCLKN_P1" : { "J1_P1_XF.B13" : {} } } }, "C231_XF.1" : { "C231_XF.2" : { "AC_PCIE1_REFN_XF" : { "U1_XF.AU14" : {} } } } }, "UNNAMED_3_RESISTOR_I33_A_MP" : { "R16_MP.2" : { "R16_MP.1" : { "GND" : {} } }, "R15_MP.1" : { "R15_MP.2" : { "P5VSB" : {} } }, "U1_MP.15" : {} }, "C3_DDR4_DQ<40>_XF" : { "J4_XF.108" : {}, "U1_XF.C24" : {} }, "UNNAMED_17_RESISTOR_I60_A_XF" : { "R81_XF.1" : { "R81_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I57_B_XF" : { "U1_XF.CC37" : {}, "C140_XF.2" : { "C140_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I57_A_XF" : { "U1_XF.CC36" : {}, "R80_XF.2" : { "R80_XF.1" : { "UNNAMED_17_RESISTOR_I59_A_XF" : { "R111_XF.2" : { "R111_XF.1" : { "GND" : {} } }, "R110_XF.2" : { "R110_XF.1" : { "VMON_AVTT_RLC_LIN_XF" : { "R56_FL_XF.2" : { "R56_FL_XF.1" : { "VS_AVTT_RLC_LIN_FL" : { "NS3_FL_XF.2" : { "NS3_FL_XF.1" : { "PWR_AVTT_RLC_XF" : {} } }, "U1_FL_XF.19" : {} } } } } } } } } } } } } } } }, "R112_XF.2" : { "R112_XF.1" : { "GND" : {} } }, "R113_XF.2" : { "R113_XF.1" : { "GND" : {} } } }, "OCL3_PET_P<1>_XF" : { "J1_O3_XF.B6" : {}, "C256_XF.2" : { "C256_XF.1" : { "AC_OCL3_PET_P<1>_XF" : { "U1_XF.BH9" : {} } } } }, "UNNAMED_4_LTM4650FIXED_I78_PGOOD1_SP" : { "PM4_SP_XF.G9" : { "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} } } }, "UNNAMED_6_BYPASSCAPNPOL_I465_B_SP" : { "PM2_SP_XF.K9" : { "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : {} } } } }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} } } }, "C0_DDR4_DQ<12>_XF" : { "J1_XF.14" : {}, "U1_XF.CC26" : {} }, "E1S1_PET_N<1>_XF" : { "C136_XF.2" : { "C136_XF.1" : { "AC_E1S1_PET_N<1>_XF" : { "U1_XF.N10" : {} } } }, "J1_E1_XF.B20" : {} }, "DDR4_SYS_CLK_N<2>_XF" : { "C365_XF.1" : { "C365_XF.2" : { "C2_SYS_CLK_N_XF" : { "R252_XF.1" : { "R252_XF.2" : { "GND" : {} } }, "R248_XF.2" : { "R248_XF.1" : { "PWR_NDIMM_VDD_XF" : {} } }, "U1_XF.J60" : {} } } }, "U6_XF.11" : {} }, "C1_DDR4_DQ<21>_XF" : { "U1_XF.BV54" : {}, "J2_XF.170" : {} }, "AC_E1S3_PET_P<5>_XF" : { "C327_XF.1" : { "C327_XF.2" : { "E1S3_PET_P<5>_XF" : { "J1_E3_XF.B34" : {} } } }, "U1_XF.AK13" : {} }, "VS_VCCAUX_LIN_N_XF" : { "NS14_FL_XF.2" : { "NS14_FL_XF.1" : { "GND" : {} } }, "R23_SP_XF.2" : { "R23_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I155_A_SP" : { "U1_SP_XF.64" : {}, "C14_SP_XF.1" : { "C14_SP_XF.2" : { "GND" : {} } } } } } }, "C2_DDR4_DQ<16>_XF" : { "J3_XF.27" : {}, "U1_XF.E63" : {} }, "FSET_4650_BL_SP" : { "R26_SP_XF.2" : { "R26_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "PM3_SP_XF.C6" : { "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} } } } }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G3" : { "GND" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} } } }, "UNNAMED_21_RESISTOR_I29_B_XF" : { "U1_XF.M53" : {}, "R47_XF.2" : { "R47_XF.1" : { "GND" : {} } } }, "UNNAMED_7_LT3071_I30_EN_FL" : { "U4_FL_XF.28" : {}, "R32_FL_XF.1" : { "R32_FL_XF.2" : { "P3R3V" : {} } } }, "C2_DDR4_DQ<29>_XF" : { "U1_XF.J52" : {}, "J3_XF.181" : {} }, "C2_DDR4_ACT_N_XF" : { "U1_XF.L57" : {}, "J3_XF.62" : {} }, "OCL3_3R3V_CPRSNT_F_XF" : { "U1_XF.BB18" : {}, "J1_O3_XF.A13" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I48_A_XF" : { "U1_XF.AM25" : {}, "C138_XF.1" : { "C138_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I48_B_XF" : { "R77_XF.2" : { "R77_XF.1" : { "UNNAMED_17_RESISTOR_I52_A_XF" : { "R3_XF.2" : { "R3_XF.1" : { "GND" : {} } }, "R4_XF.2" : { "R4_XF.1" : { "GND" : {} } } } } }, "U1_XF.AN24" : {} } } }, "R76_XF.2" : { "R76_XF.1" : { "UNNAMED_17_RESISTOR_I51_A_XF" : { "R2_XF.2" : { "R2_XF.1" : { "GND" : {} } }, "R1_XF.2" : { "R1_XF.1" : { "VMON_AVCC_RN_LIN_XF" : { "R84_FL_XF.2" : { "R84_FL_XF.1" : { "VS_AVCC_RN_LIN_FL" : { "U6_FL_XF.19" : {}, "NS4_FL_XF.2" : { "NS4_FL_XF.1" : { "PWR_AVCC_RN_XF" : {} } } } } } } } } } } } }, "POR_OVERRIDE_XF" : { "U1_XF.AK19" : {}, "R7_XF.2" : { "R7_XF.1" : { "GND" : {} } }, "R16_XF.2" : { "R16_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } } }, "E1S3_3R3V_PRSNT_F<0>_XF" : { "R8_E3_XF.2" : { "R8_E3_XF.1" : { "P3R3V" : {} } }, "J1_E3_XF.A12" : {}, "U1_XF.T17" : {} }, "C1_DDR4_SA<1>_XF" : { "J2_XF.140" : {}, "R263_XF.2" : { "R263_XF.1" : { "P3R3V" : {} } } }, "C1_DDR4_ADR<6>_XF" : { "U1_XF.BW49" : {}, "J2_XF.69" : {} }, "NC_TL_2_SP" : {}, "PCIE0_RXP<3>_XF" : { "J1_P0_XF.A18" : {}, "U1_XF.AY4" : {} }, "PRSNT_F_P0" : { "J2_P0_XF.A13" : {}, "J1_P0_XF.A13" : {} }, "E1S1_PET_N<7>_XF" : { "J1_E1_XF.B39" : {}, "C130_XF.2" : { "C130_XF.1" : { "AC_E1S1_PET_N<7>_XF" : { "U1_XF.R6" : {} } } } }, "UNNAMED_7_BYPASSCAPNPOL_I64_B_SP" : { "PM1_SP_XF.K9" : { "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} 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{} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" 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"PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} } } }, "UNNAMED_10_RESISTOR_I75_A_FL" : { "R86_FL_XF.1" : { "R86_FL_XF.2" : { "PWR_RN_RUC_MGTVCCAUX_XF" : {} } }, "C84_FL_XF.1" : { "C84_FL_XF.2" : { "PWR_RN_RUC_MGTVCCAUX_XF" : {} } }, "R87_FL_XF.1" : { "R87_FL_XF.2" : { "GND" : {} } }, "U8_FL_XF.3" : {} }, "C3_RDIMM_DQS_C<9>_XF" : { "U1_XF.K15" : {}, "J4_XF.8" : {} }, "SCL_P1" : { "J1_P1_XF.A9" : {} }, "RFU_<2>_E2" : { "J1_E2_XF.B8" : {} }, "C3_RDIMM_DQS_T<11>_XF" : { "J4_XF.29" : {}, "U1_XF.E28" : {} }, "PCIE_X1_REFP_XF" : { "C101_XF.1" : { "C101_XF.2" : { "AC_PCIE_X1_REFP_XF" : { "U1_XF.BG15" : {} } } }, "J1_PX1_XF.A13" : {} }, "UNNAMED_7_LTM4671_I87_MODECLKIN0_SP" : { "R115_SP_XF.1" : { "R115_SP_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I44_B_SP" : { "R113_SP_XF.2" : { "R113_SP_XF.1" : { "UNNAMED_7_LTM4671_I87_PHMODE0_SP" : { "PM1_SP_XF.E6" : { "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.G11" : { "UNNAMED_7_LTM4671_I87_MODECLKIN0_SP" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" 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"PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : {} } } } } }, "U11.13" : {} } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {}, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} } }, "R101_SP_XF.2" : { "R101_SP_XF.1" : { "PM1_SP_AGND_SP" : {} } } } } } } } } }, "E1S2_FPGA_REFCLK_P<1>_XF" : { "R195_XF.1" : { "R195_XF.2" : { "E1S2_FPGA_REFCLK_N<1>_XF" : {} } }, "U1_XF.AA15" : {}, "R194_XF.1" : { "R194_XF.2" : { "GND" : {} } }, "R186_XF.2" : { "R186_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "C18_E2_XF.2" : { "C18_E2_XF.1" : { "AC_FPGA_CLK_REF_P<1>_3" : { "U1_E2_XF.27" : {} } } } }, "OCL2_PER_P<3>_XF" : { "J1_O2_XF.A18" : {}, "U1_XF.BK4" : {} }, "VMON_RN_RUC_MGTVCCAUX" : { "R83_FL_XF.2" : { "R83_FL_XF.1" : { "PWR_RN_RUC_MGTVCCAUX_XF" : {} } }, "R46.2" : { "R46.1" : { "UNNAMED_4_MAX116XXQSOP16_I97_AIN2" : { "R28.1" : { "R28.2" : { "GND" : {} } }, "C47.1" : { "C47.2" : { "GND" : {} } }, "U11.7" : {} } } } }, "C3_DDR4_DQ<6>_XF" : { "U1_XF.J17" : {}, "J4_XF.10" : {} }, "FP_JT_VREF" : { "C15.2" : { "C15.1" : { "GND" : {} } }, "J5.17" : {}, "R41.2" : { "R41.1" : { "CPLD_P1R8V_1" : {} } } }, "OCL0_PET_N<3>_XF" : { "J1_O0_XF.B19" : {}, "C258_XF.2" : { "C258_XF.1" : { "AC_OCL0_PET_N<3>_XF" : { "U1_XF.CA10" : {} } } } }, "PWR_NDIMM_VTT_XF" : { "C37_ND_XF.1" : { "C37_ND_XF.2" : { "GND" : {} } }, "J3_XF.221" : {}, "J3_XF.77" : {}, "U2_ND_XF.3" : {}, "C44_ND_XF.1" : { "C44_ND_XF.2" : { "GND" : {} } }, "J4_XF.77" : {}, "R92_XF.1" : { "R92_XF.2" : { "NDIMM_VTT_BNC_XF" : { "J6_XF.C" : {} } } }, "J4_XF.221" : {}, "C36_ND_XF.1" : { "C36_ND_XF.2" : { "GND" : {} } }, "C38_ND_XF.1" : { "C38_ND_XF.2" : { "GND" : {} } }, "NS3_ND_XF.1" : { "NS3_ND_XF.2" : { "VS_DIMM_VTT_LIN_ND" : {} } } }, "AC_E1S1_PET_N<0>_XF" : { "U1_XF.P8" : {}, "C137_XF.1" : { "C137_XF.2" : { "E1S1_PET_N<0>_XF" : { "J1_E1_XF.B17" : {} } } } }, "UNNAMED_4_PI6CB33401_I37_OE2F_E1" : { "R2_E1_XF.2" : { "R2_E1_XF.1" : { "GND" : {} } }, "U1_E1_XF.29" : {}, "U1_E1_XF.24" : {} }, "C0_DDR4_DQ<8>_XF" : { "U1_XF.CC28" : {}, "J1_XF.16" : {} }, "C3_DDR4_DQ<3>_XF" : { "U1_XF.K19" : {}, "J4_XF.157" : {} }, "C1_DDR4_DQ<9>_XF" : { "J2_XF.161" : {}, "U1_XF.BT53" : {} }, "OCL0_CONN_REFCLK_N_XF" : { "C384_XF.2" : { "C384_XF.1" : { "AC_OCL0_CONN_REFCLK_N_XF" : { "U7_XF.14" : {} } } }, "J1_O0_XF.B13" : {} }, "CONN_CLK_REFP<1>_E3" : { "C20_E3_XF.2" : { "C20_E3_XF.1" : { "AC_CONN_CLK_REFP<1>_2" : { "U1_E3_XF.17" : {} } } }, "J1_E3_XF.A15" : {} }, "C0_DDR4_DQ<14>_XF" : { "U1_XF.CA26" : {}, "J1_XF.21" : {} }, "PCIE0_RESET_3V_F" : { "J1_P0_XF.A12" : {}, "U1_CPLD.F14" : {} }, "INTVCC_4650_TL_SP" : { "PM4_SP_XF.H8" : { "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G9" : { "UNNAMED_4_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} } }, "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } }, "UNNAMED_7_LTM4671_I87_COMP0A_SP" : { "PM1_SP_XF.H10" : { "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {} } }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} } } }, "C0_RDIMM_DQS_T<3>_XF" : { "U1_XF.BT23" : {}, "J1_XF.186" : {} }, "UNNAMED_3_LTC2975_I168_FAULT0F_SP" : { "U1_SP_XF.25" : {}, "R119_SP_XF.2" : { "R119_SP_XF.1" : { "P3R3V" : {} } } }, "UNNAMED_21_RESISTOR_I25_B_XF" : { "U1_XF.T47" : {}, "R115_XF.2" : { "R115_XF.1" : { "GND" : {} } } }, "PCIE0_RXN<7>_XF" : { "J2_P0_XF.A19" : {}, "U1_XF.BC1" : {} }, "C1_DDR4_DQ<37>_XF" : { "U1_XF.BU63" : {}, "J2_XF.240" : {} }, "C1_RDIMM_DQS_T<13>_XF" : { "U1_XF.BV61" : {}, "J2_XF.99" : {} }, "AC_E1S2_PET_P<3>_XF" : { "C152_XF.1" : { "C152_XF.2" : { "E1S2_PET_P<3>_XF" : { "J1_E2_XF.B27" : {} } } }, "U1_XF.U11" : {} }, "UNNAMED_9_LED_I13_A_CPLD" : { "R116_CPLD.1" : { "R116_CPLD.2" : { "CPLD_P3R3V" : {} } }, "D5_CPLD.2" : { "D5_CPLD.1" : { "STAT_LED_ON_F<3>_CPLD" : { "U1_CPLD.D7" : {} } } } }, "UNNAMED_8_LT3071_I30_V00_FL" : { "R17_FL_XF.2" : { "R17_FL_XF.1" : { "GND" : {} } }, "R54_FL_XF.1" : { "R54_FL_XF.2" : { "P3R3V" : {} } }, "U5_FL_XF.23" : {} }, "C1_DDR4_DQ<49>_XF" : { "J2_XF.264" : {}, "U1_XF.BM58" : {} }, "C2_DDR4_BG<1>_XF" : { "U1_XF.M55" : {}, "J3_XF.207" : {} }, "OCL0_3R3V_CWAKE_F_XF" : { "U1_XF.BM18" : {}, "J1_O0_XF.B10" : {} }, "E1S3_FPGA_REFCLK_N<1>_XF" : { "U1_XF.AN14" : {}, "R191_XF.2" : { "R191_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R201_XF.2" : { "R201_XF.1" : { "E1S3_FPGA_REFCLK_P<1>_XF" : {} } }, "R202_XF.1" : { "R202_XF.2" : { "GND" : {} } }, "C22_E3_XF.2" : { "C22_E3_XF.1" : { "AC_FPGA_CLK_REF_N<1>_2" : { "U1_E3_XF.28" : {} } } } }, "BASE_1R8V_SCL" : { "Q3.2" : { "Q3.3" : { "BASE_3R3V_SCL_2" : { "U11.13" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.2" : { "FPGA_1R8V_SCL" : { "R33.1" : { "R33.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } }, "U1.16" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I156_A_SP" : { "R22_SP_XF.1" : { "R22_SP_XF.2" : { "VS_VCCINT_P_SP" : { "PM4_SP_XF.E8" : { "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } } } }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} } } } } } }, "PCIE1_TXN<1>_XF" : { "C48_XF.2" : { "C48_XF.1" : { "AC_PCIE1_TXN<1>_XF" : { "U1_XF.AM12" : {} } } }, "J1_P1_XF.B7" : {} }, "C0_DDR4_DQ<52>_XF" : { "J1_XF.117" : {}, "U1_XF.BK23" : {} }, "AC_OCL3_PET_N<0>_XF" : { "C281_XF.1" : { "C281_XF.2" : { "OCL3_PET_N<0>_XF" : { "J1_O3_XF.B4" : {} } } }, "U1_XF.BJ10" : {} }, "E1S1_PET_N<5>_XF" : { "J1_E1_XF.B33" : {}, "C132_XF.2" : { "C132_XF.1" : { "AC_E1S1_PET_N<5>_XF" : { "U1_XF.T8" : {} } } } }, "C2_DDR4_DQ<56>_XF" : { "U1_XF.L51" : {}, "J3_XF.130" : {} }, "BP_TYPE_P0" : { "J1_P0_XF.B9" : {} }, "OCL1_PER_N<2>_XF" : { "U1_XF.BT3" : {}, "J1_O1_XF.A16" : {} }, "AC_PCIE0_TXP<5>_XF" : { "C36_XF.1" : { "C36_XF.2" : { "PCIE0_TXP<5>_XF" : { "J2_P0_XF.B6" : {} } } }, "U1_XF.BA11" : {} }, "PCIE0_TXP<5>_XF" : { "J2_P0_XF.B6" : {}, "C36_XF.2" : { "C36_XF.1" : { "AC_PCIE0_TXP<5>_XF" : { "U1_XF.BA11" : {} } } } }, "C0_DDR4_DQ<4>_XF" : { "J1_XF.3" : {}, "U1_XF.CB24" : {} }, "E1S3_PER_P<2>_XF" : { "U1_XF.AH4" : {}, "J1_E3_XF.A24" : {} }, "UNNAMED_9_LT3071_I30_IMON_FL" : { "R90_FL_XF.2" : { "R90_FL_XF.1" : { "IMON_VCCAUX_LIN_XF" : { "R113_FL_XF.1" : { "R113_FL_XF.2" : { "UNNAMED_9_LT3071_I66_IMON_FL" : { "IMON_VCCAUX_B_TP_FL_XF.1" : {}, "U11_FL_XF.21" : {} } } }, "R14_XF.1" : { "R14_XF.2" : { "UNNAMED_17_RESISTOR_I196_A_XF" : { "R17_XF.2" : { "R17_XF.1" : { "UNNAMED_17_RESISTOR_I201_A_XF" : { "R10_XF.2" : { "R10_XF.1" : { "GND" : {} } } } } }, "R25_XF.1" : { "R25_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I198_A_XF" : { "C315_XF.1" : { "C315_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I198_B_XF" : { "R26_XF.2" : { "R26_XF.1" : { "UNNAMED_17_RESISTOR_I199_A_XF" : { "R21_XF.2" : { "R21_XF.1" : { "GND" : {} } }, "R23_XF.2" : { "R23_XF.1" : { "UNNAMED_17_RESISTOR_I202_A_XF" : { "R13_XF.2" : { "R13_XF.1" : { "GND" : {} } } } } } } } }, "U1_XF.BW40" : {} } } }, "U1_XF.BW39" : {} } } } } } }, "IMON_VCCAUX_TP_FL_XF.1" : {} } } }, "IMON_VCCAUX_A_TP_FL_XF.1" : {}, "U7_FL_XF.21" : {} }, "C0_RDIMM_DQS_C<16>_XF" : { "U1_XF.BH28" : {}, "J1_XF.133" : {} }, "UNNAMED_11_LTM4650FIXED_I150_CLKOUT_SP" : { "PM7_SP_XF.G5" : { "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.G3" : { "GND" : {} } } }, "UNNAMED_7_LTM4671_I37_FB1_SP" : { "PM1_SP_XF.H9" : { "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {}, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} } } }, "PCIE1_RXP<6>_XF" : { "J2_P1_XF.A15" : {}, "U1_XF.AU2" : {} }, "C3_DDR4_CK_C<0>_XF" : { "J4_XF.75" : {}, "U1_XF.N26" : {} }, "AC_OCL0_PET_P<3>_XF" : { "C176_XF.1" : { "C176_XF.2" : { "OCL0_PET_P<3>_XF" : { "J1_O0_XF.B18" : {} } } }, "U1_XF.CA11" : {} }, "C2_DDR4_DQ<41>_XF" : { "J3_XF.253" : {}, "U1_XF.A53" : {} }, "VS_AVTT_RS_LIN_FL" : { "U2_FL_XF.19" : {}, "R4_FL_XF.1" : { "R4_FL_XF.2" : { "VMON_AVTT_RS_LIN_XF" : { "R93_XF.2" : { "R93_XF.1" : { "UNNAMED_17_RESISTOR_I40_A_XF" : { "R99_XF.2" : { "R99_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I46_A_XF" : { "C147_XF.1" : { "C147_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I46_B_XF" : { "R100_XF.1" : { "R100_XF.2" : { "UNNAMED_17_RESISTOR_I41_A_XF" : { "R95_XF.1" : { "R95_XF.2" : { "GND" : {} } }, "R96_XF.1" : { "R96_XF.2" : { "GND" : {} } } } } }, "U1_XF.CA33" : {} } } }, "U1_XF.BY33" : {} } } }, "R94_XF.1" : { "R94_XF.2" : { "GND" : {} } } } } }, "R137_XF.2" : { "R137_XF.1" : { "UNNAMED_17_RESISTOR_I110_A_XF" : { "R138_XF.1" : { "R138_XF.2" : { "GND" : {} } }, "R129_XF.2" : { "R129_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I116_A_XF" : { "C268_XF.1" : { "C268_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I116_B_XF" : { "U1_XF.BW32" : {}, "R130_XF.1" : { "R130_XF.2" : { "UNNAMED_17_RESISTOR_I113_A_XF" : { "R139_XF.1" : { "R139_XF.2" : { "GND" : {} } }, "R141_XF.1" : { "R141_XF.2" : { "GND" : {} } } } } } } } }, "U1_XF.BW31" : {} } } } } } } } } }, "NS5_FL_XF.2" : { "NS5_FL_XF.1" : { "PWR_AVTT_RS_XF" : {} } } }, "C1_DDR4_DQ<67>_XF" : { "U1_XF.BP59" : {}, "J2_XF.201" : {} }, "C0_RDIMM_DQS_T<7>_XF" : { "J1_XF.278" : {}, "U1_XF.BJ27" : {} }, "C3_DDR4_SA<0>_XF" : { "R15_XF.2" : { "R15_XF.1" : { "GND" : {} } }, "J4_XF.139" : {} }, "C2_RDIMM_DQS_T<8>_XF" : { "U1_XF.B59" : {}, "J3_XF.197" : {} }, "AC_E1S1_PET_N<7>_XF" : { "C130_XF.1" : { "C130_XF.2" : { "E1S1_PET_N<7>_XF" : { "J1_E1_XF.B39" : {} } } }, "U1_XF.R6" : {} }, "C2_DDR4_DQ<35>_XF" : { "J3_XF.249" : {}, "U1_XF.F55" : {} }, "UNNAMED_8_1G97_I16_Y_CPLD" : { "U3_CPLD.4" : {}, "R17_CPLD.1" : { "R17_CPLD.2" : { "CPLD_TDI_PIN_CPLD" : { "U1_CPLD.A6" : {} } } } }, "IS_VCCINTUR_SW_P_SP" : { "R193_SP_XF.1" : { "R193_SP_XF.2" : { "UNNAMED_9_ACS711_I5_VIOUT_SP" : { "U2_SP_XF.11" : {} } } }, "R194_SP_XF.2" : { "R194_SP_XF.1" : { "GND" : {} } }, "C182_SP_XF.1" : { "C182_SP_XF.2" : { "GND" : {} } }, "R46_SP_XF.2" : { "R46_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I143_A_SP" : { "U1_SP_XF.47" : {}, "C25_SP_XF.1" : { "C25_SP_XF.2" : { "GND" : {} } } } } } }, "UNNAMED_12_LT3071_I30_EN_FL" : { "U10_FL_XF.28" : {}, "R96_FL_XF.1" : { "R96_FL_XF.2" : { "P3R3V" : {} } } }, "UNNAMED_3_BYPASSCAPNPOL_I51_A_SP" : { "U1_SP_XF.38" : {}, "C64_SP_XF.1" : { "C64_SP_XF.2" : { "UNNAMED_3_BYPASSCAPNPOL_I51_B_SP" : { "U1_SP_XF.40" : {} } } } }, "UNNAMED_4_PI6CB33401_I37_SADRTRI_E2" : { "U1_E2_XF.32" : {}, "R12_E2_XF.2" : { "R12_E2_XF.1" : { "GND" : {} } } }, "C0_DDR4_DQ<0>_XF" : { "U1_XF.BW24" : {}, "J1_XF.5" : {} }, "C1_DDR4_VREFCA_1_XF" : { "C441_XF.1" : { "C441_XF.2" : { "GND" : {} } }, "R246_XF.1" : { "R246_XF.2" : { "GND" : {} } }, "R245_XF.1" : { "R245_XF.2" : { "PWR_SDIMM_VDD_XF" : {} } }, "J2_XF.146" : {}, "C440_XF.1" : { "C440_XF.2" : { "GND" : {} } } }, "OCL2_PET_N<2>_XF" : { "C275_XF.2" : { "C275_XF.1" : { "AC_OCL2_PET_N<2>_XF" : { "U1_XF.BL10" : {} } } }, "J1_O2_XF.B16" : {} }, "E1S0_PET_P<5>_XF" : { "J1_E0_XF.B34" : {}, "C104_XF.2" : { "C104_XF.1" : { "AC_E1S0_PET_P<5>_XF" : { "U1_XF.E11" : {} } } } }, "C3_DDR4_ADR<17>_XF" : { "J4_XF.234" : {} }, "DAC_AVCC_LIN_XF" : { "R11_FL_XF.1" : { "R11_FL_XF.2" : { "UNNAMED_3_BYPASSCAPNPOL_I31_B_FL" : { "C66_FL_XF.2" : { "C66_FL_XF.1" : { "GND" : {} } }, "R12_FL_XF.1" : { "R12_FL_XF.2" : { "UNNAMED_3_LT3071_I32_MARGA_FL" : { "U3_FL_XF.22" : {} } } } } } }, "R93_FL_XF.1" : { "R93_FL_XF.2" : { "UNNAMED_12_BYPASSCAPNPOL_I23_B_FL" : { "C94_FL_XF.2" : { "C94_FL_XF.1" : { "GND" : {} } }, "R94_FL_XF.1" : { "R94_FL_XF.2" : { "UNNAMED_12_LT3071_I30_MARGA_FL" : { "U10_FL_XF.22" : {} } } } } } }, "U1_SP_XF.57" : {}, "R21_FL_XF.1" : { "R21_FL_XF.2" : { "UNNAMED_4_BYPASSCAPNPOL_I23_B_FL" : { "R22_FL_XF.1" : { "R22_FL_XF.2" : { "UNNAMED_4_LT3071_I30_MARGA_FL" : { "U6_FL_XF.22" : {} } } }, "C5_FL_XF.2" : { "C5_FL_XF.1" : { "GND" : {} } } } } } }, "AC_E1S1_PET_P<6>_XF" : { "U1_XF.R11" : {}, "C111_XF.1" : { "C111_XF.2" : { "E1S1_PET_P<6>_XF" : { "J1_E1_XF.B37" : {} } } } }, "UNNAMED_6_LT3071_I30_VIOC_FL" : { "U2_FL_XF.1" : {}, "C35_FL_XF.1" : { "C35_FL_XF.2" : { "GND" : {} } } }, "SDIMM_LTM4675_ALERT_OD_F" : { "U1_CPLD.L8" : {}, "PM4_SD_XF.E3" : { "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } } } }, "UNNAMED_3_BYPASSCAPNPOL_I145_A_SP" : { "U1_SP_XF.45" : {}, "C27_SP_XF.1" : { "C27_SP_XF.2" : { "GND" : {} } }, "R48_SP_XF.1" : { "R48_SP_XF.2" : { "IS_VCCINTLR_SW_P_SP" : { "R195_SP_XF.1" : { "R195_SP_XF.2" : { "UNNAMED_9_ACS711_I28_VIOUT_SP" : { "U3_SP_XF.11" : {} } } }, "R196_SP_XF.2" : { "R196_SP_XF.1" : { "GND" : {} } }, "C183_SP_XF.1" : { "C183_SP_XF.2" : { "GND" : {} } } } } } }, "C3_RDIMM_DQS_T<16>_XF" : { "U1_XF.B16" : {}, "J4_XF.132" : {} }, "C3_DDR4_DQ<59>_XF" : { "U1_XF.C19" : {}, "J4_XF.282" : {} }, "OCL0_PER_P<2>_XF" : { "J1_O0_XF.A15" : {}, "U1_XF.BW2" : {} }, "E1S2_PER_N<5>_XF" : { "U1_XF.AC5" : {}, "J1_E2_XF.A33" : {} }, "AC_PCIE_X1_TXN_XF" : { "C294_XF.1" : { "C294_XF.2" : { "PCIE_X1_TXN_XF" : { "J1_PX1_XF.A17" : {} } } }, "U1_XF.BF8" : {} }, "C1_DDR4_DQ<10>_XF" : { "U1_XF.BV53" : {}, "J2_XF.23" : {} }, "C0_DDR4_DQ<18>_XF" : { "J1_XF.34" : {}, "U1_XF.BP17" : {} }, "C3_RDIMM_DQS_C<7>_XF" : { "J4_XF.277" : {}, "U1_XF.B18" : {} }, "CKO_LTM4650_PM3_SP" : { "R60_SP_XF.1" : { "R60_SP_XF.2" : { "UNNAMED_11_LTM4650FIXED_I150_MODEPLLIN_SP" : { "R82_SP_XF.2" : { "R82_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R80_SP_XF.2" : { "R80_SP_XF.1" : { "INTVCC_4650_BR_SP" : { "C188_SP_XF.1" : { "C188_SP_XF.2" : { "GND" : {} } }, "PM7_SP_XF.H8" : { "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.F4" : { "UNNAMED_11_LTM4650FIXED_I150_MODEPLLIN_SP" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.G3" : { "GND" : {} } } } } } } } } }, "UNNAMED_4_LT3071_I30_IMON_FL" : { "R15_FL_XF.1" : { "R15_FL_XF.2" : { "IMON_AVCC_LIN_XF" : { "R72_XF.1" : { "R72_XF.2" : { "UNNAMED_17_RESISTOR_I53_A_XF" : { "R82_XF.1" : { "R82_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_A_XF" : { "U1_XF.BY38" : {}, "C141_XF.1" : { "C141_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_B_XF" : { "U1_XF.CA38" : {}, "R83_XF.2" : { "R83_XF.1" : { "UNNAMED_17_RESISTOR_I54_A_XF" : { "R75_XF.2" : { "R75_XF.1" : { "UNNAMED_17_RESISTOR_I187_B_XF" : { "R119_XF.2" : { "R119_XF.1" : { "GND" : {} } } } } }, "R74_XF.2" : { "R74_XF.1" : { "GND" : {} } } } } } } } } } } }, "R73_XF.2" : { "R73_XF.1" : { "UNNAMED_17_RESISTOR_I188_B_XF" : { "R118_XF.2" : { "R118_XF.1" : { "GND" : {} } } } } } } } }, "R7_FL_XF.2" : { "R7_FL_XF.1" : { "UNNAMED_3_LT3071_I32_IMON_FL" : { "U3_FL_XF.21" : {} } } }, "R91_FL_XF.2" : { "R91_FL_XF.1" : { "UNNAMED_12_LT3071_I30_IMON_FL" : { "U10_FL_XF.21" : {} } } } } } }, "U6_FL_XF.21" : {} }, "UNNAMED_3_RESISTOR_I60_A" : { "FPNL_CONN.12" : {}, "R69.1" : { "R69.2" : { "P3R3V" : {} } } }, "ENB3V_SEQ_K" : { "R80.2" : { "R80.1" : { "GND" : {} } }, "R7_CPLD.1" : { "R7_CPLD.2" : { "GND" : {} } }, "R83.1" : { "R83.2" : { "UNNAMED_20_NMOSFETVMT3_I61_G" : { "Q14.1" : { "Q14.3" : { "UNNAMED_20_FERRITEBEAD_I72_A" : { "R82.2" : { "R82.1" : { "P5VSB" : {} } }, "FB9.1" : { "FB9.2" : { "UNNAMED_20_FERRITEBEAD_I72_B" : { "P6.2" : {} } } } } }, "Q14.2" : { "UNNAMED_20_NMOSFETVMT3_I61_S" : { "R81.2" : { "R81.1" : { "GND" : {} } } } } } } } }, "U1_CPLD.M16" : {} }, "CLKIN_N_E2" : { "R15_E2_XF.2" : { "R15_E2_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R17_E2_XF.2" : { "R17_E2_XF.1" : { "CLKIN_P_E2" : {} } }, "R18_E2_XF.1" : { "R18_E2_XF.2" : { "GND" : {} } }, "C17_E2_XF.2" : { "C17_E2_XF.1" : { "E1S_REF_CLK_N<2>" : { "U1.34" : {} } } }, "U1_E2_XF.6" : {} }, "C2_DDR4_ADR<0>_XF" : { "U1_XF.K63" : {}, "J3_XF.79" : {} }, "TS_FPGA_N_XF" : { "R157_XF.1" : { "R157_XF.2" : { "GND" : {} } }, "U1_XF.AP24" : {}, "U4_SP_XF.2" : {} }, "C2_DDR4_DQ<65>_XF" : { "U1_XF.D57" : {}, "J3_XF.194" : {} }, "E1S0_PET_P<7>_XF" : { "J1_E0_XF.B40" : {}, "C102_XF.2" : { "C102_XF.1" : { "AC_E1S0_PET_P<7>_XF" : { "U1_XF.C11" : {} } } } }, "UNNAMED_4_PI6CB33401_I37_SCLK_E3" : { "R11_E3_XF.2" : { "R11_E3_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E3_XF.9" : {} }, "SDA_P1" : { "J1_P1_XF.A10" : {} }, "C0_RDIMM_DQS_C<11>_XF" : { "J1_XF.30" : {}, "U1_XF.BV18" : {} }, "E1S3_3R3V_PWRDIS_XF" : { "J1_E3_XF.B12" : {}, "U1_XF.V18" : {} }, "UNNAMED_17_RESISTOR_I119_A_XF" : { "R143_XF.1" : { "R143_XF.2" : { "GND" : {} } }, "R142_XF.1" : { "R142_XF.2" : { "VMON_AVTT_SW_XF" : { "R99_SP_XF.2" : { "R99_SP_XF.1" : { "PWR_AVTT_SW_XF" : {} } } } } }, "R131_XF.2" : { "R131_XF.1" : { "UNNAMED_17_RESISTOR_I121_A_XF" : { "U1_XF.BY29" : {}, "C269_XF.1" : { "C269_XF.2" : { "UNNAMED_17_RESISTOR_I124_A_XF" : { "U1_XF.BY30" : {}, "R132_XF.1" : { "R132_XF.2" : { "UNNAMED_17_RESISTOR_I122_A_XF" : { "R144_XF.1" : { "R144_XF.2" : { "GND" : {} } }, "R145_XF.1" : { "R145_XF.2" : { "GND" : {} } } } } } } } } } } } }, "OCL2_3R3V_SCL_XF" : { "R271_XF.2" : { "R271_XF.1" : { "P3R3V" : {} } }, "J1_O2_XF.A9" : {}, "U1_XF.AY18" : {} }, "E1S3_PET_N<6>_XF" : { "C175_XF.2" : { "C175_XF.1" : { "AC_E1S3_PET_N<6>_XF" : { "U1_XF.AK8" : {} } } }, "J1_E3_XF.B36" : {} }, "UNNAMED_29_PI6CB33401_I63_SADRTRI_XF" : { "U5_XF.32" : {}, "R152_XF.2" : { "R152_XF.1" : { "GND" : {} } } }, "PHASMD_4650_TL_SP" : { "PM4_SP_XF.G4" : { "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G9" : { "UNNAMED_4_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} } } }, "C1_DDR4_DQ<62>_XF" : { "J2_XF.135" : {}, "U1_XF.BK52" : {} }, "C0_RDIMM_DQS_T<9>_XF" : { "J1_XF.7" : {}, "U1_XF.CB23" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I57_B_XF" : { "R81_XF.2" : { "R81_XF.1" : { "UNNAMED_17_RESISTOR_I60_A_XF" : { "R112_XF.2" : { "R112_XF.1" : { "GND" : {} } }, "R113_XF.2" : { "R113_XF.1" : { "GND" : {} } } } } }, "C140_XF.2" : { "C140_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I57_A_XF" : { "R80_XF.2" : { "R80_XF.1" : { "UNNAMED_17_RESISTOR_I59_A_XF" : { "R111_XF.2" : { "R111_XF.1" : { "GND" : {} } }, "R110_XF.2" : { "R110_XF.1" : { "VMON_AVTT_RLC_LIN_XF" : { "R56_FL_XF.2" : { "R56_FL_XF.1" : { "VS_AVTT_RLC_LIN_FL" : { "NS3_FL_XF.2" : { "NS3_FL_XF.1" : { "PWR_AVTT_RLC_XF" : {} } }, "U1_FL_XF.19" : {} } } } } } } } } }, "U1_XF.CC36" : {} } } }, "U1_XF.CC37" : {} }, "AC_OCL2_CONN_REFCLK_N_XF" : { "U5_XF.14" : {}, "C388_XF.1" : { "C388_XF.2" : { "OCL2_CONN_REFCLK_N_XF" : { "J1_O2_XF.B13" : {} } } } }, "SI5341_RST_N" : { "U1.6" : {}, "U1_CPLD.E2" : {} }, "AC_CONN_CLK_REFP<1>_2" : { "C20_E3_XF.1" : { "C20_E3_XF.2" : { "CONN_CLK_REFP<1>_E3" : { "J1_E3_XF.A15" : {} } } }, "U1_E3_XF.17" : {} }, "POK_OD_AVCC_SW_P<0>" : { "PM2_SP_XF.H8" : { "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.E6" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : { "U11.12" : {}, "C33.2" : { "C33.1" : { "GND" : {} } }, "R74.2" : { "R74.1" : { "GND" : {} } } } } } } }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } }, "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } } } }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} } }, "U1_CPLD.N11" : {} }, "C0_DDR4_DQ<57>_XF" : { "J1_XF.275" : {}, "U1_XF.BH26" : {} }, "DDR4_SYS_CLK_P<2>_XF" : { "C364_XF.1" : { "C364_XF.2" : { "C2_SYS_CLK_P_XF" : { "R249_XF.2" : { "R249_XF.1" : { "PWR_NDIMM_VDD_XF" : {} } }, "R250_XF.1" : { "R250_XF.2" : { "GND" : {} } }, "U1_XF.J59" : {} } } }, "U6_XF.12" : {} }, "C3_RDIMM_DQS_C<3>_XF" : { "J4_XF.185" : {}, "U1_XF.G21" : {} }, "OCL1_PET_P<3>_XF" : { "C181_XF.2" : { "C181_XF.1" : { "AC_OCL1_PET_P<3>_XF" : { "U1_XF.BV9" : {} } } }, "J1_O1_XF.B18" : {} }, "OCL0_3R3V_PERST_F_XF" : { "J1_O0_XF.A12" : {}, "U1_XF.BM20" : {} }, "UNNAMED_3_LTC2975_I168_ASEL0_SP" : { "R21_SP_XF.2" : { "R21_SP_XF.1" : { "GND" : {} } }, "R19_SP_XF.2" : { "R19_SP_XF.1" : { "P3R3V" : {} } }, "U1_SP_XF.35" : {} }, "UNNAMED_20_NMOSFETVMT3_I61_G" : { "Q14.1" : { "Q14.2" : { "UNNAMED_20_NMOSFETVMT3_I61_S" : { "R81.2" : { "R81.1" : { "GND" : {} } } } }, "Q14.3" : { "UNNAMED_20_FERRITEBEAD_I72_A" : { "FB9.1" : { "FB9.2" : { "UNNAMED_20_FERRITEBEAD_I72_B" : { "P6.2" : {} } } }, "R82.2" : { "R82.1" : { "P5VSB" : {} } } } } }, "R83.2" : { "R83.1" : { "ENB3V_SEQ_K" : { "U1_CPLD.M16" : {}, "R7_CPLD.1" : { "R7_CPLD.2" : { "GND" : {} } }, "R80.2" : { "R80.1" : { "GND" : {} } } } } } }, "AC_OCL3_FPGA_REFCLK_P_XF" : { "C357_XF.1" : { "C357_XF.2" : { "OCL3_FPGA_REFCLK_P_XF" : { "R227_XF.1" : { "R227_XF.2" : { "GND" : {} } }, "U1_XF.BJ15" : {}, "R216_XF.2" : { "R216_XF.1" : { "P3R3V" : {} } } } } }, "U5_XF.27" : {} }, "C0_DDR4_ADR<12>_XF" : { "U1_XF.BU19" : {}, "J1_XF.65" : {} }, "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : { "J2_XF.141" : {}, "U12.6" : {}, "R34.2" : { "R34.1" : { "P3R3V" : {} } }, "U1_CPLD.A9" : {}, "J4_XF.141" : {}, "J1_XF.141" : {}, "J3_XF.141" : {}, "U11.13" : {}, "J5.5" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R6.2" : { "R6.1" : { "CPLD_P1R8V_1" : {} } }, "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : {} } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {}, "R121.1" : { "R121.2" : { "CPLD_P1R8V_1" : {} } } } } }, "PM4_ND_XF.E4" : { "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.H7" : { "NC" : {} }, "PM4_ND_XF.J4" : { "NC" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.L1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.B9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.A9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.C9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.J5" : { "NC" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.D1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.J1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.G7" : { "NC" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.G2" : { "NDIMM_I2C_ASEL_RESISTOR_XF" : {} }, "PM4_ND_XF.K1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.E8" : { "NC" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.B8" : { "SW0_NODE_ND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.B1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.A1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.F9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.H5" : { "NC" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.E3" : { "NDIMM_LTM4675_ALERT_OD_F_1" : { "U1_CPLD.M6" : {} } }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.L9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.F7" : { "NC" : {} }, "PM4_ND_XF.M9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.E5" : { "CKI_LTM4675_ND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.D8" : { "NC" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.C1" : { "PWR_NDIMM_VDD_XF" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.J9" : { "P12V_FUSED_4675_ND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} } } } }, "Q1.2" : { "FPGA_1R8V_SCL" : { "U1_XF.BW30" : {}, "R33.1" : { "R33.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U1_CPLD.C9" : {}, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } } } }, "AC_PCIE0_TXN<3>_XF" : { "C83_XF.1" : { "C83_XF.2" : { "PCIE0_TXN<3>_XF" : { "J1_P0_XF.B19" : {} } } }, "U1_XF.AW10" : {} }, "C2_RDIMM_DQS_T<6>_XF" : { "J3_XF.267" : {}, "U1_XF.J51" : {} }, "E1S3_PET_N<3>_XF" : { "C328_XF.2" : { "C328_XF.1" : { "AC_E1S3_PET_N<3>_XF" : { "U1_XF.AF12" : {} } } }, "J1_E3_XF.B26" : {} }, "FAN_TACH_OD<1>" : { "U1_CPLD.H12" : {}, "P5.3" : {} }, "C1_DDR4_DQ<32>_XF" : { "J2_XF.97" : {}, "U1_XF.BR62" : {} }, "E1S2_PER_N<7>_XF" : { "U1_XF.AB3" : {}, "J1_E2_XF.A39" : {} }, "SGND_PM4_SP" : { "C20_SP_XF.2" : { "C20_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "R13_SP_XF.1" : { "R13_SP_XF.2" : { "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } } } } } } }, "LTC2975_CPLD_ENB_C" : { "U1_CPLD.L12" : {}, "U1_SP_XF.5" : {} }, "E1S0_3R3V_CKEN_F<0>_XF" : { "U1_E0_XF.12" : {}, "U1_XF.V17" : {} }, "E1S3_PER_N<5>_XF" : { "U1_XF.AL5" : {}, "J1_E3_XF.A33" : {} }, "LTC2975_CPLD_ENB_B" : { "U1_CPLD.J11" : {}, "U1_SP_XF.4" : {} }, "C1_DDR4_ADR<15>_XF" : { "U1_XF.BW52" : {}, "J2_XF.86" : {} }, "P12V_4650_BR_SP" : { "PM7_SP_XF.K4" : {}, "PM7_SP_XF.J10" : {}, "PM7_SP_XF.L7" : {}, "C184_SP_XF.1" : { "C184_SP_XF.2" : { "GND" : {} } }, "PM7_SP_XF.M7" : {}, "PM7_SP_XF.M9" : {}, "PM7_SP_XF.L2" : {}, "PM7_SP_XF.M2" : {}, "PM7_SP_XF.L9" : {}, "PM7_SP_XF.L5" : {}, "F16_SP_XF.2" : { "F16_SP_XF.1" : { "P12V_4650_LRIGHT_SP" : {} } }, "PM7_SP_XF.M5" : {}, "PM7_SP_XF.J4" : {}, "PM7_SP_XF.L3" : {}, "PM7_SP_XF.M3" : {}, "C185_SP_XF.1" : { "C185_SP_XF.2" : { "GND" : {} } }, "PM7_SP_XF.K10" : {}, "PM7_SP_XF.M11" : {}, "PM7_SP_XF.L11" : {}, "PM7_SP_XF.L4" : {}, "PM7_SP_XF.M4" : {}, "PM7_SP_XF.J3" : {}, "PM7_SP_XF.L8" : {}, "PM7_SP_XF.M8" : {}, "PM7_SP_XF.M6" : {}, "PM7_SP_XF.L6" : {}, "PM7_SP_XF.K9" : {}, "PM7_SP_XF.J11" : {}, "PM7_SP_XF.K2" : {}, "PM7_SP_XF.K3" : {}, "PM7_SP_XF.L10" : {}, "PM7_SP_XF.M10" : {}, "C187_SP_XF.1" : { "C187_SP_XF.2" : { "GND" : {} } }, "PM7_SP_XF.K11" : {}, "PM7_SP_XF.J9" : {}, "PM7_SP_XF.J2" : {} }, "C3_DDR4_CS_N<0>_XF" : { "U1_XF.N22" : {}, "J4_XF.84" : {} }, "C1_RDIMM_DQS_C<17>_XF" : { "U1_XF.BR58" : {}, "J2_XF.52" : {} }, "IS_VCCINTLR_SW_P_SP" : { "C183_SP_XF.1" : { "C183_SP_XF.2" : { "GND" : {} } }, "R195_SP_XF.1" : { "R195_SP_XF.2" : { "UNNAMED_9_ACS711_I28_VIOUT_SP" : { "U3_SP_XF.11" : {} } } }, "R196_SP_XF.2" : { "R196_SP_XF.1" : { "GND" : {} } }, "R48_SP_XF.2" : { "R48_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I145_A_SP" : { "C27_SP_XF.1" : { "C27_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.45" : {} } } } }, "TS_FPGA_P_XF" : { "U1_XF.AP25" : {}, "U4_SP_XF.1" : {} }, "C1_DDR4_DQ<25>_XF" : { "U1_XF.BY59" : {}, "J2_XF.183" : {} }, "C2_RDIMM_DQS_C<0>_XF" : { "J3_XF.152" : {}, "U1_XF.V48" : {} }, "C1_DDR4_CS_N<3>_XF" : { "U1_XF.BY62" : {}, "J2_XF.237" : {} }, "FPGA_INIT_F_1" : { "U1_CPLD.J6" : {}, "R28_XF.2" : { "R28_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.AJ19" : {} }, "JTAG_CTL_TDI" : { "U1_CPLD.G5" : {}, "U1_XF.BY32" : {} }, "C2_DDR4_ADR<11>_XF" : { "U1_XF.L56" : {}, "J3_XF.210" : {} }, "C3_DDR4_DQ<17>_XF" : { "J4_XF.172" : {}, "U1_XF.H26" : {} }, "UNNAMED_17_RESISTOR_I54_A_XF" : { "R74_XF.2" : { "R74_XF.1" : { "GND" : {} } }, "R75_XF.2" : { "R75_XF.1" : { "UNNAMED_17_RESISTOR_I187_B_XF" : { "R119_XF.2" : { "R119_XF.1" : { "GND" : {} } } } } }, "R83_XF.1" : { "R83_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_B_XF" : { "U1_XF.CA38" : {}, "C141_XF.2" : { "C141_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I49_A_XF" : { "U1_XF.BY38" : {}, "R82_XF.2" : { "R82_XF.1" : { "UNNAMED_17_RESISTOR_I53_A_XF" : { "R73_XF.2" : { "R73_XF.1" : { "UNNAMED_17_RESISTOR_I188_B_XF" : { "R118_XF.2" : { "R118_XF.1" : { "GND" : {} } } } } }, "R72_XF.2" : { "R72_XF.1" : { "IMON_AVCC_LIN_XF" : { "R15_FL_XF.2" : { "R15_FL_XF.1" : { "UNNAMED_4_LT3071_I30_IMON_FL" : { "U6_FL_XF.21" : {} } } }, "R91_FL_XF.2" : { "R91_FL_XF.1" : { "UNNAMED_12_LT3071_I30_IMON_FL" : { "U10_FL_XF.21" : {} } } }, "R7_FL_XF.2" : { "R7_FL_XF.1" : { "UNNAMED_3_LT3071_I32_IMON_FL" : { "U3_FL_XF.21" : {} } } } } } } } } } } } } } } } }, "E1S1_3R3V_CKEN_F<1>_XF" : { "U1_E1_XF.19" : {}, "U1_XF.AD17" : {} }, "CLKIN_N_E0" : { "U1_E0_XF.6" : {}, "C17_E0_XF.2" : { "C17_E0_XF.1" : { "E1S_REF_CLK_N<0>" : { "U1.27" : {} } } }, "R15_E0_XF.2" : { "R15_E0_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R17_E0_XF.2" : { "R17_E0_XF.1" : { "CLKIN_P_E0" : {} } }, "R18_E0_XF.1" : { "R18_E0_XF.2" : { "GND" : {} } } }, "C2_RDIMM_DQS_C<1>_XF" : { "J3_XF.163" : {}, "U1_XF.N46" : {} }, "MFG_E1" : { "J1_E1_XF.B7" : {} }, "UNNAMED_5_LT3071_I30_MARGA_FL" : { "U1_FL_XF.22" : {}, "R31_FL_XF.2" : { "R31_FL_XF.1" : { "UNNAMED_5_BYPASSCAPNPOL_I25_B_FL" : { "R29_FL_XF.2" : { "R29_FL_XF.1" : { "DAC_AVTT_LIN_XF" : { "R36_FL_XF.1" : { "R36_FL_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I25_B_FL" : { "R42_FL_XF.1" : { "R42_FL_XF.2" : { "UNNAMED_6_LT3071_I30_MARGA_FL" : { "U2_FL_XF.22" : {} } } }, "C22_FL_XF.2" : { "C22_FL_XF.1" : { "GND" : {} } } } } }, "R38_FL_XF.1" : { "R38_FL_XF.2" : { "UNNAMED_8_BYPASSCAPNPOL_I25_B_FL" : { "R44_FL_XF.1" : { "R44_FL_XF.2" : { "UNNAMED_8_LT3071_I30_MARGA_FL" : { "U5_FL_XF.22" : {} } } }, "C25_FL_XF.2" : { "C25_FL_XF.1" : { "GND" : {} } } } } }, "U1_SP_XF.58" : {}, "R37_FL_XF.1" : { "R37_FL_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I25_B_FL" : { "C24_FL_XF.2" : { "C24_FL_XF.1" : { "GND" : {} } }, "R43_FL_XF.1" : { "R43_FL_XF.2" : { "UNNAMED_7_LT3071_I30_MARGA_FL" : { "U4_FL_XF.22" : {} } } } } } } } } }, "C20_FL_XF.2" : { "C20_FL_XF.1" : { "GND" : {} } } } } } }, "E1S1_PET_P<2>_XF" : { "J1_E1_XF.B24" : {}, "C115_XF.2" : { "C115_XF.1" : { "AC_E1S1_PET_P<2>_XF" : { "U1_XF.M9" : {} } } } }, "C3_DDR4_DQ<23>_XF" : { "J4_XF.177" : {}, "U1_XF.F27" : {} }, "BOARD_CFG_SW<3>" : { "U1_XF.CB34" : {}, "S1.6" : { "S1.1" : { "BOARD_CFG_SW<0>" : { "U1_CPLD.P2" : {}, "U1_XF.CB35" : {} } }, "S1.4" : { "BOARD_CFG_SW<1>" : { "U1_XF.CA36" : {}, "U1_CPLD.R1" : {} } }, "S1.2" : { "GND" : {} }, "S1.5" : { "GND" : {} }, "S1.3" : { "BOARD_CFG_SW<2>" : { "U1_CPLD.N3" : {}, "U1_XF.BY35" : {} } } }, "U1_CPLD.M2" : {} }, "C3_DDR4_ADR<14>_XF" : { "J4_XF.228" : {}, "U1_XF.M23" : {} }, "VDDO2" : { "U1.29" : {}, "FB3.2" : { "FB3.1" : { "CPLD_P1R8V_1" : {} } }, "C22.1" : { "C22.2" : { "GND" : {} } } }, "PSU_PWR_OK" : { "U1_CPLD.R7" : {}, "J3.8" : {} }, "C3_DDR4_CS_N<1>_XF" : { "J4_XF.89" : {}, "U1_XF.N21" : {} }, "AC_OCL1_CONN_REFCLK_P_XF" : { "C355_XF.1" : { "C355_XF.2" : { "OCL1_CONN_REFCLK_P_XF" : { "J1_O1_XF.B12" : {} } } }, "U7_XF.17" : {} }, "IMON_AVTT_LIN_XF" : { "R64_FL_XF.2" : { "R64_FL_XF.1" : { "UNNAMED_7_LT3071_I30_IMON_FL" : { "U4_FL_XF.21" : {} } } }, "R25_FL_XF.2" : { "R25_FL_XF.1" : { "UNNAMED_6_LT3071_I30_IMON_FL" : { "U2_FL_XF.21" : {} } } }, "R82_FL_XF.2" : { "R82_FL_XF.1" : { "UNNAMED_8_LT3071_I30_IMON_FL" : { "U5_FL_XF.21" : {}, "R26_FL_XF.2" : { "R26_FL_XF.1" : { "GND" : {} } } } } }, "R133_XF.2" : { "R133_XF.1" : { "UNNAMED_17_RESISTOR_I101_A_XF" : { "R127_XF.2" : { "R127_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I107_A_XF" : { "U1_XF.CB33" : {}, "C267_XF.1" : { "C267_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I107_B_XF" : { "R128_XF.1" : { "R128_XF.2" : { "UNNAMED_17_RESISTOR_I104_A_XF" : { "R136_XF.1" : { "R136_XF.2" : { "UNNAMED_17_RESISTOR_I105_B_XF" : { "R121_XF.1" : { "R121_XF.2" : { "GND" : {} } } } } }, "R135_XF.1" : { "R135_XF.2" : { "GND" : {} } } } } }, "U1_XF.CC33" : {} } } } } } }, "R134_XF.1" : { "R134_XF.2" : { "UNNAMED_17_RESISTOR_I101_B_XF" : { "R120_XF.1" : { "R120_XF.2" : { "GND" : {} } } } } } } } }, "R24_FL_XF.2" : { "R24_FL_XF.1" : { "UNNAMED_5_LT3071_I30_IMON_FL" : { "U1_FL_XF.21" : {} } } } }, "UNNAMED_9_LUMEXRGBLED_I91_BLUEK_CPLD" : { "D3_CPLD.3" : { "D3_CPLD.4" : { "UNNAMED_9_LUMEXRGBLED_I91_GREENK_CPLD" : { "R22_CPLD.1" : { "R22_CPLD.2" : { "RGB_LED_GREEN<1>_CPLD" : { "U1_CPLD.F7" : {} } } } } }, "D3_CPLD.2" : { "UNNAMED_9_LUMEXRGBLED_I91_REDK_CPLD" : { "R21_CPLD.1" : { "R21_CPLD.2" : { "RGB_LED_RED<1>_CPLD" : { "U1_CPLD.D8" : {} } } } } }, "D3_CPLD.1" : { "CPLD_P3R3V" : {} } }, "R23_CPLD.1" : { "R23_CPLD.2" : { "RGB_LED_BLUE<1>_CPLD" : { "U1_CPLD.C7" : {} } } } }, "C2_DDR4_ADR<10>_XF" : { "J3_XF.225" : {}, "U1_XF.H62" : {} }, "C1_DDR4_DQ<44>_XF" : { "J2_XF.106" : {}, "U1_XF.BN61" : {} }, "FP_LAN_ACTLED_N<2>" : { "FPNL_CONN.24" : {}, "U1_CPLD.G16" : {} }, "UNNAMED_10_RESISTOR_I143_A_FL" : { "R88_FL_XF.1" : { "R88_FL_XF.2" : { "PWR_RS_RLC_MGTVCCAUX_XF" : {} } }, "C85_FL_XF.1" : { "C85_FL_XF.2" : { "PWR_RS_RLC_MGTVCCAUX_XF" : {} } }, "R89_FL_XF.1" : { "R89_FL_XF.2" : { "GND" : {} } }, "U9_FL_XF.3" : {} }, "OCL3_PET_N<2>_XF" : { "C279_XF.2" : { "C279_XF.1" : { "AC_OCL3_PET_N<2>_XF" : { "U1_XF.BG10" : {} } } }, "J1_O3_XF.B16" : {} }, "VS_AVCC_RN_LIN_FL" : { "U6_FL_XF.19" : {}, "NS4_FL_XF.2" : { "NS4_FL_XF.1" : { "PWR_AVCC_RN_XF" : {} } }, "R84_FL_XF.1" : { "R84_FL_XF.2" : { "VMON_AVCC_RN_LIN_XF" : { "R1_XF.1" : { "R1_XF.2" : { "UNNAMED_17_RESISTOR_I51_A_XF" : { "R2_XF.2" : { "R2_XF.1" : { "GND" : {} } }, "R76_XF.1" : { "R76_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I48_A_XF" : { "U1_XF.AM25" : {}, "C138_XF.1" : { "C138_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I48_B_XF" : { "U1_XF.AN24" : {}, "R77_XF.2" : { "R77_XF.1" : { "UNNAMED_17_RESISTOR_I52_A_XF" : { "R4_XF.2" : { "R4_XF.1" : { "GND" : {} } }, "R3_XF.2" : { "R3_XF.1" : { "GND" : {} } } } } } } } } } } } } } } } } } }, "AC_OCL0_FPGA_REFCLK_N_XF" : { "C370_XF.1" : { "C370_XF.2" : { "OCL0_FPGA_REFCLK_N_XF" : { "R211_XF.2" : { "R211_XF.1" : { "P3R3V" : {} } }, "U1_XF.CB12" : {}, "R220_XF.1" : { "R220_XF.2" : { "GND" : {} } } } } }, "U7_XF.23" : {} }, "VMON_AVTT_RLC_LIN_XF" : { "R56_FL_XF.2" : { "R56_FL_XF.1" : { "VS_AVTT_RLC_LIN_FL" : { "U1_FL_XF.19" : {}, "NS3_FL_XF.2" : { "NS3_FL_XF.1" : { "PWR_AVTT_RLC_XF" : {} } } } } }, "R110_XF.1" : { "R110_XF.2" : { "UNNAMED_17_RESISTOR_I59_A_XF" : { "R80_XF.1" : { "R80_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I57_A_XF" : { "U1_XF.CC36" : {}, "C140_XF.1" : { "C140_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I57_B_XF" : { "U1_XF.CC37" : {}, "R81_XF.2" : { "R81_XF.1" : { "UNNAMED_17_RESISTOR_I60_A_XF" : { "R113_XF.2" : { "R113_XF.1" : { "GND" : {} } }, "R112_XF.2" : { "R112_XF.1" : { "GND" : {} } } } } } } } } } } }, "R111_XF.2" : { "R111_XF.1" : { "GND" : {} } } } } } }, "VDD_VS_P_SD" : { "PM4_SD_XF.J7" : { "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { 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: { "GND" : {} } }, "U1_XF.Y11" : {}, "U1_XF.AJ15" : {}, "U1_XF.AG9" : {}, "U5_FL_XF.17" : {}, "U1_XF.AC13" : {}, "U1_XF.U9" : {}, "C461_XF.1" : { "C461_XF.2" : { "GND" : {} } }, "U1_XF.AL9" : {}, "U1_XF.V11" : {}, "U1_XF.AG13" : {}, "U5_FL_XF.18" : {}, "U5_FL_XF.15" : {}, "U5_FL_XF.16" : {}, "C462_XF.1" : { "C462_XF.2" : { "GND" : {} } }, "U1_XF.AC9" : {}, "R267_XF.1" : { "R267_XF.2" : { "MGTRREF_LN_XF" : { "U1_XF.AJ14" : {} } } }, "C458_XF.1" : { "C458_XF.2" : { "GND" : {} } }, "C61_FL_XF.1" : { "C61_FL_XF.2" : { "GND" : {} } }, "C459_XF.1" : { "C459_XF.2" : { "GND" : {} } }, "C34_FL_XF.1" : { "C34_FL_XF.2" : { "GND" : {} } }, "C457_XF.1" : { "C457_XF.2" : { "GND" : {} } }, "U1_XF.AA9" : {}, "U1_XF.AE9" : {}, "NS9_FL_XF.1" : { "NS9_FL_XF.2" : { "VS_AVTT_RUC_LIN_FL" : {} } }, "U1_XF.AJ9" : {} }, "POK_OD_SDIMM_VDD_SW" : { "U1_CPLD.L9" : {}, "R2_SD_XF.2" : { "R2_SD_XF.1" : { "UNNAMED_3_DIODESOD923F_I70_A_SD" : { "PM4_SD_XF.E2" : { "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : {} } } } } } }, "U1_CPLD.C9" : {} } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } } } } } } }, "UNNAMED_7_LT3071_I30_PWRGD_FL" : { "R19_FL_XF.1" : { "R19_FL_XF.2" : { "POK_OD_AVTT_RN_LIN" : { "U1_CPLD.T10" : {} } } }, "U4_FL_XF.2" : {} }, "C3_DDR4_DQ<58>_XF" : { "U1_XF.C18" : {}, "J4_XF.137" : {} }, "E1S2_PET_N<3>_XF" : { "C170_XF.2" : { "C170_XF.1" : { "AC_E1S2_PET_N<3>_XF" : { "U1_XF.U10" : {} } } }, "J1_E2_XF.B26" : {} }, "C0_DDR4_DQ<26>_XF" : { "J1_XF.45" : {}, "U1_XF.BT25" : {} }, "E1S0_PER_P<6>_XF" : { "J1_E0_XF.A37" : {}, "U1_XF.G6" : {} }, "C3_DDR4_BA<0>_XF" : { "U1_XF.R22" : {}, "J4_XF.81" : {} }, "SW0_NODE_ND" : { "PM4_ND_XF.B8" : { "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U1_CPLD.C9" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "UNNAMED_3_598BICOLORLED_I68_L2A" : { "R79.2" : { "R79.1" : { "P3R3V" : {} } }, "D1.1" : { "D1.3" : { "FP_RST_SW_N" : { "U1_CPLD.J13" : {}, "R78.2" : { "R78.1" : { "P3R3V" : {} } }, "S2.3" : { "S2.2" : { "UNNAMED_3_598BICOLORLED_I68_L2C" : {} }, "S2.1" : { "GND" : {} }, "S2.4" : { "GND" : {} } }, "FPNL_CONN.15" : {} } }, "D1.4" : { "GND" : {} }, "D1.2" : { "UNNAMED_3_598BICOLORLED_I68_L2C" : {} } } }, "AC_E1S1_PET_N<5>_XF" : { "C132_XF.1" : { "C132_XF.2" : { "E1S1_PET_N<5>_XF" : { "J1_E1_XF.B33" : {} } } }, "U1_XF.T8" : {} }, "C0_DDR4_DQ<19>_XF" : { "U1_XF.BR17" : {}, "J1_XF.179" : {} }, "AC_E1S0_PET_P<4>_XF" : { "C105_XF.1" : { "C105_XF.2" : { "E1S0_PET_P<4>_XF" : { "J1_E0_XF.B31" : {} } } }, "U1_XF.F9" : {} }, "E1S3_PER_N<7>_XF" : { "U1_XF.AK3" : {}, "J1_E3_XF.A39" : {} }, "E1S_REF_CLK_P<2>" : { "U1.35" : {}, "C16_E2_XF.1" : { "C16_E2_XF.2" : { "CLKIN_P_E2" : { "R14_E2_XF.2" : { "R14_E2_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E2_XF.5" : {}, "R16_E2_XF.1" : { "R16_E2_XF.2" : { "GND" : {} } } } } } }, "OCL3_3R3V_SCL_XF" : { "R273_XF.2" : { "R273_XF.1" : { "P3R3V" : {} } }, "U1_XF.BC19" : {}, "J1_O3_XF.A9" : {} }, "E1S2_3R3V_PWRDIS_XF" : { "J1_E2_XF.B12" : {}, "U1_XF.P19" : {} }, "C2_DDR4_DQ<22>_XF" : { "U1_XF.G60" : {}, "J3_XF.32" : {} }, "UNNAMED_3_LTC2975_I168_ASEL1_SP" : { "R18_SP_XF.2" : { "R18_SP_XF.1" : { "GND" : {} } }, "U1_SP_XF.36" : {}, "R17_SP_XF.2" : { "R17_SP_XF.1" : { "P3R3V" : {} } } }, "AC_CONN_CLK_REFP<1>_1" : { "C20_E0_XF.1" : { "C20_E0_XF.2" : { "CONN_CLK_REFP<1>_E0" : { "J1_E0_XF.A15" : {} } } }, "U1_E0_XF.17" : {} }, "FPGA_CPLD_SSTAT_CLK" : { "U1_XF.BV37" : {}, "U1_CPLD.J1" : {} }, "UNNAMED_3_LTM4675_I40_TSNS01_SD" : { "PM4_SD_XF.C3" : { "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } } } } } } } } } } } } } } } }, "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "E1S0_PER_P<3>_XF" : { "J1_E0_XF.A27" : {}, "U1_XF.D4" : {} }, "E1S2_PET_N<6>_XF" : { "C157_XF.2" : { "C157_XF.1" : { "AC_E1S2_PET_N<6>_XF" : { "U1_XF.AA10" : {} } } }, "J1_E2_XF.B36" : {} }, "E1S1_3R3V_LED_XF" : { "R6_E1_XF.2" : { "R6_E1_XF.1" : { "P3R3V" : {} } }, "J1_E1_XF.A10" : {}, "U1_XF.AF17" : {} }, "JTAG_CTL_TMS" : { "U1_XF.CA31" : {}, "U1_CPLD.G4" : {} }, "C0_DDR4_ADR<1>_XF" : { "J1_XF.72" : {}, "U1_XF.CA16" : {} }, "C1_DDR4_DQ<1>_XF" : { "J2_XF.150" : {}, "U1_XF.BM51" : {} }, "UNNAMED_21_RESISTOR_I31_B_XF" : { "R24_XF.2" : { "R24_XF.1" : { "GND" : {} } }, "U1_XF.BK50" : {} }, "UNNAMED_7_BYPASSCAPNPOL_I44_B_SP" : { "R115_SP_XF.2" : { "R115_SP_XF.1" : { "UNNAMED_7_LTM4671_I87_MODECLKIN0_SP" : { "PM1_SP_XF.G11" : { "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {} } }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.E7" : { "UNNAMED_7_BYPASSCAPNPOL_I44_B_SP" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} } } } } } }, "FP_FAULT_LED_N<1>" : { "R50.2" : { "R50.1" : { "UNNAMED_3_RESISTOR_I58_A" : { "FPNL_CONN.8" : {} } } }, "U1_CPLD.J16" : {} }, "UNNAMED_10_RESISTOR_I70_B" : { "R339.2" : { "R339.1" : { "P3R3V" : {} } }, "U1.39" : {} }, "C2_RDIMM_DQS_T<5>_XF" : { "U1_XF.E52" : {}, "J3_XF.256" : {} }, "E1S1_PER_N<6>_XF" : { "U1_XF.T3" : {}, "J1_E1_XF.A36" : {} }, "SP_ENB3V_SEQ_N_CPLD" : { "R1_CPLD.1" : { "R1_CPLD.2" : { "GND" : {} } }, "U1_CPLD.L16" : {} }, "UNNAMED_10_RESISTOR_I66_B" : { "U1.4" : {}, "R136.2" : { "R136.1" : { "GND" : {} } } }, "UNNAMED_3_BYPASSCAPNPOL_I157_A_SP" : { "R20_SP_XF.1" : { "R20_SP_XF.2" : { "VS_VCCINT_N_SP" : { "PM4_SP_XF.E9" : { "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} } } } } } }, "AC_PCIE_X1_REFP_XF" : { "U1_XF.BG15" : {}, "C101_XF.2" : { "C101_XF.1" : { "PCIE_X1_REFP_XF" : { "J1_PX1_XF.A13" : {} } } } }, "RFU_<2>_E0" : { "J1_E0_XF.B8" : {} }, "JT_CPLD_TDO" : { "U1_CPLD.C6" : {}, "U1_CPLD.A13" : {}, "J5.14" : {} }, "UNNAMED_4_PI6CB33401_I37_SDATA_E1" : { "R9_E1_XF.2" : { "R9_E1_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E1_XF.10" : {} }, "DIMM_EVENT_OD_F<0>" : { "J1_XF.78" : {}, "U1_CPLD.K14" : {} }, "UNNAMED_22_RESISTOR_I34_B_XF" : { "U1_XF.L20" : {}, "R49_XF.2" : { "R49_XF.1" : { "GND" : {} } } }, "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {}, "PM2_SP_XF.E11" : { "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : { "U11.12" : {}, "R74.2" : { "R74.1" : { "GND" : {} } }, "C33.2" : { "C33.1" : { "GND" : {} } } } } } } }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.E6" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} } } }, "C2_RDIMM_DQS_C<15>_XF" : { "U1_XF.G49" : {}, "J3_XF.122" : {} }, "E1S1_PER_N<3>_XF" : { "U1_XF.M3" : {}, "J1_E1_XF.A26" : {} }, "C3_DDR4_DQ<12>_XF" : { "J4_XF.14" : {}, "U1_XF.M24" : {} }, "E1S0_3R3V_SCL_XF" : { "J1_E0_XF.A7" : {}, "R182_XF.2" : { "R182_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_XF.AC19" : {}, "R3_E0_XF.2" : { "R3_E0_XF.1" : { "P3R3V" : {} } } }, "UNNAMED_29_PI6CB33401_I63_PDF_XF" : { "U5_XF.31" : {}, "R153_XF.2" : { "R153_XF.1" : { "GND" : {} } } }, "AC_E1S1_PET_N<1>_XF" : { "U1_XF.N10" : {}, "C136_XF.1" : { "C136_XF.2" : { "E1S1_PET_N<1>_XF" : { "J1_E1_XF.B20" : {} } } } }, "UNNAMED_9_LUMEXRGBLED_I90_BLUEK_CPLD" : { "R20_CPLD.1" : { "R20_CPLD.2" : { "RGB_LED_BLUE<2>_CPLD" : { "U1_CPLD.B7" : {} } } }, "D2_CPLD.3" : { "D2_CPLD.1" : { "CPLD_P3R3V" : {} }, "D2_CPLD.4" : { "UNNAMED_9_LUMEXRGBLED_I90_GREENK_CPLD" : { "R5_CPLD.1" : { "R5_CPLD.2" : { "RGB_LED_GREEN<2>_CPLD" : { "U1_CPLD.A8" : {} } } } } }, "D2_CPLD.2" : { "UNNAMED_9_LUMEXRGBLED_I90_REDK_CPLD" : { "R4_CPLD.1" : { "R4_CPLD.2" : { "RGB_LED_RED<2>_CPLD" : { "U1_CPLD.D9" : {} } } } } } } }, "C0_DDR4_DQ<40>_XF" : { "U1_XF.BN27" : {}, "J1_XF.108" : {} }, "UNNAMED_4_BYPASSCAPNPOL_I103_B" : { "R21.2" : { "R21.1" : { "GND" : {} } }, "U11.2" : {}, "C51.2" : { "C51.1" : { "GND" : {} } }, "R68.2" : { "R68.1" : { "VMON_CPLD_P3R3V_SW" : { "R14_MP.2" : { "R14_MP.1" : { "CPLD_P3R3V" : {} } } } } } }, "CONN_CLK_REFP<0>_E3" : { "C21_E3_XF.2" : { "C21_E3_XF.1" : { "AC_CONN_CLK_REFP<0>_2" : { "U1_E3_XF.13" : {} } } }, "J1_E3_XF.B15" : {} }, "C1_DDR4_DQ<48>_XF" : { "J2_XF.119" : {}, "U1_XF.BK58" : {} }, "UNNAMED_9_LT3071_I30_PWRGD_FL" : { "U7_FL_XF.2" : {}, "R55_FL_XF.1" : { "R55_FL_XF.2" : { "POK_OD_VCCAUX_A_LIN" : { "U1_CPLD.M8" : {} } } } }, "OCL3_PER_P<3>_XF" : { "U1_XF.BG2" : {}, "J1_O3_XF.A18" : {} }, "CLK125M_FROM_CPLD" : { "U1_XF.BW35" : {}, "U1_CPLD.H5" : {} }, "E1S3_FPGA_REFCLK_P<1>_XF" : { "U1_XF.AN15" : {}, "R200_XF.1" : { "R200_XF.2" : { "GND" : {} } }, "C18_E3_XF.2" : { "C18_E3_XF.1" : { "AC_FPGA_CLK_REF_P<1>_2" : { "U1_E3_XF.27" : {} } } }, "R201_XF.1" : { "R201_XF.2" : { "E1S3_FPGA_REFCLK_N<1>_XF" : {} } }, "R190_XF.2" : { "R190_XF.1" : { "PWR_FPGA_3R3V" : {} } } }, "UNNAMED_20_FERRITEBEAD_I72_B" : { "FB9.2" : { "FB9.1" : { "UNNAMED_20_FERRITEBEAD_I72_A" : { "R82.2" : { "R82.1" : { "P5VSB" : {} } }, "Q14.3" : { "Q14.1" : { "UNNAMED_20_NMOSFETVMT3_I61_G" : { "R83.2" : { "R83.1" : { "ENB3V_SEQ_K" : { "R80.2" : { "R80.1" : { "GND" : {} } }, "R7_CPLD.1" : { "R7_CPLD.2" : { "GND" : {} } }, "U1_CPLD.M16" : {} } } } } }, "Q14.2" : { "UNNAMED_20_NMOSFETVMT3_I61_S" : { "R81.2" : { "R81.1" : { "GND" : {} } } } } } } } }, "P6.2" : {} }, "P12V_4650_BL_SP" : { "PM3_SP_XF.J2" : {}, "PM3_SP_XF.K11" : {}, "PM3_SP_XF.J9" : {}, "PM3_SP_XF.M10" : {}, "PM3_SP_XF.L10" : {}, "PM3_SP_XF.K3" : {}, "PM3_SP_XF.K2" : {}, "PM3_SP_XF.J11" : {}, "PM3_SP_XF.K9" : {}, "C57_SP_XF.1" : { "C57_SP_XF.2" : { "GND" : {} } }, "PM3_SP_XF.L6" : {}, "PM3_SP_XF.M6" : {}, "PM3_SP_XF.M8" : {}, "PM3_SP_XF.L8" : {}, "PM3_SP_XF.J3" : {}, "C75_SP_XF.1" : { "C75_SP_XF.2" : { "GND" : {} } }, "PM3_SP_XF.M4" : {}, "PM3_SP_XF.L4" : {}, "PM3_SP_XF.L11" : {}, "PM3_SP_XF.M11" : {}, "PM3_SP_XF.K10" : {}, "PM3_SP_XF.M3" : {}, "C77_SP_XF.1" : { "C77_SP_XF.2" : { "GND" : {} } }, "PM3_SP_XF.L3" : {}, "F1_SP_XF.2" : { "F1_SP_XF.1" : { "P12V_4650_LLEFT_SP" : {} } }, "PM3_SP_XF.J4" : {}, "PM3_SP_XF.M5" : {}, "PM3_SP_XF.L5" : {}, "PM3_SP_XF.L9" : {}, "PM3_SP_XF.M2" : {}, "PM3_SP_XF.M9" : {}, "PM3_SP_XF.L2" : {}, "PM3_SP_XF.M7" : {}, "PM3_SP_XF.L7" : {}, "PM3_SP_XF.J10" : {}, "PM3_SP_XF.K4" : {} }, "C3_DDR4_DQ<60>_XF" : { "U1_XF.A17" : {}, "J4_XF.128" : {} }, "PCIE0_TXN<5>_XF" : { "J2_P0_XF.B7" : {}, "C77_XF.2" : { "C77_XF.1" : { "AC_PCIE0_TXN<5>_XF" : { "U1_XF.BA10" : {} } } } }, "AC_E1S0_PET_P<2>_XF" : { "C107_XF.1" : { "C107_XF.2" : { "E1S0_PET_P<2>_XF" : { "J1_E0_XF.B24" : {} } } }, "U1_XF.A11" : {} }, "UNNAMED_20_NMOSFETVMT3_I61_S" : { "Q14.2" : { "Q14.1" : { "UNNAMED_20_NMOSFETVMT3_I61_G" : { "R83.2" : { "R83.1" : { "ENB3V_SEQ_K" : { "U1_CPLD.M16" : {}, "R7_CPLD.1" : { "R7_CPLD.2" : { "GND" : {} } }, "R80.2" : { "R80.1" : { "GND" : {} } } } } } } }, "Q14.3" : { "UNNAMED_20_FERRITEBEAD_I72_A" : { "R82.2" : { "R82.1" : { "P5VSB" : {} } }, "FB9.1" : { "FB9.2" : { "UNNAMED_20_FERRITEBEAD_I72_B" : { "P6.2" : {} } } } } } }, "R81.2" : { "R81.1" : { "GND" : {} } } }, "PCIE1_CLKREQ_XF" : { "U1_XF.BE17" : {} }, "VS_DIMM_VTT_LIN_SD" : { "U2_SD_XF.5" : {}, "NS3_SD_XF.2" : { "NS3_SD_XF.1" : { "PWR_SDIMM_VTT_XF" : {} } }, "R4_SD_XF.1" : { "R4_SD_XF.2" : { "VMON_SDIMM_VTT_LIN" : { "R94.2" : { "R94.1" : { "UNNAMED_4_MAX116XXQSOP16_I97_AIN4" : { "C45.1" : { "C45.2" : { "GND" : {} } }, "U11.9" : {} } } } } } } }, "AC_OCL3_PET_N<1>_XF" : { "C280_XF.1" : { "C280_XF.2" : { "OCL3_PET_N<1>_XF" : { "J1_O3_XF.B7" : {} } } }, "U1_XF.BH8" : {} }, "SP_REF_CLK_P<0>" : { "SPARE_TP_P.1" : {}, "U1.51" : {} }, "CKI_LTM4675_SD" : { "PM4_SD_XF.E5" : { "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } }, "U1_CPLD.C9" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } } } }, "C3_DDR4_ADR<5>_XF" : { "U1_XF.R27" : {}, "J4_XF.213" : {} }, "UNNAMED_3_LT3071_I32_PWRGD_FL" : { "U3_FL_XF.2" : {}, "R70_FL_XF.1" : { "R70_FL_XF.2" : { "POK_OD_AVCC_RS_RLC_LIN" : { "U1_CPLD.N10" : {} } } } }, "PCIE1_RXN<6>_XF" : { "J2_P1_XF.A16" : {}, "U1_XF.AU1" : {} }, "C3_DDR4_DQ<54>_XF" : { "U1_XF.D17" : {}, "J4_XF.124" : {} }, "C2_DDR4_DQ<27>_XF" : { "U1_XF.H53" : {}, "J3_XF.190" : {} }, "OCL0_CONN_REFCLK_P_XF" : { "C356_XF.2" : { "C356_XF.1" : { "AC_OCL0_CONN_REFCLK_P_XF" : { "U7_XF.13" : {} } } }, "J1_O0_XF.B12" : {} }, "E1S2_PER_P<2>_XF" : { "U1_XF.Y4" : {}, "J1_E2_XF.A24" : {} }, "VS_AVTT_LIN_P_XF" : { "NS8_FL_XF.2" : { "NS8_FL_XF.1" : { "PWR_AVTT_RN_XF" : {} } }, "U4_FL_XF.19" : {}, "R36_SP_XF.2" : { "R36_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I150_A_SP" : { "U1_SP_XF.49" : {}, "C24_SP_XF.1" : { "C24_SP_XF.2" : { "GND" : {} } } } } } }, "C2_DDR4_DQ<13>_XF" : { "J3_XF.159" : {}, "U1_XF.T50" : {} }, "E1S2_FPGA_REFCLK_N<1>_XF" : { "R195_XF.2" : { "R195_XF.1" : { "E1S2_FPGA_REFCLK_P<1>_XF" : {} } }, "C22_E2_XF.2" : { "C22_E2_XF.1" : { "AC_FPGA_CLK_REF_N<1>_3" : { "U1_E2_XF.28" : {} } } }, "R187_XF.2" : { "R187_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_XF.AA14" : {}, "R196_XF.1" : { "R196_XF.2" : { "GND" : {} } } }, "UNNAMED_4_PI6CB33401_I37_SCLK_E1" : { "R11_E1_XF.2" : { "R11_E1_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E1_XF.9" : {} }, "PCIE0_RXP<7>_XF" : { "J2_P0_XF.A18" : {}, "U1_XF.BC2" : {} }, "UNNAMED_4_LT3071_I30_V00_FL" : { "U6_FL_XF.23" : {}, "R23_FL_XF.1" : { "R23_FL_XF.2" : { "P3R3V" : {} } }, "R6_FL_XF.2" : { "R6_FL_XF.1" : { "GND" : {} } } }, "E1S0_PET_N<2>_XF" : { "J1_E0_XF.B23" : {}, "C127_XF.2" : { "C127_XF.1" : { "AC_E1S0_PET_N<2>_XF" : { "U1_XF.A10" : {} } } } }, "C1_DDR4_ADR<3>_XF" : { "J2_XF.71" : {}, "U1_XF.CA50" : {} }, "AC_OCL2_PET_P<2>_XF" : { "U1_XF.BL11" : {}, "C236_XF.1" : { "C236_XF.2" : { "OCL2_PET_P<2>_XF" : { "J1_O2_XF.B15" : {} } } } }, "E1S1_3R3V_SDA_XF" : { "J1_E1_XF.A8" : {}, "R4_E1_XF.2" : { "R4_E1_XF.1" : { "P3R3V" : {} } }, "U1_XF.AG18" : {}, "R185_XF.2" : { "R185_XF.1" : { "PWR_FPGA_3R3V" : {} } } }, "C3_DDR4_DQ<30>_XF" : { "U1_XF.H24" : {}, "J4_XF.43" : {} }, "PCIE1_TXP<1>_XF" : { "J1_P1_XF.B6" : {}, "C32_XF.2" : { "C32_XF.1" : { "AC_PCIE1_TXP<1>_XF" : { "U1_XF.AM13" : {} } } } }, "FP_PWR_SW_N" : { "U1_CPLD.H11" : {}, "FPNL_CONN.11" : {} }, "C0_DDR4_CK_C<0>_XF" : { "U1_XF.BW16" : {}, "J1_XF.75" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I49_A_XF" : { "U1_XF.BY38" : {}, "C141_XF.1" : { "C141_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_B_XF" : { "R83_XF.2" : { "R83_XF.1" : { "UNNAMED_17_RESISTOR_I54_A_XF" : { "R74_XF.2" : { "R74_XF.1" : { "GND" : {} } }, "R75_XF.2" : { "R75_XF.1" : { "UNNAMED_17_RESISTOR_I187_B_XF" : { "R119_XF.2" : { "R119_XF.1" : { "GND" : {} } } } } } } } }, "U1_XF.CA38" : {} } } }, "R82_XF.2" : { "R82_XF.1" : { "UNNAMED_17_RESISTOR_I53_A_XF" : { "R72_XF.2" : { "R72_XF.1" : { "IMON_AVCC_LIN_XF" : { "R15_FL_XF.2" : { "R15_FL_XF.1" : { "UNNAMED_4_LT3071_I30_IMON_FL" : { "U6_FL_XF.21" : {} } } }, "R91_FL_XF.2" : { "R91_FL_XF.1" : { "UNNAMED_12_LT3071_I30_IMON_FL" : { "U10_FL_XF.21" : {} } } }, "R7_FL_XF.2" : { "R7_FL_XF.1" : { "UNNAMED_3_LT3071_I32_IMON_FL" : { "U3_FL_XF.21" : {} } } } } } }, "R73_XF.2" : { "R73_XF.1" : { "UNNAMED_17_RESISTOR_I188_B_XF" : { "R118_XF.2" : { "R118_XF.1" : { "GND" : {} } } } } } } } } }, "C3_RDIMM_DQS_T<7>_XF" : { "U1_XF.B19" : {}, "J4_XF.278" : {} }, "C0_DDR4_SA<0>_XF" : { "R19_XF.2" : { "R19_XF.1" : { "P3R3V" : {} } }, "J1_XF.139" : {} }, "UNNAMED_3_LTM4675_I40_VTRIM1CFG_ND" : { "PM4_ND_XF.H4" : { "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "UNNAMED_6_LT3071_I30_V01_FL" : { "U2_FL_XF.24" : {}, "R39_FL_XF.1" : { "R39_FL_XF.2" : { "P3R3V" : {} } }, "R61_FL_XF.2" : { "R61_FL_XF.1" : { "GND" : {} } } }, "C3_RDIMM_DQS_C<16>_XF" : { "U1_XF.B15" : {}, "J4_XF.133" : {} }, "PWR_AVTT_RLC_XF" : { "U1_XF.BE9" : {}, "C27_FL_XF.1" : { "C27_FL_XF.2" : { "GND" : {} } }, "U1_XF.AN9" : {}, "U1_XF.AU13" : {}, "U1_XF.BD11" : {}, "U1_XF.AW13" : {}, "NS3_FL_XF.1" : { "NS3_FL_XF.2" : { "VS_AVTT_RLC_LIN_FL" : {} } }, "U1_XF.BA9" : {}, "C54_FL_XF.1" : { "C54_FL_XF.2" : { "GND" : {} } }, "C470_XF.1" : { "C470_XF.2" : { "GND" : {} } }, "U1_FL_XF.15" : {}, "U1_XF.BC9" : {}, "U1_XF.BF11" : {}, "U1_FL_XF.16" : {}, "U1_XF.AR13" : {}, "C469_XF.1" : { "C469_XF.2" : { "GND" : {} } }, "C467_XF.1" : { "C467_XF.2" : { "GND" : {} } }, "C468_XF.1" : { "C468_XF.2" : { "GND" : {} } }, "U1_FL_XF.18" : {}, "U1_XF.AL13" : {}, "R268_XF.1" : { "R268_XF.2" : { "MGTRREF_LS_XF" : { "U1_XF.BE14" : {} } } }, "U1_FL_XF.17" : {}, "C53_FL_XF.1" : { "C53_FL_XF.2" : { "GND" : {} } }, "U1_XF.AR9" : {}, "U1_XF.BB11" : {}, "U1_XF.BE15" : {}, "C472_XF.1" : { "C472_XF.2" : { "GND" : {} } }, "U1_XF.AN13" : {}, "U1_XF.AU9" : {}, "C52_FL_XF.1" : { "C52_FL_XF.2" : { "GND" : {} } }, "C471_XF.1" : { "C471_XF.2" : { "GND" : {} } }, "U1_XF.AW9" : {} }, "C3_DDR4_DQ<4>_XF" : { "U1_XF.J15" : {}, "J4_XF.3" : {} }, "UNNAMED_3_RESISTOR_I70_B_E3" : { "J1_E3_XF.MH1" : {}, "J1_E3_XF.MH2" : {}, "R1_E3_XF.2" : { "R1_E3_XF.1" : { "GND" : {} } }, "J1_E3_XF.MH3" : {} }, "UNNAMED_6_LT3071_I30_PWRGD_FL" : { "R18_FL_XF.1" : { "R18_FL_XF.2" : { "POK_OD_AVTT_RS_LIN" : { "U1_CPLD.T9" : {} } } }, "U2_FL_XF.2" : {} }, "C2_DDR4_DQ<28>_XF" : { "J3_XF.36" : {}, "U1_XF.K52" : {} }, "CPLD_FPGA_DCLK_1" : { "U1_CPLD.D10" : {}, "U1_XF.BL31" : {} }, "UNNAMED_12_LT3071_I30_V02_FL" : { "R101_FL_XF.2" : { "R101_FL_XF.1" : { "GND" : {} } }, "R98_FL_XF.1" : { "R98_FL_XF.2" : { "P3R3V" : {} } }, "U10_FL_XF.25" : {} }, "E1S_REF_CLK_N<3>" : { "C17_E3_XF.1" : { "C17_E3_XF.2" : { "CLKIN_N_E3" : { "R15_E3_XF.2" : { "R15_E3_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R18_E3_XF.1" : { "R18_E3_XF.2" : { "GND" : {} } }, "U1_E3_XF.6" : {} } } }, "U1.37" : {} }, "PCIE1_RXP<4>_XF" : { "J2_P1_XF.A3" : {}, "U1_XF.AR6" : {} }, "E1S3_PET_N<0>_XF" : { "J1_E3_XF.B17" : {}, "C314_XF.2" : { "C314_XF.1" : { "AC_E1S3_PET_N<0>_XF" : { "U1_XF.AH12" : {} } } } }, "UNNAMED_3_RESISTOR_I56_B" : { "R44.2" : { "R44.1" : { "P3R3V" : {} } }, "FPNL_CONN.7" : {} }, "AC_E1S3_PET_N<6>_XF" : { "C175_XF.1" : { "C175_XF.2" : { "E1S3_PET_N<6>_XF" : { "J1_E3_XF.B36" : {} } } }, "U1_XF.AK8" : {} }, "AC_PCIE1_TXP<3>_XF" : { "U1_XF.AP9" : {}, "C30_XF.1" : { "C30_XF.2" : { "PCIE1_TXP<3>_XF" : { "J1_P1_XF.B18" : {} } } } }, "C3_DDR4_DQ<52>_XF" : { "U1_XF.E19" : {}, "J4_XF.117" : {} }, "STAT_LED_ON_F<0>_CPLD" : { "U1_CPLD.A3" : {}, "D1_CPLD.2" : { "D1_CPLD.1" : { "UNNAMED_9_598BICOLORLED_I16_L2A_CPLD" : { "R119_CPLD.1" : { "R119_CPLD.2" : { "CPLD_P3R3V" : {} } } } }, "D1_CPLD.3" : { "UNNAMED_9_598BICOLORLED_I16_L1A_CPLD" : { "R118_CPLD.1" : { "R118_CPLD.2" : { "CPLD_P3R3V" : {} } } } }, "D1_CPLD.4" : { "STAT_LED_ON_F<1>_CPLD" : { "U1_CPLD.E7" : {} } } } }, "C2_RDIMM_DQS_C<8>_XF" : { "J3_XF.196" : {}, "U1_XF.B60" : {} }, "E1S3_3R3V_SMB_RST_F_XF" : { "J1_E3_XF.A9" : {}, "U1_XF.U19" : {}, "R5_E3_XF.2" : { "R5_E3_XF.1" : { "P3R3V" : {} } } }, "OCL1_PET_P<0>_XF" : { "C232_XF.2" : { "C232_XF.1" : { "AC_OCL1_PET_P<0>_XF" : { "U1_XF.CA7" : {} } } }, "J1_O1_XF.B3" : {} }, "AC_CONN_CLK_REFN<0>_1" : { "U1_E0_XF.14" : {}, "C25_E0_XF.1" : { "C25_E0_XF.2" : { "CONN_CLK_REFN<0>_E0" : { "J1_E0_XF.B14" : {} } } } }, "CPLD_P3R3V" : { "C14_CPLD.1" : { "C14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.T1" : {}, "R117_CPLD.2" : { "R117_CPLD.1" : { "UNNAMED_9_LED_I15_A_CPLD" : {} } }, "R119_CPLD.2" : { "R119_CPLD.1" : { "UNNAMED_9_598BICOLORLED_I16_L2A_CPLD" : {} } }, "R118_CPLD.2" : { "R118_CPLD.1" : { "UNNAMED_9_598BICOLORLED_I16_L1A_CPLD" : {} } }, "U1_CPLD.J10" : {}, "U1_CPLD.K7" : {}, "U1_CPLD.N5" : {}, "C52_CPLD.2" : { "C52_CPLD.1" : { "GND" : {} } }, "C46_CPLD.2" : { "C46_CPLD.1" : { "GND" : {} } }, "C51_CPLD.2" : { "C51_CPLD.1" : { "GND" : {} } }, "C47_CPLD.2" : { "C47_CPLD.1" : { "GND" : {} } }, "U1_CPLD.A16" : {}, "U1_CPLD.T16" : {}, "R116_CPLD.2" : { "R116_CPLD.1" : { "UNNAMED_9_LED_I13_A_CPLD" : {} } }, "L2_MP.2" : { "L2_MP.1" : { "UNNAMED_4_BYPASSCAPNPOL_I12_B_MP" : { "C11_MP.2" : { "C11_MP.1" : { "UNNAMED_4_BYPASSCAPNPOL_I12_A_MP" : { "U2_MP.13" : {} } } }, "U2_MP.11" : {}, "U2_MP.12" : {}, "U2_MP.10" : {} } } }, "U1_CPLD.G7" : {}, "R14_MP.1" : { "R14_MP.2" : { "VMON_CPLD_P3R3V_SW" : {} } }, "C4_CPLD.1" : { "C4_CPLD.2" : { "GND" : {} } }, "C13_CPLD.1" : { "C13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.K9" : {}, "C5_CPLD.1" : { "C5_CPLD.2" : { "GND" : {} } }, "U1_CPLD.A1" : {}, "D4_CPLD.1" : {}, "D3_CPLD.1" : {}, "U1_CPLD.E13" : {}, "U1_CPLD.G10" : {}, "C15_CPLD.2" : { "C15_CPLD.1" : { "GND" : {} } }, "C13_MP.1" : { "C13_MP.2" : { "GND" : {} } }, "C53_CPLD.2" : { "C53_CPLD.1" : { "GND" : {} } }, "D2_CPLD.1" : {}, "C50_CPLD.2" : { "C50_CPLD.1" : { "GND" : {} } }, "U1_CPLD.N12" : {}, "U1_CPLD.H10" : {}, "C6_CPLD.1" : { "C6_CPLD.2" : { "GND" : {} } }, "U1_CPLD.K10" : {}, "C54_CPLD.2" : { "C54_CPLD.1" : { "GND" : {} } }, "C48_CPLD.2" : { "C48_CPLD.1" : { "GND" : {} } }, "C12_CPLD.1" : { "C12_CPLD.2" : { "GND" : {} } }, "C45_CPLD.2" : { "C45_CPLD.1" : { "GND" : {} } }, "R13_MP.2" : { "R13_MP.1" : { "UNNAMED_4_RESISTOR_I8_A_MP" : {} } }, "U1_CPLD.K8" : {}, "U1_CPLD.M13" : {}, "C14_MP.1" : { "C14_MP.2" : { "GND" : {} } } }, "UNNAMED_17_RESISTOR_I201_A_XF" : { "R10_XF.2" : { "R10_XF.1" : { "GND" : {} } }, "R17_XF.1" : { "R17_XF.2" : { "UNNAMED_17_RESISTOR_I196_A_XF" : { "R25_XF.1" : { "R25_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I198_A_XF" : { "C315_XF.1" : { "C315_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I198_B_XF" : { "U1_XF.BW40" : {}, "R26_XF.2" : { "R26_XF.1" : { "UNNAMED_17_RESISTOR_I199_A_XF" : { "R23_XF.2" : { "R23_XF.1" : { "UNNAMED_17_RESISTOR_I202_A_XF" : { "R13_XF.2" : { "R13_XF.1" : { "GND" : {} } } } } }, "R21_XF.2" : { "R21_XF.1" : { "GND" : {} } } } } } } } }, "U1_XF.BW39" : {} } } }, "R14_XF.2" : { "R14_XF.1" : { "IMON_VCCAUX_LIN_XF" : { "IMON_VCCAUX_TP_FL_XF.1" : {}, "R90_FL_XF.1" : { "R90_FL_XF.2" : { "UNNAMED_9_LT3071_I30_IMON_FL" : { "U7_FL_XF.21" : {}, "IMON_VCCAUX_A_TP_FL_XF.1" : {} } } }, "R113_FL_XF.1" : { "R113_FL_XF.2" : { "UNNAMED_9_LT3071_I66_IMON_FL" : { "IMON_VCCAUX_B_TP_FL_XF.1" : {}, "U11_FL_XF.21" : {} } } } } } } } } } }, "CONN_CLK_REFP<1>_E2" : { "J1_E2_XF.A15" : {}, "C20_E2_XF.2" : { "C20_E2_XF.1" : { "AC_CONN_CLK_REFP<1>_3" : { "U1_E2_XF.17" : {} } } } }, "AC_E1S3_PET_P<7>_XF" : { "C235_XF.1" : { "C235_XF.2" : { "E1S3_PET_P<7>_XF" : { "J1_E3_XF.B40" : {} } } }, "U1_XF.AJ11" : {} }, "C2_RDIMM_DQS_C<6>_XF" : { "J3_XF.266" : {}, "U1_XF.H51" : {} }, "UNNAMED_3_RESISTOR_I20_B_MP" : { "C4_MP.1" : { "C4_MP.2" : { "GND" : {} } }, "R3_MP.2" : { "R3_MP.1" : { "UNNAMED_3_RESISTOR_I20_A_MP" : { "U1_MP.7" : {} } } } }, "C1_DDR4_DQ<69>_XF" : { "U1_XF.BV58" : {}, "J2_XF.192" : {} }, "OCL1_FPGA_REFCLK_N_XF" : { "R222_XF.2" : { "R222_XF.1" : { "OCL1_FPGA_REFCLK_P_XF" : {} } }, "U1_XF.BT12" : {}, "C369_XF.2" : { "C369_XF.1" : { "AC_OCL1_FPGA_REFCLK_N_XF" : { "U7_XF.28" : {} } } }, "R223_XF.1" : { "R223_XF.2" : { "GND" : {} } }, "R213_XF.2" : { "R213_XF.1" : { "P3R3V" : {} } } }, "OCL2_3R3V_CPRSNT_F_XF" : { "U1_XF.AW17" : {}, "J1_O2_XF.A13" : {} }, "C2_DDR4_DQ<31>_XF" : { "U1_XF.G53" : {}, "J3_XF.188" : {} }, "C3_RDIMM_DQS_T<3>_XF" : { "U1_XF.H21" : {}, "J4_XF.186" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I150_A_SP" : { "R36_SP_XF.1" : { "R36_SP_XF.2" : { "VS_AVTT_LIN_P_XF" : { "NS8_FL_XF.2" : { "NS8_FL_XF.1" : { "PWR_AVTT_RN_XF" : {} } }, "U4_FL_XF.19" : {} } } }, "U1_SP_XF.49" : {}, "C24_SP_XF.1" : { "C24_SP_XF.2" : { "GND" : {} } } }, "OCL0_PER_N<1>_XF" : { "J1_O0_XF.A7" : {}, "U1_XF.BW5" : {} }, "C3_DDR4_DQ<14>_XF" : { "J4_XF.21" : {}, "U1_XF.K24" : {} }, "CONN_CLK_REFP<1>_E0" : { "J1_E0_XF.A15" : {}, "C20_E0_XF.2" : { "C20_E0_XF.1" : { "AC_CONN_CLK_REFP<1>_1" : { "U1_E0_XF.17" : {} } } } }, "PCIE0_RXN<3>_XF" : { "U1_XF.AY3" : {}, "J1_P0_XF.A19" : {} }, "E1S2_3R3V_PRSNT_F<0>_XF" : { "U1_XF.M19" : {}, "J1_E2_XF.A12" : {}, "R8_E2_XF.2" : { "R8_E2_XF.1" : { "P3R3V" : {} } } }, "CONN_CLK_REFP<0>_E1" : { "J1_E1_XF.B15" : {}, "C21_E1_XF.2" : { "C21_E1_XF.1" : { "AC_CONN_CLK_REFP<0>" : { "U1_E1_XF.13" : {} } } } }, "UNNAMED_17_RESISTOR_I41_A_XF" : { "R96_XF.1" : { "R96_XF.2" : { "GND" : {} } }, "R95_XF.1" : { "R95_XF.2" : { "GND" : {} } }, "R100_XF.2" : { "R100_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I46_B_XF" : { "C147_XF.2" : { "C147_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I46_A_XF" : { "U1_XF.BY33" : {}, "R99_XF.1" : { "R99_XF.2" : { "UNNAMED_17_RESISTOR_I40_A_XF" : { "R94_XF.1" : { "R94_XF.2" : { "GND" : {} } }, "R93_XF.1" : { "R93_XF.2" : { "VMON_AVTT_RS_LIN_XF" : { "R4_FL_XF.2" : { "R4_FL_XF.1" : { "VS_AVTT_RS_LIN_FL" : { "NS5_FL_XF.2" : { "NS5_FL_XF.1" : { "PWR_AVTT_RS_XF" : {} } }, "U2_FL_XF.19" : {} } } }, "R137_XF.2" : { "R137_XF.1" : { "UNNAMED_17_RESISTOR_I110_A_XF" : { "R138_XF.1" : { "R138_XF.2" : { "GND" : {} } }, "R129_XF.2" : { "R129_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I116_A_XF" : { "C268_XF.1" : { "C268_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I116_B_XF" : { "U1_XF.BW32" : {}, "R130_XF.1" : { "R130_XF.2" : { "UNNAMED_17_RESISTOR_I113_A_XF" : { "R141_XF.1" : { "R141_XF.2" : { "GND" : {} } }, "R139_XF.1" : { "R139_XF.2" : { "GND" : {} } } } } } } } }, "U1_XF.BW31" : {} } } } } } } } } } } } } } } }, "U1_XF.CA33" : {} } } } }, "HOST_3R3V_SCL" : { "U1_CPLD.C12" : {}, "R37.2" : { "R37.1" : { "CPLD_P1R8V_1" : {} } } }, "C3_DDR4_DQ<8>_XF" : { "J4_XF.16" : {}, "U1_XF.L27" : {} }, "C0_DDR4_DQ<3>_XF" : { "J1_XF.157" : {}, "U1_XF.BY24" : {} }, "C2_DDR4_ADR<16>_XF" : { "J3_XF.82" : {}, "U1_XF.J61" : {} }, "UNNAMED_3_RESISTOR_I28_B_MP" : { "R10_MP.2" : { "R10_MP.1" : { "UNNAMED_3_RESISTOR_I28_A_MP" : { "R1_MP.2" : { "R1_MP.1" : { "GND" : {} } } } } }, "U1_MP.8" : {} }, "E1S3_3R3V_PRSNT_F<1>_XF" : { "J1_E3_XF.B42" : {}, "U1_XF.T18" : {} }, "UNNAMED_9_BYPASSCAPNPOL_I25_B_FL" : { "C75_FL_XF.2" : { "C75_FL_XF.1" : { "GND" : {} } }, "R81_FL_XF.1" : { "R81_FL_XF.2" : { "UNNAMED_9_LT3071_I30_MARGA_FL" : { "U7_FL_XF.22" : {} } } }, "R77_FL_XF.2" : { "R77_FL_XF.1" : { "DAC_VCCAUX_LIN_XF" : { "R108_FL_XF.1" : { "R108_FL_XF.2" : { "UNNAMED_9_BYPASSCAPNPOL_I59_B_FL" : { "C104_FL_XF.2" : { "C104_FL_XF.1" : { "GND" : {} } }, "R112_FL_XF.1" : { "R112_FL_XF.2" : { "UNNAMED_9_LT3071_I66_MARGA_FL" : { "U11_FL_XF.22" : {} } } } } } }, "U1_SP_XF.54" : {} } } } }, "C2_DDR4_DQ<53>_XF" : { "J3_XF.262" : {}, "U1_XF.J50" : {} }, "C0_DDR4_DQ<6>_XF" : { "U1_XF.BY22" : {}, "J1_XF.10" : {} }, "OCL2_PET_P<1>_XF" : { "C237_XF.2" : { "C237_XF.1" : { "AC_OCL2_PET_P<1>_XF" : { "U1_XF.BM9" : {} } } }, "J1_O2_XF.B6" : {} }, "C0_RDIMM_DQS_T<11>_XF" : { "J1_XF.29" : {}, "U1_XF.BU18" : {} }, "C2_DDR4_DQ<61>_XF" : { "J3_XF.273" : {}, "U1_XF.L47" : {} }, "UNNAMED_5_LTM4650FIXED_I78_PGOOD1_SP" : { "PM5_SP_XF.G9" : { "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } } } }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.H1" : { "GND" : {} } } }, "C0_RDIMM_DQS_C<9>_XF" : { "U1_XF.CC23" : {}, "J1_XF.8" : {} }, "POK_OD_VCCINT_BRSW_P<1>" : { "U1_CPLD.R13" : {}, "R96_SP_XF.2" : { "R96_SP_XF.1" : { "UNNAMED_11_LTM4650FIXED_I150_PGOOD2_SP" : { "PM7_SP_XF.G8" : { "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.F12" : { "GND" : {} } } } } } }, "C1_DDR4_DQ<47>_XF" : { "U1_XF.BL62" : {}, "J2_XF.258" : {} }, "C2_DDR4_ALERT_N_XF" : { "J3_XF.208" : {}, "U1_XF.H57" : {}, "R247_XF.2" : { "R247_XF.1" : { "PWR_NDIMM_VDD_XF" : {} } } }, "EMC1428_ALERT_OD_F" : { "U4_SP_XF.7" : {}, "R126_SP_XF.1" : { "R126_SP_XF.2" : { "P3R3V" : {} } }, "U1_CPLD.N7" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I107_A_XF" : { "R127_XF.1" : { "R127_XF.2" : { "UNNAMED_17_RESISTOR_I101_A_XF" : { "R133_XF.1" : { "R133_XF.2" : { "IMON_AVTT_LIN_XF" : { "R24_FL_XF.2" : { "R24_FL_XF.1" : { "UNNAMED_5_LT3071_I30_IMON_FL" : { "U1_FL_XF.21" : {} } } }, "R82_FL_XF.2" : { "R82_FL_XF.1" : { "UNNAMED_8_LT3071_I30_IMON_FL" : { "R26_FL_XF.2" : { "R26_FL_XF.1" : { "GND" : {} } }, "U5_FL_XF.21" : {} } } }, "R25_FL_XF.2" : { "R25_FL_XF.1" : { "UNNAMED_6_LT3071_I30_IMON_FL" : { "U2_FL_XF.21" : {} } } }, "R64_FL_XF.2" : { "R64_FL_XF.1" : { "UNNAMED_7_LT3071_I30_IMON_FL" : { "U4_FL_XF.21" : {} } } } } } }, "R134_XF.1" : { "R134_XF.2" : { "UNNAMED_17_RESISTOR_I101_B_XF" : { "R120_XF.1" : { "R120_XF.2" : { "GND" : {} } } } } } } } }, "C267_XF.1" : { "C267_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I107_B_XF" : { "U1_XF.CC33" : {}, "R128_XF.1" : { "R128_XF.2" : { "UNNAMED_17_RESISTOR_I104_A_XF" : { "R136_XF.1" : { "R136_XF.2" : { "UNNAMED_17_RESISTOR_I105_B_XF" : { "R121_XF.1" : { "R121_XF.2" : { "GND" : {} } } } } }, "R135_XF.1" : { "R135_XF.2" : { "GND" : {} } } } } } } } }, "U1_XF.CB33" : {} }, "UNNAMED_22_RESISTOR_I42_B_XF" : { "R61_XF.2" : { "R61_XF.1" : { "GND" : {} } }, "U1_XF.BL25" : {} }, "C1_DDR4_DQ<39>_XF" : { "U1_XF.BU61" : {}, "J2_XF.247" : {} }, "E1S3_PER_N<1>_XF" : { "J1_E3_XF.A20" : {}, "U1_XF.AJ1" : {} }, "UNNAMED_4_PI6CB33401_I37_OE2F_E2" : { "U1_E2_XF.24" : {}, "U1_E2_XF.29" : {}, "R2_E2_XF.2" : { "R2_E2_XF.1" : { "GND" : {} } } }, "UNNAMED_3_LT3071_I32_V02_FL" : { "U3_FL_XF.25" : {}, "R47_FL_XF.2" : { "R47_FL_XF.1" : { "GND" : {} } }, "R45_FL_XF.1" : { "R45_FL_XF.2" : { "P3R3V" : {} } } }, "UNNAMED_7_SM050TP_I158_1_CPLD" : { "U1_CPLD.R3" : {}, "TP16_CPLD.1" : {} }, "AC_OCL2_PET_N<3>_XF" : { "C274_XF.1" : { "C274_XF.2" : { "OCL2_PET_N<3>_XF" : { "J1_O2_XF.B19" : {} } } }, "U1_XF.BK8" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I31_B_FL" : { "R11_FL_XF.2" : { "R11_FL_XF.1" : { "DAC_AVCC_LIN_XF" : { "R93_FL_XF.1" : { "R93_FL_XF.2" : { "UNNAMED_12_BYPASSCAPNPOL_I23_B_FL" : { "R94_FL_XF.1" : { "R94_FL_XF.2" : { "UNNAMED_12_LT3071_I30_MARGA_FL" : { "U10_FL_XF.22" : {} } } }, "C94_FL_XF.2" : { "C94_FL_XF.1" : { "GND" : {} } } } } }, "U1_SP_XF.57" : {}, "R21_FL_XF.1" : { "R21_FL_XF.2" : { "UNNAMED_4_BYPASSCAPNPOL_I23_B_FL" : { "C5_FL_XF.2" : { "C5_FL_XF.1" : { "GND" : {} } }, "R22_FL_XF.1" : { "R22_FL_XF.2" : { "UNNAMED_4_LT3071_I30_MARGA_FL" : { "U6_FL_XF.22" : {} } } } } } } } } }, "R12_FL_XF.1" : { "R12_FL_XF.2" : { "UNNAMED_3_LT3071_I32_MARGA_FL" : { "U3_FL_XF.22" : {} } } }, "C66_FL_XF.2" : { "C66_FL_XF.1" : { "GND" : {} } } }, "PSU_1R8V_SCL" : { "Q10.2" : { "Q10.3" : { "PSU_3R3V_SCL" : {} }, "Q10.1" : { "UNNAMED_12_NMOSFETVMT3_I4_G" : { "R8.2" : { "R8.1" : { "UNNAMED_12_RESISTOR_I13_A" : { "R4.2" : { "R4.1" : { "DIS_1R8V_I2C_XLAT_F" : { "R58.1" : { "R58.2" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } } } } } } } } } } } }, "U1_CPLD.H3" : {} } } }, "R1.2" : { "R1.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "R7.1" : { "R7.2" : { "UNNAMED_12_NMOSFETVMT3_I12_G" : { "Q11.1" : { "Q11.3" : { "PSU_3R3V_SDA" : { "R24.2" : { "R24.1" : { "P3R3V" : {} } }, "J4.2" : {} } }, "Q11.2" : { "PSU_1R8V_SDA" : { "R19.1" : { "R19.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.CA37" : {} } } } } } } } } } } } }, "U1_XF.CA35" : {}, "R9.1" : { "R9.2" : { "FPGA_VCCAUX_P1R8V" : {} } } }, "UNNAMED_7_SM050TP_I163_1_CPLD" : { "U1_CPLD.B4" : {}, "TP3_CPLD.1" : {} }, "C3_DDR4_ADR<12>_XF" : { "U1_XF.T26" : {}, "J4_XF.65" : {} }, "OCL1_PER_P<1>_XF" : { "U1_XF.BU2" : {}, "J1_O1_XF.A6" : {} }, "AC_E1S3_PET_P<0>_XF" : { "C343_XF.1" : { "C343_XF.2" : { "E1S3_PET_P<0>_XF" : { "J1_E3_XF.B18" : {} } } }, "U1_XF.AH13" : {} }, "C2_DDR4_DQ<24>_XF" : { "U1_XF.L52" : {}, "J3_XF.38" : {} }, "SW1_4650_TR_SP" : { "PM5_SP_XF.G2" : { "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } } } }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} } } }, "C3_DDR4_DQ<57>_XF" : { "U1_XF.A20" : {}, "J4_XF.275" : {} }, "C0_RDIMM_DQS_C<3>_XF" : { "U1_XF.BT22" : {}, "J1_XF.185" : {} }, "UNNAMED_4_PI6CB33401_I37_SCLK_E0" : { "R11_E0_XF.2" : { "R11_E0_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E0_XF.9" : {} }, "UNNAMED_8_LT3071_I30_EN_FL" : { "U5_FL_XF.28" : {}, "R34_FL_XF.1" : { "R34_FL_XF.2" : { "P3R3V" : {} } } }, "C1_DDR4_DQ<7>_XF" : { "U1_XF.BL51" : {}, "J2_XF.155" : {} }, "PCIE0_TXN<2>_XF" : { "J1_P0_XF.B16" : {}, "C84_XF.2" : { "C84_XF.1" : { "AC_PCIE0_TXN<2>_XF" : { "U1_XF.AV12" : {} } } } }, "C3_RDIMM_DQS_T<9>_XF" : { "U1_XF.L15" : {}, "J4_XF.7" : {} }, "AC_PCIE1_TXN<5>_XF" : { "C44_XF.1" : { "C44_XF.2" : { "PCIE1_TXN<5>_XF" : { "J2_P1_XF.B7" : {} } } }, "U1_XF.AR10" : {} }, "CLKIN_P_E2" : { "R16_E2_XF.1" : { "R16_E2_XF.2" : { "GND" : {} } }, "C16_E2_XF.2" : { "C16_E2_XF.1" : { "E1S_REF_CLK_P<2>" : { "U1.35" : {} } } }, "R17_E2_XF.1" : { "R17_E2_XF.2" : { "CLKIN_N_E2" : {} } }, "R14_E2_XF.2" : { "R14_E2_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E2_XF.5" : {} }, "UNNAMED_4_PI6CB33401_I37_PDF_E0" : { "U1_E0_XF.31" : {}, "R13_E0_XF.2" : { "R13_E0_XF.1" : { "GND" : {} } } }, "MFG_E0" : { "J1_E0_XF.B7" : {} }, "PCIE_X1_RESET_3V_F" : { "U1_CPLD.F12" : {}, "J1_PX1_XF.A11" : {} }, "UNNAMED_9_LUMEXRGBLED_I91_GREENK_CPLD" : { "D3_CPLD.4" : { "D3_CPLD.2" : { "UNNAMED_9_LUMEXRGBLED_I91_REDK_CPLD" : { "R21_CPLD.1" : { "R21_CPLD.2" : { "RGB_LED_RED<1>_CPLD" : { "U1_CPLD.D8" : {} } } } } }, "D3_CPLD.1" : { "CPLD_P3R3V" : {} }, "D3_CPLD.3" : { "UNNAMED_9_LUMEXRGBLED_I91_BLUEK_CPLD" : { "R23_CPLD.1" : { "R23_CPLD.2" : { "RGB_LED_BLUE<1>_CPLD" : { "U1_CPLD.C7" : {} } } } } } }, "R22_CPLD.1" : { "R22_CPLD.2" : { "RGB_LED_GREEN<1>_CPLD" : { "U1_CPLD.F7" : {} } } } }, "UNNAMED_3_BYPASSCAPNPOL_I149_A_SP" : { "U1_SP_XF.41" : {}, "C40_SP_XF.1" : { "C40_SP_XF.2" : { "GND" : {} } }, "R52_SP_XF.1" : { "R52_SP_XF.2" : { "IS_VCCINTLL_SW_P_SP" : { "C130_SP_XF.1" : { "C130_SP_XF.2" : { "GND" : {} } }, "R134_SP_XF.2" : { "R134_SP_XF.1" : { "GND" : {} } }, "R133_SP_XF.1" : { "R133_SP_XF.2" : { "UNNAMED_8_ACS711_I94_VIOUT_SP" : { "U6_SP_XF.11" : {} } } } } } } }, "UNNAMED_3_LTM4675_I40_VTRIM0CFG_SD" : { "PM4_SD_XF.H3" : { "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } }, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } } } }, "E1S3_3R3V_PERST_CLKREQ_F<1>_XF" : { "R7_E3_XF.2" : { "R7_E3_XF.1" : { "P3R3V" : {} } }, "J1_E3_XF.A11" : {}, "U1_XF.T21" : {} }, "C2_DDR4_DQ<45>_XF" : { "U1_XF.D54" : {}, "J3_XF.251" : {} }, "TS_1428_SPARE_N_SP" : { "TS_SP_N_SP_XF.1" : {}, "U4_SP_XF.14" : {} }, "C3_RDIMM_DQS_C<11>_XF" : { "J4_XF.30" : {}, "U1_XF.E27" : {} }, "C2_DDR4_CS_N<2>_XF" : { "U1_XF.J55" : {}, "J3_XF.93" : {} }, "AC_E1S0_PET_N<3>_XF" : { "C126_XF.1" : { "C126_XF.2" : { "E1S0_PET_N<3>_XF" : { "J1_E0_XF.B26" : {} } } }, "U1_XF.A6" : {} }, "UNNAMED_3_LTM4675_I40_COMP0B_ND" : { "PM4_ND_XF.D6" : { "PM4_ND_XF.E6" : { "UNNAMED_3_LTM4675_I40_COMP0A_ND" : {} }, "PM4_ND_XF.F5" : { "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF" : {} }, "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.H6" : { "UNNAMED_3_LTM4675_I40_COMP1A_ND" : {} }, "PM4_ND_XF.G6" : { "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF" : {} }, "PM4_ND_XF.F6" : { "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U1_CPLD.C9" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } } } } } } } } } } } } } }, "PM4_ND_XF.G5" : { "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF" : {} } }, "R108_ND_XF.1" : { "R108_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_COMP0A_ND" : {} } }, "R111_ND_XF.2" : { "R111_ND_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I28_A_ND" : { "C81_ND_XF.1" : { "C81_ND_XF.2" : { "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF" : {} } } } } }, "R109_ND_XF.1" : { "R109_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_COMP1A_ND" : {} } } }, "DIMM_EVENT_OD_F<2>" : { "J3_XF.78" : {}, "U1_CPLD.K13" : {} }, "E1S1_FPGA_REFCLK_N<0>_XF" : { "U1_XF.P12" : {}, "R169_XF.2" : { "R169_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "C23_E1_XF.2" : { "C23_E1_XF.1" : { "AC_FPGA_CLK_REF_N<0>" : { "U1_E1_XF.23" : {} } } }, "R180_XF.2" : { "R180_XF.1" : { "E1S1_FPGA_REFCLK_P<0>_XF" : {} } }, "R181_XF.1" : { "R181_XF.2" : { "GND" : {} } } }, "CPLD_FPGA_DQ<1>" : { "U1_XF.BV33" : {}, "U1_CPLD.E10" : {} }, "UNNAMED_6_BYPASSCAPNPOL_I31_A_FL" : { "U2_FL_XF.3" : {}, "C38_FL_XF.1" : { "C38_FL_XF.2" : { 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"UNNAMED_6_LTM4671_I456_PHMODE3_SP" : {} } }, "C82_SP_XF.1" : { "C82_SP_XF.2" : { "UNNAMED_6_TIMINGCAPNPOL_I426_B_SP" : {} } }, "R53_SP_XF.1" : { "R53_SP_XF.2" : { "UNNAMED_6_RESISTOR_I469_A_SP" : {} } }, "NS2_SP_XF.1" : { "NS2_SP_XF.2" : { "GND" : {} } }, "C81_SP_XF.1" : { "C81_SP_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : {} } }, "C83_SP_XF.1" : { "C83_SP_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I402_B_SP" : {} } }, "C132_SP_XF.1" : { "C132_SP_XF.2" : { "UNNAMED_6_LTM4671_I457_FB1_SP" : {} } }, "C133_SP_XF.1" : { "C133_SP_XF.2" : { "UNNAMED_6_LTM4671_I457_FB1_SP" : {} } }, "C134_SP_XF.1" : { "C134_SP_XF.2" : { "UNNAMED_6_LTM4671_I456_FB3_SP" : {} } }, "C131_SP_XF.1" : { "C131_SP_XF.2" : { "UNNAMED_6_LTM4671_I456_FB3_SP" : {} } }, "C85_SP_XF.1" : { "C85_SP_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I465_B_SP" : {} } }, "R97_SP_XF.1" : { "R97_SP_XF.2" : { "UNNAMED_6_RESISTOR_I222_A_SP" : {} } }, "R41_SP_XF.1" : { "R41_SP_XF.2" : { "UNNAMED_6_RESISTOR_I409_A_SP" : {} } }, "R43_SP_XF.1" : { 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{} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { 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"PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } } } }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} 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"PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {}, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} } } }, "UNNAMED_3_RESISTOR_I70_B_E1" : { "R1_E1_XF.2" : { "R1_E1_XF.1" : { "GND" : {} } }, "J1_E1_XF.MH3" : {}, "J1_E1_XF.MH1" : {}, "J1_E1_XF.MH2" : {} }, "CPLD_FPGA_DQ<0>" : { "U1_CPLD.B10" : {}, "U1_XF.BV34" : {} }, "LTC2975_CPLD_ENB_A" : { "U1_SP_XF.3" : {}, "U1_CPLD.K15" : {} }, "C1_RDIMM_DQS_C<13>_XF" : { "J2_XF.100" : {}, "U1_XF.BV62" : {} }, "OCL0_PET_N<0>_XF" : { "J1_O0_XF.B4" : {}, "C266_XF.2" : { "C266_XF.1" : { "AC_OCL0_PET_N<0>_XF" : { "U1_XF.CC10" : {} } } } }, "SI5341_INTR" : { "R434.2" : { "R434.1" : { "UNNAMED_10_RESISTOR_I48_A" : { "U1.12" : {} } } }, "U1_CPLD.C1" : {} }, "C3_DDR4_DQ<0>_XF" : { "J4_XF.5" : {}, "U1_XF.L17" : {} }, "SW1_4650_BL_SP" : { "PM3_SP_XF.G2" : { "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} } } } }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.G3" : { "GND" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} } } }, "C1_DDR4_CKE<0>_XF" : { "J2_XF.60" : {}, "U1_XF.CB50" : {} }, "C1_DDR4_DQ<5>_XF" : { "U1_XF.BN49" : {}, "J2_XF.148" : {} }, "PCIE1_TXP<0>_XF" : { "C33_XF.2" : { "C33_XF.1" : { "AC_PCIE1_TXP<0>_XF" : { "U1_XF.AM9" : {} } } }, "J1_P1_XF.B3" : {} }, "UNNAMED_7_LT3071_I30_V01_FL" : { "R62_FL_XF.2" : { "R62_FL_XF.1" : { "GND" : {} } }, "R40_FL_XF.1" : { "R40_FL_XF.2" : { "P3R3V" : {} } }, "U4_FL_XF.24" : {} }, "UNNAMED_4_PI6CB33401_I37_BWSELTRI_E1" : { "U1_E1_XF.1" : {}, "R10_E1_XF.2" : { "R10_E1_XF.1" : { "GND" : {} } } }, "PCIE_X1_TXP_XF" : { "J1_PX1_XF.A16" : {}, "C290_XF.2" : { "C290_XF.1" : { "AC_PCIE_X1_TXP_XF" : { "U1_XF.BF9" : {} } } } }, "C2_DDR4_CS_N<0>_XF" : { "U1_XF.H59" : {}, "J3_XF.84" : {} }, "JT_FPGA_INST_F" : { "U1_CPLD.B13" : {}, "R62.1" : { "R62.2" : { "CPLD_P1R8V_1" : {} } }, "J5.19" : {} }, "C3_RDIMM_DQS_C<0>_XF" : { "J4_XF.152" : {}, "U1_XF.K18" : {} }, "POK_OD_VCCINT_TRSW_P<0>" : { "R91_SP_XF.2" : { "R91_SP_XF.1" : { "UNNAMED_5_LTM4650FIXED_I78_PGOOD1_SP" : { "PM5_SP_XF.G9" : { "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} } } } } }, "U1_CPLD.T13" : {} }, "C2_DDR4_DQ<17>_XF" : { "J3_XF.172" : {}, "U1_XF.E62" : {} }, "E1S2_PER_P<1>_XF" : { "J1_E2_XF.A21" : {}, "U1_XF.AA2" : {} }, "AC_E1S0_PET_P<7>_XF" : { "U1_XF.C11" : {}, "C102_XF.1" : { "C102_XF.2" : { "E1S0_PET_P<7>_XF" : { "J1_E0_XF.B40" : {} } } } }, "C3_DDR4_ADR<11>_XF" : { "U1_XF.T27" : {}, "J4_XF.210" : {} }, "E1S_REF_CLK_P<0>" : { "U1.28" : {}, "C16_E0_XF.1" : { "C16_E0_XF.2" : { "CLKIN_P_E0" : { "R14_E0_XF.2" : { "R14_E0_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E0_XF.5" : {}, "R16_E0_XF.1" : { "R16_E0_XF.2" : { "GND" : {} } } } } } }, "IS_VCCINTUR_SW_N_SP" : { "R45_SP_XF.2" : { "R45_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I27_A_SP" : { "U1_SP_XF.48" : {}, "C65_SP_XF.1" : { "C65_SP_XF.2" : { "GND" : {} } } } } }, "R190_SP_XF.2" : { "R190_SP_XF.1" : { "GND" : {} } }, "C180_SP_XF.1" : { "C180_SP_XF.2" : { "GND" : {} } }, "R189_SP_XF.1" : { "R189_SP_XF.2" : { "P3R3V" : {} } } }, "AC_E1S0_PET_N<6>_XF" : { "C119_XF.1" : { "C119_XF.2" : { "E1S0_PET_N<6>_XF" : { "J1_E0_XF.B36" : {} } } }, "U1_XF.D8" : {} }, "C1_DDR4_ADR<7>_XF" : { "U1_XF.CB53" : {}, "J2_XF.211" : {} }, "UNNAMED_7_SM050TP_I167_1_CPLD" : { "U1_CPLD.N1" : {}, "TP8_CPLD.1" : {} }, "C1_DDR4_ADR<13>_XF" : { "J2_XF.232" : {}, "U1_XF.BY58" : {} }, "UNNAMED_12_BYPASSCAPNPOL_I23_B_FL" : { "C94_FL_XF.2" : { "C94_FL_XF.1" : { "GND" : {} } }, "R94_FL_XF.1" : { "R94_FL_XF.2" : { "UNNAMED_12_LT3071_I30_MARGA_FL" : { "U10_FL_XF.22" : {} } } }, "R93_FL_XF.2" : { "R93_FL_XF.1" : { "DAC_AVCC_LIN_XF" : { "U1_SP_XF.57" : {}, "R11_FL_XF.1" : { "R11_FL_XF.2" : { "UNNAMED_3_BYPASSCAPNPOL_I31_B_FL" : { "C66_FL_XF.2" : { "C66_FL_XF.1" : { "GND" : {} } }, "R12_FL_XF.1" : { "R12_FL_XF.2" : { "UNNAMED_3_LT3071_I32_MARGA_FL" : { "U3_FL_XF.22" : {} } } } } } }, "R21_FL_XF.1" : { "R21_FL_XF.2" : { "UNNAMED_4_BYPASSCAPNPOL_I23_B_FL" : { "C5_FL_XF.2" : { "C5_FL_XF.1" : { "GND" : {} } }, "R22_FL_XF.1" : { "R22_FL_XF.2" : { "UNNAMED_4_LT3071_I30_MARGA_FL" : { "U6_FL_XF.22" : {} } } } } } } } } } }, "UNNAMED_3_BYPASSCAPNPOL_I154_A_SP" : { "R25_SP_XF.1" : { "R25_SP_XF.2" : { "VS_VCCAUX_LIN_P_XF" : { "NS12_FL_XF.2" : { "NS12_FL_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "C15_SP_XF.1" : { "C15_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.63" : {} }, "SI5341_SYNC_N" : { "U1.5" : {}, "U1_CPLD.E3" : {} }, "C2_DDR4_CS_N<1>_XF" : { "U1_XF.J57" : {}, "J3_XF.89" : {} }, "C3_DDR4_ADR<10>_XF" : { "U1_XF.L23" : {}, "J4_XF.225" : {} }, "UNNAMED_29_RESISTOR_I15_B_XF" : { "U6_XF.1" : {}, "U6_XF.8" : {}, "U6_XF.2" : {}, "U6_XF.3" : {}, "R5_XF.2" : { "R5_XF.1" : { "PWR_FPGA_3R3V" : {} } } }, "C1_RDIMM_DQS_C<10>_XF" : { "J2_XF.19" : {}, "U1_XF.BU51" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I2_B_SP" : { "U1_SP_XF.13" : {}, "C50_SP_XF.2" : { "C50_SP_XF.1" : { "GND" : {} } }, "U1_SP_XF.14" : {} }, "POK_OD_VCCAUX_A_LIN" : { "R55_FL_XF.2" : { "R55_FL_XF.1" : { "UNNAMED_9_LT3071_I30_PWRGD_FL" : { "U7_FL_XF.2" : {} } } }, "U1_CPLD.M8" : {} }, "E1S0_PET_N<1>_XF" : { "J1_E0_XF.B20" : {}, "C128_XF.2" : { "C128_XF.1" : { "AC_E1S0_PET_N<1>_XF" : { "U1_XF.B8" : {} } } } }, "C3_RDIMM_DQS_C<1>_XF" : { "J4_XF.163" : {}, "U1_XF.L25" : {} }, "UNNAMED_3_LTC2975_I168_SHARECLK_SP" : { "R120_SP_XF.2" : { "R120_SP_XF.1" : { "P3R3V" : {} } }, "U1_SP_XF.18" : {} }, "C2_DDR4_DQ<23>_XF" : { "U1_XF.F60" : {}, "J3_XF.177" : {} }, "C2_DDR4_ADR<14>_XF" : { "J3_XF.228" : {}, "U1_XF.K60" : {} }, "OCL3_PER_N<0>_XF" : { "U1_XF.BJ5" : {}, "J1_O3_XF.A4" : {} }, "C2_DDR4_DQ<58>_XF" : { "U1_XF.K48" : {}, "J3_XF.137" : {} }, "C2_DDR4_BA<0>_XF" : { "U1_XF.H63" : {}, "J3_XF.81" : {} }, "UNNAMED_15_MAX4641_I1_NO2_XF" : { "U4_XF.5" : {}, "U2_XF.C2" : {}, "R66_XF.1" : { "R66_XF.2" : { "FPGA_VCCAUX_P1R8V" : {} } } }, "UNNAMED_7_LTM4671_I36_FREQ3_SP" : { "PM1_SP_XF.P8" : { "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {} } }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} } } }, "PCIE1_TXP<6>_XF" : { "J2_P1_XF.B15" : {}, "C27_XF.2" : { "C27_XF.1" : { "AC_PCIE1_TXP<6>_XF" : { "U1_XF.AT9" : {} } } } }, "E1S2_PET_P<4>_XF" : { "J1_E2_XF.B31" : {}, "C151_XF.2" : { "C151_XF.1" : { "AC_E1S2_PET_P<4>_XF" : { "U1_XF.AC11" : {} } } } }, "E1S1_PER_P<0>_XF" : { "U1_XF.P4" : {}, "J1_E1_XF.A18" : {} }, "UNNAMED_17_RESISTOR_I215_B_XF" : { "R63_XF.1" : { "R63_XF.2" : { "GND" : {} } }, "R70_XF.1" : { "R70_XF.2" : { "GND" : {} } }, "R69_XF.2" : { "R69_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I216_B_XF" : { "C316_XF.2" : { "C316_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I216_A_XF" : { "R68_XF.1" : { "R68_XF.2" : { "UNNAMED_17_RESISTOR_I214_B_XF" : { "R39_XF.1" : { "R39_XF.2" : { "VMON_AVCC_RUC_LIN_XF" : { "R102_FL_XF.2" : { "R102_FL_XF.1" : { "VS_AVCC_RUC_LIN_FL" : { "U10_FL_XF.19" : {}, "NS1_FL_XF.2" : { "NS1_FL_XF.1" : { "PWR_AVCC_RUC_XF" : {} } } } } } } } }, "R62_XF.1" : { "R62_XF.2" : { "GND" : {} } } } } }, "U1_XF.CA40" : {} } } }, "U1_XF.CB40" : {} } } } }, "C0_RDIMM_DQS_C<5>_XF" : { "J1_XF.255" : {}, "U1_XF.BP26" : {} }, "OCL0_FPGA_REFCLK_P_XF" : { "R219_XF.1" : { "R219_XF.2" : { "OCL0_FPGA_REFCLK_N_XF" : {} } }, "R218_XF.1" : { "R218_XF.2" : { "GND" : {} } }, "C354_XF.2" : { "C354_XF.1" : { "AC_OCL0_FPGA_REFCLK_P_XF" : { "U7_XF.22" : {} } } }, "U1_XF.CB13" : {}, "R210_XF.2" : { "R210_XF.1" : { "P3R3V" : {} } } }, "PCIE0_RXP<5>_XF" : { "J2_P0_XF.A6" : {}, "U1_XF.BA6" : {} }, "C1_DDR4_CKE<1>_XF" : { "U1_XF.CC51" : {}, "J2_XF.203" : {} }, "SP_REF_CLK_N<0>" : { "SPARE_TP_N.1" : {}, "U1.50" : {} }, "PCIE1_RXN<1>_XF" : { "U1_XF.AN5" : {}, "J1_P1_XF.A7" : {} }, "UNNAMED_3_598BICOLORLED_I68_L2C" : { "S2.2" : { "S2.1" : { "GND" : {} }, "S2.4" : { "GND" : {} }, "S2.3" : { "FP_RST_SW_N" : {} } }, "D1.2" : { "D1.3" : { "FP_RST_SW_N" : { "R78.2" : { "R78.1" : { "P3R3V" : {} } }, "U1_CPLD.J13" : {}, "FPNL_CONN.15" : {} } }, "D1.1" : { "UNNAMED_3_598BICOLORLED_I68_L2A" : { "R79.2" : { "R79.1" : { "P3R3V" : {} } } } }, "D1.4" : { "GND" : {} } } }, "C0_RDIMM_DQS_T<15>_XF" : { "U1_XF.BJ25" : {}, "J1_XF.121" : {} }, "PCIE0_WAKE_F_XF" : { "J1_P0_XF.B10" : {}, "U1_XF.BD17" : {} }, "PCIE0_TXN<7>_XF" : { "J2_P0_XF.B19" : {}, "C50_XF.2" : { "C50_XF.1" : { "AC_PCIE0_TXN<7>_XF" : { "U1_XF.BC10" : {} } } } }, "C3_DDR4_DQ<22>_XF" : { "U1_XF.F26" : {}, "J4_XF.32" : {} }, "E1S0_PER_N<4>_XF" : { "U1_XF.J1" : {}, "J1_E0_XF.A30" : {} }, "CPLD_TDI_PIN_CPLD" : { "R17_CPLD.2" : { "R17_CPLD.1" : { "UNNAMED_8_1G97_I16_Y_CPLD" : { "U3_CPLD.4" : {} } } }, "U1_CPLD.A6" : {} }, "UNNAMED_7_LTM4671_I36_RUN3_SP" : { "PM1_SP_XF.P7" : { "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} } } } } } } }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} } } }, "UNNAMED_6_LT3071_I30_EN_FL" : { "U2_FL_XF.28" : {}, "R30_FL_XF.1" : { "R30_FL_XF.2" : { "P3R3V" : {} } } }, "FPGA_P1R8V_TMS" : { "U1_CPLD.F3" : {}, "U1_XF.AP17" : {} }, "AC_CONN_CLK_REFN<1>_2" : { "U1_E3_XF.18" : {}, "C24_E3_XF.1" : { "C24_E3_XF.2" : { "CONN_CLK_REFN<1>_E3" : { "J1_E3_XF.A14" : {} } } } }, "C3_RDIMM_DQS_T<5>_XF" : { "J4_XF.256" : {}, "U1_XF.D22" : {} }, "C0_DDR4_ACT_N_XF" : { "U1_XF.BU20" : {}, "J1_XF.62" : {} }, "C0_DDR4_DQ<29>_XF" : { "J1_XF.181" : {}, "U1_XF.BV23" : {} }, "UNNAMED_5_LTM4650FIXED_I78_MODEPLLIN_SP" : { "PM5_SP_XF.F4" : { "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } } } }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.G12" : { "GND" : {} } } }, "AC_E1S3_PET_N<3>_XF" : { "U1_XF.AF12" : {}, "C328_XF.1" : { "C328_XF.2" : { "E1S3_PET_N<3>_XF" : { "J1_E3_XF.B26" : {} } } } }, "C0_DDR4_DQ<16>_XF" : { "U1_XF.BT17" : {}, "J1_XF.27" : {} }, "VMON_SDIMM_VTT_LIN" : { "R4_SD_XF.2" : { "R4_SD_XF.1" : { "VS_DIMM_VTT_LIN_SD" : { "U2_SD_XF.5" : {}, "NS3_SD_XF.2" : { "NS3_SD_XF.1" : { "PWR_SDIMM_VTT_XF" : {} } } } } }, "R94.2" : { "R94.1" : { "UNNAMED_4_MAX116XXQSOP16_I97_AIN4" : { "C45.1" : { "C45.2" : { "GND" : {} } }, "U11.9" : {} } } } }, "AC_FPGA_CLK_REF_N<0>_3" : { "C23_E2_XF.1" : { "C23_E2_XF.2" : { "E1S2_FPGA_REFCLK_N<0>_XF" : { "U1_XF.W14" : {}, "R189_XF.2" : { "R189_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R199_XF.1" : { "R199_XF.2" : { "GND" : {} } } } } }, "U1_E2_XF.23" : {} }, "UNNAMED_4_CAPACITOR_I64_B_SP" : { "R61_SP_XF.1" : { "R61_SP_XF.2" : { "VFB_4650_SP" : { "PM4_SP_XF.D5" : { "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} } }, "R11_SP_XF.2" : { "R11_SP_XF.1" : { "UNNAMED_4_RESISTOR_I12_B_SP" : { "R12_SP_XF.2" : { "R12_SP_XF.1" : { "SGND_PM4_SP" : {} } } } } } } } }, "C4_SP_XF.2" : { "C4_SP_XF.1" : { "SGND_PM4_SP" : {} } }, "R3_SP_XF.2" : { "R3_SP_XF.1" : { "DAC_VCCINT_SP" : { "U1_SP_XF.53" : {} } } } }, "FPGA_REF_CLK_P" : { "U1_XF.BN32" : {}, "U1.54" : {} }, "E1S0_PER_N<0>_XF" : { "U1_XF.F3" : {}, "J1_E0_XF.A17" : {} }, "AC_OCL2_PET_P<0>_XF" : { "C238_XF.1" : { "C238_XF.2" : { "OCL2_PET_P<0>_XF" : { "J1_O2_XF.B3" : {} } } }, "U1_XF.BN11" : {} }, "VMON_NDIMM_VPP_SW" : { "R123_SP_XF.2" : { "R123_SP_XF.1" : { "PWR_NDIMM_VPP_XF" : {} } }, "R54.2" : { "R54.1" : { "UNNAMED_4_MAX116XXQSOP16_I97_AIN5" : { "C43.1" : { "C43.2" : { "GND" : {} } }, "U11.10" : {}, "R76.1" : { "R76.2" : { "GND" : {} } } } } } }, "UNNAMED_15_MAX4641_I1_NO1_XF" : { "U3_XF.C2" : {}, "R65_XF.2" : { "R65_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "R117_XF.2" : { "R117_XF.1" : { "CFG_FLASH_RDWR_FCS_B_0_XF" : { "U4_XF.6" : {}, "R11_XF.2" : { "R11_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.AN17" : {}, "U4_XF.2" : {} } } }, "U4_XF.1" : {} }, "AC_FPGA_CLK_REF_P<1>_2" : { "U1_E3_XF.27" : {}, "C18_E3_XF.1" : { "C18_E3_XF.2" : { "E1S3_FPGA_REFCLK_P<1>_XF" : { "R200_XF.1" : { "R200_XF.2" : { "GND" : {} } }, "U1_XF.AN15" : {}, "R190_XF.2" : { "R190_XF.1" : { "PWR_FPGA_3R3V" : {} } } } } } }, "UNNAMED_8_LT3071_I30_VIOC_FL" : { "C37_FL_XF.1" : { "C37_FL_XF.2" : { "GND" : {} } }, "U5_FL_XF.1" : {} }, "UNNAMED_6_LTM4671_I457_COMP1_SP" : { "PM2_SP_XF.J11" : { "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : {} } } } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} } } }, "UNNAMED_17_RESISTOR_I104_A_XF" : { "R128_XF.2" : { "R128_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I107_B_XF" : { "C267_XF.2" : { "C267_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I107_A_XF" : { "R127_XF.1" : { "R127_XF.2" : { "UNNAMED_17_RESISTOR_I101_A_XF" : { "R133_XF.1" : { "R133_XF.2" : { "IMON_AVTT_LIN_XF" : { "R24_FL_XF.2" : { "R24_FL_XF.1" : { "UNNAMED_5_LT3071_I30_IMON_FL" : { "U1_FL_XF.21" : {} } } }, "R64_FL_XF.2" : { "R64_FL_XF.1" : { "UNNAMED_7_LT3071_I30_IMON_FL" : { "U4_FL_XF.21" : {} } } }, "R82_FL_XF.2" : { "R82_FL_XF.1" : { "UNNAMED_8_LT3071_I30_IMON_FL" : { "U5_FL_XF.21" : {}, "R26_FL_XF.2" : { "R26_FL_XF.1" : { "GND" : {} } } } } }, "R25_FL_XF.2" : { "R25_FL_XF.1" : { "UNNAMED_6_LT3071_I30_IMON_FL" : { "U2_FL_XF.21" : {} } } } } } }, "R134_XF.1" : { "R134_XF.2" : { "UNNAMED_17_RESISTOR_I101_B_XF" : { "R120_XF.1" : { "R120_XF.2" : { "GND" : {} } } } } } } } }, "U1_XF.CB33" : {} } } }, "U1_XF.CC33" : {} } } }, "R135_XF.1" : { "R135_XF.2" : { "GND" : {} } }, "R136_XF.1" : { "R136_XF.2" : { "UNNAMED_17_RESISTOR_I105_B_XF" : { "R121_XF.1" : { "R121_XF.2" : { "GND" : {} } } } } } }, "C1_DDR4_DQ<2>_XF" : { "J2_XF.12" : {}, "U1_XF.BP52" : {} }, "AC_E1S0_PET_P<0>_XF" : { "U1_XF.C7" : {}, "C109_XF.1" : { "C109_XF.2" : { "E1S0_PET_P<0>_XF" : { "J1_E0_XF.B18" : {} } } } }, "C1_DDR4_ADR<2>_XF" : { "U1_XF.BW55" : {}, "J2_XF.216" : {} }, "UNNAMED_7_SM050TP_I168_1_CPLD" : { "TP2_CPLD.1" : {}, "U1_CPLD.P1" : {} }, "E1S2_PET_P<0>_XF" : { "C155_XF.2" : { "C155_XF.1" : { "AC_E1S2_PET_P<0>_XF" : { "U1_XF.W11" : {} } } }, "J1_E2_XF.B18" : {} }, "E1S1_PER_P<4>_XF" : { "J1_E1_XF.A31" : {}, "U1_XF.V4" : {} }, "C3_RDIMM_DQS_C<15>_XF" : { "J4_XF.122" : {}, "U1_XF.E18" : {} }, "C2_DDR4_DQ<12>_XF" : { "U1_XF.R50" : {}, "J3_XF.14" : {} }, "UNNAMED_17_RESISTOR_I40_A_XF" : { "R94_XF.1" : { "R94_XF.2" : { "GND" : {} } }, "R99_XF.2" : { "R99_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I46_A_XF" : { "U1_XF.BY33" : {}, "C147_XF.1" : { "C147_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I46_B_XF" : { "R100_XF.1" : { "R100_XF.2" : { "UNNAMED_17_RESISTOR_I41_A_XF" : { "R96_XF.1" : { "R96_XF.2" : { "GND" : {} } }, "R95_XF.1" : { "R95_XF.2" : { "GND" : {} } } } } }, "U1_XF.CA33" : {} } } } } } }, "R93_XF.1" : { "R93_XF.2" : { "VMON_AVTT_RS_LIN_XF" : { "R4_FL_XF.2" : { "R4_FL_XF.1" : { "VS_AVTT_RS_LIN_FL" : { "NS5_FL_XF.2" : { "NS5_FL_XF.1" : { "PWR_AVTT_RS_XF" : {} } }, "U2_FL_XF.19" : {} } } }, "R137_XF.2" : { "R137_XF.1" : { "UNNAMED_17_RESISTOR_I110_A_XF" : { "R138_XF.1" : { "R138_XF.2" : { "GND" : {} } }, "R129_XF.2" : { "R129_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I116_A_XF" : { "U1_XF.BW31" : {}, "C268_XF.1" : { "C268_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I116_B_XF" : { "U1_XF.BW32" : {}, "R130_XF.1" : { "R130_XF.2" : { "UNNAMED_17_RESISTOR_I113_A_XF" : { "R139_XF.1" : { "R139_XF.2" : { "GND" : {} } }, "R141_XF.1" : { "R141_XF.2" : { "GND" : {} } } } } } } } } } } } } } } } } } }, "FPGA_CFG_PUDC_F_XF" : { "R35_XF.2" : { "R35_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.AL17" : {} }, "C3_DDR4_DQ<27>_XF" : { "J4_XF.190" : {}, "U1_XF.F21" : {} }, "PCIE_X1_RST_F" : { "U1_XF.BE19" : {}, "U1_CPLD.F15" : {} }, "C2_DDR4_DQ<54>_XF" : { "U1_XF.H48" : {}, "J3_XF.124" : {} }, "CPLD_SELF_TMS_CPLD" : { "U1_CPLD.C13" : {}, "U2_CPLD.3" : {} }, "C1_DDR4_DQ<15>_XF" : { "U1_XF.BV51" : {}, "J2_XF.166" : {} }, "PWR_AVTT_RS_XF" : { "U1_XF.BH11" : {}, "U1_XF.BM11" : {}, "U1_XF.BN9" : {}, "C123_XF.1" : { "C123_XF.2" : { "GND" : {} } }, "U1_XF.BY11" : {}, "C480_XF.1" : { "C480_XF.2" : { "GND" : {} } }, "C483_XF.1" : { "C483_XF.2" : { "GND" : {} } }, "U2_FL_XF.17" : {}, "C56_FL_XF.1" : { "C56_FL_XF.2" : { "GND" : {} } }, "U1_XF.BG9" : {}, "U1_XF.BK11" : {}, "C62_FL_XF.1" : { "C62_FL_XF.2" : { "GND" : {} } }, "NS5_FL_XF.1" : { "NS5_FL_XF.2" : { "VS_AVTT_RS_LIN_FL" : {} } }, "U1_XF.BL9" : {}, "U2_FL_XF.15" : {}, "U2_FL_XF.16" : {}, "U1_XF.BR9" : {}, "U1_XF.CA9" : {}, "U1_XF.BT11" : {}, "C59_FL_XF.1" : { "C59_FL_XF.2" : { "GND" : {} } }, "U2_FL_XF.18" : {}, "R147_XF.1" : { "R147_XF.2" : { "AVTT_RS_BNC_XF" : { "J10_XF.C" : {} } } }, "C32_FL_XF.1" : { "C32_FL_XF.2" : { "GND" : {} } }, "U1_XF.BW9" : {}, "R270_XF.2" : { "R270_XF.1" : { "MGTRREF_RS_XF" : { "U1_XF.BV12" : {} } } }, "U1_XF.BV11" : {}, "U1_XF.BP11" : {}, "C482_XF.1" : { "C482_XF.2" : { "GND" : {} } }, "U1_XF.BV13" : {}, "U1_XF.BJ9" : {}, "U1_XF.BU9" : {}, "C484_XF.1" : { "C484_XF.2" : { "GND" : {} } }, "C481_XF.1" : { "C481_XF.2" : { "GND" : {} } } }, "C2_DDR4_DQ<60>_XF" : { "J3_XF.128" : {}, "U1_XF.L48" : {} }, "UNNAMED_17_RESISTOR_I188_B_XF" : { "R118_XF.2" : { "R118_XF.1" : { "GND" : {} } }, "R73_XF.1" : { "R73_XF.2" : { "UNNAMED_17_RESISTOR_I53_A_XF" : { "R72_XF.2" : { "R72_XF.1" : { "IMON_AVCC_LIN_XF" : { "R15_FL_XF.2" : { "R15_FL_XF.1" : { "UNNAMED_4_LT3071_I30_IMON_FL" : { "U6_FL_XF.21" : {} } } }, "R91_FL_XF.2" : { "R91_FL_XF.1" : { "UNNAMED_12_LT3071_I30_IMON_FL" : { "U10_FL_XF.21" : {} } } }, "R7_FL_XF.2" : { "R7_FL_XF.1" : { "UNNAMED_3_LT3071_I32_IMON_FL" : { "U3_FL_XF.21" : {} } } } } } }, "R82_XF.1" : { "R82_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_A_XF" : { "C141_XF.1" : { "C141_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_B_XF" : { "U1_XF.CA38" : {}, "R83_XF.2" : { "R83_XF.1" : { "UNNAMED_17_RESISTOR_I54_A_XF" : { "R74_XF.2" : { "R74_XF.1" : { "GND" : {} } }, "R75_XF.2" : { "R75_XF.1" : { "UNNAMED_17_RESISTOR_I187_B_XF" : { "R119_XF.2" : { "R119_XF.1" : { "GND" : {} } } } } } } } } } } }, "U1_XF.BY38" : {} } } } } } } }, "C0_RDIMM_DQS_T<0>_XF" : { "J1_XF.153" : {}, "U1_XF.CA23" : {} }, "C2_DDR4_ADR<5>_XF" : { "U1_XF.L58" : {}, "J3_XF.213" : {} }, "E1S0_FPGA_REFCLK_P<0>_XF" : { "U1_XF.D13" : {}, "R174_XF.1" : { "R174_XF.2" : { "E1S0_FPGA_REFCLK_N<0>_XF" : {} } }, "R163_XF.2" : { "R163_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "C19_E0_XF.2" : { "C19_E0_XF.1" : { "AC_FPGA_CLK_REF_P<0>_1" : { "U1_E0_XF.22" : {} } } }, "R173_XF.1" : { "R173_XF.2" : { "GND" : {} } } }, "C0_RDIMM_DQS_T<1>_XF" : { "J1_XF.164" : {}, "U1_XF.BY27" : {} }, "UNNAMED_10_RESISTOR_I48_A" : { "U1.12" : {}, "R434.1" : { "R434.2" : { "SI5341_INTR" : { "U1_CPLD.C1" : {} } } } }, "OCL3_PET_N<1>_XF" : { "C280_XF.2" : { "C280_XF.1" : { "AC_OCL3_PET_N<1>_XF" : { "U1_XF.BH8" : {} } } }, "J1_O3_XF.B7" : {} }, "UNNAMED_7_LTM4671_I36_FB3_SP" : { "PM1_SP_XF.N10" : { "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} } } } } } } }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} } } }, "PCIE1_REFP_XF" : { "R1_P1_XF.2" : { "R1_P1_XF.1" : { "UNNAMED_3_OCULINKX4CONN_I86_REFCLKP_P1" : { "J1_P1_XF.B12" : {} } } }, "C230_XF.1" : { "C230_XF.2" : { "AC_PCIE1_REFP_XF" : { "U1_XF.AU15" : {} } } } }, "UNNAMED_6_LT3071_I30_IMON_FL" : { "R25_FL_XF.1" : { "R25_FL_XF.2" : { "IMON_AVTT_LIN_XF" : { "R133_XF.2" : { "R133_XF.1" : { "UNNAMED_17_RESISTOR_I101_A_XF" : { "R127_XF.2" : { "R127_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I107_A_XF" : { "C267_XF.1" : { "C267_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I107_B_XF" : { "U1_XF.CC33" : {}, "R128_XF.1" : { "R128_XF.2" : { "UNNAMED_17_RESISTOR_I104_A_XF" : { "R135_XF.1" : { "R135_XF.2" : { "GND" : {} } }, "R136_XF.1" : { "R136_XF.2" : { "UNNAMED_17_RESISTOR_I105_B_XF" : { "R121_XF.1" : { "R121_XF.2" : { "GND" : {} } } } } } } } } } } }, "U1_XF.CB33" : {} } } }, "R134_XF.1" : { "R134_XF.2" : { "UNNAMED_17_RESISTOR_I101_B_XF" : { "R120_XF.1" : { "R120_XF.2" : { "GND" : {} } } } } } } } }, "R24_FL_XF.2" : { "R24_FL_XF.1" : { "UNNAMED_5_LT3071_I30_IMON_FL" : { "U1_FL_XF.21" : {} } } }, "R64_FL_XF.2" : { "R64_FL_XF.1" : { "UNNAMED_7_LT3071_I30_IMON_FL" : { "U4_FL_XF.21" : {} } } }, "R82_FL_XF.2" : { "R82_FL_XF.1" : { "UNNAMED_8_LT3071_I30_IMON_FL" : { "U5_FL_XF.21" : {}, "R26_FL_XF.2" : { "R26_FL_XF.1" : { "GND" : {} } } } } } } } }, "U2_FL_XF.21" : {} }, "C2_DDR4_DQ<30>_XF" : { "U1_XF.G54" : {}, "J3_XF.43" : {} }, "UNNAMED_3_AMPHPCIEX136PCONN_I14_PRSNT1F_PX1" : { "J1_PX1_XF.B17" : {}, "J1_PX1_XF.A1" : {} }, "AC_OCL1_PET_N<3>_XF" : { "U1_XF.BV8" : {}, "C270_XF.1" : { "C270_XF.2" : { "OCL1_PET_N<3>_XF" : { "J1_O1_XF.B19" : {} } } } }, "C3_DDR4_DQ<13>_XF" : { "U1_XF.M25" : {}, "J4_XF.159" : {} }, "E1S1_PET_P<1>_XF" : { "C116_XF.2" : { "C116_XF.1" : { "AC_E1S1_PET_P<1>_XF" : { "U1_XF.N11" : {} } } }, "J1_E1_XF.B21" : {} }, "UNNAMED_9_LUMEXRGBLED_I92_REDK_CPLD" : { "D4_CPLD.2" : { "D4_CPLD.4" : { "UNNAMED_9_LUMEXRGBLED_I92_GREENK_CPLD" : { "R25_CPLD.1" : { "R25_CPLD.2" : { "RGB_LED_GREEN<0>_CPLD" : { "U1_CPLD.E8" : {} } } } } }, "D4_CPLD.3" : { "UNNAMED_9_LUMEXRGBLED_I92_BLUEK_CPLD" : { "R26_CPLD.1" : { "R26_CPLD.2" : { "RGB_LED_BLUE<0>_CPLD" : { "U1_CPLD.E6" : {} } } } } }, "D4_CPLD.1" : { "CPLD_P3R3V" : {} } }, "R24_CPLD.1" : { "R24_CPLD.2" : { "RGB_LED_RED<0>_CPLD" : { "U1_CPLD.E9" : {} } } } }, "UNNAMED_4_RESISTOR_I23_B_MP" : { "R17_MP.1" : { "R17_MP.2" : { "P5VSB" : {} } }, "R18_MP.2" : { "R18_MP.1" : { "GND" : {} } }, "U2_MP.15" : {} }, "RFU_<1>_E1" : { "J1_E1_XF.A42" : {} }, "VCCAUX_BNC_XF" : { "R86_XF.2" : { "R86_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "J7_XF.C" : {} }, "UNNAMED_6_RESISTOR_I409_A_SP" : { "R8_SP_XF.1" : { "R8_SP_XF.2" : { "UNNAMED_6_LTM4671_I456_FB3_SP" : { "PM2_SP_XF.N10" : { "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : {} } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} } }, "R109_SP_XF.2" : { "R109_SP_XF.1" : { "UNNAMED_6_RESISTOR_I222_A_SP" : { "R97_SP_XF.2" : { "R97_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } } } } } }, "C2_DDR4_DQ<4>_XF" : { "U1_XF.V46" : {}, "J3_XF.3" : {} }, "UNNAMED_7_SM050TP_I169_1_CPLD" : { "TP6_CPLD.1" : {}, "U1_CPLD.L1" : {} }, "C0_DDR4_DQ<56>_XF" : { "U1_XF.BG28" : {}, "J1_XF.130" : {} }, "C3_DDR4_DQ<28>_XF" : { "J4_XF.36" : {}, "U1_XF.E23" : {} }, "OCL0_PET_P<3>_XF" : { "C176_XF.2" : { "C176_XF.1" : { "AC_OCL0_PET_P<3>_XF" : { "U1_XF.CA11" : {} } } }, "J1_O0_XF.B18" : {} }, "OCL1_3R3V_PERST_F_XF" : { "J1_O1_XF.A12" : {}, "U1_XF.BK19" : {} }, "AC_PCIE1_TXP<5>_XF" : { "C28_XF.1" : { "C28_XF.2" : { "PCIE1_TXP<5>_XF" : { "J2_P1_XF.B6" : {} } } }, "U1_XF.AR11" : {} }, "PCIE_X1_TXN_XF" : { "J1_PX1_XF.A17" : {}, "C294_XF.2" : { "C294_XF.1" : { "AC_PCIE_X1_TXN_XF" : { "U1_XF.BF8" : {} } } } }, "C0_DDR4_DQ<41>_XF" : { "U1_XF.BN26" : {}, "J1_XF.253" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I155_A_SP" : { "C14_SP_XF.1" : { "C14_SP_XF.2" : { "GND" : {} } }, "R23_SP_XF.1" : { "R23_SP_XF.2" : { "VS_VCCAUX_LIN_N_XF" : { "NS14_FL_XF.2" : { "NS14_FL_XF.1" : { "GND" : {} } } } } }, "U1_SP_XF.64" : {} }, "TS_LT4650_TL_SP" : { "PM4_SP_XF.J6" : { "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } } } }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G9" : { "UNNAMED_4_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} } } }, "C2_RDIMM_DQS_T<7>_XF" : { "U1_XF.M50" : {}, "J3_XF.278" : {} }, "C1_RDIMM_DQS_T<14>_XF" : { "J2_XF.110" : {}, "U1_XF.BM63" : {} }, "C2_RDIMM_DQS_C<16>_XF" : { "U1_XF.M49" : {}, "J3_XF.133" : {} }, "RFU_<2>_E3" : { "J1_E3_XF.B8" : {} }, "CFG_FLASH_D00_MOSI_0_XF" : { "U2_XF.D3" : {}, "U1_XF.AR17" : {}, "U3_XF.D3" : {} }, "POK_OD_AVTT_RLC_LIN" : { "R10_FL_XF.2" : { "R10_FL_XF.1" : { "UNNAMED_5_LT3071_I30_PWRGD_FL" : { "U1_FL_XF.2" : {} } } }, "U1_CPLD.L10" : {} }, "UNNAMED_9_LT3071_I30_MARGA_FL" : { "R81_FL_XF.2" : { "R81_FL_XF.1" : { "UNNAMED_9_BYPASSCAPNPOL_I25_B_FL" : { "C75_FL_XF.2" : { "C75_FL_XF.1" : { "GND" : {} } }, "R77_FL_XF.2" : { "R77_FL_XF.1" : { "DAC_VCCAUX_LIN_XF" : { "U1_SP_XF.54" : {}, "R108_FL_XF.1" : { "R108_FL_XF.2" : { "UNNAMED_9_BYPASSCAPNPOL_I59_B_FL" : { "C104_FL_XF.2" : { "C104_FL_XF.1" : { "GND" : {} } }, "R112_FL_XF.1" : { "R112_FL_XF.2" : { "UNNAMED_9_LT3071_I66_MARGA_FL" : { "U11_FL_XF.22" : {} } } } } } } } } } } } }, "U7_FL_XF.22" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I46_A_XF" : { "U1_XF.BY33" : {}, "C147_XF.1" : { "C147_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I46_B_XF" : { "R100_XF.1" : { "R100_XF.2" : { "UNNAMED_17_RESISTOR_I41_A_XF" : { "R95_XF.1" : { "R95_XF.2" : { "GND" : {} } }, "R96_XF.1" : { "R96_XF.2" : { "GND" : {} } } } } }, "U1_XF.CA33" : {} } } }, "R99_XF.1" : { "R99_XF.2" : { "UNNAMED_17_RESISTOR_I40_A_XF" : { "R94_XF.1" : { "R94_XF.2" : { "GND" : {} } }, "R93_XF.1" : { "R93_XF.2" : { "VMON_AVTT_RS_LIN_XF" : { "R137_XF.2" : { "R137_XF.1" : { "UNNAMED_17_RESISTOR_I110_A_XF" : { "R138_XF.1" : { "R138_XF.2" : { "GND" : {} } }, "R129_XF.2" : { "R129_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I116_A_XF" : { "U1_XF.BW31" : {}, "C268_XF.1" : { "C268_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I116_B_XF" : { "R130_XF.1" : { "R130_XF.2" : { "UNNAMED_17_RESISTOR_I113_A_XF" : { "R141_XF.1" : { "R141_XF.2" : { "GND" : {} } }, "R139_XF.1" : { "R139_XF.2" : { "GND" : {} } } } } }, "U1_XF.BW32" : {} } } } } } } } } }, "R4_FL_XF.2" : { "R4_FL_XF.1" : { "VS_AVTT_RS_LIN_FL" : { "U2_FL_XF.19" : {}, "NS5_FL_XF.2" : { "NS5_FL_XF.1" : { "PWR_AVTT_RS_XF" : {} } } } } } } } } } } } }, "AC_E1S2_PET_N<5>_XF" : { "C168_XF.1" : { "C168_XF.2" : { "E1S2_PET_N<5>_XF" : { "J1_E2_XF.B33" : {} } } }, "U1_XF.AB8" : {} }, "C0_DDR4_BG<1>_XF" : { "U1_XF.BV21" : {}, "J1_XF.207" : {} }, "UNNAMED_3_LTM4675_I40_VOUT1CFG_SD" : { "PM4_SD_XF.G4" : { "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U1_CPLD.C9" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "SI5341_XTAL_B" : { "U1.9" : {}, "TP19.1" : {}, "X1.3" : { "X1.4" : { "XTAL_SHLD" : { "U1.7" : {}, "U1.10" : {} } }, "X1.1" : { "SI5341_XTAL_A" : { "U1.8" : {}, "XA.1" : {} } }, "X1.2" : { "XTAL_SHLD" : {} } } }, "UNNAMED_4_TIMINGCAPNPOL_I15_A_MP" : { "C10_MP.1" : { "C10_MP.2" : { "GND" : {} } }, "U2_MP.9" : {} }, "UNNAMED_10_RESISTOR_I67_B" : { "U1.3" : {}, "R137.2" : { "R137.1" : { "GND" : {} } } }, "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {}, "PM2_SP_XF.M8" : { "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } }, "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } } } }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : { "U11.12" : {}, "R74.2" : { "R74.1" : { "GND" : {} } }, "C33.2" : { "C33.1" : { "GND" : {} } } } } } } }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.E6" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} } } }, "E1S1_PET_P<7>_XF" : { "C110_XF.2" : { "C110_XF.1" : { "AC_E1S1_PET_P<7>_XF" : { "U1_XF.R7" : {} } } }, "J1_E1_XF.B40" : {} }, "AC_CONN_CLK_REFP<0>_2" : { "C21_E3_XF.1" : { "C21_E3_XF.2" : { "CONN_CLK_REFP<0>_E3" : { "J1_E3_XF.B15" : {} } } }, "U1_E3_XF.13" : {} }, "C1_DDR4_PARITY_XF" : { "J2_XF.222" : {}, "U1_XF.CA51" : {} }, "C1_RDIMM_DQS_C<12>_XF" : { "U1_XF.CC59" : {}, "J2_XF.41" : {} }, "OCL2_PER_N<3>_XF" : { "J1_O2_XF.A19" : {}, "U1_XF.BK3" : {} }, "UNNAMED_3_LTM4675_I40_VOUT1CFG_ND" : { "PM4_ND_XF.G4" : { "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } } } }, "C2_DDR4_DQ<52>_XF" : { "U1_XF.K50" : {}, "J3_XF.117" : {} }, "JT_CPLD_TCK" : { "J5.16" : {}, "R65.2" : { "R65.1" : { "GND" : {} } }, "U4_CPLD.1" : {} }, "PCIE0_RXP<2>_XF" : { "U1_XF.AW6" : {}, "J1_P0_XF.A15" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I144_A_SP" : { "C26_SP_XF.1" : { "C26_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.46" : {}, "R47_SP_XF.1" : { "R47_SP_XF.2" : { "IS_VCCINTLR_SW_N_SP" : { "R191_SP_XF.1" : { "R191_SP_XF.2" : { "P3R3V" : {} } }, "R192_SP_XF.2" : { "R192_SP_XF.1" : { "GND" : {} } }, "C181_SP_XF.1" : { "C181_SP_XF.2" : { "GND" : {} } } } } } }, "C3_RDIMM_DQS_C<8>_XF" : { "J4_XF.196" : {}, "U1_XF.H17" : {} }, "FPGA_CPLD_RSVD<3>_1" : { "U1_XF.BU30" : {}, "U1_CPLD.E11" : {} }, "C2_DDR4_DQ<14>_XF" : { "U1_XF.N47" : {}, "J3_XF.21" : {} }, "STAT_LED_ON_F<2>_CPLD" : { "D6_CPLD.1" : { "D6_CPLD.2" : { "UNNAMED_9_LED_I15_A_CPLD" : { "R117_CPLD.1" : { "R117_CPLD.2" : { "CPLD_P3R3V" : {} } } } } }, "U1_CPLD.D6" : {} }, "PWR_NDIMM_VDD_XF" : { "C444_XF.2" : { "C444_XF.1" : { "GND" : {} } }, "J3_XF.206" : {}, "C59_XF.1" : { "C59_XF.2" : { "GND" : {} } }, "R91_XF.1" : { "R91_XF.2" : { "NDIMM_VDD_BNC_XF" : { "J5_XF.C" : {} } } }, "C215_XF.2" : { "C215_XF.1" : { "GND" : {} } }, "U1_XF.E61" : {}, "C212_XF.2" : { "C212_XF.1" : { "GND" : {} } }, "R255_XF.1" : { "R255_XF.2" : { "C3_DDR4_ALERT_N_XF" : { "J4_XF.208" : {}, "U1_XF.K23" : {} } } }, "U1_XF.D58" : {}, "C58_XF.1" : { "C58_XF.2" : { "GND" : {} } }, "J3_XF.209" : {}, "U2_ND_XF.2" : {}, "U1_XF.J53" : {}, "C337_XF.1" : { "C337_XF.2" : { "GND" : {} } }, "C211_XF.2" : { "C211_XF.1" : { "GND" : {} } }, "J4_XF.70" : {}, "C18_ND_XF.1" : { "C18_ND_XF.2" : { "GND" : {} } }, "C443_XF.2" : { "C443_XF.1" : { "GND" : {} } }, "J3_XF.88" : {}, "R260_XF.2" : { "R260_XF.1" : { "C3_DDR4_VREFCA_1_XF" : {} } }, "C209_XF.2" : { "C209_XF.1" : { "GND" : {} } }, "J3_XF.212" : {}, "C62_XF.1" : { "C62_XF.2" : { "GND" : {} } }, "C184_XF.2" : { "C184_XF.1" : { "GND" : {} } }, "PM4_ND_XF.A1" : {}, "J4_XF.90" : {}, "J3_XF.85" : {}, "J3_XF.80" : {}, "J4_XF.80" : {}, "C189_XF.2" : { "C189_XF.1" : { "GND" : {} } }, "J4_XF.85" : {}, "C187_XF.2" : { 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} }, "C450_XF.2" : { "C450_XF.1" : { "GND" : {} } }, "C203_XF.2" : { "C203_XF.1" : { "GND" : {} } }, "J4_XF.206" : {}, "U1_XF.C25" : {}, "C42_ND_XF.1" : { "C42_ND_XF.2" : { "GND" : {} } }, "C56_XF.1" : { "C56_XF.2" : { "GND" : {} } }, "U1_XF.T49" : {}, "C221_XF.2" : { "C221_XF.1" : { "GND" : {} } }, "J4_XF.61" : {}, "J4_XF.236" : {}, "J3_XF.226" : {}, "J3_XF.217" : {}, "C222_XF.2" : { "C222_XF.1" : { "GND" : {} } }, "U1_XF.R26" : {}, "J4_XF.233" : {}, "PM4_ND_XF.C1" : {}, "R253_XF.2" : { "R253_XF.1" : { "C2_DDR4_VREFCA_1_XF" : {} } }, "C442_XF.2" : { "C442_XF.1" : { "GND" : {} } }, "J3_XF.223" : {}, "J3_XF.231" : {}, "C445_XF.2" : { "C445_XF.1" : { "GND" : {} } }, "C451_XF.2" : { "C451_XF.1" : { "GND" : {} } }, "U1_XF.L59" : {}, "J3_XF.229" : {}, "U1_XF.L24" : {}, "J3_XF.204" : {}, "U1_XF.K56" : {}, "J4_XF.220" : {}, "C214_XF.2" : { "C214_XF.1" : { "GND" : {} } }, "C185_XF.2" : { "C185_XF.1" : { "GND" : {} } }, "J3_XF.215" : {}, "J3_XF.73" : {}, "U1_XF.H15" : {}, "C191_XF.2" : { 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"GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} } } }, "C2_DDR4_DQ<8>_XF" : { "J3_XF.16" : {}, "U1_XF.P50" : {} }, "OCL1_PER_P<2>_XF" : { "U1_XF.BT4" : {}, "J1_O1_XF.A15" : {} }, "INTVCC_4650_BR_SP" : { "C188_SP_XF.1" : { "C188_SP_XF.2" : { "GND" : {} } }, "PM7_SP_XF.H8" : { "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.D2" : { "GND" : {} } } }, "C3_RDIMM_DQS_C<6>_XF" : { "J4_XF.266" : {}, "U1_XF.C16" : {} }, "C1_DDR4_ADR<4>_XF" : { "J2_XF.214" : {}, "U1_XF.BW54" : {} }, "SGND_PM3_SP" : { "C56_SP_XF.2" : { "C56_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "R10_SP_XF.1" : { "R10_SP_XF.2" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } } } } } } } } }, "C2_RDIMM_DQS_T<3>_XF" : { "U1_XF.J54" : {}, "J3_XF.186" : {} }, "OCL2_3R3V_BP_TYPE_XF" : { "J1_O2_XF.B9" : {}, "U1_XF.AV17" : {} }, "CPLD_P1R8V_1" : { "R120.2" : { "R120.1" : { "BASE_1R8V_SDA" : {} } }, "C2.2" : {}, "R66.2" : { "R66.1" : { "JT_CPLD_TMS" : { "J5.11" : {}, "U2_CPLD.1" : {} } } }, "C3_CPLD.2" : { "C3_CPLD.1" : { "GND" : {} } }, "C65_CPLD.1" : { "C65_CPLD.2" : { "GND" : {} } }, "C5_MP.1" : { "C5_MP.2" : { "GND" : {} } }, "U1_CPLD.E4" : {}, "R14.1" : { "R14.2" : { "VDDO6" : {} } }, "R62.2" : { "R62.1" : { "JT_FPGA_INST_F" : { "J5.19" : {}, "U1_CPLD.B13" : {} } } }, "R15.1" : { "R15.2" : { "VDDO7" : {} } }, "U1_CPLD.D5" : {}, "C64_CPLD.1" : { "C64_CPLD.2" : { "GND" : {} } }, "U1_CPLD.J7" : {}, "FB2.1" : { "FB2.2" : { "VDDO1" : {} } }, "C7_CPLD.2" : { "C7_CPLD.1" : { "GND" : {} } }, "L1_MP.2" : { "L1_MP.1" : { "UNNAMED_3_BYPASSCAPNPOL_I7_B_MP" : { "U1_MP.11" : {}, "U1_MP.10" : {}, "C3_MP.2" : { "C3_MP.1" : { "UNNAMED_3_BYPASSCAPNPOL_I7_A_MP" : { "U1_MP.13" : {} } } }, "U1_MP.12" : {} } } }, "C10_CPLD.2" : { "C10_CPLD.1" : { "GND" : {} } }, "C2_CPLD.2" : { "C2_CPLD.1" : { "GND" : {} } }, "R40.1" : { "R40.2" : { "CJTAG_REF" : {} } }, "R18.1" : { "R18.2" : { "VDDO0" : {} } }, "R11_MP.1" : { "R11_MP.2" : { "VMON_CPLD_P1R8V_SW" : {} } }, "C63_CPLD.1" : { "C63_CPLD.2" : { "GND" : {} } }, "R5_MP.2" : { "R5_MP.1" : { "UNNAMED_3_RESISTOR_I15_A_MP" : {} } }, "C9_MP.1" : { "C9_MP.2" : { "GND" : {} } }, "R88.1" : { "R88.2" : { "JT_CPLD_INST_F" : { "U4_CPLD.6" : {}, "J5.18" : {}, "U2_CPLD.6" : {}, "U3_CPLD.6" : {} } } }, "U1_CPLD.G8" : {}, "U4_CPLD.5" : {}, "U1_CPLD.M4" : {}, "R13.1" : { "R13.2" : { "VDDO5" : {} } }, "R37.1" : { "R37.2" : { "HOST_3R3V_SCL" : { "U1_CPLD.C12" : {} } } }, "R38.1" : { "R38.2" : { "HOST_3R3V_SDA" : { "U1_CPLD.B12" : {} } } }, "U3_CPLD.5" : {}, "U1_CPLD.H7" : {}, "FB3.1" : { "FB3.2" : { "VDDO2" : {} } }, "U1_CPLD.D12" : {}, "R63.2" : { "R63.1" : { "JT_FPGA_TMS" : { "J5.2" : {}, "U1_CPLD.A11" : {} } } }, "C9_CPLD.2" : { "C9_CPLD.1" : { "GND" : {} } }, "C1_CPLD.2" : { "C1_CPLD.1" : { "GND" : {} } }, "R41.1" : { "R41.2" : { "FP_JT_VREF" : {} } }, "U2_CPLD.5" : {}, "C11_CPLD.2" : { "C11_CPLD.1" : { "GND" : {} } }, "R17.1" : { "R17.2" : { "VDDO9" : {} } }, "U1_CPLD.G9" : {}, "R12.1" : { "R12.2" : { "VDDO4" : {} } }, "C59.1" : { "C59.2" : { "GND" : {} } }, "C8_CPLD.2" : { "C8_CPLD.1" : { "GND" : {} } }, "R121.2" : { "R121.1" : { "BASE_1R8V_SCL" : {} } }, "R16.1" : { "R16.2" : { "VDDO8" : {} } }, "R6.1" : { "R6.2" : { "UNNAMED_13_RESISTOR_I34_A" : {} } }, "FB4.1" : { "FB4.2" : { "VDDO3" : {} } } }, "E1S3_PER_N<2>_XF" : { "J1_E3_XF.A23" : {}, "U1_XF.AH3" : {} }, "C3_DDR4_DQ<31>_XF" : { "J4_XF.188" : {}, "U1_XF.G24" : {} }, "PCIE1_RXN<0>_XF" : { "U1_XF.AN1" : {}, "J1_P1_XF.A4" : {} }, "UNNAMED_6_LT3071_I30_MARGA_FL" : { "U2_FL_XF.22" : {}, "R42_FL_XF.2" : { "R42_FL_XF.1" : { "UNNAMED_6_BYPASSCAPNPOL_I25_B_FL" : { "C22_FL_XF.2" : { "C22_FL_XF.1" : { "GND" : {} } }, "R36_FL_XF.2" : { "R36_FL_XF.1" : { "DAC_AVTT_LIN_XF" : { "R37_FL_XF.1" : { "R37_FL_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I25_B_FL" : { "C24_FL_XF.2" : { "C24_FL_XF.1" : { "GND" : {} } }, "R43_FL_XF.1" : { "R43_FL_XF.2" : { "UNNAMED_7_LT3071_I30_MARGA_FL" : { "U4_FL_XF.22" : {} } } } } } }, "U1_SP_XF.58" : {}, "R29_FL_XF.1" : { "R29_FL_XF.2" : { "UNNAMED_5_BYPASSCAPNPOL_I25_B_FL" : { "C20_FL_XF.2" : { "C20_FL_XF.1" : { "GND" : {} } }, "R31_FL_XF.1" : { "R31_FL_XF.2" : { "UNNAMED_5_LT3071_I30_MARGA_FL" : { "U1_FL_XF.22" : {} } } } } } }, "R38_FL_XF.1" : { "R38_FL_XF.2" : { "UNNAMED_8_BYPASSCAPNPOL_I25_B_FL" : { "R44_FL_XF.1" : { "R44_FL_XF.2" : { "UNNAMED_8_LT3071_I30_MARGA_FL" : { "U5_FL_XF.22" : {} } } }, "C25_FL_XF.2" : { "C25_FL_XF.1" : { "GND" : {} } } } } } } } } } } } }, "OCL2_3R3V_SDA_XF" : { "U1_XF.BA17" : {}, "J1_O2_XF.A10" : {}, "R272_XF.2" : { "R272_XF.1" : { "P3R3V" : {} } } }, "C3_DDR4_DQ<61>_XF" : { "J4_XF.273" : {}, "U1_XF.A18" : {} }, "DIMM_EVENT_OD_F<3>" : { "J4_XF.78" : {}, "U1_CPLD.L14" : {} }, "DAC_AVTT_LIN_XF" : { "R29_FL_XF.1" : { "R29_FL_XF.2" : { "UNNAMED_5_BYPASSCAPNPOL_I25_B_FL" : { "R31_FL_XF.1" : { "R31_FL_XF.2" : { "UNNAMED_5_LT3071_I30_MARGA_FL" : { "U1_FL_XF.22" : {} } } }, "C20_FL_XF.2" : { "C20_FL_XF.1" : { "GND" : {} } } } } }, "U1_SP_XF.58" : {}, "R37_FL_XF.1" : { "R37_FL_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I25_B_FL" : { "R43_FL_XF.1" : { "R43_FL_XF.2" : { "UNNAMED_7_LT3071_I30_MARGA_FL" : { "U4_FL_XF.22" : {} } } }, "C24_FL_XF.2" : { "C24_FL_XF.1" : { "GND" : {} } } } } }, "R36_FL_XF.1" : { "R36_FL_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I25_B_FL" : { "R42_FL_XF.1" : { "R42_FL_XF.2" : { "UNNAMED_6_LT3071_I30_MARGA_FL" : { "U2_FL_XF.22" : {} } } }, "C22_FL_XF.2" : { "C22_FL_XF.1" : { "GND" : {} } } } } }, "R38_FL_XF.1" : { "R38_FL_XF.2" : { "UNNAMED_8_BYPASSCAPNPOL_I25_B_FL" : { "R44_FL_XF.1" : { "R44_FL_XF.2" : { "UNNAMED_8_LT3071_I30_MARGA_FL" : { "U5_FL_XF.22" : {} } } }, "C25_FL_XF.2" : { "C25_FL_XF.1" : { "GND" : {} } } } } } }, "C3_DDR4_ALERT_N_XF" : { "J4_XF.208" : {}, "R255_XF.2" : { "R255_XF.1" : { "PWR_NDIMM_VDD_XF" : {} } }, "U1_XF.K23" : {} }, "C1_SYS_CLK_P_XF" : { "U1_XF.BY54" : {}, "R151_XF.2" : { "R151_XF.1" : { "PWR_SDIMM_VDD_XF" : {} } }, "R243_XF.1" : { "R243_XF.2" : { "C1_SYS_CLK_N_XF" : {} } }, "C362_XF.2" : { "C362_XF.1" : { "DDR4_SYS_CLK_P<1>_XF" : { "U6_XF.14" : {} } } }, "R242_XF.1" : { "R242_XF.2" : { "GND" : {} } } }, "AC_E1S3_PET_P<4>_XF" : { "C339_XF.1" : { "C339_XF.2" : { "E1S3_PET_P<4>_XF" : { "J1_E3_XF.B31" : {} } } }, "U1_XF.AL11" : {} }, "NDIMM_VTT_BNC_XF" : { "R92_XF.2" : { "R92_XF.1" : { "PWR_NDIMM_VTT_XF" : {} } }, "J6_XF.C" : {} }, "C3_DDR4_ADR<16>_XF" : { "U1_XF.N23" : {}, "J4_XF.82" : {} }, "TS_LTM4671_CMN<0>" : { "PM2_SP_XF.K8" : { "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.E6" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} } }, "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : { "C33.2" : { "C33.1" : { "GND" : {} } }, "R74.2" : { "R74.1" : { "GND" : {} } }, "U11.12" : {} } } } }, "C3_DDR4_DQ<53>_XF" : { "U1_XF.E20" : {}, "J4_XF.262" : {} }, "E1S1_PET_P<5>_XF" : { "C112_XF.2" : { "C112_XF.1" : { "AC_E1S1_PET_P<5>_XF" : { "U1_XF.T9" : {} } } }, "J1_E1_XF.B34" : {} }, "UNNAMED_9_LT3071_I66_IMON_FL" : { "U11_FL_XF.21" : {}, "R113_FL_XF.2" : { "R113_FL_XF.1" : { "IMON_VCCAUX_LIN_XF" : { "R90_FL_XF.1" : { "R90_FL_XF.2" : { "UNNAMED_9_LT3071_I30_IMON_FL" : { "U7_FL_XF.21" : {}, "IMON_VCCAUX_A_TP_FL_XF.1" : {} } } }, "IMON_VCCAUX_TP_FL_XF.1" : {}, "R14_XF.1" : { "R14_XF.2" : { "UNNAMED_17_RESISTOR_I196_A_XF" : { "R17_XF.2" : { "R17_XF.1" : { "UNNAMED_17_RESISTOR_I201_A_XF" : { "R10_XF.2" : { "R10_XF.1" : { "GND" : {} } } } } }, "R25_XF.1" : { "R25_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I198_A_XF" : { "C315_XF.1" : { "C315_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I198_B_XF" : { "U1_XF.BW40" : {}, "R26_XF.2" : { "R26_XF.1" : { "UNNAMED_17_RESISTOR_I199_A_XF" : { "R23_XF.2" : { "R23_XF.1" : { "UNNAMED_17_RESISTOR_I202_A_XF" : { "R13_XF.2" : { "R13_XF.1" : { "GND" : {} } } } } }, "R21_XF.2" : { "R21_XF.1" : { "GND" : {} } } } } } } } }, "U1_XF.BW39" : {} } } } } } } } } }, "IMON_VCCAUX_B_TP_FL_XF.1" : {} }, "AC_OCL3_FPGA_REFCLK_N_XF" : { "U5_XF.28" : {}, "C385_XF.1" : { "C385_XF.2" : { "OCL3_FPGA_REFCLK_N_XF" : { "R217_XF.2" : { "R217_XF.1" : { "P3R3V" : {} } }, "R229_XF.1" : { "R229_XF.2" : { "GND" : {} } }, "U1_XF.BJ14" : {} } } } }, "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "PM2_SP_XF.J8" : { "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } }, "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } } } }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.E6" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : { "U11.12" : {}, "C33.2" : { "C33.1" : { "GND" : {} } }, "R74.2" : { "R74.1" : { "GND" : {} } } } } } } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} } }, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } }, "UNNAMED_7_BYPASSCAPNPOL_I25_B_FL" : { "R37_FL_XF.2" : { "R37_FL_XF.1" : { "DAC_AVTT_LIN_XF" : { "R38_FL_XF.1" : { "R38_FL_XF.2" : { "UNNAMED_8_BYPASSCAPNPOL_I25_B_FL" : { "C25_FL_XF.2" : { "C25_FL_XF.1" : { "GND" : {} } }, "R44_FL_XF.1" : { "R44_FL_XF.2" : { "UNNAMED_8_LT3071_I30_MARGA_FL" : { "U5_FL_XF.22" : {} } } } } } }, "R36_FL_XF.1" : { "R36_FL_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I25_B_FL" : { "C22_FL_XF.2" : { "C22_FL_XF.1" : { "GND" : {} } }, "R42_FL_XF.1" : { "R42_FL_XF.2" : { "UNNAMED_6_LT3071_I30_MARGA_FL" : { "U2_FL_XF.22" : {} } } } } } }, "R29_FL_XF.1" : { "R29_FL_XF.2" : { "UNNAMED_5_BYPASSCAPNPOL_I25_B_FL" : { "C20_FL_XF.2" : { "C20_FL_XF.1" : { "GND" : {} } }, "R31_FL_XF.1" : { "R31_FL_XF.2" : { "UNNAMED_5_LT3071_I30_MARGA_FL" : { "U1_FL_XF.22" : {} } } } } } }, "U1_SP_XF.58" : {} } } }, "R43_FL_XF.1" : { "R43_FL_XF.2" : { "UNNAMED_7_LT3071_I30_MARGA_FL" : { "U4_FL_XF.22" : {} } } }, "C24_FL_XF.2" : { "C24_FL_XF.1" : { "GND" : {} } } }, "UNNAMED_3_BYPASSCAPNPOL_I147_A_SP" : { "R50_SP_XF.1" : { "R50_SP_XF.2" : { "IS_VCCINTUL_SW_P_SP" : { "C129_SP_XF.1" : { "C129_SP_XF.2" : { "GND" : {} } }, "R132_SP_XF.2" : { "R132_SP_XF.1" : { "GND" : {} } }, "R131_SP_XF.1" : { "R131_SP_XF.2" : { "UNNAMED_8_ACS711_I102_VIOUT_SP" : { "U5_SP_XF.11" : {} } } } } } }, "C34_SP_XF.1" : { "C34_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.43" : {} }, "C2_DDR4_ADR<12>_XF" : { "J3_XF.65" : {}, "U1_XF.M59" : {} }, "UNNAMED_29_PI6CB33401_I89_BWSELTRI_XF" : { "U7_XF.1" : {}, "R89_XF.2" : { "R89_XF.1" : { "GND" : {} } } }, "C0_RDIMM_DQS_T<6>_XF" : { "J1_XF.267" : {}, "U1_XF.BG23" : {} }, "SI5334_TP_CLK_P<3>" : { "SI5335_TP_P.1" : {}, "U1.59" : {} }, "PCIE1_TXN<4>_XF" : { "C45_XF.2" : { "C45_XF.1" : { "AC_PCIE1_TXN<4>_XF" : { "U1_XF.AP12" : {} } } }, "J2_P1_XF.B4" : {} }, "C2_DDR4_DQ<57>_XF" : { "U1_XF.L50" : {}, "J3_XF.275" : {} }, "E1S2_PER_P<5>_XF" : { "J1_E2_XF.A34" : {}, "U1_XF.AC6" : {} }, "AC_PCIE1_TXN<3>_XF" : { "U1_XF.AP8" : {}, "C46_XF.1" : { "C46_XF.2" : { "PCIE1_TXN<3>_XF" : { "J1_P1_XF.B19" : {} } } } }, "C3_DDR4_DQ<24>_XF" : { "J4_XF.38" : {}, "U1_XF.H23" : {} }, "OCL0_PER_N<2>_XF" : { "J1_O0_XF.A16" : {}, "U1_XF.BW1" : {} }, "AC_OCL1_PET_P<2>_XF" : { "U1_XF.BW11" : {}, "C182_XF.1" : { "C182_XF.2" : { "OCL1_PET_P<2>_XF" : { "J1_O1_XF.B15" : {} } } } }, "UNNAMED_9_BYPASSCAPNPOL_I59_B_FL" : { "R108_FL_XF.2" : { "R108_FL_XF.1" : { "DAC_VCCAUX_LIN_XF" : { "R77_FL_XF.1" : { "R77_FL_XF.2" : { "UNNAMED_9_BYPASSCAPNPOL_I25_B_FL" : { "C75_FL_XF.2" : { "C75_FL_XF.1" : { "GND" : {} } }, "R81_FL_XF.1" : { "R81_FL_XF.2" : { "UNNAMED_9_LT3071_I30_MARGA_FL" : { "U7_FL_XF.22" : {} } } } } } }, "U1_SP_XF.54" : {} } } }, "R112_FL_XF.1" : { "R112_FL_XF.2" : { "UNNAMED_9_LT3071_I66_MARGA_FL" : { "U11_FL_XF.22" : {} } } }, "C104_FL_XF.2" : { "C104_FL_XF.1" : { "GND" : {} } } }, "UNNAMED_4_PI6CB33401_I37_OE2F_E0" : { "U1_E0_XF.24" : {}, "R2_E0_XF.2" : { "R2_E0_XF.1" : { "GND" : {} } }, "U1_E0_XF.29" : {} }, "UNNAMED_9_LT3071_I66_V00_FL" : { "R111_FL_XF.2" : { "R111_FL_XF.1" : { "GND" : {} } }, "R107_FL_XF.1" : { "R107_FL_XF.2" : { "P3R3V" : {} } }, "U11_FL_XF.23" : {} }, "UNNAMED_3_LTM4675_I40_FSWPHCFG_ND" : { "PM4_ND_XF.H2" : { "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } } } }, "PWR_SDIMM_VPP_XF" : { "PM1_SP_XF.M2" : {}, "PM1_SP_XF.L2" : {}, "C414_XF.1" : { "C414_XF.2" : { "GND" : {} } }, "C117_SP_XF.1" : { "C117_SP_XF.2" : { "GND" : {} } }, "J1_XF.286" : {}, "C113_SP_XF.1" : { "C113_SP_XF.2" : { "GND" : {} } }, "C158_XF.2" : { "C158_XF.1" : { "GND" : {} } }, "PM1_SP_XF.M3" : {}, "PM1_SP_XF.L3" : {}, "C415_XF.1" : { "C415_XF.2" : { "GND" : {} } }, "PM1_SP_XF.M1" : {}, "PM1_SP_XF.L1" : {}, "J2_XF.286" : {}, "C121_SP_XF.1" : { "C121_SP_XF.2" : { "GND" : {} } }, "J2_XF.142" : {}, "C412_XF.2" : { "C412_XF.1" : { "GND" : {} } }, "J2_XF.143" : {}, "C413_XF.1" : { "C413_XF.2" : { "GND" : {} } }, "PM1_SP_XF.M4" : {}, "PM1_SP_XF.L4" : {}, "J1_XF.143" : {}, "J1_XF.142" : {}, "C411_XF.2" : { "C411_XF.1" : { "GND" : {} } }, "PM1_SP_XF.L10" : {}, "C436_XF.2" : { "C436_XF.1" : { "GND" : {} } }, "R124_SP_XF.1" : { "R124_SP_XF.2" : { "VMON_SDIMM_VPP_SW" : { "R52.1" : { "R52.2" : { "UNNAMED_4_BYPASSCAPNPOL_I51_B" : {} } } } } }, "J2_XF.288" : {}, "J2_XF.287" : {}, "J1_XF.287" : {}, "J1_XF.288" : {}, "C438_XF.1" : { "C438_XF.2" : { "GND" : {} } }, "C437_XF.1" : { "C437_XF.2" : { "GND" : {} } }, "C439_XF.1" : { "C439_XF.2" : { "GND" : {} } } }, "E1S2_3R3V_PERST_F<0>_XF" : { "U1_XF.N17" : {}, "J1_E2_XF.B10" : {} }, "ENB3V_SEQ_F" : { "R107_SP_XF.2" : { "R107_SP_XF.1" : { "UNNAMED_7_LTM4671_I36_RUN3_SP" : { "PM1_SP_XF.P7" : { "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} } } } } } } }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} } } } } }, "R11_CPLD.1" : { "R11_CPLD.2" : { "GND" : {} } }, "U1_CPLD.M15" : {} }, "C1_DDR4_DQ<66>_XF" : { "U1_XF.BT60" : {}, "J2_XF.56" : {} }, "SGND_PM7_SP" : { "R89_SP_XF.1" : { "R89_SP_XF.2" : { "FSET_4650_BR_SP" : { "PM7_SP_XF.C6" : { "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K6" : { "GND" : {} } } } } } }, "C1_DDR4_DQ<43>_XF" : { "J2_XF.260" : {}, "U1_XF.BK60" : {} }, "VMON_AVTT_RUC_LIN_XF" : { "R106_XF.1" : { "R106_XF.2" : { "UNNAMED_17_RESISTOR_I61_A_XF" : { "R107_XF.2" : { "R107_XF.1" : { "GND" : {} } }, "R97_XF.1" : { "R97_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I58_A_XF" : { "U1_XF.BV36" : {}, "C146_XF.1" : { "C146_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I58_B_XF" : { "U1_XF.BW36" : {}, "R98_XF.2" : { "R98_XF.1" : { "UNNAMED_17_RESISTOR_I95_B_XF" : { "R109_XF.2" : { "R109_XF.1" : { "GND" : {} } }, "R108_XF.2" : { "R108_XF.1" : { "GND" : {} } } } } } } } } } } } } } }, "R57_FL_XF.2" : { "R57_FL_XF.1" : { "VS_AVTT_RUC_LIN_FL" : { "U5_FL_XF.19" : {}, "NS9_FL_XF.2" : { "NS9_FL_XF.1" : { "PWR_AVTT_RUC_XF" : {} } } } } } }, "OCL1_3R3V_CWAKE_F_XF" : { "U1_XF.BN18" : {}, "J1_O1_XF.B10" : {} }, "E1S3_3R3V_DUALPORTEN_F_XF" : { "J1_E3_XF.B9" : {}, "U1_XF.V19" : {} }, "UNNAMED_3_RESISTOR_I61_A" : { "R77.1" : { "R77.2" : { "P3R3V" : {} } }, "FPNL_CONN.22" : {} }, "C3_DDR4_DQ<45>_XF" : { "J4_XF.251" : {}, "U1_XF.B24" : {} }, "CLKIN_N_E3" : { "C17_E3_XF.2" : { "C17_E3_XF.1" : { "E1S_REF_CLK_N<3>" : { "U1.37" : {} } } }, "U1_E3_XF.6" : {}, "R15_E3_XF.2" : { "R15_E3_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R17_E3_XF.2" : { "R17_E3_XF.1" : { "CLKIN_P_E3" : {} } }, "R18_E3_XF.1" : { "R18_E3_XF.2" : { "GND" : {} } } }, "UNNAMED_3_LTM4675_I40_TSNS01_ND" : { "PM4_ND_XF.C3" : { "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } } } } } } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "C3_DDR4_CS_N<2>_XF" : { "J4_XF.93" : {}, "U1_XF.J22" : {} }, "C2_RDIMM_DQS_C<11>_XF" : { "J3_XF.30" : {}, "U1_XF.F62" : {} }, "FPGA_REF_CLK_N" : { "U1.53" : {}, "U1_XF.BN31" : {} }, "C1_DDR4_DQ<36>_XF" : { "U1_XF.BV63" : {}, "J2_XF.95" : {} }, "C2_RDIMM_DQS_T<9>_XF" : { "U1_XF.V51" : {}, "J3_XF.7" : {} }, "E1S0_PET_N<5>_XF" : { "C124_XF.2" : { "C124_XF.1" : { "AC_E1S0_PET_N<5>_XF" : { "U1_XF.E10" : {} } } }, "J1_E0_XF.B33" : {} }, "C1_RDIMM_DQS_T<4>_XF" : { "U1_XF.BT62" : {}, "J2_XF.245" : {} }, "PHASMD_4650_BR_SP" : { "R73_SP_XF.2" : { "R73_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R70_SP_XF.2" : { "R70_SP_XF.1" : { "INTVCC_4650_BR_SP" : { "PM7_SP_XF.H8" : { "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.G4" : { "PHASMD_4650_BR_SP" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A6" : { "GND" : {} } }, "C188_SP_XF.1" : { "C188_SP_XF.2" : { "GND" : {} } } } } } }, "OCL2_PET_P<2>_XF" : { "C236_XF.2" : { "C236_XF.1" : { "AC_OCL2_PET_P<2>_XF" : { "U1_XF.BL11" : {} } } }, "J1_O2_XF.B15" : {} }, "RGB_LED_GREEN<2>_CPLD" : { "U1_CPLD.A8" : {}, "R5_CPLD.2" : { "R5_CPLD.1" : { "UNNAMED_9_LUMEXRGBLED_I90_GREENK_CPLD" : { "D2_CPLD.4" : { "D2_CPLD.2" : { "UNNAMED_9_LUMEXRGBLED_I90_REDK_CPLD" : { "R4_CPLD.1" : { "R4_CPLD.2" : { "RGB_LED_RED<2>_CPLD" : { "U1_CPLD.D9" : {} } } } } }, "D2_CPLD.1" : { "CPLD_P3R3V" : {} }, "D2_CPLD.3" : { "UNNAMED_9_LUMEXRGBLED_I90_BLUEK_CPLD" : { "R20_CPLD.1" : { "R20_CPLD.2" : { "RGB_LED_BLUE<2>_CPLD" : { "U1_CPLD.B7" : {} } } } } } } } } } }, "ENB3V_LTC2975" : { "U1_SP_XF.23" : {}, "U1_SP_XF.33" : {}, "R6_CPLD.1" : { "R6_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R12" : {}, "U1_SP_XF.22" : {}, "U1_SP_XF.32" : {} }, "UNNAMED_19_NMOSFETVMT3_I39_G" : { "R57.1" : { "R57.2" : { "PSU_PWR_ON" : { "R61.1" : { "R61.2" : { "GND" : {} } }, "U1_CPLD.P7" : {} } } }, "Q5.1" : { "Q5.2" : { "GND" : {} }, "Q5.3" : { "PS_ON_N" : { "J3.16" : {} } } } }, "OCL2_3R3V_CKEN_F<1>_XF" : { "U1_XF.AU19" : {}, "U5_XF.12" : {} }, "UNNAMED_3_LTM4675_I40_TSNS1A_ND" : { "PM4_ND_XF.J3" : { "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } } } }, "AC_FPGA_CLK_REF_N<0>_1" : { "C23_E0_XF.1" : { "C23_E0_XF.2" : { "E1S0_FPGA_REFCLK_N<0>_XF" : { "U1_XF.D12" : {}, "R175_XF.1" : { "R175_XF.2" : { "GND" : {} } }, "R164_XF.2" : { "R164_XF.1" : { "PWR_FPGA_3R3V" : {} } } } } }, "U1_E0_XF.23" : {} }, "PM2_VOSNS03_N_SP" : { "PM2_SP_XF.P10" : { "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.E6" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : { "R74.2" : { "R74.1" : { "GND" : {} } }, "C33.2" : { "C33.1" : { "GND" : {} } }, "U11.12" : {} } } } } }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} } } }, "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : { "PM4_SP_XF.F4" : { "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } } } }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.G9" : { "UNNAMED_4_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} } } }, "VDDO3" : { "FB4.2" : { "FB4.1" : { "CPLD_P1R8V_1" : {} } }, "U1.33" : {}, "C24.1" : { "C24.2" : { "GND" : {} } } }, "C2_DDR4_DQ<18>_XF" : { "U1_XF.D62" : {}, "J3_XF.34" : {} }, "UNNAMED_4_CAPACITOR_I11_A_SP" : { "R13_SP_XF.1" : { "R13_SP_XF.2" : { "CMP_4650_SP" : { "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } } } }, "AC_E1S2_PET_N<1>_XF" : { "U1_XF.W6" : {}, "C172_XF.1" : { "C172_XF.2" : { "E1S2_PET_N<1>_XF" : { "J1_E2_XF.B20" : {} } } } }, "OCL1_CONN_REFCLK_N_XF" : { "C383_XF.2" : { "C383_XF.1" : { "AC_OCL1_CONN_REFCLK_N_XF" : { "U7_XF.18" : {} } } }, "J1_O1_XF.B13" : {} }, "PCIE0_TXP<3>_XF" : { "C38_XF.2" : { "C38_XF.1" : { "AC_PCIE0_TXP<3>_XF" : { "U1_XF.AW11" : {} } } }, "J1_P0_XF.B18" : {} }, "OCL1_PET_N<3>_XF" : { "C270_XF.2" : { "C270_XF.1" : { "AC_OCL1_PET_N<3>_XF" : { "U1_XF.BV8" : {} } } }, "J1_O1_XF.B19" : {} }, "PSU_N12V" : { "C31.1" : { "C31.2" : { "GND" : {} } }, "J3.14" : {}, "N12V_TP.1" : {} }, "C1_DDR4_ADR<8>_XF" : { "U1_XF.CC54" : {}, "J2_XF.68" : {} }, "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "J5.6" : {}, "J2_XF.285" : {}, "J3_XF.285" : {}, "PM4_ND_XF.D4" : { "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.E8" : { "NC" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.G2" : { "NDIMM_I2C_ASEL_RESISTOR_XF" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.G7" : { "NC" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.J5" : { "NC" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.J4" : { "NC" : {} }, "PM4_ND_XF.H7" : { "NC" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.D8" : { "NC" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.E5" : { "CKI_LTM4675_ND" : {} }, "PM4_ND_XF.F7" : { "NC" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.E3" : { "NDIMM_LTM4675_ALERT_OD_F_1" : { "U1_CPLD.M6" : {} } }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.H5" : { "NC" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} } }, "J4_XF.285" : {}, "J1_XF.285" : {}, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.BW29" : {} } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : {} } } } } } } } } } } } } } } } } }, "U11.13" : {} } } } } } } }, "VMON_CPLD_P1R8V_SW" : { "R59.1" : { "R59.2" : { "UNNAMED_4_BYPASSCAPNPOL_I105_B" : { "R26.2" : { "R26.1" : { "GND" : {} } }, "U11.1" : {}, "C50.2" : { "C50.1" : { "GND" : {} } } } } }, "R11_MP.2" : { "R11_MP.1" : { "CPLD_P1R8V_1" : {} } } }, "E1S2_PER_P<7>_XF" : { "J1_E2_XF.A40" : {}, "U1_XF.AB4" : {} }, "C0_DDR4_DQ<65>_XF" : { "J1_XF.194" : {}, "U1_XF.BT28" : {} }, "UNNAMED_3_LTM4675_I40_COMP0B_SD" : { "R108_SD_XF.1" : { "R108_SD_XF.2" : { "UNNAMED_3_LTM4675_I40_COMP0A_SD" : {} } }, "R109_SD_XF.1" : { "R109_SD_XF.2" : { "UNNAMED_3_LTM4675_I40_COMP1A_SD" : {} } }, "PM4_SD_XF.D6" : { "PM4_SD_XF.F6" : { "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF" : {} }, "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U1_CPLD.C9" : {} } } } } } } } } } } } } } }, "PM4_SD_XF.G5" : { "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF" : {} }, "PM4_SD_XF.E6" : { "UNNAMED_3_LTM4675_I40_COMP0A_SD" : {} }, "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_SD_XF.F5" : { "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF" : {} }, "PM4_SD_XF.H6" : { "UNNAMED_3_LTM4675_I40_COMP1A_SD" : {} }, "PM4_SD_XF.G6" : { "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF" : {} } }, "R111_SD_XF.2" : { "R111_SD_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I28_A_SD" : { "C81_SD_XF.1" : { "C81_SD_XF.2" : { "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF" : {} } } } } } }, "UNNAMED_3_RESISTOR_I70_B_E2" : { "J1_E2_XF.MH3" : {}, "R1_E2_XF.2" : { "R1_E2_XF.1" : { "GND" : {} } }, "J1_E2_XF.MH2" : {}, "J1_E2_XF.MH1" : {} }, "TS_LT4650_TR_SP" : { "PM5_SP_XF.J6" : { "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} } } } }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.G5" : { "NC" : {} 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{ "AC_E1S0_PET_N<7>_XF" : { "U1_XF.C10" : {} } } } }, "C1_DDR4_CK_T<0>_XF" : { "U1_XF.CB49" : {}, "J2_XF.74" : {} }, "PCIE1_RST_F" : { "R156_XF.1" : { "R156_XF.2" : { "UNNAMED_11_RESISTOR_I773_B_XF" : { "R158_XF.2" : { "R158_XF.1" : { "GND" : {} } }, "U1_XF.BG34" : {} } } }, "U1_CPLD.E16" : {} }, "CPLD_FPGA_SSTAT" : { "U1_CPLD.J2" : {}, "U1_XF.BY34" : {} }, "C0_DDR4_DQ<35>_XF" : { "U1_XF.BL23" : {}, "J1_XF.249" : {} }, "UNNAMED_11_RESISTOR_I773_B_XF" : { "U1_XF.BG34" : {}, "R156_XF.2" : { "R156_XF.1" : { "PCIE1_RST_F" : { "U1_CPLD.E16" : {} } } }, "R158_XF.2" : { "R158_XF.1" : { "GND" : {} } } }, "BASE_1R8V_SDA" : { "Q4.2" : { "Q4.1" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "R5.2" : { "R5.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R3.1" : { "R3.2" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "Q3.1" : { "Q3.3" : { "BASE_3R3V_SCL_2" : { "U12.6" : {}, "Q1.3" : { "Q1.1" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "R32.2" : { "R32.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R31.1" : { "R31.2" : { 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{ "GND" : {} } }, "J2.7" : {}, "C6_E0_XF.2" : { "C6_E0_XF.1" : { "GND" : {} } }, "C122_SP_XF.1" : { "C122_SP_XF.2" : { "GND" : {} } }, "PM2_SP_XF.D7" : {}, "PM2_SP_XF.H6" : {}, "U3_SP_XF.1_2" : {}, "J1_E2_XF.B3" : {}, "J1_E3_XF.B1" : {}, "C66.1" : { "C66.2" : { "GND" : {} } }, "PM1_SP_XF.D11" : {}, "C55.1" : { "C55.2" : { "GND" : {} } }, "PM2_SP_XF.D10" : {}, "J1_E1_XF.B6" : {}, "C4_E3_XF.1" : { "C4_E3_XF.2" : { "GND" : {} } }, "C12_E2_XF.2" : { "C12_E2_XF.1" : { "GND" : {} } }, "J1_E3_XF.B5" : {}, "C27.1" : { "C27.2" : { "GND" : {} } }, "U6_SP_XF.1_2" : {}, "J1_E0_XF.B1" : {}, "PM2_SP_XF.D8" : {}, "FB5.1" : { "FB5.2" : { "UNNAMED_20_FERRITEBEAD_I58_B" : { "P2.2" : {} } } }, "C21.1" : { "C21.2" : { "GND" : {} } }, "C26.1" : { "C26.2" : { "GND" : {} } }, "C6_E3_XF.2" : { "C6_E3_XF.1" : { "GND" : {} } }, "J1.5" : {}, "J1_E2_XF.B6" : {}, "J2.6" : {} }, "SI5341_FINC" : { "U1.48" : {}, "U1_CPLD.G6" : {} }, "UNNAMED_12_RESISTOR_I13_A" : { "R7.1" : { "R7.2" : { "UNNAMED_12_NMOSFETVMT3_I12_G" : { "Q11.1" : { "Q11.2" : { "PSU_1R8V_SDA" : { "U1_XF.CA37" : {}, "R19.1" : { "R19.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q11.3" : { "PSU_3R3V_SDA" : { "J4.2" : {}, "R24.2" : { "R24.1" : { "P3R3V" : {} } } } } } } } }, "R8.1" : { "R8.2" : { "UNNAMED_12_NMOSFETVMT3_I4_G" : { "Q10.1" : { "Q10.3" : { "PSU_3R3V_SCL" : { "R25.2" : { "R25.1" : { "P3R3V" : {} } }, "J4.1" : {} } }, "Q10.2" : { "PSU_1R8V_SCL" : { "R9.1" : { "R9.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.CA35" : {} } } } } } }, "R4.2" : { "R4.1" : { "DIS_1R8V_I2C_XLAT_F" : { "U1_CPLD.H3" : {}, "R58.1" : { "R58.2" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { 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"U12.3" : {} }, "C2_DDR4_ADR<1>_XF" : { "J3_XF.72" : {}, "U1_XF.L62" : {} }, "E1S0_3R3V_SDA_XF" : { "U1_XF.AC18" : {}, "J1_E0_XF.A8" : {}, "R4_E0_XF.2" : { "R4_E0_XF.1" : { "P3R3V" : {} } }, "R183_XF.2" : { "R183_XF.1" : { "PWR_FPGA_3R3V" : {} } } }, "OCL3_PET_P<2>_XF" : { "C255_XF.2" : { "C255_XF.1" : { "AC_OCL3_PET_P<2>_XF" : { "U1_XF.BG11" : {} } } }, "J1_O3_XF.B15" : {} }, "C3_RDIMM_DQS_T<15>_XF" : { "J4_XF.121" : {}, "U1_XF.F18" : {} }, "UNNAMED_22_RESISTOR_I35_B_XF" : { "R48_XF.2" : { "R48_XF.1" : { "GND" : {} } }, "U1_XF.J19" : {} }, "UNNAMED_20_MLXKK1004PINBOSS_I25_P4" : { "P3.4" : {}, "Q8.3" : { "Q8.1" : { "UNNAMED_20_NMOSFETVMT3_I16_G" : { "R55.2" : { "R55.1" : { "FAN_PWM_OD" : { "U1_CPLD.J12" : {}, "R39.1" : { "R39.2" : { "UNNAMED_20_NMOSFETVMT3_I20_G" : { "Q6.1" : { "Q6.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I30_P4" : { "P2.4" : {} } }, "Q6.2" : { "GND" : {} } } } } }, "R42.1" : { "R42.2" : { "UNNAMED_20_NMOSFETVMT3_I12_G" : { "Q7.1" : { "Q7.2" : { "GND" : {} }, "Q7.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I26_P4" : { "P4.4" : {} } } } } } }, "R56.1" : { "R56.2" : { "UNNAMED_20_NMOSFETVMT3_I8_G" : { "Q9.1" : { "Q9.2" : { "GND" : {} }, "Q9.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I27_P4" : { "P5.4" : {} } } } } } } } } } } }, "Q8.2" : { "GND" : {} } } }, "OCL3_3R3V_CKEN_F<1>_XF" : { "U5_XF.19" : {}, "U1_XF.AY19" : {} }, "UNNAMED_3_RESISTOR_I20_A_MP" : { "R3_MP.1" : { "R3_MP.2" : { "UNNAMED_3_RESISTOR_I20_B_MP" : { "C4_MP.1" : { "C4_MP.2" : { "GND" : {} } } } } }, "U1_MP.7" : {} }, "C1_DDR4_ADR<9>_XF" : { "U1_XF.CC53" : {}, "J2_XF.66" : {} }, "PCIE1_TXP<4>_XF" : { "J2_P1_XF.B3" : {}, "C29_XF.2" : { "C29_XF.1" : { "AC_PCIE1_TXP<4>_XF" : { "U1_XF.AP13" : {} } } } }, "P3R3V" : { "C9.1" : { "C9.2" : { "GND" : {} } }, "R25.1" : { "R25.2" : { "PSU_3R3V_SCL" : {} } }, "R3_E1_XF.1" : { "R3_E1_XF.2" : { "E1S1_3R3V_SCL_XF" : {} } }, "U6_SP_XF.12" : {}, "R34.1" : { "R34.2" : { "BASE_3R3V_SCL_2" : {} } }, "R6_XF.1" : { "R6_XF.2" : { "C2_DDR4_SA<2>_XF" : { "J3_XF.238" : {} } } }, "R3_E2_XF.1" : { "R3_E2_XF.2" : { "E1S2_3R3V_SCL_XF" : {} } }, "R7_E3_XF.1" : { "R7_E3_XF.2" : { "E1S3_3R3V_PERST_CLKREQ_F<1>_XF" : { "U1_XF.T21" : {}, "J1_E3_XF.A11" : {} } } }, "R189_SP_XF.2" : { "R189_SP_XF.1" : { "IS_VCCINTUR_SW_N_SP" : {} } }, "U5_FL_XF.27" : {}, "R24.1" : { "R24.2" : { "PSU_3R3V_SDA" : {} } }, "R216_XF.1" : { "R216_XF.2" : { "OCL3_FPGA_REFCLK_P_XF" : {} } }, "R6_E2_XF.1" : { "R6_E2_XF.2" : { "E1S2_3R3V_LED_XF" : { "U1_XF.N19" : {}, "J1_E2_XF.A10" : {} } } }, "C1_FL_XF.1" : { "C1_FL_XF.2" : { "GND" : {} } }, "R103_FL_XF.2" : { "R103_FL_XF.1" : { "UNNAMED_9_LT3071_I66_EN_FL" : { "U11_FL_XF.28" : {} } } }, "C103_FL_XF.1" : { "C103_FL_XF.2" : { "GND" : {} } }, "R210_XF.1" : { "R210_XF.2" : { "OCL0_FPGA_REFCLK_P_XF" : {} } }, "U2_SP_XF.12" : {}, "R40_FL_XF.2" : { "R40_FL_XF.1" : { "UNNAMED_7_LT3071_I30_V01_FL" : {} } }, "R217_XF.1" : { "R217_XF.2" : { "OCL3_FPGA_REFCLK_N_XF" : {} } }, "C54.1" : { "C54.2" : { "GND" : {} } }, "R9_FL_XF.2" : { "R9_FL_XF.1" : { "UNNAMED_9_LT3071_I30_EN_FL" : { "U7_FL_XF.28" : {} } } }, "R95_FL_XF.2" : { "R95_FL_XF.1" : { "UNNAMED_12_LT3071_I30_V00_FL" : {} } }, "R6_E1_XF.1" : { "R6_E1_XF.2" : { "E1S1_3R3V_LED_XF" : { "U1_XF.AF17" : {}, "J1_E1_XF.A10" : {} } } }, "U3_SP_XF.12" : {}, "R5_E0_XF.1" : { "R5_E0_XF.2" : { "E1S0_3R3V_SMB_RST_F_XF" : { "U1_XF.AB18" : {}, "J1_E0_XF.A9" : {} } } }, "J1_E1_XF.B11" : {}, "R23_FL_XF.2" : { "R23_FL_XF.1" : { "UNNAMED_4_LT3071_I30_V00_FL" : {} } }, "R30_FL_XF.2" : { "R30_FL_XF.1" : { "UNNAMED_6_LT3071_I30_EN_FL" : { "U2_FL_XF.28" : {} } } }, "C81.2" : { "C81.1" : { "GND" : {} } }, "J1_E2_XF.B11" : {}, "C70.2" : { "C70.1" : { "GND" : {} } }, "C179_SP_XF.1" : { "C179_SP_XF.2" : { "GND" : {} } }, "R263_XF.1" : { "R263_XF.2" : { "C1_DDR4_SA<1>_XF" : { "J2_XF.140" : {} } } }, "R4_E2_XF.1" : { "R4_E2_XF.2" : { "E1S2_3R3V_SDA_XF" : {} } }, "R8_E1_XF.1" : { "R8_E1_XF.2" : { "E1S1_3R3V_PRSNT_F<0>_XF" : { "J1_E1_XF.A12" : {}, "U1_XF.AD19" : {} } } }, "R8_E2_XF.1" : { "R8_E2_XF.2" : { "E1S2_3R3V_PRSNT_F<0>_XF" : { "J1_E2_XF.A12" : {}, "U1_XF.M19" : {} } } }, "C74_FL_XF.1" : { "C74_FL_XF.2" : { "GND" : {} } }, "R44.1" : { "R44.2" : { "UNNAMED_3_RESISTOR_I56_B" : { "FPNL_CONN.7" : {} } } }, "R22.1" : { "R22.2" : { "UNNAMED_7_NMOSFETVMT3_I2_D" : {} } }, "R4_E1_XF.1" : { "R4_E1_XF.2" : { "E1S1_3R3V_SDA_XF" : {} } }, "C96.2" : {}, "C86_FL_XF.1" : { "C86_FL_XF.2" : { "GND" : {} } }, "C69.2" : { "C69.1" : { "GND" : {} } }, "U4_FL_XF.27" : {}, "R29.1" : { "R29.2" : { "UNNAMED_3_RESISTOR_I55_B" : { "FPNL_CONN.1" : {} } } }, "R19_SP_XF.1" : { "R19_SP_XF.2" : { "UNNAMED_3_LTC2975_I168_ASEL0_SP" : {} } }, "C7_E3_XF.2" : { "C7_E3_XF.1" : { "GND" : {} } }, "R6_E0_XF.1" : { "R6_E0_XF.2" : { "E1S0_3R3V_LED_XF" : { "J1_E0_XF.A10" : {}, "U1_XF.AA17" : {} } } }, "C1.1" : { "C1.2" : { "GND" : {} } }, "C84.2" : { "C84.1" : { "GND" : {} } }, "U4_SP_XF.16" : {}, "J3_XF.284" : {}, "R233_XF.1" : { "R233_XF.2" : { "OCL1_3R3V_SDA_XF" : { "U1_XF.BN17" : {}, "J1_O1_XF.A10" : {} } } }, "R69.2" : { "R69.1" : { "UNNAMED_3_RESISTOR_I60_A" : { "FPNL_CONN.12" : {} } } }, "R99_FL_XF.2" : { "R99_FL_XF.1" : { "UNNAMED_12_LT3071_I30_V01_FL" : {} } }, "R119_SP_XF.1" : { "R119_SP_XF.2" : { "UNNAMED_3_LTC2975_I168_FAULT0F_SP" : { "U1_SP_XF.25" : {} } } }, "R3_E0_XF.1" : { "R3_E0_XF.2" : { "E1S0_3R3V_SCL_XF" : {} } }, "Q13.3" : {}, "R285_XF.1" : { "R285_XF.2" : { "PCIE_X1_CLKREQ_XF" : { "U1_XF.BF17" : {}, "J1_PX1_XF.B12" : {} } } }, "U1_SP_XF.10" : {}, "J2_XF.284" : {}, "R98_FL_XF.2" : { "R98_FL_XF.1" : { "UNNAMED_12_LT3071_I30_V02_FL" : {} } }, "R53_FL_XF.2" : { "R53_FL_XF.1" : { "UNNAMED_7_LT3071_I30_V00_FL" : {} } }, "R211_XF.1" : { "R211_XF.2" : { "OCL0_FPGA_REFCLK_N_XF" : {} } }, "U6_FL_XF.27" : {}, "R8_E0_XF.1" : { "R8_E0_XF.2" : { "E1S0_3R3V_PRSNT_F<0>_XF" : { "J1_E0_XF.A12" : {}, "U1_XF.W19" : {} } } }, "C82.2" : { "C82.1" : { "GND" : {} } }, "C11_FL_XF.1" : { "C11_FL_XF.2" : { "GND" : {} } }, "R212_XF.1" : { "R212_XF.2" : { "OCL1_FPGA_REFCLK_P_XF" : {} } }, "U11_FL_XF.27" : {}, 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"UNNAMED_6_LT3071_I30_V02_FL" : {} } }, "U3_FL_XF.27" : {}, "R17_SP_XF.1" : { "R17_SP_XF.2" : { "UNNAMED_3_LTC2975_I168_ASEL1_SP" : {} } }, "R5_E2_XF.1" : { "R5_E2_XF.2" : { "E1S2_3R3V_SMB_RST_F_XF" : { "U1_XF.R19" : {}, "J1_E2_XF.A9" : {} } } }, "R59_FL_XF.2" : { "R59_FL_XF.1" : { "UNNAMED_4_LT3071_I30_V01_FL" : {} } }, "R45_FL_XF.2" : { "R45_FL_XF.1" : { "UNNAMED_3_LT3071_I32_V02_FL" : {} } }, "FB6_SD_XF.1" : { "FB6_SD_XF.2" : { "DIMM_VTT_3VFLT_SD" : {} } }, "R231_XF.1" : { "R231_XF.2" : { "OCL0_3R3V_SDA_XF" : { "U1_XF.BL18" : {}, "J1_O0_XF.A10" : {} } } }, "C7_E2_XF.2" : { "C7_E2_XF.1" : { "GND" : {} } }, "C125_SP_XF.1" : { "C125_SP_XF.2" : { "GND" : {} } }, "R76_FL_XF.2" : { "R76_FL_XF.1" : { "UNNAMED_8_LT3071_I30_V02_FL" : {} } }, "R32_FL_XF.2" : { "R32_FL_XF.1" : { "UNNAMED_7_LT3071_I30_EN_FL" : { "U4_FL_XF.28" : {} } } }, "R78.1" : { "R78.2" : { "FP_RST_SW_N" : {} } }, "C10_FL_XF.1" : { "C10_FL_XF.2" : { "GND" : {} } }, "R232_XF.1" : { "R232_XF.2" : { "OCL1_3R3V_SCL_XF" : { "J1_O1_XF.A9" : {}, "U1_XF.BK20" : {} } } }, "R266_XF.1" : { "R266_XF.2" : { "C3_DDR4_SA<1>_XF" : { "J4_XF.140" : {} } } }, "R79.1" : { "R79.2" : { "UNNAMED_3_598BICOLORLED_I68_L2A" : {} } }, "U10_FL_XF.27" : {}, "C7_E1_XF.2" : { "C7_E1_XF.1" : { "GND" : {} } }, "R58_FL_XF.2" : { "R58_FL_XF.1" : { "UNNAMED_4_LT3071_I30_V02_FL" : {} } }, "Q13.2" : {}, "C8.1" : { "C8.2" : { "GND" : {} } }, "R37_SP_XF.1" : { "R37_SP_XF.2" : { "UNNAMED_3_LTC2975_I168_WP_SP" : {} } }, "R118_SP_XF.1" : { "R118_SP_XF.2" : { "UNNAMED_3_LTC2975_I168_FAULT1F_SP" : { "U1_SP_XF.26" : {} } } }, "R20.1" : { "R20.2" : { "UNNAMED_17_RESISTOR_I7_B" : { "U12.3" : {} } } }, "R120_SP_XF.1" : { "R120_SP_XF.2" : { "UNNAMED_3_LTC2975_I168_SHARECLK_SP" : { "U1_SP_XF.18" : {} } } }, "U1_FL_XF.27" : {}, "R7_E0_XF.1" : { "R7_E0_XF.2" : { "E1S0_3R3V_PERST_CLKREQ_F<1>_XF" : { "U1_XF.Y18" : {}, "J1_E0_XF.A11" : {} } } }, "C72.2" : { "C72.1" : { "GND" : {} } }, "Q13.1" : {}, "FB6_ND_XF.1" : { "FB6_ND_XF.2" : { "DIMM_VTT_3VFLT_ND" : {} } }, "R214_XF.1" : { "R214_XF.2" : { "OCL2_FPGA_REFCLK_P_XF" : {} } }, "R39_SP_XF.1" : { "R39_SP_XF.2" : { "UNNAMED_3_LTC2975_I168_WDIRESETF_SP" : { "U1_SP_XF.24" : {} } } }, "R65_FL_XF.2" : { "R65_FL_XF.1" : { "UNNAMED_9_LT3071_I30_V02_FL" : {} } }, "R104.1" : { "R104.2" : { "UNNAMED_17_RESISTOR_I9_B" : { "U12.1" : {} } } }, "R106_FL_XF.2" : { "R106_FL_XF.1" : { "UNNAMED_9_LT3071_I66_V01_FL" : {} } }, "R274_XF.1" : { "R274_XF.2" : { "OCL3_3R3V_SDA_XF" : { "J1_O3_XF.A10" : {}, "U1_XF.BC18" : {} } } }, "R34_FL_XF.2" : { "R34_FL_XF.1" : { "UNNAMED_8_LT3071_I30_EN_FL" : { "U5_FL_XF.28" : {} } } }, "U7_FL_XF.27" : {}, "R103.1" : { "R103.2" : { "UNNAMED_17_RESISTOR_I8_B" : { "U12.2" : {} } } }, "R213_XF.1" : { "R213_XF.2" : { "OCL1_FPGA_REFCLK_N_XF" : {} } }, "R5_E3_XF.1" : { "R5_E3_XF.2" : { "E1S3_3R3V_SMB_RST_F_XF" : { "J1_E3_XF.A9" : {}, "U1_XF.U19" : {} } } }, "R77.2" : { "R77.1" : { "UNNAMED_3_RESISTOR_I61_A" : { "FPNL_CONN.22" : {} } } }, "R273_XF.1" : { "R273_XF.2" : { "OCL3_3R3V_SCL_XF" : { "U1_XF.BC19" : {}, "J1_O3_XF.A9" : {} } } }, "J3.12" : {}, "J1_XF.284" : {}, "R35_FL_XF.2" : { "R35_FL_XF.1" : { "UNNAMED_5_LT3071_I30_V00_FL" : {} } }, "R3_FL_XF.2" : { "R3_FL_XF.1" : { "UNNAMED_5_LT3071_I30_V01_FL" : {} } }, "R107_FL_XF.2" : { "R107_FL_XF.1" : { "UNNAMED_9_LT3071_I66_V00_FL" : {} } }, "R2.1" : { "R2.2" : { "BASE_3R3V_SDA_2" : {} } }, "C4_FL_XF.1" : { "C4_FL_XF.2" : { "GND" : {} } }, "R7_E2_XF.1" : { "R7_E2_XF.2" : { "E1S2_3R3V_PERST_CLKREQ_F<1>_XF" : { "J1_E2_XF.A11" : {}, "U1_XF.P17" : {} } } }, "R3_E3_XF.1" : { "R3_E3_XF.2" : { "E1S3_3R3V_SCL_XF" : {} } }, "R13_FL_XF.2" : { "R13_FL_XF.1" : { "UNNAMED_3_LT3071_I32_V00_FL" : {} } }, "R54_FL_XF.2" : { "R54_FL_XF.1" : { "UNNAMED_8_LT3071_I30_V00_FL" : {} } }, "R57_SP_XF.2" : { "R57_SP_XF.1" : { "EMC1428_SYS_SHDN_OD_F" : { "U4_SP_XF.6" : {}, "U1_CPLD.P6" : {} } } }, "C83.2" : { "C83.1" : { "GND" : {} } }, "R105_FL_XF.2" : { "R105_FL_XF.1" : { "UNNAMED_9_LT3071_I66_V02_FL" : {} } }, "R7_E1_XF.1" : { "R7_E1_XF.2" : { "E1S1_3R3V_PERST_CLKREQ_F<1>_XF" : { "U1_XF.AE18" : {}, "J1_E1_XF.A11" : {} } } }, "R27_FL_XF.2" : { "R27_FL_XF.1" : { "UNNAMED_4_LT3071_I30_EN_FL" : { "U6_FL_XF.28" : {} } } }, "C71.2" : { "C71.1" : { "GND" : {} } }, "R6_E3_XF.1" : { "R6_E3_XF.2" : { "E1S3_3R3V_LED_XF" : { "U1_XF.U18" : {}, "J1_E3_XF.A10" : {} } } }, "U1_SP_XF.11" : {}, "R67_FL_XF.2" : { "R67_FL_XF.1" : { "UNNAMED_9_LT3071_I30_V01_FL" : {} } }, "C7_E0_XF.2" : { "C7_E0_XF.1" : { "GND" : {} } }, "R126_SP_XF.2" : { "R126_SP_XF.1" : { "EMC1428_ALERT_OD_F" : { "U4_SP_XF.7" : {}, "U1_CPLD.N7" : {} } } }, "R19_XF.1" : { "R19_XF.2" : { "C0_DDR4_SA<0>_XF" : { "J1_XF.139" : {} } } }, "R68_FL_XF.2" : { "R68_FL_XF.1" : { "UNNAMED_9_LT3071_I30_V00_FL" : {} } }, "R73_FL_XF.2" : { "R73_FL_XF.1" : { "UNNAMED_5_LT3071_I30_V02_FL" : {} } }, "C67_SP_XF.1" : { "C67_SP_XF.2" : { "GND" : {} } }, "C6_FL_XF.1" : { "C6_FL_XF.2" : { "GND" : {} } }, "J1_E3_XF.B11" : {}, "C126_SP_XF.1" : { "C126_SP_XF.2" : { "GND" : {} } }, "R69_FL_XF.2" : { "R69_FL_XF.1" : { "UNNAMED_3_LT3071_I32_EN_FL" : { "U3_FL_XF.28" : {} } } }, "R265_XF.1" : { "R265_XF.2" : { "C3_DDR4_SA<2>_XF" : { "J4_XF.238" : {} } } }, "R96_FL_XF.2" : { "R96_FL_XF.1" : { "UNNAMED_12_LT3071_I30_EN_FL" : { "U10_FL_XF.28" : {} } } }, "R8_E3_XF.1" : { "R8_E3_XF.2" : { "E1S3_3R3V_PRSNT_F<0>_XF" : { "U1_XF.T17" : {}, "J1_E3_XF.A12" : {} } } }, "R28_FL_XF.2" : { "R28_FL_XF.1" : { "UNNAMED_5_LT3071_I30_EN_FL" : { "U1_FL_XF.28" : {} } } }, "U1_SP_XF.12" : {}, "C49_SP_XF.1" : { "C49_SP_XF.2" : { "GND" : {} } }, "R52_FL_XF.2" : { "R52_FL_XF.1" : { "UNNAMED_6_LT3071_I30_V00_FL" : {} } }, "C178_SP_XF.1" : { "C178_SP_XF.2" : { "GND" : {} } }, "R41_FL_XF.2" : { "R41_FL_XF.1" : { "UNNAMED_8_LT3071_I30_V01_FL" : {} } }, "R230_XF.1" : { "R230_XF.2" : { "OCL0_3R3V_SCL_XF" : { "U1_XF.BM19" : {}, "J1_O0_XF.A9" : {} } } }, "R39_FL_XF.2" : { "R39_FL_XF.1" : { "UNNAMED_6_LT3071_I30_V01_FL" : {} } }, "U12.8" : {}, "R127_SP_XF.2" : { "R127_SP_XF.1" : { "IS_VCCINTUL_SW_N_SP" : {} } }, "U11.16" : {}, "J3.2" : {}, "R4_E3_XF.1" : { "R4_E3_XF.2" : { "E1S3_3R3V_SDA_XF" : {} } }, "R191_SP_XF.2" : { "R191_SP_XF.1" : { "IS_VCCINTLR_SW_N_SP" : {} } }, "J3.1" : {}, "C3_FL_XF.1" : { "C3_FL_XF.2" : { "GND" : {} } } }, "C3_RDIMM_DQS_C<5>_XF" : { "U1_XF.D21" : {}, "J4_XF.255" : {} }, "C1_DDR4_SA<2>_XF" : { "J2_XF.238" : {}, "R20_XF.2" : { "R20_XF.1" : { "GND" : {} } } }, "E1S3_PER_P<5>_XF" : { "U1_XF.AL6" : {}, "J1_E3_XF.A34" : {} }, "AC_FPGA_CLK_REF_N<1>_1" : { "C22_E0_XF.1" : { "C22_E0_XF.2" : { "E1S0_FPGA_REFCLK_N<1>_XF" : { "R172_XF.1" : { "R172_XF.2" : { "GND" : {} } }, "U1_XF.H12" : {}, "R162_XF.2" : { "R162_XF.1" : { "PWR_FPGA_3R3V" : {} } } } } }, "U1_E0_XF.28" : {} }, "E1S3_3R3V_PERST_F<0>_XF" : { "J1_E3_XF.B10" : {}, "U1_XF.T20" : {} }, "AC_E1S1_PET_P<3>_XF" : { "C114_XF.1" : { "C114_XF.2" : { "E1S1_PET_P<3>_XF" : { "J1_E1_XF.B27" : {} } } }, "U1_XF.L11" : {} }, "C2_DDR4_DQ<19>_XF" : { "U1_XF.D61" : {}, "J3_XF.179" : {} }, "VDDO7" : { "U1.49" : {}, "R15.2" : { "R15.1" : { "CPLD_P1R8V_1" : {} } }, "C13.1" : { "C13.2" : { "GND" : {} } } }, "OCL1_CONN_REFCLK_P_XF" : { "J1_O1_XF.B12" : {}, "C355_XF.2" : { "C355_XF.1" : { "AC_OCL1_CONN_REFCLK_P_XF" : { "U7_XF.17" : {} } } } }, "C2_DDR4_DQ<26>_XF" : { "J3_XF.45" : {}, "U1_XF.H52" : {} }, "UNNAMED_3_RESISTOR_I55_B" : { "FPNL_CONN.1" : {}, "R29.2" : { "R29.1" : { "P3R3V" : {} } } }, "E1S2_PET_P<6>_XF" : { "J1_E2_XF.B37" : {}, "C149_XF.2" : { "C149_XF.1" : { "AC_E1S2_PET_P<6>_XF" : { "U1_XF.AA11" : {} } } } }, "E1S0_PER_N<3>_XF" : { "U1_XF.D3" : {}, "J1_E0_XF.A26" : {} }, "UNNAMED_10_RESISTOR_I87_B_FL" : { "R8_FL_XF.2" : { "R8_FL_XF.1" : { "PWR_VCCAUX_SW_XF" : {} } }, "U8_FL_XF.5" : {} }, "PCIE_X1_RXN_XF" : { "J1_PX1_XF.B15" : {}, "U1_XF.BF3" : {} }, "AC_OCL3_PET_P<3>_XF" : { "U1_XF.BG7" : {}, "C254_XF.1" : { "C254_XF.2" : { "OCL3_PET_P<3>_XF" : { "J1_O3_XF.B18" : {} } } } }, "C0_RDIMM_DQS_C<1>_XF" : { "U1_XF.CA27" : {}, "J1_XF.163" : {} }, "UNNAMED_3_LTC2975_I168_PWRGD_SP" : { "U1_SP_XF.17" : {}, "R56_SP_XF.2" : { "R56_SP_XF.1" : { "POK_OD_LTC2975" : { "U1_CPLD.T15" : {} } } } }, "CLK_O_VIS_P_XF" : { "CLK_VIS_P_XF.1" : {}, "U1_XF.CA30" : {} }, "CFG_FLASH_CLK_XF" : { "R40_XF.2" : { "R40_XF.1" : { "UNNAMED_18_RESISTOR_I23_A_XF" : { "U1_XF.AM18" : {} } } }, "U3_XF.B2" : {}, "U2_XF.B2" : {} }, "C0_DDR4_ADR<10>_XF" : { "U1_XF.CC19" : {}, "J1_XF.225" : {} }, "UNNAMED_20_NMOSFETVMT3_I8_G" : { "R56.2" : { "R56.1" : { "FAN_PWM_OD" : { "U1_CPLD.J12" : {}, "R55.1" : { "R55.2" : { "UNNAMED_20_NMOSFETVMT3_I16_G" : { "Q8.1" : { "Q8.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I25_P4" : { "P3.4" : {} } }, "Q8.2" : { "GND" : {} } } } } }, "R39.1" : { "R39.2" : { "UNNAMED_20_NMOSFETVMT3_I20_G" : { "Q6.1" : { "Q6.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I30_P4" : { "P2.4" : {} } }, "Q6.2" : { "GND" : {} } } } } }, "R42.1" : { "R42.2" : { "UNNAMED_20_NMOSFETVMT3_I12_G" : { "Q7.1" : { "Q7.2" : { "GND" : {} }, "Q7.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I26_P4" : { "P4.4" : {} } } } } } } } } }, "Q9.1" : { "Q9.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I27_P4" : { "P5.4" : {} } }, "Q9.2" : { "GND" : {} } } }, "AC_E1S2_PET_N<0>_XF" : { "C173_XF.1" : { "C173_XF.2" : { "E1S2_PET_N<0>_XF" : { "J1_E2_XF.B17" : {} } } }, "U1_XF.W10" : {} }, "UNNAMED_4_LT3071_I30_EN_FL" : { "U6_FL_XF.28" : {}, "R27_FL_XF.1" : { "R27_FL_XF.2" : { "P3R3V" : {} } } }, "UNNAMED_7_SM050TP_I159_1_CPLD" : { "U1_CPLD.T2" : {}, "TP13_CPLD.1" : {} }, "E1S1_3R3V_SCL_XF" : { "R184_XF.2" : { "R184_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_XF.AG19" : {}, "J1_E1_XF.A7" : {}, "R3_E1_XF.2" : { "R3_E1_XF.1" : { "P3R3V" : {} } } }, "UNNAMED_3_LED_I24_C_MP" : { "U1_MP.14" : {}, "CPLD_P1R8V_FLT_MP.1" : { "CPLD_P1R8V_FLT_MP.2" : { "UNNAMED_3_LED_I24_A_MP" : { "R2_MP.2" : { "R2_MP.1" : { "P5VSB" : {} } } } } } }, "PCIE0_TXN<3>_XF" : { "C83_XF.2" : { "C83_XF.1" : { "AC_PCIE0_TXN<3>_XF" : { "U1_XF.AW10" : {} } } }, "J1_P0_XF.B19" : {} }, "UNNAMED_4_LTM4650FIXED_I78_PGOOD2_SP" : { "PM4_SP_XF.G8" : { "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} } } }, "AC_OCL0_PET_N<0>_XF" : { "C266_XF.1" : { "C266_XF.2" : { "OCL0_PET_N<0>_XF" : { "J1_O0_XF.B4" : {} } } }, "U1_XF.CC10" : {} }, "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {}, "PM2_SP_XF.R7" : { "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : { "R74.2" : { "R74.1" : { "GND" : {} } }, "C33.2" : { "C33.1" : { "GND" : {} } }, "U11.12" : {} } } } } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.E6" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} } } }, "UNNAMED_3_LTM4675_I40_GPIO1F_SD" : { "PM4_SD_XF.F2" : { "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } } } } } } } } } } } } } }, "U11.13" : {} } }, "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "C0_RDIMM_DQS_C<0>_XF" : { "U1_XF.CA22" : {}, "J1_XF.152" : {} }, "E1S3_PER_P<7>_XF" : { "J1_E3_XF.A40" : {}, "U1_XF.AK4" : {} }, "C0_DDR4_ADR<11>_XF" : { "U1_XF.CA21" : {}, "J1_XF.210" : {} }, "UNNAMED_7_SM050TP_I165_1_CPLD" : { "TP5_CPLD.1" : {}, "U1_CPLD.B5" : {} }, "E1S2_3R3V_PERST_CLKREQ_F<1>_XF" : { "J1_E2_XF.A11" : {}, "U1_XF.P17" : {}, "R7_E2_XF.2" : { "R7_E2_XF.1" : { "P3R3V" : {} } } }, "E1S2_PET_P<3>_XF" : { "C152_XF.2" : { "C152_XF.1" : { "AC_E1S2_PET_P<3>_XF" : { "U1_XF.U11" : {} } } }, "J1_E2_XF.B27" : {} }, "E1S0_PER_N<6>_XF" : { "J1_E0_XF.A36" : {}, "U1_XF.G5" : {} }, "PSU_3R3V_SDA" : { "Q11.3" : { "Q11.1" : { "UNNAMED_12_NMOSFETVMT3_I12_G" : { "R7.2" : { "R7.1" : { "UNNAMED_12_RESISTOR_I13_A" : { "R1.2" : { "R1.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "R4.2" : { "R4.1" : { "DIS_1R8V_I2C_XLAT_F" : { "R58.1" : { "R58.2" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } } } } } } } } }, "U1_CPLD.H3" : {} } } }, "R8.1" : { "R8.2" : { "UNNAMED_12_NMOSFETVMT3_I4_G" : { "Q10.1" : { "Q10.2" : { "PSU_1R8V_SCL" : { "R9.1" : { "R9.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.CA35" : {} } }, "Q10.3" : { "PSU_3R3V_SCL" : { "J4.1" : {}, "R25.2" : { "R25.1" : { "P3R3V" : {} } } } } } } } } } } } } }, "Q11.2" : { "PSU_1R8V_SDA" : { "R19.1" : { "R19.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.CA37" : {} } } } }, "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G9" : { "UNNAMED_4_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } }, "C1_RDIMM_DQS_T<10>_XF" : { "J2_XF.18" : {}, "U1_XF.BU50" : {} }, "E1S1_PER_P<3>_XF" : { "J1_E1_XF.A27" : {}, "U1_XF.M4" : {} }, "UNNAMED_3_RESISTOR_I70_B_E0" : { "R1_E0_XF.2" : { "R1_E0_XF.1" : { "GND" : {} } }, "J1_E0_XF.MH3" : {}, "J1_E0_XF.MH1" : {}, "J1_E0_XF.MH2" : {} }, "UNNAMED_17_RESISTOR_I51_A_XF" : { "R1_XF.2" : { "R1_XF.1" : { "VMON_AVCC_RN_LIN_XF" : { "R84_FL_XF.2" : { "R84_FL_XF.1" : { "VS_AVCC_RN_LIN_FL" : { "NS4_FL_XF.2" : { "NS4_FL_XF.1" : { "PWR_AVCC_RN_XF" : {} } }, "U6_FL_XF.19" : {} } } } } } }, "R76_XF.1" : { "R76_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I48_A_XF" : { "U1_XF.AM25" : {}, "C138_XF.1" : { "C138_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I48_B_XF" : { "R77_XF.2" : { "R77_XF.1" : { "UNNAMED_17_RESISTOR_I52_A_XF" : { "R3_XF.2" : { "R3_XF.1" : { "GND" : {} } }, "R4_XF.2" : { "R4_XF.1" : { "GND" : {} } } } } }, "U1_XF.AN24" : {} } } } } } }, "R2_XF.2" : { "R2_XF.1" : { "GND" : {} } } }, "C0_DDR4_DQ<13>_XF" : { "J1_XF.159" : {}, "U1_XF.CA25" : {} }, "UNNAMED_6_LTM4671_I457_FB1_SP" : { "PM2_SP_XF.H9" : { "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : {} } } } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} } } }, "OCL3_PER_N<3>_XF" : { "J1_O3_XF.A19" : {}, "U1_XF.BG1" : {} }, "PCIE0_RXN<2>_XF" : { "U1_XF.AW5" : {}, "J1_P0_XF.A16" : {} }, "VDDO0" : { "U1.22" : {}, "C16.1" : { "C16.2" : { "GND" : {} } }, "R18.2" : { "R18.1" : { "CPLD_P1R8V_1" : {} } } }, "UNNAMED_7_LTM4671_I37_MODECLKIN12_SP" : { "PM1_SP_XF.L9" : { "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {} } }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} } } }, "C3_RDIMM_DQS_T<1>_XF" : { "J4_XF.164" : {}, "U1_XF.L26" : {} }, "UNNAMED_4_PI6CB33401_I37_SCLK_E2" : { "R11_E2_XF.2" : { "R11_E2_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E2_XF.9" : {} }, "E1S0_3R3V_LED_XF" : { "U1_XF.AA17" : {}, "J1_E0_XF.A10" : {}, "R6_E0_XF.2" : { "R6_E0_XF.1" : { "P3R3V" : {} } } }, "UNNAMED_3_BYPASSCAPNPOL_I181_B_SP" : { "C68_SP_XF.2" : { "C68_SP_XF.1" : { "GND" : {} } }, "U1_SP_XF.51" : {} }, "UNNAMED_11_LTM4650FIXED_I150_PGOOD2_SP" : { "PM7_SP_XF.G8" : { "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} } }, "R96_SP_XF.1" : { "R96_SP_XF.2" : { "POK_OD_VCCINT_BRSW_P<1>" : { "U1_CPLD.R13" : {} } } } }, "FPGA_VCCAUX_P1R8V" : { "U1_XF.AN42" : {}, "C206_XF.1" : { "C206_XF.2" : { "GND" : {} } }, "R35.2" : { "R35.1" : { "FPGA_1R8V_SDA" : {} } }, "U4_XF.8" : {}, "R35_XF.1" : { "R35_XF.2" : { "FPGA_CFG_PUDC_F_XF" : { "U1_XF.AL17" : {} } } }, "R86_XF.1" : { "R86_XF.2" : { "VCCAUX_BNC_XF" : { "J7_XF.C" : {} } } }, "U1_XF.AT43" : {}, "R38_XF.1" : { "R38_XF.2" : { "FPGA_CFG_DONE_1" : { "U1_CPLD.H1" : {}, "U1_XF.AL18" : {} } } }, "C349_XF.1" : { "C349_XF.2" : { "GND" : {} } }, "C167_XF.2" : { "C167_XF.1" : { "GND" : {} } }, "R42_XF.1" : { "R42_XF.2" : { "CFG_FLASH_D02_0_XF" : { "U2_XF.C4" : {}, "U3_XF.C4" : {}, "U1_XF.AR19" : {} } } }, "U1_XF.AU44" : {}, "R114_FL_XF.1" : { "R114_FL_XF.2" : { "PWR_VCCAUX_A_FL" : {} } }, "R28_XF.1" : { "R28_XF.2" : { "FPGA_INIT_F_1" : { "U1_CPLD.J6" : {}, "U1_XF.AJ19" : {} } } }, "R34_XF.1" : { "R34_XF.2" : { "CFG_FLASH_RST_F" : {} } }, "C64_XF.2" : { "C64_XF.1" : { "GND" : {} } }, "C389_XF.1" : { "C389_XF.2" : { "GND" : {} } }, "U1_XF.AW44" : {}, "C87_XF.2" : { "C87_XF.1" : { "GND" : {} } }, "U1_XF.AM43" : {}, "C144_XF.1" : { "C144_XF.2" : { "GND" : {} } }, "C89_XF.1" : { "C89_XF.2" : { "GND" : {} } }, "C82_XF.2" : { "C82_XF.1" : { "GND" : {} } }, "R33.2" : { "R33.1" : { "FPGA_1R8V_SCL" : {} } }, "U1_XF.CA34" : {}, "U1_XF.AH43" : {}, "C207_XF.1" : { "C207_XF.2" : { "GND" : {} } }, "C208_XF.1" : { "C208_XF.2" : { "GND" : {} } }, "R64_XF.1" : { "R64_XF.2" : { "CFG_FLASH_D03_0_XF" : { "U3_XF.D4" : {}, "U1_XF.AP19" : {}, "U2_XF.D4" : {} } } }, "R11_XF.1" : { "R11_XF.2" : { "CFG_FLASH_RDWR_FCS_B_0_XF" : {} } }, "R66_XF.2" : { "R66_XF.1" : { "UNNAMED_15_MAX4641_I1_NO2_XF" : { "U4_XF.5" : {}, "U2_XF.C2" : {} } } }, "U1_XF.AJ42" : {}, "R65_XF.1" : { "R65_XF.2" : { "UNNAMED_15_MAX4641_I1_NO1_XF" : {} } }, "C145_XF.1" : { "C145_XF.2" : { "GND" : {} } }, "U1_XF.AK43" : {}, "FB2_XF.2" : { "FB2_XF.1" : { "VCCADC_XF" : {} } }, "U1_XF.AG44" : {}, "C90_XF.1" : { "C90_XF.2" : { "GND" : {} } }, "C178_XF.1" : { "C178_XF.2" : { "GND" : {} } }, "R16_XF.1" : { "R16_XF.2" : { "POR_OVERRIDE_XF" : {} } }, "U1_XF.BJ33" : {}, "R1.1" : { "R1.2" : { "UNNAMED_12_RESISTOR_I13_A" : {} } }, "U1_XF.AF43" : {}, "U3_XF.B4" : {}, "U1_XF.BW38" : {}, "U1_XF.BY31" : {}, "C205_XF.1" : { "C205_XF.2" : { "GND" : {} } }, "R19.2" : { "R19.1" : { "PSU_1R8V_SDA" : {} } }, "C57_XF.1" : { "C57_XF.2" : { "GND" : {} } }, "R115_FL_XF.2" : { "R115_FL_XF.1" : { "PWR_VCCAUX_B_FL" : {} } }, "R9.2" : { "R9.1" : { "PSU_1R8V_SCL" : {} } }, "U2_XF.B4" : {}, "C163_XF.2" : { "C163_XF.1" : { "GND" : {} } }, "U1_XF.BM32" : {}, "U1_XF.AE44" : {}, "U1_XF.AP43" : {}, "U1_XF.AD43" : {}, "U1_XF.BR31" : {}, "NS12_FL_XF.1" : { "NS12_FL_XF.2" : { "VS_VCCAUX_LIN_P_XF" : { "R25_SP_XF.2" : { "R25_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I154_A_SP" : {} } } } } }, "C88_XF.2" : { "C88_XF.1" : { "GND" : {} } }, "U1_XF.AG42" : {}, "U1_XF.AV43" : {}, "U1_XF.AY43" : {}, "C291_XF.1" : { "C291_XF.2" : { "GND" : {} } }, "C165_XF.2" : { "C165_XF.1" : { "GND" : {} } }, "U1_XF.AL42" : {}, "U1_XF.AM17" : {}, "U1_XF.BA44" : {}, "U1_XF.AR42" : {}, "U1_XF.AU42" : {}, "U1_XF.AT19" : {}, "R37_XF.1" : { "R37_XF.2" : { "CFG_FLASH_RST_F" : {} } }, "R116_XF.2" : { "R116_XF.1" : { "UNNAMED_15_MAX4641_I1_IN2_XF" : {} } }, "C164_XF.2" : { "C164_XF.1" : { "GND" : {} } }, "C161_XF.2" : { "C161_XF.1" : { "GND" : {} } }, "R27.1" : { "R27.2" : { "UNNAMED_13_RESISTOR_I101_A" : {} } } }, "C3_RDIMM_DQS_T<0>_XF" : { "U1_XF.L18" : {}, "J4_XF.153" : {} }, "AC_OCL1_CONN_REFCLK_N_XF" : { "C383_XF.1" : { "C383_XF.2" : { "OCL1_CONN_REFCLK_N_XF" : { "J1_O1_XF.B13" : {} } } }, "U7_XF.18" : {} }, "AC_CONN_CLK_REFP<0>_1" : { "C21_E0_XF.1" : { "C21_E0_XF.2" : { "CONN_CLK_REFP<0>_E0" : { "J1_E0_XF.B15" : {} } } }, "U1_E0_XF.13" : {} }, "PWR_AVCC_RUC_XF" : { "U10_FL_XF.18" : {}, "U1_XF.W13" : {}, "U10_FL_XF.17" : {}, "U10_FL_XF.16" : {}, "U1_XF.AF15" : {}, "C455_XF.1" : { "C455_XF.2" : { "GND" : {} } }, "C97_FL_XF.1" : { "C97_FL_XF.2" : { "GND" : {} } }, "U1_XF.AH15" : {}, "C87_FL_XF.1" : { "C87_FL_XF.2" : { "GND" : {} } }, "U1_XF.Y15" : {}, "C456_XF.1" : { "C456_XF.2" : { "GND" : {} } }, "NS1_FL_XF.1" : { "NS1_FL_XF.2" : { "VS_AVCC_RUC_LIN_FL" : {} } }, "C454_XF.1" : { "C454_XF.2" : { "GND" : {} } }, "U1_XF.AA13" : {}, "C88_FL_XF.1" : { "C88_FL_XF.2" : { "GND" : {} } }, "C453_XF.1" : { "C453_XF.2" : { "GND" : {} } }, "U10_FL_XF.15" : {}, "C96_FL_XF.1" : { "C96_FL_XF.2" : { "GND" : {} } }, "U1_XF.AB15" : {}, "U1_XF.V15" : {}, "U1_XF.AD15" : {} }, "MGTRREF_LN_XF" : { "R267_XF.2" : { "R267_XF.1" : { "PWR_AVTT_RUC_XF" : {} } }, "U1_XF.AJ14" : {} }, "UNNAMED_12_LT3071_I30_PWRGD_FL" : { "U10_FL_XF.2" : {}, "R92_FL_XF.1" : { "R92_FL_XF.2" : { "POK_OD_AVCC_RUC_LIN" : { "U1_CPLD.R10" : {} } } } }, "E1S1_PER_P<6>_XF" : { "J1_E1_XF.A37" : {}, "U1_XF.T4" : {} }, "UNNAMED_4_MAX116XXQSOP16_I97_AIN3" : { "R45.1" : { "R45.2" : { "VMON_NDIMM_VTT_LIN" : { "R4_ND_XF.2" : { "R4_ND_XF.1" : { "VS_DIMM_VTT_LIN_ND" : { "NS3_ND_XF.2" : { "NS3_ND_XF.1" : { "PWR_NDIMM_VTT_XF" : {} } }, "U2_ND_XF.5" : {} } } } } } }, "C46.1" : { "C46.2" : { "GND" : {} } }, "U11.8" : {} }, "C0_DDR4_DQ<27>_XF" : { "U1_XF.BU25" : {}, "J1_XF.190" : {} }, "CFG_FLASH_RDWR_FCS_B_0_XF" : { "R117_XF.1" : { "R117_XF.2" : { "UNNAMED_15_MAX4641_I1_NO1_XF" : { "U4_XF.1" : {}, "U3_XF.C2" : {}, "R65_XF.2" : { "R65_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U4_XF.2" : {}, "U1_XF.AN17" : {}, "R11_XF.2" : { "R11_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U4_XF.6" : {} }, "C0_RDIMM_DQS_C<15>_XF" : { "J1_XF.122" : {}, "U1_XF.BJ24" : {} }, "PSU_SMBALERTN_OD" : { "J4.3" : {}, "U1_CPLD.M7" : {} }, "E1S0_PET_P<2>_XF" : { "J1_E0_XF.B24" : {}, "C107_XF.2" : { "C107_XF.1" : { "AC_E1S0_PET_P<2>_XF" : { "U1_XF.A11" : {} } } } }, "OCL3_3R3V_SDA_XF" : { "J1_O3_XF.A10" : {}, "R274_XF.2" : { "R274_XF.1" : { "P3R3V" : {} } }, "U1_XF.BC18" : {} }, "UNNAMED_10_LTM4650FIXED_I151_RUN1_SP" : { "R16_SP_XF.2" : { "R16_SP_XF.1" : { "ENB3V_SEQ_A" : { "U1_CPLD.P15" : {}, "R16_CPLD.1" : { "R16_CPLD.2" : { "GND" : {} } }, "R78_SP_XF.1" : { "R78_SP_XF.2" : { "UNNAMED_11_LTM4650FIXED_I150_RUN1_SP" : { "PM7_SP_XF.F5" : { "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "PM4_SP_XF.E6" : { "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} } } } } } } } } }, "PCIE1_RXP<0>_XF" : { "J1_P1_XF.A3" : {}, "U1_XF.AN2" : {} }, "E1S0_3R3V_CKEN_F<1>_XF" : { "U1_E0_XF.19" : {}, "U1_XF.W17" : {} }, "CFG_FLASH_D02_0_XF" : { "U1_XF.AR19" : {}, "R42_XF.2" : { "R42_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U3_XF.C4" : {}, "U2_XF.C4" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I153_A_SP" : { "C16_SP_XF.1" : { "C16_SP_XF.2" : { "GND" : {} } }, "R30_SP_XF.1" : { "R30_SP_XF.2" : { "VS_AVCC_LIN_N_XF" : { "NS6_FL_XF.2" : { "NS6_FL_XF.1" : { "GND" : {} } } } } }, "U1_SP_XF.62" : {} }, "UNNAMED_5_LT3071_I30_EN_FL" : { "R28_FL_XF.1" : { "R28_FL_XF.2" : { "P3R3V" : {} } }, "U1_FL_XF.28" : {} }, "AC_FPGA_CLK_REF_P<0>" : { "U1_E1_XF.22" : {}, "C19_E1_XF.1" : { "C19_E1_XF.2" : { "E1S1_FPGA_REFCLK_P<0>_XF" : { "U1_XF.P13" : {}, "R168_XF.2" : { "R168_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R179_XF.1" : { "R179_XF.2" : { "GND" : {} } } } } } }, "C1_DDR4_BG<0>_XF" : { "U1_XF.CA56" : {}, "J2_XF.63" : {} }, "AC_OCL0_FPGA_REFCLK_P_XF" : { "U7_XF.22" : {}, "C354_XF.1" : { "C354_XF.2" : { "OCL0_FPGA_REFCLK_P_XF" : { "U1_XF.CB13" : {}, "R210_XF.2" : { "R210_XF.1" : { "P3R3V" : {} } }, "R218_XF.1" : { "R218_XF.2" : { "GND" : {} } } } } } }, "OCL_REF_CLK_N<0>" : { "U7_XF.6" : {}, "U1.41" : {}, "R276_XF.2" : { "R276_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R281_XF.1" : { "R281_XF.2" : { "GND" : {} } }, "R280_XF.2" : { "R280_XF.1" : { "OCL_REF_CLK_P<0>" : {} } } }, "C2_DDR4_DQ<40>_XF" : { "U1_XF.B54" : {}, "J3_XF.108" : {} }, "FPGA_P1R8V_TDI" : { "U1_CPLD.F5" : {}, "U1_XF.AN19" : {} }, "UNNAMED_12_LT3071_I30_VIOC_FL" : { "U10_FL_XF.1" : {}, "C89_FL_XF.1" : { "C89_FL_XF.2" : { "GND" : {} } } }, "POK_OD_AVTT_RS_LIN" : { "U1_CPLD.T9" : {}, "R18_FL_XF.2" : { "R18_FL_XF.1" : { "UNNAMED_6_LT3071_I30_PWRGD_FL" : { "U2_FL_XF.2" : {} } } } }, "AC_E1S2_PET_P<6>_XF" : { "U1_XF.AA11" : {}, "C149_XF.1" : { "C149_XF.2" : { "E1S2_PET_P<6>_XF" : { "J1_E2_XF.B37" : {} } } } }, "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } }, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "E1S1_3R3V_CKEN_F<0>_XF" : { "U1_XF.AC17" : {}, "U1_E1_XF.12" : {} }, "C3_DDR4_DQ<16>_XF" : { "U1_XF.H27" : {}, "J4_XF.27" : {} }, "UNNAMED_7_SM050TP_I170_1_CPLD" : { "U1_CPLD.N2" : {}, "TP7_CPLD.1" : {} }, "UNNAMED_5_LT3071_I30_IMON_FL" : { "U1_FL_XF.21" : {}, "R24_FL_XF.1" : { "R24_FL_XF.2" : { "IMON_AVTT_LIN_XF" : { "R133_XF.2" : { "R133_XF.1" : { "UNNAMED_17_RESISTOR_I101_A_XF" : { "R134_XF.1" : { "R134_XF.2" : { "UNNAMED_17_RESISTOR_I101_B_XF" : { "R120_XF.1" : { "R120_XF.2" : { "GND" : {} } } } } }, "R127_XF.2" : { "R127_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I107_A_XF" : { "U1_XF.CB33" : {}, "C267_XF.1" : { "C267_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I107_B_XF" : { "U1_XF.CC33" : {}, "R128_XF.1" : { "R128_XF.2" : { "UNNAMED_17_RESISTOR_I104_A_XF" : { "R136_XF.1" : { "R136_XF.2" : { "UNNAMED_17_RESISTOR_I105_B_XF" : { "R121_XF.1" : { "R121_XF.2" : { "GND" : {} } } } } }, "R135_XF.1" : { "R135_XF.2" : { "GND" : {} } } } } } } } } } } } } } }, "R25_FL_XF.2" : { "R25_FL_XF.1" : { "UNNAMED_6_LT3071_I30_IMON_FL" : { "U2_FL_XF.21" : {} } } }, "R82_FL_XF.2" : { "R82_FL_XF.1" : { "UNNAMED_8_LT3071_I30_IMON_FL" : { "U5_FL_XF.21" : {}, "R26_FL_XF.2" : { "R26_FL_XF.1" : { "GND" : {} } } } } }, "R64_FL_XF.2" : { "R64_FL_XF.1" : { "UNNAMED_7_LT3071_I30_IMON_FL" : { "U4_FL_XF.21" : {} } } } } } } }, "JT_CPLD_TMS" : { "R66.1" : { "R66.2" : { "CPLD_P1R8V_1" : {} } }, "U2_CPLD.1" : {}, "J5.11" : {} }, "UNNAMED_7_SM050TP_I164_1_CPLD" : { "U1_CPLD.A5" : {}, "TP1_CPLD.1" : {} }, "C0_RDIMM_DQS_T<5>_XF" : { "U1_XF.BP27" : {}, "J1_XF.256" : {} }, "C3_DDR4_ACT_N_XF" : { "J4_XF.62" : {}, "U1_XF.U24" : {} }, "E1S2_PER_N<2>_XF" : { "J1_E2_XF.A23" : {}, "U1_XF.Y3" : {} }, "OCL3_3R3V_BP_TYPE_XF" : { "U1_XF.AW19" : {}, "J1_O3_XF.B9" : {} }, "AC_E1S2_PET_N<7>_XF" : { "C156_XF.1" : { "C156_XF.2" : { "E1S2_PET_N<7>_XF" : { "J1_E2_XF.B39" : {} } } }, "U1_XF.Y8" : {} }, "C3_DDR4_DQ<29>_XF" : { "J4_XF.181" : {}, "U1_XF.E24" : {} }, "SDIMM_VDD_BNC_XF" : { "J11_XF.C" : {}, "R101_XF.2" : { "R101_XF.1" : { "PWR_SDIMM_VDD_XF" : {} } } }, "SW2_4650_TR_SP" : { "PM5_SP_XF.G11" : { "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "PM4_SP_XF.E6" : { "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} } } }, "NDIMM_LTM4675_ALERT_OD_F_1" : { "PM4_ND_XF.E3" : { "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } } } }, "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} } }, "U1_CPLD.M6" : {} }, "C2_RDIMM_DQS_T<11>_XF" : { "U1_XF.F61" : {}, "J3_XF.29" : {} }, "AC_FPGA_CLK_REF_N<1>_3" : { "C22_E2_XF.1" : { "C22_E2_XF.2" : { "E1S2_FPGA_REFCLK_N<1>_XF" : { "R187_XF.2" : { "R187_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R196_XF.1" : { "R196_XF.2" : { "GND" : {} } }, "U1_XF.AA14" : {} } } }, "U1_E2_XF.28" : {} }, "AC_OCL2_PET_P<1>_XF" : { "U1_XF.BM9" : {}, "C237_XF.1" : { "C237_XF.2" : { "OCL2_PET_P<1>_XF" : { "J1_O2_XF.B6" : {} } } } }, "AC_FPGA_CLK_REF_P<0>_2" : { "U1_E3_XF.22" : {}, "C19_E3_XF.1" : { "C19_E3_XF.2" : { "E1S3_FPGA_REFCLK_P<0>_XF" : { "R192_XF.2" : { "R192_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R203_XF.1" : { "R203_XF.2" : { "GND" : {} } }, "U1_XF.AG15" : {} } } } }, "C0_DDR4_ADR<16>_XF" : { "U1_XF.CC18" : {}, "J1_XF.82" : {} }, "UNNAMED_5_LT3071_I30_V00_FL" : { "R1_FL_XF.2" : { "R1_FL_XF.1" : { "GND" : {} } }, "R35_FL_XF.1" : { "R35_FL_XF.2" : { "P3R3V" : {} } }, "U1_FL_XF.23" : {} }, "E1S3_PET_P<0>_XF" : { "C343_XF.2" : { "C343_XF.1" : { "AC_E1S3_PET_P<0>_XF" : { "U1_XF.AH13" : {} } } }, "J1_E3_XF.B18" : {} }, "C0_DDR4_DQ<53>_XF" : { "U1_XF.BJ21" : {}, "J1_XF.262" : {} }, "UNNAMED_11_LTM4650FIXED_I150_PGOOD1_SP" : { "R95_SP_XF.1" : { "R95_SP_XF.2" : { "POK_OD_VCCINT_BRSW_P<0>" : { "U1_CPLD.T14" : {} } } }, "PM7_SP_XF.G9" : { "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} } } }, "C2_DDR4_DQ<6>_XF" : { "J3_XF.10" : {}, "U1_XF.T51" : {} }, "C0_DDR4_ALERT_N_XF" : { "U1_XF.BP20" : {}, "J1_XF.208" : {}, "R234_XF.2" : { "R234_XF.1" : { "PWR_SDIMM_VDD_XF" : {} } } }, "NC_TR_1_SP" : {}, "UNNAMED_21_RESISTOR_I32_B_XF" : { "R30_XF.2" : { "R30_XF.1" : { "GND" : {} } }, "U1_XF.BR49" : {} }, "UNNAMED_4_PI6CB33401_I37_OE2F_E3" : { "R2_E3_XF.2" : { "R2_E3_XF.1" : { "GND" : {} } }, "U1_E3_XF.29" : {}, "U1_E3_XF.24" : {} }, "C0_DDR4_DQ<61>_XF" : { "J1_XF.273" : {}, "U1_XF.BK28" : {} }, "VMON_SP_9" : { "ADC_SPARE.1" : {}, "R70.1" : { "R70.2" : { "UNNAMED_4_BYPASSCAPNPOL_I101_B" : { "C52.2" : { "C52.1" : { "GND" : {} } }, "U11.3" : {}, "R71.2" : { "R71.1" : { "GND" : {} } } } } } }, "OCL1_PET_N<0>_XF" : { "C273_XF.2" : { "C273_XF.1" : { "AC_OCL1_PET_N<0>_XF" : { "U1_XF.CA6" : {} } } }, "J1_O1_XF.B4" : {} }, "C2_RDIMM_DQS_C<9>_XF" : { "J3_XF.8" : {}, "U1_XF.U51" : {} }, "C1_RDIMM_DQS_C<4>_XF" : { "J2_XF.244" : {}, "U1_XF.BT63" : {} }, "UNNAMED_4_RESISTOR_I17_A_ND" : { "R66_ND_XF.1" : { "R66_ND_XF.2" : { "DIMM_VTT_3VFLT_ND" : { "FB6_ND_XF.2" : { "FB6_ND_XF.1" : { "P3R3V" : {} } }, "U2_ND_XF.10" : {}, "C43_ND_XF.1" : { "C43_ND_XF.2" : { "GND" : {} } } } } }, "U2_ND_XF.7" : {} }, "MGTRREF_LS_XF" : { "R268_XF.2" : { "R268_XF.1" : { "PWR_AVTT_RLC_XF" : {} } }, "U1_XF.BE14" : {} }, "C0_DDR4_DQ<31>_XF" : { "J1_XF.188" : {}, "U1_XF.BV24" : {} }, "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "PM2_SP_XF.P7" : { "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.E6" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : { "U11.12" : {}, "R74.2" : { "R74.1" : { "GND" : {} } }, "C33.2" : { "C33.1" : { "GND" : {} } } } } } } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} } }, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } }, "C0_RDIMM_DQS_C<6>_XF" : { "J1_XF.266" : {}, "U1_XF.BH23" : {} }, "NDIMM_I2C_ASEL_RESISTOR_XF" : { "PM4_ND_XF.G2" : { "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { 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"PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" 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"PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {}, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} } } } } } }, "AC_E1S0_PET_P<1>_XF" : { "U1_XF.B9" : {}, "C108_XF.1" : { "C108_XF.2" : { "E1S0_PET_P<1>_XF" : { "J1_E0_XF.B21" : {} } } } }, "UNNAMED_7_SM050TP_I154_1_CPLD" : { "U1_CPLD.C15" : {}, "TP14_CPLD.1" : {} }, "UNNAMED_17_RESISTOR_I52_A_XF" : { "R3_XF.2" : { "R3_XF.1" : { "GND" : {} } }, "R77_XF.1" : { "R77_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I48_B_XF" : { "C138_XF.2" : { "C138_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I48_A_XF" : { "R76_XF.2" : { "R76_XF.1" : { "UNNAMED_17_RESISTOR_I51_A_XF" : { "R1_XF.2" : { "R1_XF.1" : { "VMON_AVCC_RN_LIN_XF" : { "R84_FL_XF.2" : { "R84_FL_XF.1" : { "VS_AVCC_RN_LIN_FL" : { "U6_FL_XF.19" : {}, "NS4_FL_XF.2" : { "NS4_FL_XF.1" : { "PWR_AVCC_RN_XF" : {} } } } } } } } }, "R2_XF.2" : { "R2_XF.1" : { "GND" : {} } } } } }, "U1_XF.AM25" : {} } } }, "U1_XF.AN24" : {} } } }, "R4_XF.2" : { "R4_XF.1" : { "GND" : {} } } }, "OCL2_PET_N<1>_XF" : { "J1_O2_XF.B7" : {}, "C276_XF.2" : { "C276_XF.1" : { "AC_OCL2_PET_N<1>_XF" : { "U1_XF.BM8" : {} } } } }, "AC_PCIE0_TXP<3>_XF" : { "C38_XF.1" : { "C38_XF.2" : { "PCIE0_TXP<3>_XF" : { "J1_P0_XF.B18" : {} } } }, "U1_XF.AW11" : {} }, "UNNAMED_7_LTM4671_I36_VOSNS3N_SP" : { "PM1_SP_XF.P10" : { "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {}, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} } } }, "PCIE_X1_RXP_XF" : { "J1_PX1_XF.B14" : {}, "U1_XF.BF4" : {} }, "POK_OD_SDIMM_VTT_LIN" : { "R61_SD_XF.2" : { "R61_SD_XF.1" : { "UNNAMED_4_RESISTOR_I7_A_SD" : { "U2_SD_XF.9" : {} } } }, "U1_CPLD.T7" : {} }, "C0_RDIMM_DQS_C<8>_XF" : { "U1_XF.BV28" : {}, "J1_XF.196" : {} }, "C1_RDIMM_DQS_C<2>_XF" : { "U1_XF.BV57" : {}, "J2_XF.174" : {} }, "AC_E1S1_PET_N<2>_XF" : { "U1_XF.M8" : {}, "C135_XF.1" : { "C135_XF.2" : { "E1S1_PET_N<2>_XF" : { "J1_E1_XF.B23" : {} } } } }, "PM1_SP_AGND_SP" : { "C136_SP_XF.1" : { "C136_SP_XF.2" : { "UNNAMED_7_LTM4671_I36_FB3_SP" : {} } }, "R102_SP_XF.1" : { "R102_SP_XF.2" : { "UNNAMED_7_LTM4671_I36_PHMODE3_SP" : {} } }, "C106_SP_XF.1" : { "C106_SP_XF.2" : { "UNNAMED_7_LTM4671_I36_TRACKSS3_SP" : {} } }, "R104_SP_XF.1" : { "R104_SP_XF.2" : { "UNNAMED_7_LTM4671_I87_FREQ0_SP" : {} } }, "R101_SP_XF.1" : { "R101_SP_XF.2" : { "UNNAMED_7_LTM4671_I87_PHMODE0_SP" : {} } }, "C135_SP_XF.1" : { "C135_SP_XF.2" : { "UNNAMED_7_LTM4671_I87_FB0_SP" : {} } }, "C105_SP_XF.1" : { "C105_SP_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I55_B_SP" : {} } }, "R106_SP_XF.1" : { "R106_SP_XF.2" : { "UNNAMED_7_LTM4671_I36_FREQ3_SP" : {} } }, "R105_SP_XF.1" : { "R105_SP_XF.2" : { "UNNAMED_7_LTM4671_I37_FREQ12_SP" : {} } }, "NS5_SP_XF.1" : { "NS5_SP_XF.2" : { "GND" : {} } }, "C104_SP_XF.1" : { "C104_SP_XF.2" : { "UNNAMED_7_LTM4671_I87_TRACKSS0_SP" : {} } }, "R64_SP_XF.1" : { "R64_SP_XF.2" : { "UNNAMED_7_RESISTOR_I61_A_SP" : {} } }, "R103_SP_XF.1" : { "R103_SP_XF.2" : { "UNNAMED_7_LTM4671_I36_RUN3_SP" : { "R107_SP_XF.1" : { "R107_SP_XF.2" : { "ENB3V_SEQ_F" : { "R11_CPLD.1" : { "R11_CPLD.2" : { "GND" : {} } }, "U1_CPLD.M15" : {} } } }, "PM1_SP_XF.P7" : {} } } }, "C108_SP_XF.1" : { "C108_SP_XF.2" : { "UNNAMED_7_LTM4671_I39_TRACKSS2_SP" : {} } }, "R58_SP_XF.1" : { "R58_SP_XF.2" : { "UNNAMED_7_RESISTOR_I42_A_SP" : {} } }, "C109_SP_XF.1" : { "C109_SP_XF.2" : { "UNNAMED_7_LTM4671_I37_TRACKSS1_SP" : {} } }, "C107_SP_XF.1" : { "C107_SP_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I64_B_SP" : {} } }, "C138_SP_XF.1" : { "C138_SP_XF.2" : { "UNNAMED_7_LTM4671_I39_FB2_SP" : {} } }, "C137_SP_XF.1" : { "C137_SP_XF.2" : { "UNNAMED_7_LTM4671_I37_FB1_SP" : {} } }, "C103_SP_XF.1" : { "C103_SP_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I44_B_SP" : {} } }, "R59_SP_XF.1" : { "R59_SP_XF.2" : { "UNNAMED_7_RESISTOR_I53_A_SP" : { "R71_SP_XF.1" : { "R71_SP_XF.2" : { "UNNAMED_7_LTM4671_I36_FB3_SP" : {} } } } } }, "R65_SP_XF.1" : { "R65_SP_XF.2" : { "UNNAMED_7_RESISTOR_I68_A_SP" : {} } } }, "UNNAMED_4_PI6CB33401_I37_BWSELTRI_E0" : { "U1_E0_XF.1" : {}, "R10_E0_XF.2" : { "R10_E0_XF.1" : { "GND" : {} } } }, "UNNAMED_11_LTM4650FIXED_I150_MODEPLLIN_SP" : { "R60_SP_XF.2" : { "R60_SP_XF.1" : { "CKO_LTM4650_PM3_SP" : { "R135_SP_XF.2" : { "R135_SP_XF.1" : { "UNNAMED_10_LTM4650FIXED_I151_CLKOUT_SP" : { "PM3_SP_XF.G5" : { "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.G3" : { "GND" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} } } } }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K5" : { "GND" : {} } } } } } } } } }, "UNNAMED_3_OCULINKX4CONN_I86_REFCLKN_P0" : { "J1_P0_XF.B13" : {}, "R2_P0_XF.1" : { "R2_P0_XF.2" : { "PCIE0_REFN_XF" : { "C288_XF.1" : { "C288_XF.2" : { "AC_PCIE0_REFN_XF" : { "U1_XF.BB12" : {} } } } } } } }, "P12V_4650_ULEFT_SP" : { "U5_SP_XF.3_4" : {}, "C33_SP_XF.1" : { "C33_SP_XF.2" : { "GND" : {} } }, "F4_SP_XF.1" : { "F4_SP_XF.2" : { "P12V_4650_TL_SP" : {} } } }, "CLK_O_VIS_N_XF" : { "CLK_VIS_N_XF.1" : {}, "U1_XF.CB30" : {} }, "C3_DDR4_BG<1>_XF" : { "J4_XF.207" : {}, "U1_XF.T25" : {} }, "UNNAMED_22_RESISTOR_I60_B_XF" : { "U1_XF.BV32" : {}, "R159_XF.2" : { "R159_XF.1" : { "GND" : {} } } }, "POK_OD_VCCINT_BRSW_P<0>" : { "U1_CPLD.T14" : {}, "R95_SP_XF.2" : { "R95_SP_XF.1" : { "UNNAMED_11_LTM4650FIXED_I150_PGOOD1_SP" : { "PM7_SP_XF.G9" : { "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H6" : { "GND" : {} } } } } } }, "FP_RST_SW_N" : { "FPNL_CONN.15" : {}, "D1.3" : { "D1.2" : { "UNNAMED_3_598BICOLORLED_I68_L2C" : {} }, "D1.1" : { "UNNAMED_3_598BICOLORLED_I68_L2A" : { "R79.2" : { "R79.1" : { "P3R3V" : {} } } } }, "D1.4" : { "GND" : {} } }, "U1_CPLD.J13" : {}, "R78.2" : { "R78.1" : { "P3R3V" : {} } }, "S2.3" : { "S2.1" : { "GND" : {} }, "S2.4" : { "GND" : {} }, "S2.2" : { "UNNAMED_3_598BICOLORLED_I68_L2C" : {} } } }, "UNNAMED_8_1G97_I18_Y_CPLD" : { "U4_CPLD.4" : {}, "R18_CPLD.1" : { "R18_CPLD.2" : { "CPLD_TCK_PIN_CPLD" : { "U1_CPLD.A7" : {} } } } }, "C2_DDR4_CK_C<0>_XF" : { "J3_XF.75" : {}, "U1_XF.L63" : {} }, "C3_DDR4_DQ<41>_XF" : { "U1_XF.D24" : {}, "J4_XF.253" : {} }, "SW2_4650_BL_SP" : { "PM3_SP_XF.G11" : { "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.G3" : { "GND" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F12" : { "GND" : {} } } }, "C2_DDR4_SA<0>_XF" : { "J3_XF.139" : {}, "R12_XF.2" : { "R12_XF.1" : { "GND" : {} } } }, "C0_DDR4_DQ<28>_XF" : { "U1_XF.BR22" : {}, "J1_XF.36" : {} }, "C3_DDR4_DQ<56>_XF" : { "U1_XF.B20" : {}, "J4_XF.130" : {} }, "CPLD_FPGA_DVAL_1" : { "U1_CPLD.F9" : {}, "U1_XF.CB36" : {} }, "SI5341_VDD" : { "U1.60" : {}, "C6.2" : { "C6.1" : { "GND" : {} } }, "C2.1" : {}, "U1.32" : {}, "C4.2" : { "C4.1" : { "GND" : {} } }, "U1.46" : {}, "C5.2" : { "C5.1" : { "GND" : {} } } }, "UNNAMED_6_RESISTOR_I469_A_SP" : { "R55_SP_XF.1" : { "R55_SP_XF.2" : { "UNNAMED_6_LTM4671_I457_FB1_SP" : { "PM2_SP_XF.H9" : { "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : {} } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} } } } } } }, "PWR_FPGA_3R3V" : { "C15_E2_XF.1" : { "C15_E2_XF.2" : { "GND" : {} } }, "C347_XF.1" : { "C347_XF.2" : { "GND" : {} } }, "U1_E3_XF.21" : {}, "R161_XF.1" : { "R161_XF.2" : { "E1S0_FPGA_REFCLK_P<1>_XF" : {} } }, "R276_XF.1" : { "R276_XF.2" : { "OCL_REF_CLK_N<0>" : {} } }, "C3_E3_XF.2" : { "C3_E3_XF.1" : { "GND" : {} } }, "R162_XF.1" : { "R162_XF.2" : { "E1S0_FPGA_REFCLK_N<1>_XF" : {} } }, "R11_E3_XF.1" : { "R11_E3_XF.2" : { "UNNAMED_4_PI6CB33401_I37_SCLK_E3" : { "U1_E3_XF.9" : {} } } }, "C2_E3_XF.2" : { "C2_E3_XF.1" : { "GND" : {} } }, "U1_XF.BM17" : {}, "C309_XF.2" : { "C309_XF.1" : { "GND" : {} } }, "R188_XF.1" : { "R188_XF.2" : { "E1S2_FPGA_REFCLK_P<0>_XF" : {} } }, "U1_E0_XF.25" : {}, "U5_XF.4" : {}, "C14_E2_XF.1" : { "C14_E2_XF.2" : { "GND" : {} } }, "R87_XF.1" : { "R87_XF.2" : { "UNNAMED_29_PI6CB33401_I63_SDATA_XF" : { "U5_XF.10" : {} } } }, "R11_E0_XF.1" : { "R11_E0_XF.2" : { "UNNAMED_4_PI6CB33401_I37_SCLK_E0" : { "U1_E0_XF.9" : {} } } }, "C15_E0_XF.1" : { "C15_E0_XF.2" : { "GND" : {} } }, "C350_XF.2" : { "C350_XF.1" : { "GND" : {} } }, "R277_XF.1" : { "R277_XF.2" : { "OCL_REF_CLK_P<1>" : {} } }, "U1_E0_XF.21" : {}, "Q13.6" : {}, "C15_E3_XF.1" : { "C15_E3_XF.2" : { "GND" : {} } }, "C3_E0_XF.2" : { "C3_E0_XF.1" : { "GND" : {} } }, "C14_E3_XF.1" : { "C14_E3_XF.2" : { "GND" : {} } }, "U1_E3_XF.25" : {}, "U1_XF.AF19" : {}, "Q13.7" : {}, "C14_E0_XF.1" : { "C14_E0_XF.2" : { "GND" : {} } }, "C2_E0_XF.2" : { "C2_E0_XF.1" : { "GND" : {} } }, "Q13.5" : {}, "U1_XF.AB17" : {}, "R11_E2_XF.1" : { "R11_E2_XF.2" : { "UNNAMED_4_PI6CB33401_I37_SCLK_E2" : { "U1_E2_XF.9" : {} } } }, "C1_E2_XF.2" : { "C1_E2_XF.1" : { "GND" : {} } }, "R126_XF.1" : { "R126_XF.2" : { "UNNAMED_29_PI6CB33401_I63_SCLK_XF" : { "U5_XF.9" : {} } } }, "R9_E1_XF.1" : { "R9_E1_XF.2" : { "UNNAMED_4_PI6CB33401_I37_SDATA_E1" : { "U1_E1_XF.10" : {} } } }, "U1_E0_XF.15" : {}, "R9_E2_XF.1" : { "R9_E2_XF.2" : { "UNNAMED_4_PI6CB33401_I37_SDATA_E2" : { "U1_E2_XF.10" : {} } } }, "C1_E1_XF.2" : { "C1_E1_XF.1" : { "GND" : {} } }, "U1_E3_XF.11" : {}, "C282_XF.2" : { "C282_XF.1" : { "GND" : {} } }, "C295_XF.2" : { "C295_XF.1" : { "GND" : {} } }, "R88_XF.1" : { "R88_XF.2" : { "UNNAMED_29_PI6CB33401_I89_SDATA_XF" : { "U7_XF.10" : {} } } }, "U7_XF.4" : {}, "C285_XF.1" : { "C285_XF.2" : { "GND" : {} } }, "U1_E3_XF.15" : {}, "U1_E2_XF.4" : {}, "R182_XF.1" : { "R182_XF.2" : { "E1S0_3R3V_SCL_XF" : {} } }, "R14_E1_XF.1" : { "R14_E1_XF.2" : { "CLKIN_P_E1" : {} } }, "R15_E1_XF.1" : { "R15_E1_XF.2" : { "CLKIN_N_E1" : {} } }, "R168_XF.1" : { "R168_XF.2" : { "E1S1_FPGA_REFCLK_P<0>_XF" : {} } }, "R191_XF.1" : { "R191_XF.2" : { "E1S3_FPGA_REFCLK_N<1>_XF" : {} } }, "R208_XF.1" : { "R208_XF.2" : { "E1S3_3R3V_SCL_XF" : {} } }, "C344_XF.1" : { "C344_XF.2" : { "GND" : {} } }, "U1_E1_XF.4" : {}, "R192_XF.1" : { "R192_XF.2" : { "E1S3_FPGA_REFCLK_P<0>_XF" : {} } }, "U1_E0_XF.11" : {}, "R185_XF.1" : { "R185_XF.2" : { "E1S1_3R3V_SDA_XF" : {} } }, "C348_XF.1" : { "C348_XF.2" : { "GND" : {} } }, "C287_XF.1" : { "C287_XF.2" : { "GND" : {} } }, "C2_E2_XF.2" : { "C2_E2_XF.1" : { "GND" : {} } }, "R164_XF.1" : { "R164_XF.2" : { "E1S0_FPGA_REFCLK_N<0>_XF" : {} } }, "R125_XF.1" : { "R125_XF.2" : { "UNNAMED_29_PI6CB33401_I89_SCLK_XF" : { "U7_XF.9" : {} } } }, "C3_E1_XF.2" : { "C3_E1_XF.1" : { "GND" : {} } }, "U1_E1_XF.21" : {}, "U1_E2_XF.21" : {}, "C3_E2_XF.2" : { "C3_E2_XF.1" : { "GND" : {} } }, "C296_XF.2" : { "C296_XF.1" : { "GND" : {} } }, "R189_XF.1" : { "R189_XF.2" : { "E1S2_FPGA_REFCLK_N<0>_XF" : {} } }, "R11_E1_XF.1" : { "R11_E1_XF.2" : { "UNNAMED_4_PI6CB33401_I37_SCLK_E1" : { "U1_E1_XF.9" : {} } } }, "C2_E1_XF.2" : { "C2_E1_XF.1" : { "GND" : {} } }, "R187_XF.1" : { "R187_XF.2" : { "E1S2_FPGA_REFCLK_N<1>_XF" : {} } }, "R190_XF.1" : { "R190_XF.2" : { "E1S3_FPGA_REFCLK_P<1>_XF" : {} } }, "U7_XF.21" : {}, "U1_E2_XF.25" : {}, "U5_XF.11" : {}, "C15_E1_XF.1" : { "C15_E1_XF.2" : { "GND" : {} } }, "R163_XF.1" : { "R163_XF.2" : { "E1S0_FPGA_REFCLK_P<0>_XF" : {} } }, "R278_XF.1" : { "R278_XF.2" : { "OCL_REF_CLK_N<1>" : {} } }, "C286_XF.1" : { "C286_XF.2" : { "GND" : {} } }, "U1_XF.U17" : {}, "R186_XF.1" : { "R186_XF.2" : { "E1S2_FPGA_REFCLK_P<1>_XF" : {} } }, "C14_E1_XF.1" : { "C14_E1_XF.2" : { "GND" : {} } }, "U5_XF.25" : {}, "U1_E1_XF.25" : {}, "U7_XF.15" : {}, "U1_XF.M17" : {}, "R183_XF.1" : { "R183_XF.2" : { "E1S0_3R3V_SDA_XF" : {} } }, "U5_XF.15" : {}, "R9_E3_XF.1" : { "R9_E3_XF.2" : { "UNNAMED_4_PI6CB33401_I37_SDATA_E3" : { "U1_E3_XF.10" : {} } } }, "C35.1" : { "C35.2" : { "GND" : {} } }, "C352_XF.2" : { "C352_XF.1" : { "GND" : {} } }, "U1_E2_XF.11" : {}, "U7_XF.25" : {}, "U6_XF.4" : {}, "R14_E2_XF.1" : { "R14_E2_XF.2" : { "CLKIN_P_E2" : {} } }, "R5_XF.1" : { "R5_XF.2" : { "UNNAMED_29_RESISTOR_I15_B_XF" : { "U6_XF.1" : {}, "U6_XF.2" : {}, "U6_XF.8" : {}, "U6_XF.3" : {} } } }, "U1_XF.BB17" : {}, "R275_XF.1" : { "R275_XF.2" : { "OCL_REF_CLK_P<0>" : {} } }, "C351_XF.2" : { "C351_XF.1" : { "GND" : {} } }, "R15_E2_XF.1" : { "R15_E2_XF.2" : { "CLKIN_N_E2" : {} } }, "C34.1" : { "C34.2" : { "GND" : {} } }, "C1_E3_XF.2" : { "C1_E3_XF.1" : { "GND" : {} } }, "U7_XF.11" : {}, "U1_E1_XF.11" : {}, "R206_XF.1" : { "R206_XF.2" : { "E1S2_3R3V_SCL_XF" : {} } }, "R193_XF.1" : { "R193_XF.2" : { "E1S3_FPGA_REFCLK_N<0>_XF" : {} } }, "U5_XF.21" : {}, "U1_XF.AW18" : {}, "R166_XF.1" : { "R166_XF.2" : { "E1S1_FPGA_REFCLK_P<1>_XF" : {} } }, "U1_E0_XF.4" : {}, "R14_E3_XF.1" : { "R14_E3_XF.2" : { "CLKIN_P_E3" : {} } }, "R14_E0_XF.1" : { "R14_E0_XF.2" : { "CLKIN_P_E0" : {} } }, "R9_E0_XF.1" : { "R9_E0_XF.2" : { "UNNAMED_4_PI6CB33401_I37_SDATA_E0" : { "U1_E0_XF.10" : {} } } }, "U1_E1_XF.15" : {}, "R184_XF.1" : { "R184_XF.2" : { "E1S1_3R3V_SCL_XF" : {} } }, "R169_XF.1" : { "R169_XF.2" : { "E1S1_FPGA_REFCLK_N<0>_XF" : {} } }, "C1_E0_XF.2" : { "C1_E0_XF.1" : { "GND" : {} } }, "R167_XF.1" : { "R167_XF.2" : { "E1S1_FPGA_REFCLK_N<1>_XF" : {} } }, "U1_E2_XF.15" : {}, "R15_E0_XF.1" : { "R15_E0_XF.2" : { "CLKIN_N_E0" : {} } }, "Q13.8" : {}, "C284_XF.1" : { "C284_XF.2" : { "GND" : {} } }, "U1_E3_XF.4" : {}, "R209_XF.1" : { "R209_XF.2" : { "E1S3_3R3V_SDA_XF" : {} } }, "R207_XF.1" : { "R207_XF.2" : { "E1S2_3R3V_SDA_XF" : {} } }, "C20.1" : { "C20.2" : { "GND" : {} } }, "R15_E3_XF.1" : { "R15_E3_XF.2" : { "CLKIN_N_E3" : {} } }, "U1_XF.BG17" : {}, "C283_XF.2" : { "C283_XF.1" : { "GND" : {} } }, "C342_XF.1" : { "C342_XF.2" : { "GND" : {} } } }, "OCL0_PER_P<1>_XF" : { "J1_O0_XF.A6" : {}, "U1_XF.BW6" : {} }, "C1_DDR4_DQ<20>_XF" : { "J2_XF.25" : {}, "U1_XF.BU54" : {} }, "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : { "PM4_SP_XF.G5" : { "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G9" : { "UNNAMED_4_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} } } }, "UNNAMED_9_LT3071_I30_V01_FL" : { "R79_FL_XF.2" : { "R79_FL_XF.1" : { "GND" : {} } }, "R67_FL_XF.1" : { "R67_FL_XF.2" : { "P3R3V" : {} } }, "U7_FL_XF.24" : {} }, "UNNAMED_7_RESISTOR_I42_A_SP" : { "R69_SP_XF.1" : { "R69_SP_XF.2" : { "UNNAMED_7_LTM4671_I87_FB0_SP" : { "PM1_SP_XF.G9" : { "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {} } }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} } } } } } }, "NC_TL_1_SP" : {}, "C1_DDR4_DQ<51>_XF" : { "J2_XF.271" : {}, "U1_XF.BK59" : {} }, "C2_DDR4_ADR<17>_XF" : { "J3_XF.234" : {} }, "IS_VCCINTLR_SW_N_SP" : { "C181_SP_XF.1" : { "C181_SP_XF.2" : { "GND" : {} } }, "R191_SP_XF.1" : { "R191_SP_XF.2" : { "P3R3V" : {} } }, "R192_SP_XF.2" : { "R192_SP_XF.1" : { "GND" : {} } }, "R47_SP_XF.2" : { "R47_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I144_A_SP" : { "C26_SP_XF.1" : { "C26_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.46" : {} } } } }, "C3_RDIMM_DQS_T<8>_XF" : { "J4_XF.197" : {}, "U1_XF.H18" : {} }, "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF" : { "R5_ND_XF.1" : { "R5_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_VOUT0CFG_ND" : {} } }, "C81_ND_XF.2" : { "C81_ND_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I28_A_ND" : {} } }, "C68_ND_XF.1" : { "C68_ND_XF.2" : { "P12V_FUSED_4675_ND" : {} } }, "PM4_ND_XF.G6" : {}, "R9_ND_XF.1" : { "R9_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_FSWPHCFG_ND" : {} } }, "NS13_ND_XF.2" : { "NS13_ND_XF.1" : { "GND" : {} } }, "R8_ND_XF.1" : { "R8_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_VTRIM1CFG_ND" : { "PM4_ND_XF.H4" : {} } } }, "PM4_ND_XF.F5" : {}, "PM4_ND_XF.G5" : {}, "PM4_ND_XF.F6" : {}, "R7_ND_XF.1" : { "R7_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_VOUT1CFG_ND" : {} } }, "C67_ND_XF.1" : { "C67_ND_XF.2" : { "P12V_FUSED_4675_ND" : {} } }, "R26_ND_XF.1" : { "R26_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_WP_ND" : {} } }, "R122_XF.1" : { "R122_XF.2" : { "NDIMM_I2C_ASEL_RESISTOR_XF" : {} } }, "R6_ND_XF.1" : { "R6_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_VTRIM0CFG_ND" : { "PM4_ND_XF.H3" : {} } } } }, "C1_DDR4_DQ<63>_XF" : { "U1_XF.BL52" : {}, "J2_XF.280" : {} }, "C3_DDR4_DQ<35>_XF" : { "U1_XF.D25" : {}, "J4_XF.249" : {} }, "C1_DDR4_DQ<46>_XF" : { "U1_XF.BL63" : {}, "J2_XF.113" : {} }, "C1_RDIMM_DQS_T<12>_XF" : { "J2_XF.40" : {}, "U1_XF.CC58" : {} }, "E1S_REF_CLK_P<1>" : { "U1.31" : {}, "C16_E1_XF.1" : { "C16_E1_XF.2" : { "CLKIN_P_E1" : { "R16_E1_XF.1" : { "R16_E1_XF.2" : { "GND" : {} } }, "R14_E1_XF.2" : { "R14_E1_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E1_XF.5" : {} } } } }, "SW1_NODE_ND" : { "PM4_ND_XF.L8" : { "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } }, "U1_CPLD.C9" : {} } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } }, "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "UNNAMED_3_OCULINKX4CONN_I86_REFCLKN_P1" : { "J1_P1_XF.B13" : {}, "R2_P1_XF.1" : { "R2_P1_XF.2" : { "PCIE1_REFN_XF" : { "C231_XF.1" : { "C231_XF.2" : { "AC_PCIE1_REFN_XF" : { "U1_XF.AU14" : {} } } } } } } }, "C3_DDR4_ADR<0>_XF" : { "U1_XF.R23" : {}, "J4_XF.79" : {} }, "UNNAMED_12_LT3071_I30_V01_FL" : { "R99_FL_XF.1" : { "R99_FL_XF.2" : { "P3R3V" : {} } }, "U10_FL_XF.24" : {}, "R97_FL_XF.2" : { "R97_FL_XF.1" : { "GND" : {} } } }, "UNNAMED_6_LTM4671_I516_MODECLKIN0_SP" : { "R93_SP_XF.1" : { "R93_SP_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } }, "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } }, "PM2_SP_XF.E6" : { "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.G11" : { "UNNAMED_6_LTM4671_I516_MODECLKIN0_SP" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} } } } } } } } } }, "OCL0_FPGA_REFCLK_N_XF" : { "U1_XF.CB12" : {}, "R219_XF.2" : { "R219_XF.1" : { "OCL0_FPGA_REFCLK_P_XF" : {} } }, "R220_XF.1" : { "R220_XF.2" : { "GND" : {} } }, "C370_XF.2" : { "C370_XF.1" : { "AC_OCL0_FPGA_REFCLK_N_XF" : { "U7_XF.23" : {} } } }, "R211_XF.2" : { "R211_XF.1" : { "P3R3V" : {} } } }, "C1_DDR4_DQ<33>_XF" : { "U1_XF.BR63" : {}, "J2_XF.242" : {} }, "E1S3_PER_P<1>_XF" : { "U1_XF.AJ2" : {}, "J1_E3_XF.A21" : {} }, "AC_PCIE0_REFN_XF" : { "C288_XF.2" : { "C288_XF.1" : { "PCIE0_REFN_XF" : { "R2_P0_XF.2" : { "R2_P0_XF.1" : { "UNNAMED_3_OCULINKX4CONN_I86_REFCLKN_P0" : { "J1_P0_XF.B13" : {} } } } } } }, "U1_XF.BB12" : {} }, "POK_OD_SDIMM_VPP_SW" : { "PM1_SP_XF.M8" : { "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} } } } } }, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} } }, "U1_CPLD.R8" : {} }, "C3_DDR4_DQ<65>_XF" : { "J4_XF.194" : {}, "U1_XF.F17" : {} }, "SI5341_DIS_CLKS" : { "U1_CPLD.F2" : {}, "U1.11" : {} }, "C2_RDIMM_DQS_T<16>_XF" : { "J3_XF.132" : {}, "U1_XF.N49" : {} }, "C2_DDR4_DQ<59>_XF" : { "J3_XF.282" : {}, "U1_XF.K47" : {} }, "CLKIN_P_E3" : { "R14_E3_XF.2" : { "R14_E3_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R17_E3_XF.1" : { "R17_E3_XF.2" : { "CLKIN_N_E3" : {} } }, "C16_E3_XF.2" : { "C16_E3_XF.1" : { "E1S_REF_CLK_P<3>" : { "U1.38" : {} } } }, "R16_E3_XF.1" : { "R16_E3_XF.2" : { "GND" : {} } }, "U1_E3_XF.5" : {} }, "UNNAMED_4_BYPASSCAPNPOL_I31_A_FL" : { "U6_FL_XF.3" : {}, "C19_FL_XF.1" : { "C19_FL_XF.2" : { "GND" : {} } } }, "C1_RDIMM_DQS_C<14>_XF" : { "J2_XF.111" : {}, "U1_XF.BN63" : {} }, "PCIE_X1_REFN_XF" : { "C289_XF.1" : { "C289_XF.2" : { "AC_PCIE_X1_REFN_XF" : { "U1_XF.BG14" : {} } } }, "J1_PX1_XF.A14" : {} }, "C2_RDIMM_DQS_C<7>_XF" : { "J3_XF.277" : {}, "U1_XF.M51" : {} }, "UNNAMED_22_RESISTOR_I38_B_XF" : { "U1_XF.U26" : {}, "R52_XF.2" : { "R52_XF.1" : { "GND" : {} } } }, "CPLD_TCK_PIN_CPLD" : { "R18_CPLD.2" : { "R18_CPLD.1" : { "UNNAMED_8_1G97_I18_Y_CPLD" : { "U4_CPLD.4" : {} } } }, "U1_CPLD.A7" : {} }, "OCL1_PER_N<1>_XF" : { "J1_O1_XF.A7" : {}, "U1_XF.BU1" : {} }, "ENB3V_SEQ_A" : { "U1_CPLD.P15" : {}, "R16_CPLD.1" : { "R16_CPLD.2" : { "GND" : {} } }, "R78_SP_XF.1" : { "R78_SP_XF.2" : { "UNNAMED_11_LTM4650FIXED_I150_RUN1_SP" : { "PM7_SP_XF.F5" : { "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.H6" : { "GND" : {} } } } } } }, "VMON_SDIMM_VPP_SW" : { "R124_SP_XF.2" : { "R124_SP_XF.1" : { "PWR_SDIMM_VPP_XF" : {} } }, "R52.1" : { "R52.2" : { "UNNAMED_4_BYPASSCAPNPOL_I51_B" : { "R75.2" : { "R75.1" : { "GND" : {} } }, "C42.2" : { "C42.1" : { "GND" : {} } }, "U11.11" : {} } } } }, "C1_DDR4_RESET_N_XF" : { "U1_XF.CA55" : {}, "J2_XF.58" : {} }, "AC_PCIE0_TXN<5>_XF" : { "U1_XF.BA10" : {}, "C77_XF.1" : { "C77_XF.2" : { "PCIE0_TXN<5>_XF" : { "J2_P0_XF.B7" : {} } } } }, "VMON_NDIMM_VTT_LIN" : { "R4_ND_XF.2" : { "R4_ND_XF.1" : { "VS_DIMM_VTT_LIN_ND" : { "NS3_ND_XF.2" : { "NS3_ND_XF.1" : { "PWR_NDIMM_VTT_XF" : {} } }, "U2_ND_XF.5" : {} } } }, "R45.2" : { "R45.1" : { "UNNAMED_4_MAX116XXQSOP16_I97_AIN3" : { "U11.8" : {}, "C46.1" : { "C46.2" : { "GND" : {} } } } } } }, "PCIE1_RXP<1>_XF" : { "U1_XF.AN6" : {}, "J1_P1_XF.A6" : {} }, "PWR_AVCC_RS_RLC_XF" : { "R146_XF.1" : { "R146_XF.2" : { "AVCC_S_BNC_XF" : { "J9_XF.C" : {} } } }, "U3_FL_XF.17" : {}, "U1_XF.BW13" : {}, "U1_XF.BA13" : {}, "C465_XF.1" : { "C465_XF.2" : { "GND" : {} } }, "C15_FL_XF.1" : { "C15_FL_XF.2" : { "GND" : {} } }, "U1_XF.BE13" : {}, "U1_XF.BJ13" : {}, "U1_XF.BU13" : {}, "C120_XF.1" : { "C120_XF.2" : { "GND" : {} } }, "U1_XF.BB15" : {}, "C466_XF.1" : { "C466_XF.2" : { "GND" : {} } }, "U1_XF.BM15" : {}, "U1_XF.BL13" : {}, "C464_XF.1" : { "C464_XF.2" : { "GND" : {} } }, "U1_XF.BR13" : {}, "U1_XF.CA13" : {}, "U1_XF.BC13" : {}, "U1_XF.AV15" : {}, "C67_FL_XF.1" : { "C67_FL_XF.2" : { "GND" : {} } }, "C68_FL_XF.1" : { "C68_FL_XF.2" : { "GND" : {} } }, "U1_XF.AY15" : {}, "U1_XF.BG13" : {}, "C121_XF.1" : { "C121_XF.2" : { "GND" : {} } }, "NS2_FL_XF.1" : { "NS2_FL_XF.2" : { "VS_AVCC_LIN_P_XF" : {} } }, "C13_FL_XF.1" : { "C13_FL_XF.2" : { "GND" : {} } }, "U1_XF.BD15" : {}, "C122_XF.1" : { "C122_XF.2" : { "GND" : {} } }, "U3_FL_XF.15" : {}, "U3_FL_XF.16" : {}, "U1_XF.BF15" : {}, "C479_XF.1" : { "C479_XF.2" : { "GND" : {} } }, "C463_XF.1" : { "C463_XF.2" : { "GND" : {} } }, "U1_XF.BN13" : {}, "U3_FL_XF.18" : {} }, "C0_DDR4_CS_N<2>_XF" : { "J1_XF.93" : {}, "U1_XF.CB16" : {} }, "AC_E1S0_PET_P<5>_XF" : { "C104_XF.1" : { "C104_XF.2" : { "E1S0_PET_P<5>_XF" : { "J1_E0_XF.B34" : {} } } }, "U1_XF.E11" : {} }, "AC_E1S1_PET_N<4>_XF" : { "C133_XF.1" : { "C133_XF.2" : { "E1S1_PET_N<4>_XF" : { "J1_E1_XF.B30" : {} } } }, "U1_XF.U6" : {} }, "PCIE0_TXP<7>_XF" : { "C34_XF.2" : { "C34_XF.1" : { "AC_PCIE0_TXP<7>_XF" : { "U1_XF.BC11" : {} } } }, "J2_P0_XF.B18" : {} }, "UNNAMED_7_LTM4671_I36_TRACKSS3_SP" : { "PM1_SP_XF.P9" : { "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} } } } } }, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} } } }, "OCL0_PET_P<0>_XF" : { "C180_XF.2" : { "C180_XF.1" : { "AC_OCL0_PET_P<0>_XF" : { "U1_XF.CC11" : {} } } }, "J1_O0_XF.B3" : {} }, "C0_DDR4_DQ<45>_XF" : { "J1_XF.251" : {}, "U1_XF.BP25" : {} }, "UNNAMED_9_598BICOLORLED_I16_L2A_CPLD" : { "R119_CPLD.1" : { "R119_CPLD.2" : { "CPLD_P3R3V" : {} } }, "D1_CPLD.1" : { "D1_CPLD.3" : { "UNNAMED_9_598BICOLORLED_I16_L1A_CPLD" : { "R118_CPLD.1" : { "R118_CPLD.2" : { "CPLD_P3R3V" : {} } } } }, "D1_CPLD.4" : { "STAT_LED_ON_F<1>_CPLD" : { "U1_CPLD.E7" : {} } }, "D1_CPLD.2" : { "STAT_LED_ON_F<0>_CPLD" : { "U1_CPLD.A3" : {} } } } }, "C1_DDR4_DQ<71>_XF" : { "U1_XF.BT57" : {}, "J2_XF.199" : {} }, "PCIE1_TXN<6>_XF" : { "C43_XF.2" : { "C43_XF.1" : { "AC_PCIE1_TXN<6>_XF" : { "U1_XF.AT8" : {} } } }, "J2_P1_XF.B16" : {} }, "OCL2_PER_N<0>_XF" : { "J1_O2_XF.A4" : {}, "U1_XF.BM3" : {} }, "CPLD_SELF_TCK_CPLD" : { "U1_CPLD.B14" : {}, "U4_CPLD.3" : {} }, "E1S3_PET_P<4>_XF" : { "C339_XF.2" : { "C339_XF.1" : { "AC_E1S3_PET_P<4>_XF" : { "U1_XF.AL11" : {} } } }, "J1_E3_XF.B31" : {} }, "C1_DDR4_ODT<0>_XF" : { "J2_XF.87" : {}, "U1_XF.CC56" : {} }, "PCIE0_RXN<5>_XF" : { "U1_XF.BA5" : {}, "J2_P0_XF.A7" : {} }, "UNNAMED_29_PI6CB33401_I89_SCLK_XF" : { "R125_XF.2" : { "R125_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U7_XF.9" : {} }, "C0_DDR4_DQ<24>_XF" : { "U1_XF.BW22" : {}, "J1_XF.38" : {} }, "C2_RDIMM_DQS_C<3>_XF" : { "J3_XF.185" : {}, "U1_XF.H54" : {} }, "AC_CONN_CLK_REFN<1>_1" : { "C24_E0_XF.1" : { "C24_E0_XF.2" : { "CONN_CLK_REFN<1>_E0" : { "J1_E0_XF.A14" : {} } } }, "U1_E0_XF.18" : {} }, "C3_RDIMM_DQS_T<6>_XF" : { "U1_XF.D16" : {}, "J4_XF.267" : {} }, "VMON_AVCC_RUC_LIN_XF" : { "R102_FL_XF.2" : { "R102_FL_XF.1" : { "VS_AVCC_RUC_LIN_FL" : { "NS1_FL_XF.2" : { "NS1_FL_XF.1" : { "PWR_AVCC_RUC_XF" : {} } }, "U10_FL_XF.19" : {} } } }, "R39_XF.2" : { "R39_XF.1" : { "UNNAMED_17_RESISTOR_I214_B_XF" : { "R68_XF.2" : { "R68_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I216_A_XF" : { "U1_XF.CA40" : {}, "C316_XF.1" : { "C316_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I216_B_XF" : { "R69_XF.1" : { "R69_XF.2" : { "UNNAMED_17_RESISTOR_I215_B_XF" : { "R63_XF.1" : { "R63_XF.2" : { "GND" : {} } }, "R70_XF.1" : { "R70_XF.2" : { "GND" : {} } } } } }, "U1_XF.CB40" : {} } } } } } }, "R62_XF.1" : { "R62_XF.2" : { "GND" : {} } } } } } }, "HOST_3R3V_SDA" : { "R38.2" : { "R38.1" : { "CPLD_P1R8V_1" : {} } }, "U1_CPLD.B12" : {} }, "UNNAMED_9_LT3071_I66_EN_FL" : { "R103_FL_XF.1" : { "R103_FL_XF.2" : { "P3R3V" : {} } }, "U11_FL_XF.28" : {} }, "C3_DDR4_BA<1>_XF" : { "U1_XF.N24" : {}, "J4_XF.224" : {} }, "C0_DDR4_DQ<10>_XF" : { "U1_XF.CC29" : {}, "J1_XF.23" : {} }, "UNNAMED_20_NMOSFETVMT3_I16_G" : { "Q8.1" : { "Q8.2" : { "GND" : {} }, "Q8.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I25_P4" : { "P3.4" : {} } } }, "R55.2" : { "R55.1" : { "FAN_PWM_OD" : { "U1_CPLD.J12" : {}, "R42.1" : { "R42.2" : { "UNNAMED_20_NMOSFETVMT3_I12_G" : { "Q7.1" : { "Q7.2" : { "GND" : {} }, "Q7.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I26_P4" : { "P4.4" : {} } } } } } }, "R39.1" : { "R39.2" : { "UNNAMED_20_NMOSFETVMT3_I20_G" : { "Q6.1" : { "Q6.2" : { "GND" : {} }, "Q6.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I30_P4" : { "P2.4" : {} } } } } } }, "R56.1" : { "R56.2" : { "UNNAMED_20_NMOSFETVMT3_I8_G" : { "Q9.1" : { "Q9.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I27_P4" : { "P5.4" : {} } }, "Q9.2" : { "GND" : {} } } } } } } } } }, "UNNAMED_3_LTM4675_I40_COMP0A_SD" : { "PM4_SD_XF.E6" : { "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_SD_XF.D6" : { "UNNAMED_3_LTM4675_I40_COMP0B_SD" : {} }, "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_SD_XF.J6" : { "UNNAMED_3_LTM4675_I40_COMP0B_SD" : {} } }, "R108_SD_XF.2" : { "R108_SD_XF.1" : { "UNNAMED_3_LTM4675_I40_COMP0B_SD" : {} } } }, "AC_E1S1_PET_P<2>_XF" : { "C115_XF.1" : { "C115_XF.2" : { "E1S1_PET_P<2>_XF" : { "J1_E1_XF.B24" : {} } } }, "U1_XF.M9" : {} }, "UNNAMED_3_LTM4675_I40_COMP1A_SD" : { "R109_SD_XF.2" : { "R109_SD_XF.1" : { "UNNAMED_3_LTM4675_I40_COMP0B_SD" : {} } }, "PM4_SD_XF.H6" : { "PM4_SD_XF.J6" : { "UNNAMED_3_LTM4675_I40_COMP0B_SD" : {} }, "PM4_SD_XF.D6" : { "UNNAMED_3_LTM4675_I40_COMP0B_SD" : {} }, "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } }, "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "C1_DDR4_DQ<18>_XF" : { "U1_XF.BU55" : {}, "J2_XF.34" : {} }, "C3_SYS_CLK_N_XF" : { "U1_XF.P24" : {}, "R256_XF.2" : { "R256_XF.1" : { "PWR_NDIMM_VDD_XF" : {} } }, "C367_XF.2" : { "C367_XF.1" : { "DDR4_SYS_CLK_N<3>_XF" : { "U6_XF.9" : {} } } }, "R165_XF.1" : { "R165_XF.2" : { "GND" : {} } }, "R259_XF.2" : { "R259_XF.1" : { "C3_SYS_CLK_P_XF" : {} } } }, "E1S0_PER_N<2>_XF" : { "U1_XF.E1" : {}, "J1_E0_XF.A23" : {} }, "UNNAMED_8_ACS711_I94_VIOUT_SP" : { "R133_SP_XF.2" : { "R133_SP_XF.1" : { "IS_VCCINTLL_SW_P_SP" : { "R52_SP_XF.2" : { "R52_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I149_A_SP" : { "U1_SP_XF.41" : {}, "C40_SP_XF.1" : { "C40_SP_XF.2" : { "GND" : {} } } } } }, "R134_SP_XF.2" : { "R134_SP_XF.1" : { "GND" : {} } }, "C130_SP_XF.1" : { "C130_SP_XF.2" : { "GND" : {} } } } } }, "U6_SP_XF.11" : {} }, "UNNAMED_4_RESISTOR_I2_A_MP" : { "U2_MP.7" : {}, "R9_MP.1" : { "R9_MP.2" : { "UNNAMED_4_RESISTOR_I2_B_MP" : { "C12_MP.1" : { "C12_MP.2" : { "GND" : {} } } } } } }, "C3_DDR4_DQ<42>_XF" : { "U1_XF.C22" : {}, "J4_XF.115" : {} }, "UNNAMED_9_LT3071_I30_EN_FL" : { "R9_FL_XF.1" : { "R9_FL_XF.2" : { "P3R3V" : {} } }, "U7_FL_XF.28" : {} }, "C2_DDR4_ADR<8>_XF" : { "U1_XF.L60" : {}, "J3_XF.68" : {} }, "FPGA_ERR_VIS<0>_1" : { "U1_CPLD.J5" : {}, "U1_XF.CC34" : {} }, "E1S2_PET_P<2>_XF" : { "C153_XF.2" : { "C153_XF.1" : { "AC_E1S2_PET_P<2>_XF" : { "U1_XF.V9" : {} } } }, "J1_E2_XF.B24" : {} }, "C2_DDR4_CK_T<0>_XF" : { "J3_XF.74" : {}, "U1_XF.M63" : {} }, "UNNAMED_17_RESISTOR_I214_B_XF" : { "R68_XF.2" : { "R68_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I216_A_XF" : { "U1_XF.CA40" : {}, "C316_XF.1" : { "C316_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I216_B_XF" : { "R69_XF.1" : { "R69_XF.2" : { "UNNAMED_17_RESISTOR_I215_B_XF" : { "R63_XF.1" : { "R63_XF.2" : { "GND" : {} } }, "R70_XF.1" : { "R70_XF.2" : { "GND" : {} } } } } }, "U1_XF.CB40" : {} } } } } } }, "R62_XF.1" : { "R62_XF.2" : { "GND" : {} } }, "R39_XF.1" : { "R39_XF.2" : { "VMON_AVCC_RUC_LIN_XF" : { "R102_FL_XF.2" : { "R102_FL_XF.1" : { "VS_AVCC_RUC_LIN_FL" : { "U10_FL_XF.19" : {}, "NS1_FL_XF.2" : { "NS1_FL_XF.1" : { "PWR_AVCC_RUC_XF" : {} } } } } } } } } }, "C3_DDR4_DQ<5>_XF" : { "U1_XF.J16" : {}, "J4_XF.148" : {} }, "C3_DDR4_CKE<0>_XF" : { "J4_XF.60" : {}, "U1_XF.T23" : {} }, "SW2_4650_BR_SP" : { "PM7_SP_XF.G11" : { "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.M12" : { "GND" : {} } } }, "E1S2_3R3V_CKEN_F<1>_XF" : { "U1_E2_XF.19" : {}, "U1_XF.N18" : {} }, "C1_DDR4_DQ<0>_XF" : { "J2_XF.5" : {}, "U1_XF.BN51" : {} }, "UNNAMED_29_PI6CB33401_I89_OE2F_XF" : { "R124_XF.2" : { "R124_XF.1" : { "GND" : {} } }, "U7_XF.24" : {}, "U7_XF.29" : {} }, "C2_RDIMM_DQS_T<2>_XF" : { "J3_XF.175" : {}, "U1_XF.G63" : {} }, "UNNAMED_10_LTM4650FIXED_I151_CLKOUT_SP" : { "PM3_SP_XF.G5" : { "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.G3" : { "GND" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} } } }, "UNNAMED_7_LT3071_I30_V02_FL" : { "U4_FL_XF.25" : {}, "R50_FL_XF.2" : { "R50_FL_XF.1" : { "GND" : {} } }, "R75_FL_XF.1" : { "R75_FL_XF.2" : { "P3R3V" : {} } } }, "JT_FPGA_TDI" : { "J5.8" : {}, "U1_CPLD.B11" : {}, "R64.2" : { "R64.1" : { "GND" : {} } } }, "FPGA_CPLD_RSVD<2>_1" : { "U1_XF.BT32" : {}, "U1_CPLD.B9" : {} }, "C0_DDR4_VREFCA_1_XF" : { "R240_XF.1" : { "R240_XF.2" : { "GND" : {} } }, "C416_XF.1" : { "C416_XF.2" : { "GND" : {} } }, "J1_XF.146" : {}, "R239_XF.1" : { "R239_XF.2" : { "PWR_SDIMM_VDD_XF" : {} } }, "C417_XF.1" : { "C417_XF.2" : { "GND" : {} } } }, "VMON_AVCC_RN_LIN_XF" : { "R84_FL_XF.2" : { "R84_FL_XF.1" : { "VS_AVCC_RN_LIN_FL" : { "U6_FL_XF.19" : {}, "NS4_FL_XF.2" : { "NS4_FL_XF.1" : { "PWR_AVCC_RN_XF" : {} } } } } }, "R1_XF.1" : { "R1_XF.2" : { "UNNAMED_17_RESISTOR_I51_A_XF" : { "R2_XF.2" : { "R2_XF.1" : { "GND" : {} } }, "R76_XF.1" : { "R76_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I48_A_XF" : { "U1_XF.AM25" : {}, "C138_XF.1" : { "C138_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I48_B_XF" : { "R77_XF.2" : { "R77_XF.1" : { "UNNAMED_17_RESISTOR_I52_A_XF" : { "R4_XF.2" : { "R4_XF.1" : { "GND" : {} } }, "R3_XF.2" : { "R3_XF.1" : { "GND" : {} } } } } }, "U1_XF.AN24" : {} } } } } } } } } } }, "NC_BR_1_SP" : {}, "UNNAMED_7_LTM4671_I36_MODECLKIN3_SP" : { "R116_SP_XF.1" : { "R116_SP_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I55_B_SP" : { "PM1_SP_XF.R11" : { "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.R8" : { "UNNAMED_7_LTM4671_I36_MODECLKIN3_SP" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {} } }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} } } } } } }, "E1S2_3R3V_DUALPORTEN_F_XF" : { "U1_XF.R20" : {}, "J1_E2_XF.B9" : {} }, "C3_RDIMM_DQS_C<13>_XF" : { "J4_XF.100" : {}, "U1_XF.B28" : {} }, "UNNAMED_8_1G97_I17_Y_CPLD" : { "R19_CPLD.1" : { "R19_CPLD.2" : { "CPLD_TMS_PIN_CPLD" : { "U1_CPLD.B8" : {} } } }, "U2_CPLD.4" : {} }, "FPGA_ERR_VIS<1>_1" : { "U1_XF.CC39" : {}, "U1_CPLD.K2" : {} }, "E1S0_3R3V_DUALPORTEN_F_XF" : { "U1_XF.AB19" : {}, "J1_E0_XF.B9" : {} }, "TS_LT4650_BL_SP" : { "PM3_SP_XF.J6" : { "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.G3" : { "GND" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } } } }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} } }, "U1_SP_XF.16" : {} }, "UNNAMED_17_RESISTOR_I113_A_XF" : { "R139_XF.1" : { "R139_XF.2" : { "GND" : {} } }, "R141_XF.1" : { "R141_XF.2" : { "GND" : {} } }, "R130_XF.2" : { "R130_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I116_B_XF" : { "C268_XF.2" : { "C268_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I116_A_XF" : { "U1_XF.BW31" : {}, "R129_XF.1" : { "R129_XF.2" : { "UNNAMED_17_RESISTOR_I110_A_XF" : { "R137_XF.1" : { "R137_XF.2" : { "VMON_AVTT_RS_LIN_XF" : { "R93_XF.2" : { "R93_XF.1" : { "UNNAMED_17_RESISTOR_I40_A_XF" : { "R94_XF.1" : { "R94_XF.2" : { "GND" : {} } }, "R99_XF.2" : { "R99_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I46_A_XF" : { "C147_XF.1" : { "C147_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I46_B_XF" : { "U1_XF.CA33" : {}, "R100_XF.1" : { "R100_XF.2" : { "UNNAMED_17_RESISTOR_I41_A_XF" : { "R96_XF.1" : { "R96_XF.2" : { "GND" : {} } }, "R95_XF.1" : { "R95_XF.2" : { "GND" : {} } } } } } } } }, "U1_XF.BY33" : {} } } } } } }, "R4_FL_XF.2" : { "R4_FL_XF.1" : { "VS_AVTT_RS_LIN_FL" : { "NS5_FL_XF.2" : { "NS5_FL_XF.1" : { "PWR_AVTT_RS_XF" : {} } }, "U2_FL_XF.19" : {} } } } } } }, "R138_XF.1" : { "R138_XF.2" : { "GND" : {} } } } } } } } }, "U1_XF.BW32" : {} } } } }, "DDR4_SYS_CLK_N<0>_XF" : { "U6_XF.15" : {}, "C361_XF.1" : { "C361_XF.2" : { "C0_SYS_CLK_N_XF" : { "R237_XF.1" : { "R237_XF.2" : { "GND" : {} } }, "R235_XF.2" : { "R235_XF.1" : { "PWR_SDIMM_VDD_XF" : {} } }, "U1_XF.BY19" : {} } } } }, "SW2_4650_TL_SP" : { "PM4_SP_XF.G11" : { "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G9" : { "UNNAMED_4_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } } } }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} } } }, "C1_DDR4_DQ<57>_XF" : { "J2_XF.275" : {}, "U1_XF.BL55" : {} }, "OCL3_PET_P<3>_XF" : { "C254_XF.2" : { "C254_XF.1" : { "AC_OCL3_PET_P<3>_XF" : { "U1_XF.BG7" : {} } } }, "J1_O3_XF.B18" : {} }, "UNNAMED_22_RESISTOR_I45_B_XF" : { "R60_XF.2" : { "R60_XF.1" : { "GND" : {} } }, "U1_XF.BG30" : {} }, "PCIE0_REFP_XF" : { "C100_XF.1" : { "C100_XF.2" : { "AC_PCIE0_REFP_XF" : { "U1_XF.BB13" : {} } } }, "R1_P0_XF.2" : { "R1_P0_XF.1" : { "UNNAMED_3_OCULINKX4CONN_I86_REFCLKP_P0" : { "J1_P0_XF.B12" : {} } } } }, "C1_DDR4_ADR<12>_XF" : { "U1_XF.CA53" : {}, "J2_XF.65" : {} }, "AC_OCL2_PET_N<1>_XF" : { "U1_XF.BM8" : {}, "C276_XF.1" : { "C276_XF.2" : { "OCL2_PET_N<1>_XF" : { "J1_O2_XF.B7" : {} } } } }, "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R27.2" : { "R27.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "R58.2" : { "R58.1" : { "DIS_1R8V_I2C_XLAT_F" : { "U1_CPLD.H3" : {} } } }, "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : {} } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } }, "U11.13" : {} } } } }, "C0_DDR4_DQ<32>_XF" : { "U1_XF.BM23" : {}, "J1_XF.97" : {} }, "UNNAMED_6_BYPASSCAPNPOL_I402_B_SP" : { "C83_SP_XF.2" : { "C83_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } }, "R94_SP_XF.2" : { "R94_SP_XF.1" : { "UNNAMED_6_LTM4671_I456_MODECLKIN3_SP" : { "PM2_SP_XF.R8" : { "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.R11" : { "UNNAMED_6_BYPASSCAPNPOL_I402_B_SP" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : {} } }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} } } } } } }, "C2_DDR4_DQ<43>_XF" : { "U1_XF.A52" : {}, "J3_XF.260" : {} }, "C2_DDR4_DQ<66>_XF" : { "J3_XF.56" : {}, "U1_XF.C58" : {} }, "AC_PCIE1_TXN<4>_XF" : { "C45_XF.1" : { "C45_XF.2" : { "PCIE1_TXN<4>_XF" : { "J2_P1_XF.B4" : {} } } }, "U1_XF.AP12" : {} }, "E1S1_PET_N<3>_XF" : { "C134_XF.2" : { "C134_XF.1" : { "AC_E1S1_PET_N<3>_XF" : { "U1_XF.L10" : {} } } }, "J1_E1_XF.B26" : {} }, "PWR_AVCC_SW_XF" : { "C21_FL_XF.1" : { "C21_FL_XF.2" : { "GND" : {} } }, "C45_FL_XF.1" : { "C45_FL_XF.2" : { "GND" : {} } }, "U6_FL_XF.8" : {}, "C93_FL_XF.1" : { "C93_FL_XF.2" : { "GND" : {} } }, "PM2_SP_XF.J2" : {}, "C44_FL_XF.1" : { "C44_FL_XF.2" : { "GND" : {} } }, "U6_FL_XF.5" : {}, "PM2_SP_XF.H4" : {}, "PM2_SP_XF.L10" : {}, "C91_SP_XF.1" : { "C91_SP_XF.2" : { "GND" : {} } }, "PM2_SP_XF.L2" : {}, "U3_FL_XF.5" : {}, "PM2_SP_XF.M2" : {}, "PM2_SP_XF.H1" : {}, "PM2_SP_XF.J10" : {}, "PM2_SP_XF.H3" : {}, "U3_FL_XF.8" : {}, "C95_FL_XF.1" : { "C95_FL_XF.2" : { "GND" : {} } }, "C98_SP_XF.1" : { "C98_SP_XF.2" : { "GND" : {} } }, "U10_FL_XF.7" : {}, "PM2_SP_XF.J1" : {}, "PM2_SP_XF.J3" : {}, "PM2_SP_XF.L4" : {}, "PM2_SP_XF.M4" : {}, "C92_FL_XF.1" : { "C92_FL_XF.2" : { "GND" : {} } }, "U3_FL_XF.7" : {}, "U6_FL_XF.6" : {}, "C65_FL_XF.1" : { "C65_FL_XF.2" : { "GND" : {} } }, "C95_SP_XF.1" : { "C95_SP_XF.2" : { "GND" : {} } }, "C94_SP_XF.1" : { "C94_SP_XF.2" : { "GND" : {} } }, "C91_FL_XF.1" : { "C91_FL_XF.2" : { "GND" : {} } }, "C99_SP_XF.1" : { "C99_SP_XF.2" : { "GND" : {} } }, "C90_SP_XF.1" : { "C90_SP_XF.2" : { "GND" : {} } }, "C2_FL_XF.1" : { "C2_FL_XF.2" : { "GND" : {} } }, "C7_FL_XF.1" : { "C7_FL_XF.2" : { "GND" : {} } }, "C41_FL_XF.1" : { "C41_FL_XF.2" : { "GND" : {} } }, "U10_FL_XF.6" : {}, "C42_FL_XF.1" : { "C42_FL_XF.2" : { "GND" : {} } }, "U10_FL_XF.5" : {}, "R100_SP_XF.1" : { "R100_SP_XF.2" : { "VMON_AVCC_SW_XF" : { "R102_XF.1" : { "R102_XF.2" : { "UNNAMED_17_RESISTOR_I55_A_XF" : {} } } } } }, "PM2_SP_XF.L1" : {}, "PM2_SP_XF.H2" : {}, "PM2_SP_XF.M1" : {}, "PM2_SP_XF.L3" : {}, "PM2_SP_XF.M3" : {}, "PM2_SP_XF.J4" : {}, "U3_FL_XF.6" : {}, "U10_FL_XF.8" : {}, "U6_FL_XF.7" : {} }, "C2_DDR4_DQ<36>_XF" : { "J3_XF.95" : {}, "U1_XF.D56" : {} }, "UNNAMED_8_BYPASSCAPNPOL_I31_A_FL" : { "U5_FL_XF.3" : {}, "C40_FL_XF.1" : { "C40_FL_XF.2" : { "GND" : {} } } }, "UNNAMED_4_LT3071_I30_V02_FL" : { "U6_FL_XF.25" : {}, "R60_FL_XF.2" : { "R60_FL_XF.1" : { "GND" : {} } }, "R58_FL_XF.1" : { "R58_FL_XF.2" : { "P3R3V" : {} } } }, "UNNAMED_5_LTM4650FIXED_I78_RUN1_SP" : { "PM5_SP_XF.F5" : { "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H11" : { "GND" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.F1" : { "GND" : {} } } }, "E1S1_PET_N<6>_XF" : { "C131_XF.2" : { "C131_XF.1" : { "AC_E1S1_PET_N<6>_XF" : { "U1_XF.R10" : {} } } }, "J1_E1_XF.B36" : {} }, "VS_VCCAUX_LIN_P_XF" : { "R25_SP_XF.2" : { "R25_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I154_A_SP" : { "U1_SP_XF.63" : {}, "C15_SP_XF.1" : { "C15_SP_XF.2" : { "GND" : {} } } } } }, "NS12_FL_XF.2" : { "NS12_FL_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } } }, "UNNAMED_29_PI6CB33401_I89_PDF_XF" : { "R149_XF.2" : { "R149_XF.1" : { "GND" : {} } }, "U7_XF.31" : {} }, "C1_RDIMM_DQS_C<11>_XF" : { "J2_XF.30" : {}, "U1_XF.BR55" : {} }, "UNNAMED_4_LT3071_I30_MARGA_FL" : { "U6_FL_XF.22" : {}, "R22_FL_XF.2" : { "R22_FL_XF.1" : { "UNNAMED_4_BYPASSCAPNPOL_I23_B_FL" : { "R21_FL_XF.2" : { "R21_FL_XF.1" : { "DAC_AVCC_LIN_XF" : { "R11_FL_XF.1" : { "R11_FL_XF.2" : { "UNNAMED_3_BYPASSCAPNPOL_I31_B_FL" : { "R12_FL_XF.1" : { "R12_FL_XF.2" : { "UNNAMED_3_LT3071_I32_MARGA_FL" : { "U3_FL_XF.22" : {} } } }, "C66_FL_XF.2" : { "C66_FL_XF.1" : { "GND" : {} } } } } }, "U1_SP_XF.57" : {}, "R93_FL_XF.1" : { "R93_FL_XF.2" : { "UNNAMED_12_BYPASSCAPNPOL_I23_B_FL" : { "R94_FL_XF.1" : { "R94_FL_XF.2" : { "UNNAMED_12_LT3071_I30_MARGA_FL" : { "U10_FL_XF.22" : {} } } }, "C94_FL_XF.2" : { "C94_FL_XF.1" : { "GND" : {} } } } } } } } }, "C5_FL_XF.2" : { "C5_FL_XF.1" : { "GND" : {} } } } } } }, "C0_DDR4_DQ<62>_XF" : { "J1_XF.135" : {}, "U1_XF.BG25" : {} }, "UNNAMED_12_BYPASSCAPNPOL_I31_A_FL" : { "U10_FL_XF.3" : {}, "C90_FL_XF.1" : { "C90_FL_XF.2" : { "GND" : {} } } }, "E1S1_3R3V_PWRDIS_XF" : { "J1_E1_XF.B12" : {}, "U1_XF.AF18" : {} }, "AC_OCL3_PET_P<2>_XF" : { "U1_XF.BG11" : {}, "C255_XF.1" : { "C255_XF.2" : { "OCL3_PET_P<2>_XF" : { "J1_O3_XF.B15" : {} } } } }, "E1S2_3R3V_LED_XF" : { "R6_E2_XF.2" : { "R6_E2_XF.1" : { "P3R3V" : {} } }, "U1_XF.N19" : {}, "J1_E2_XF.A10" : {} }, "C1_RDIMM_DQS_T<9>_XF" : { "U1_XF.BP50" : {}, "J2_XF.7" : {} }, "C3_DDR4_DQ<7>_XF" : { "U1_XF.K17" : {}, "J4_XF.155" : {} }, "DDR4_SYS_CLK_N<1>_XF" : { "C363_XF.1" : { "C363_XF.2" : { "C1_SYS_CLK_N_XF" : { "U1_XF.BY55" : {}, "R150_XF.2" : { "R150_XF.1" : { "PWR_SDIMM_VDD_XF" : {} } }, "R244_XF.1" : { "R244_XF.2" : { "GND" : {} } } } } }, "U6_XF.13" : {} }, "AC_E1S0_PET_N<1>_XF" : { "C128_XF.1" : { "C128_XF.2" : { "E1S0_PET_N<1>_XF" : { "J1_E0_XF.B20" : {} } } }, "U1_XF.B8" : {} }, "C2_RDIMM_DQS_T<4>_XF" : { "U1_XF.F57" : {}, "J3_XF.245" : {} }, "C1_DDR4_DQ<8>_XF" : { "J2_XF.16" : {}, "U1_XF.BT52" : {} }, "UNNAMED_15_NMOSFETVMT3_I42_G_XF" : { "Q1_XF.1" : { "Q1_XF.3" : { "UNNAMED_15_MAX4641_I1_IN2_XF" : { "U4_XF.3" : {}, "R116_XF.1" : { "R116_XF.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q1_XF.2" : { "GND" : {} } }, "R114_XF.2" : { "R114_XF.1" : { "CPLD_SEL_CFG_FLASH" : { "U4_XF.7" : {}, "U1_CPLD.J4" : {} } } } }, "C0_DDR4_DQ<9>_XF" : { "J1_XF.161" : {}, "U1_XF.CA28" : {} }, "AC_OCL1_FPGA_REFCLK_N_XF" : { "U7_XF.28" : {}, "C369_XF.1" : { "C369_XF.2" : { "OCL1_FPGA_REFCLK_N_XF" : { "U1_XF.BT12" : {}, "R223_XF.1" : { "R223_XF.2" : { "GND" : {} } }, "R213_XF.2" : { "R213_XF.1" : { "P3R3V" : {} } } } } } }, "C2_DDR4_DQ<55>_XF" : { "U1_XF.H49" : {}, "J3_XF.269" : {} }, "VS_VCCINT_N_SP" : { "PM4_SP_XF.E9" : { "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "C71_SP_XF.2" : { "C71_SP_XF.1" : { "SGND_PM4_SP" : {} } }, "PM5_SP_XF.E6" : { "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.K4" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M5" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.E9" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.M3" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M4" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.F4" : { "UNNAMED_5_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM5_SP_XF.G11" : { "SW2_4650_TR_SP" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M6" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.F6" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K3" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.G9" : { "UNNAMED_5_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.M7" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.M2" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.L9" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.F7" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.K10" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.L11" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.M8" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.K2" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.J11" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.M10" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.J9" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.J4" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.L5" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.G8" : { "UNNAMED_5_LTM4650FIXED_I78_PGOOD2_SP" : {} }, "PM5_SP_XF.L3" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J6" : { "TS_LT4650_TR_SP" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.D6" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L4" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.J3" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.C7" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.L6" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.G7" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.H8" : { "INTVCC_4650_TR_SP" : { "C32_SP_XF.1" : { "C32_SP_XF.2" : { "GND" : {} } } } }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.G2" : { "SW1_4650_TR_SP" : {} }, "PM5_SP_XF.E8" : { "INTVCC_4650_TR_SP" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C6" : { "FSET_4650_TR_SP" : { "R9_SP_XF.2" : { "R9_SP_XF.1" : { "SGND_PM5_SP" : {} } } } }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J10" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.L7" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.L2" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C30_SP_XF.1" : { "C30_SP_XF.2" : { "SGND_PM5_SP" : {} } } } }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M9" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.G6" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.G4" : { "PHASMD_4650_TR_SP" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.M11" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.L8" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.K9" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L10" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J2" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.K11" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.B6" : { "GND" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} } } }, "C1_DDR4_DQ<14>_XF" : { "J2_XF.21" : {}, "U1_XF.BV52" : {} }, "AC_E1S1_PET_P<4>_XF" : { "U1_XF.U7" : {}, "C113_XF.1" : { "C113_XF.2" : { "E1S1_PET_P<4>_XF" : { "J1_E1_XF.B31" : {} } } } }, "UNNAMED_3_LTM4675_I40_VTRIM0CFG_ND" : { "PM4_ND_XF.H3" : { "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } } } }, "UNNAMED_3_LTM4675_I40_TSNS1A_SD" : { "PM4_SD_XF.J3" : { "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U1_CPLD.C9" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } } } } } } } } } } } } } } } }, "C1_RDIMM_DQS_T<3>_XF" : { "J2_XF.186" : {}, "U1_XF.CA60" : {} }, "AC_E1S0_PET_N<5>_XF" : { "U1_XF.E10" : {}, "C124_XF.1" : { "C124_XF.2" : { "E1S0_PET_N<5>_XF" : { "J1_E0_XF.B33" : {} } } } }, "E1S2_PER_N<6>_XF" : { "J1_E2_XF.A36" : {}, "U1_XF.AC1" : {} }, "E1S0_PET_P<3>_XF" : { "J1_E0_XF.B27" : {}, "C106_XF.2" : { "C106_XF.1" : { "AC_E1S0_PET_P<3>_XF" : { "U1_XF.A7" : {} } } } }, "UNNAMED_17_BYPASSCAPNPOL_I198_B_XF" : { "U1_XF.BW40" : {}, "C315_XF.2" : { "C315_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I198_A_XF" : { "U1_XF.BW39" : {}, "R25_XF.2" : { "R25_XF.1" : { "UNNAMED_17_RESISTOR_I196_A_XF" : { "R17_XF.2" : { "R17_XF.1" : { "UNNAMED_17_RESISTOR_I201_A_XF" : { "R10_XF.2" : { "R10_XF.1" : { "GND" : {} } } } } }, "R14_XF.2" : { "R14_XF.1" : { "IMON_VCCAUX_LIN_XF" : { "R90_FL_XF.1" : { "R90_FL_XF.2" : { "UNNAMED_9_LT3071_I30_IMON_FL" : { "U7_FL_XF.21" : {}, "IMON_VCCAUX_A_TP_FL_XF.1" : {} } } }, "IMON_VCCAUX_TP_FL_XF.1" : {}, "R113_FL_XF.1" : { "R113_FL_XF.2" : { "UNNAMED_9_LT3071_I66_IMON_FL" : { "U11_FL_XF.21" : {}, "IMON_VCCAUX_B_TP_FL_XF.1" : {} } } } } } } } } } } } }, "R26_XF.2" : { "R26_XF.1" : { "UNNAMED_17_RESISTOR_I199_A_XF" : { "R23_XF.2" : { "R23_XF.1" : { "UNNAMED_17_RESISTOR_I202_A_XF" : { "R13_XF.2" : { "R13_XF.1" : { "GND" : {} } } } } }, "R21_XF.2" : { "R21_XF.1" : { "GND" : {} } } } } } }, "C3_DDR4_DQ<69>_XF" : { "J4_XF.192" : {}, "U1_XF.F15" : {} }, "C2_DDR4_ADR<4>_XF" : { "J3_XF.214" : {}, "U1_XF.K58" : {} }, "E1S2_PER_N<3>_XF" : { "J1_E2_XF.A26" : {}, "U1_XF.W1" : {} }, "E1S0_PET_P<6>_XF" : { "C103_XF.2" : { "C103_XF.1" : { "AC_E1S0_PET_P<6>_XF" : { "U1_XF.D9" : {} } } }, "J1_E0_XF.B37" : {} }, "C3_DDR4_DQ<39>_XF" : { "U1_XF.A28" : {}, "J4_XF.247" : {} }, "POK_OD_VCCINT_BLSW_P<1>" : { "U1_CPLD.T11" : {}, "R31_SP_XF.2" : { "R31_SP_XF.1" : { "UNNAMED_10_LTM4650FIXED_I151_PGOOD2_SP" : { "PM3_SP_XF.G8" : { "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G3" : { "GND" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} } } } } } }, "UNNAMED_4_PI6CB33401_I37_BWSELTRI_E2" : { "U1_E2_XF.1" : {}, "R10_E2_XF.2" : { "R10_E2_XF.1" : { "GND" : {} } } }, "NC_BL_1_SP" : {}, "C2_SYS_CLK_P_XF" : { "R251_XF.1" : { "R251_XF.2" : { "C2_SYS_CLK_N_XF" : {} } }, "U1_XF.J59" : {}, "C364_XF.2" : { "C364_XF.1" : { "DDR4_SYS_CLK_P<2>_XF" : { "U6_XF.12" : {} } } }, "R249_XF.2" : { "R249_XF.1" : { "PWR_NDIMM_VDD_XF" : {} } }, "R250_XF.1" : { "R250_XF.2" : { "GND" : {} } } }, "E1S3_PET_N<7>_XF" : { "J1_E3_XF.B39" : {}, "C174_XF.2" : { "C174_XF.1" : { "AC_E1S3_PET_N<7>_XF" : { "U1_XF.AJ10" : {} } } } }, "C3_DDR4_DQ<47>_XF" : { "U1_XF.A21" : {}, "J4_XF.258" : {} }, "UNNAMED_7_LTM4671_I87_FREQ0_SP" : { "R108_SP_XF.1" : { "R108_SP_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I44_B_SP" : { "R115_SP_XF.2" : { "R115_SP_XF.1" : { "UNNAMED_7_LTM4671_I87_MODECLKIN0_SP" : { "PM1_SP_XF.G11" : { "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.F10" : { "UNNAMED_7_LTM4671_I87_FREQ0_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : {} } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {}, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.E7" : { "UNNAMED_7_BYPASSCAPNPOL_I44_B_SP" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} } } } } } } } } }, "UNNAMED_3_BYPASSCAPNPOL_I151_A_SP" : { "C23_SP_XF.1" : { "C23_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.50" : {}, "R35_SP_XF.1" : { "R35_SP_XF.2" : { "VS_AVTT_LIN_N_XF" : { "NS10_FL_XF.2" : { "NS10_FL_XF.1" : { "GND" : {} } } } } } }, "POK_OD_LTC2975" : { "U1_CPLD.T15" : {}, "R56_SP_XF.1" : { "R56_SP_XF.2" : { "UNNAMED_3_LTC2975_I168_PWRGD_SP" : { "U1_SP_XF.17" : {} } } } }, "RFU_<1>_E3" : { "J1_E3_XF.A42" : {} }, "POK_OD_NDIMM_VDD_SW" : { "R2_ND_XF.2" : { "R2_ND_XF.1" : { "UNNAMED_3_DIODESOD923F_I70_A_ND" : { "PM4_ND_XF.E2" : { "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : {} } } } } } }, "U1_CPLD.C9" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } } } } } }, "U1_CPLD.P8" : {} }, "EMC1428_SYS_SHDN_OD_F" : { "U1_CPLD.P6" : {}, "R57_SP_XF.1" : { "R57_SP_XF.2" : { "P3R3V" : {} } }, "U4_SP_XF.6" : {} }, "PCIE0_RXN<1>_XF" : { "U1_XF.AW1" : {}, "J1_P0_XF.A7" : {} }, "UNNAMED_9_LUMEXRGBLED_I92_GREENK_CPLD" : { "D4_CPLD.4" : { "D4_CPLD.1" : { "CPLD_P3R3V" : {} }, "D4_CPLD.3" : { "UNNAMED_9_LUMEXRGBLED_I92_BLUEK_CPLD" : { "R26_CPLD.1" : { "R26_CPLD.2" : { "RGB_LED_BLUE<0>_CPLD" : { "U1_CPLD.E6" : {} } } } } }, "D4_CPLD.2" : { "UNNAMED_9_LUMEXRGBLED_I92_REDK_CPLD" : { "R24_CPLD.1" : { "R24_CPLD.2" : { "RGB_LED_RED<0>_CPLD" : { "U1_CPLD.E9" : {} } } } } } }, "R25_CPLD.1" : { "R25_CPLD.2" : { "RGB_LED_GREEN<0>_CPLD" : { "U1_CPLD.E8" : {} } } } }, "RGB_LED_RED<0>_CPLD" : { "R24_CPLD.2" : { "R24_CPLD.1" : { "UNNAMED_9_LUMEXRGBLED_I92_REDK_CPLD" : { "D4_CPLD.2" : { "D4_CPLD.4" : { "UNNAMED_9_LUMEXRGBLED_I92_GREENK_CPLD" : { "R25_CPLD.1" : { "R25_CPLD.2" : { "RGB_LED_GREEN<0>_CPLD" : { "U1_CPLD.E8" : {} } } } } }, "D4_CPLD.1" : { "CPLD_P3R3V" : {} }, "D4_CPLD.3" : { "UNNAMED_9_LUMEXRGBLED_I92_BLUEK_CPLD" : { "R26_CPLD.1" : { "R26_CPLD.2" : { "RGB_LED_BLUE<0>_CPLD" : { "U1_CPLD.E6" : {} } } } } } } } } }, "U1_CPLD.E9" : {} }, "C1_DDR4_DQ<4>_XF" : { "U1_XF.BP49" : {}, "J2_XF.3" : {} }, "OCL3_PER_N<2>_XF" : { "U1_XF.BH3" : {}, "J1_O3_XF.A16" : {} }, "IS_VCCINTLL_SW_N_SP" : { "C128_SP_XF.1" : { "C128_SP_XF.2" : { "GND" : {} } }, "R51_SP_XF.2" : { "R51_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I148_A_SP" : { "C39_SP_XF.1" : { "C39_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.42" : {} } } }, "R130_SP_XF.2" : { "R130_SP_XF.1" : { "GND" : {} } }, "R129_SP_XF.1" : { "R129_SP_XF.2" : { "P3R3V" : {} } } }, "CKI_LTM4675_ND" : { "PM4_ND_XF.E5" : { "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U1_CPLD.C9" : {}, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } }, "U11.13" : {} } } } }, "C1_RDIMM_DQS_C<16>_XF" : { "J2_XF.133" : {}, "U1_XF.BN53" : {} }, "PCIE1_TXN<7>_XF" : { "C42_XF.2" : { "C42_XF.1" : { "AC_PCIE1_TXN<7>_XF" : { "U1_XF.AT12" : {} } } }, "J2_P1_XF.B19" : {} }, "NDIMM_VDD_BNC_XF" : { "J5_XF.C" : {}, "R91_XF.2" : { "R91_XF.1" : { "PWR_NDIMM_VDD_XF" : {} } } }, "AC_PCIE1_TXP<1>_XF" : { "U1_XF.AM13" : {}, "C32_XF.1" : { "C32_XF.2" : { "PCIE1_TXP<1>_XF" : { "J1_P1_XF.B6" : {} } } } }, "PCIE1_WAKE_F_XF" : { "J1_P1_XF.B10" : {}, "U1_XF.BE18" : {} }, "C2_RDIMM_DQS_T<14>_XF" : { "U1_XF.F53" : {}, "J3_XF.110" : {} }, "UNNAMED_17_RESISTOR_I53_A_XF" : { "R72_XF.2" : { "R72_XF.1" : { "IMON_AVCC_LIN_XF" : { "R7_FL_XF.2" : { "R7_FL_XF.1" : { "UNNAMED_3_LT3071_I32_IMON_FL" : { "U3_FL_XF.21" : {} } } }, "R15_FL_XF.2" : { "R15_FL_XF.1" : { "UNNAMED_4_LT3071_I30_IMON_FL" : { "U6_FL_XF.21" : {} } } }, "R91_FL_XF.2" : { "R91_FL_XF.1" : { "UNNAMED_12_LT3071_I30_IMON_FL" : { "U10_FL_XF.21" : {} } } } } } }, "R82_XF.1" : { "R82_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_A_XF" : { "U1_XF.BY38" : {}, "C141_XF.1" : { "C141_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_B_XF" : { "U1_XF.CA38" : {}, "R83_XF.2" : { "R83_XF.1" : { "UNNAMED_17_RESISTOR_I54_A_XF" : { "R75_XF.2" : { "R75_XF.1" : { "UNNAMED_17_RESISTOR_I187_B_XF" : { "R119_XF.2" : { "R119_XF.1" : { "GND" : {} } } } } }, "R74_XF.2" : { "R74_XF.1" : { "GND" : {} } } } } } } } } } } }, "R73_XF.2" : { "R73_XF.1" : { "UNNAMED_17_RESISTOR_I188_B_XF" : { "R118_XF.2" : { "R118_XF.1" : { "GND" : {} } } } } } }, "E1S_REF_CLK_N<1>" : { "C17_E1_XF.1" : { "C17_E1_XF.2" : { "CLKIN_N_E1" : { "R18_E1_XF.1" : { "R18_E1_XF.2" : { "GND" : {} } }, "R15_E1_XF.2" : { "R15_E1_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E1_XF.6" : {} } } }, "U1.30" : {} }, "C1_RDIMM_DQS_T<7>_XF" : { "U1_XF.BK54" : {}, "J2_XF.278" : {} }, "C0_DDR4_DQ<67>_XF" : { "U1_XF.BR27" : {}, "J1_XF.201" : {} }, "SI5341_VDDA" : { "C96.1" : { "C96.4" : { "GND" : {} }, "C96.2" : { "P3R3V" : {} }, "C96.3" : { "GND" : {} } }, "C32.2" : { "C32.1" : { "GND" : {} } }, "U1.13" : {} }, "E1S1_PER_P<2>_XF" : { "U1_XF.N2" : {}, "J1_E1_XF.A24" : {} }, "FAN_TACH_OD<3>" : { "U1_CPLD.G14" : {}, "P3.3" : {} }, "C0_DDR4_DQ<37>_XF" : { "U1_XF.BN21" : {}, "J1_XF.240" : {} }, "C0_RDIMM_DQS_T<13>_XF" : { "J1_XF.99" : {}, "U1_XF.BM24" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I116_A_XF" : { "R129_XF.1" : { "R129_XF.2" : { "UNNAMED_17_RESISTOR_I110_A_XF" : { "R138_XF.1" : { "R138_XF.2" : { "GND" : {} } }, "R137_XF.1" : { "R137_XF.2" : { "VMON_AVTT_RS_LIN_XF" : { "R93_XF.2" : { "R93_XF.1" : { "UNNAMED_17_RESISTOR_I40_A_XF" : { "R94_XF.1" : { "R94_XF.2" : { "GND" : {} } }, "R99_XF.2" : { "R99_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I46_A_XF" : { "U1_XF.BY33" : {}, "C147_XF.1" : { "C147_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I46_B_XF" : { "U1_XF.CA33" : {}, "R100_XF.1" : { "R100_XF.2" : { "UNNAMED_17_RESISTOR_I41_A_XF" : { "R96_XF.1" : { "R96_XF.2" : { "GND" : {} } }, "R95_XF.1" : { "R95_XF.2" : { "GND" : {} } } } } } } } } } } } } } }, "R4_FL_XF.2" : { "R4_FL_XF.1" : { "VS_AVTT_RS_LIN_FL" : { "U2_FL_XF.19" : {}, "NS5_FL_XF.2" : { "NS5_FL_XF.1" : { "PWR_AVTT_RS_XF" : {} } } } } } } } } } } }, "U1_XF.BW31" : {}, "C268_XF.1" : { "C268_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I116_B_XF" : { "R130_XF.1" : { "R130_XF.2" : { "UNNAMED_17_RESISTOR_I113_A_XF" : { "R141_XF.1" : { "R141_XF.2" : { "GND" : {} } }, "R139_XF.1" : { "R139_XF.2" : { "GND" : {} } } } } }, "U1_XF.BW32" : {} } } } }, "E1S1_FPGA_REFCLK_N<1>_XF" : { "C22_E1_XF.2" : { "C22_E1_XF.1" : { "AC_FPGA_CLK_REF_N<1>" : { "U1_E1_XF.28" : {} } } }, "R177_XF.2" : { "R177_XF.1" : { "E1S1_FPGA_REFCLK_P<1>_XF" : {} } }, "R178_XF.1" : { "R178_XF.2" : { "GND" : {} } }, "R167_XF.2" : { "R167_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_XF.U14" : {} }, "C0_DDR4_DQ<49>_XF" : { "J1_XF.264" : {}, "U1_XF.BG24" : {} }, "PCIE0_TXP<6>_XF" : { "C35_XF.2" : { "C35_XF.1" : { "AC_PCIE0_TXP<6>_XF" : { "U1_XF.BB9" : {} } } }, "J2_P0_XF.B15" : {} }, "AC_PCIE0_REFP_XF" : { "C100_XF.2" : { "C100_XF.1" : { "PCIE0_REFP_XF" : { "R1_P0_XF.2" : { "R1_P0_XF.1" : { "UNNAMED_3_OCULINKX4CONN_I86_REFCLKP_P0" : { "J1_P0_XF.B12" : {} } } } } } }, "U1_XF.BB13" : {} }, "UNNAMED_22_RESISTOR_I44_B_XF" : { "R56_XF.2" : { "R56_XF.1" : { "GND" : {} } }, "U1_XF.BL26" : {} }, "UNNAMED_3_LTC2975_I168_VINISP2975_SP" : { "R14_SP_XF.2" : { "R14_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I177_A_SP" : { "C63_SP_XF.1" : { "C63_SP_XF.2" : { "GND" : {} } }, "R40_SP_XF.2" : { "R40_SP_XF.1" : { "P12V_MAIN" : {} } }, "U1_SP_XF.9" : {} } } }, "U1_SP_XF.55" : {} }, "AC_PCIE1_TXP<0>_XF" : { "C33_XF.1" : { "C33_XF.2" : { "PCIE1_TXP<0>_XF" : { "J1_P1_XF.B3" : {} } } }, "U1_XF.AM9" : {} }, "E1S2_3R3V_SDA_XF" : { "R4_E2_XF.2" : { "R4_E2_XF.1" : { "P3R3V" : {} } }, "R207_XF.2" : { "R207_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_XF.P20" : {}, "J1_E2_XF.A8" : {} }, "TS_LT4650_BR_SP" : { "U1_SP_XF.27" : {}, "PM7_SP_XF.J6" : { "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} } } } }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.K6" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.G1" : { "GND" : {} } } }, "E1S3_PET_N<5>_XF" : { "C326_XF.2" : { "C326_XF.1" : { "AC_E1S3_PET_N<5>_XF" : { "U1_XF.AK12" : {} } } }, "J1_E3_XF.B33" : {} }, "C1_DDR4_DQ<52>_XF" : { "J2_XF.117" : {}, "U1_XF.BM56" : {} }, "UNNAMED_4_MAX116XXQSOP16_I97_AIN1" : { "C48.1" : { "C48.2" : { "GND" : {} } }, "R47.1" : { "R47.2" : { "VMON_RS_RLC_MGTVCCAUX" : { "R85_FL_XF.2" : { "R85_FL_XF.1" : { "PWR_RS_RLC_MGTVCCAUX_XF" : {} } } } } }, "R30.1" : { "R30.2" : { "GND" : {} } }, "U11.6" : {} }, "PCIE1_RXP<5>_XF" : { "U1_XF.AT4" : {}, "J2_P1_XF.A6" : {} }, "AC_OCL0_CONN_REFCLK_P_XF" : { "C356_XF.1" : { "C356_XF.2" : { "OCL0_CONN_REFCLK_P_XF" : { "J1_O0_XF.B12" : {} } } }, "U7_XF.13" : {} }, "UNNAMED_3_OCULINKX4CONN_I86_REFCLKP_P1" : { "R1_P1_XF.1" : { "R1_P1_XF.2" : { "PCIE1_REFP_XF" : { "C230_XF.1" : { "C230_XF.2" : { "AC_PCIE1_REFP_XF" : { "U1_XF.AU15" : {} } } } } } }, "J1_P1_XF.B12" : {} }, "C2_RDIMM_DQS_C<12>_XF" : { "J3_XF.41" : {}, "U1_XF.K54" : {} }, "C2_DDR4_PARITY_XF" : { "U1_XF.K62" : {}, "J3_XF.222" : {} }, "C2_DDR4_DQ<15>_XF" : { "U1_XF.P47" : {}, "J3_XF.166" : {} }, "UNNAMED_12_LT3071_I30_MARGA_FL" : { "R94_FL_XF.2" : { "R94_FL_XF.1" : { "UNNAMED_12_BYPASSCAPNPOL_I23_B_FL" : { "R93_FL_XF.2" : { "R93_FL_XF.1" : { "DAC_AVCC_LIN_XF" : { "R21_FL_XF.1" : { "R21_FL_XF.2" : { "UNNAMED_4_BYPASSCAPNPOL_I23_B_FL" : { "R22_FL_XF.1" : { "R22_FL_XF.2" : { "UNNAMED_4_LT3071_I30_MARGA_FL" : { "U6_FL_XF.22" : {} } } }, "C5_FL_XF.2" : { "C5_FL_XF.1" : { "GND" : {} } } } } }, "R11_FL_XF.1" : { "R11_FL_XF.2" : { "UNNAMED_3_BYPASSCAPNPOL_I31_B_FL" : { "R12_FL_XF.1" : { "R12_FL_XF.2" : { "UNNAMED_3_LT3071_I32_MARGA_FL" : { "U3_FL_XF.22" : {} } } }, "C66_FL_XF.2" : { "C66_FL_XF.1" : { "GND" : {} } } } } }, "U1_SP_XF.57" : {} } } }, "C94_FL_XF.2" : { "C94_FL_XF.1" : { "GND" : {} } } } } }, "U10_FL_XF.22" : {} }, "OCL0_PER_N<0>_XF" : { "J1_O0_XF.A4" : {}, "U1_XF.BY3" : {} }, "C1_DDR4_DQ<54>_XF" : { "J2_XF.124" : {}, "U1_XF.BN59" : {} }, "UNNAMED_3_LT3071_I32_EN_FL" : { "U3_FL_XF.28" : {}, "R69_FL_XF.1" : { "R69_FL_XF.2" : { "P3R3V" : {} } } }, "AC_OCL3_PET_N<3>_XF" : { "C278_XF.1" : { "C278_XF.2" : { "OCL3_PET_N<3>_XF" : { "J1_O3_XF.B19" : {} } } }, "U1_XF.BG6" : {} }, "UNNAMED_7_LTM4671_I87_VOSNS0N_SP" : { "PM1_SP_XF.F8" : { "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } } } } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} } } } } } } }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} } } }, "C1_DDR4_ADR<5>_XF" : { "J2_XF.213" : {}, "U1_XF.BY49" : {} }, "C0_DDR4_DQ<68>_XF" : { "U1_XF.BV26" : {}, "J1_XF.47" : {} }, "C0_RDIMM_DQS_T<17>_XF" : { "U1_XF.BW27" : {}, "J1_XF.51" : {} }, "C1_DDR4_DQ<60>_XF" : { "J2_XF.128" : {}, "U1_XF.BL53" : {} }, "OCL3_FPGA_REFCLK_P_XF" : { "R216_XF.2" : { "R216_XF.1" : { "P3R3V" : {} } }, "C357_XF.2" : { "C357_XF.1" : { "AC_OCL3_FPGA_REFCLK_P_XF" : { "U5_XF.27" : {} } } }, "U1_XF.BJ15" : {}, "R228_XF.1" : { "R228_XF.2" : { "OCL3_FPGA_REFCLK_N_XF" : {} } }, "R227_XF.1" : { "R227_XF.2" : { "GND" : {} } } }, "UNNAMED_20_FERRITEBEAD_I57_B" : { "FB6.2" : { "FB6.1" : { "P12V_MAIN" : {} } }, "P3.2" : {} }, "UNNAMED_20_FERRITEBEAD_I55_B" : { "FB8.2" : { "FB8.1" : { "P12V_MAIN" : {} } }, "P5.2" : {} }, "AC_E1S2_PET_P<0>_XF" : { "C155_XF.1" : { "C155_XF.2" : { "E1S2_PET_P<0>_XF" : { "J1_E2_XF.B18" : {} } } }, "U1_XF.W11" : {} }, "C1_DDR4_DQ<30>_XF" : { "J2_XF.43" : {}, "U1_XF.BW60" : {} }, "PCIE0_TXN<4>_XF" : { "J2_P0_XF.B4" : {}, "C78_XF.2" : { "C78_XF.1" : { "AC_PCIE0_TXN<4>_XF" : { "U1_XF.AY8" : {} } } } }, "AC_PCIE0_TXP<7>_XF" : { "C34_XF.1" : { "C34_XF.2" : { "PCIE0_TXP<7>_XF" : { "J2_P0_XF.B18" : {} } } }, "U1_XF.BC11" : {} }, "UNNAMED_4_RESISTOR_I7_A_ND" : { "R61_ND_XF.1" : { "R61_ND_XF.2" : { "POK_OD_NDIMM_VTT_LIN" : { "U1_CPLD.T8" : {} } } }, "U2_ND_XF.9" : {} }, "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF" : { "PM4_SD_XF.G6" : {}, "PM4_SD_XF.F5" : {}, "R7_SD_XF.1" : { "R7_SD_XF.2" : { "UNNAMED_3_LTM4675_I40_VOUT1CFG_SD" : {} } }, "C68_SD_XF.1" : { "C68_SD_XF.2" : { "P12V_FUSED_4675_SD" : {} } }, "R6_SD_XF.1" : { "R6_SD_XF.2" : { "UNNAMED_3_LTM4675_I40_VTRIM0CFG_SD" : { "PM4_SD_XF.H3" : {} } } }, "C81_SD_XF.2" : { "C81_SD_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I28_A_SD" : {} } }, "R123_XF.1" : { "R123_XF.2" : { "SDIMM_I2C_ASEL_RESISTOR_XF" : {} } }, "C67_SD_XF.1" : { "C67_SD_XF.2" : { "P12V_FUSED_4675_SD" : {} } }, "R5_SD_XF.1" : { "R5_SD_XF.2" : { "UNNAMED_3_LTM4675_I40_VOUT0CFG_SD" : {} } }, "R26_SD_XF.1" : { "R26_SD_XF.2" : { "UNNAMED_3_LTM4675_I40_WP_SD" : {} } }, "PM4_SD_XF.G5" : {}, "NS13_SD_XF.2" : { "NS13_SD_XF.1" : { "GND" : {} } }, "R9_SD_XF.1" : { "R9_SD_XF.2" : { "UNNAMED_3_LTM4675_I40_FSWPHCFG_SD" : {} } }, "PM4_SD_XF.F6" : {}, "R8_SD_XF.1" : { "R8_SD_XF.2" : { "UNNAMED_3_LTM4675_I40_VTRIM1CFG_SD" : { "PM4_SD_XF.H4" : {} } } } }, "PSU_3R3V_SCL" : { "Q10.3" : { "Q10.2" : { "PSU_1R8V_SCL" : { "R9.1" : { "R9.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.CA35" : {} } }, "Q10.1" : { "UNNAMED_12_NMOSFETVMT3_I4_G" : { "R8.2" : { "R8.1" : { "UNNAMED_12_RESISTOR_I13_A" : { "R7.1" : { "R7.2" : { "UNNAMED_12_NMOSFETVMT3_I12_G" : { "Q11.1" : { "Q11.3" : { "PSU_3R3V_SDA" : { "R24.2" : { "R24.1" : { "P3R3V" : {} } }, "J4.2" : {} } }, "Q11.2" : { "PSU_1R8V_SDA" : { "R19.1" : { "R19.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.CA37" : {} } } } } } }, "R4.2" : { "R4.1" : { "DIS_1R8V_I2C_XLAT_F" : { "U1_CPLD.H3" : {}, "R58.1" : { "R58.2" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } } } } } } } } } } } }, "R1.2" : { "R1.1" : { "FPGA_VCCAUX_P1R8V" : {} } } } } } } } } }, "C0_DDR4_DQ<38>_XF" : { "U1_XF.BP21" : {}, "J1_XF.102" : {} }, "UNNAMED_4_RESISTOR_I16_A_MP" : { "R6_MP.2" : { "R6_MP.1" : { "GND" : {} } }, "R7_MP.1" : { "R7_MP.2" : { "UNNAMED_4_RESISTOR_I16_B_MP" : { "U2_MP.8" : {} } } } }, "C3_DDR4_ADR<3>_XF" : { "U1_XF.N28" : {}, "J4_XF.71" : {} }, "AC_OCL0_PET_P<0>_XF" : { "C180_XF.1" : { "C180_XF.2" : { "OCL0_PET_P<0>_XF" : { "J1_O0_XF.B3" : {} } } }, "U1_XF.CC11" : {} }, "UNNAMED_20_FERRITEBEAD_I58_B" : { "P2.2" : {}, "FB5.2" : { "FB5.1" : { "P12V_MAIN" : {} } } }, "UNNAMED_4_CAPACITOR_I132_A_SP" : { "PM4_SP_XF.F8" : { "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G9" : { "UNNAMED_4_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } } } }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} } } }, "E1S3_PER_N<4>_XF" : { "J1_E3_XF.A30" : {}, "U1_XF.AM3" : {} }, "UNNAMED_17_RESISTOR_I8_B" : { "U12.2" : {}, "R103.2" : { "R103.1" : { "P3R3V" : {} } } }, "OCL2_PET_P<0>_XF" : { "J1_O2_XF.B3" : {}, "C238_XF.2" : { "C238_XF.1" : { "AC_OCL2_PET_P<0>_XF" : { "U1_XF.BN11" : {} } } } }, "OCL1_3R3V_CPRSNT_F_XF" : { "U1_XF.BN19" : {}, "J1_O1_XF.A13" : {} }, "RGB_LED_BLUE<1>_CPLD" : { "R23_CPLD.2" : { "R23_CPLD.1" : { "UNNAMED_9_LUMEXRGBLED_I91_BLUEK_CPLD" : { "D3_CPLD.3" : { "D3_CPLD.2" : { "UNNAMED_9_LUMEXRGBLED_I91_REDK_CPLD" : { "R21_CPLD.1" : { "R21_CPLD.2" : { "RGB_LED_RED<1>_CPLD" : { "U1_CPLD.D8" : {} } } } } }, "D3_CPLD.4" : { "UNNAMED_9_LUMEXRGBLED_I91_GREENK_CPLD" : { "R22_CPLD.1" : { "R22_CPLD.2" : { "RGB_LED_GREEN<1>_CPLD" : { "U1_CPLD.F7" : {} } } } } }, "D3_CPLD.1" : { "CPLD_P3R3V" : {} } } } } }, "U1_CPLD.C7" : {} }, "UNNAMED_4_PI6CB33401_I37_PDF_E3" : { "R13_E3_XF.2" : { "R13_E3_XF.1" : { "GND" : {} } }, "U1_E3_XF.31" : {} }, "UNNAMED_5_LTM4650FIXED_I78_PGOOD2_SP" : { "PM5_SP_XF.G8" : { "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } } } }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} } } }, "ENB3V_SEQ_B" : { "PM1_SP_XF.F11" : { "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {}, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.C6" : { 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: {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {}, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} } } }, "E1S1_3R3V_PRSNT_F<0>_XF" : { "R8_E1_XF.2" : { "R8_E1_XF.1" : { "P3R3V" : {} } }, "J1_E1_XF.A12" : {}, "U1_XF.AD19" : {} }, "CKO_LTM4650_PM7_SP" : { "R68_SP_XF.1" : { "R68_SP_XF.2" : { "UNNAMED_5_LTM4650FIXED_I78_MODEPLLIN_SP" : { "PM5_SP_XF.F4" : { "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.G1" : { "GND" : {} } } } } } }, "UNNAMED_3_LTM4675_I40_VOUT0CFG_SD" : { "PM4_SD_XF.G3" : { "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } }, "U1_CPLD.C9" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "C2_DDR4_ADR<2>_XF" : { "U1_XF.M60" : {}, "J3_XF.216" : {} }, "OCL1_PET_P<1>_XF" : { "C183_XF.2" : { "C183_XF.1" : { "AC_OCL1_PET_P<1>_XF" : { "U1_XF.BY9" : {} } } }, "J1_O1_XF.B6" : {} }, "RGB_LED_BLUE<0>_CPLD" : { "R26_CPLD.2" : { "R26_CPLD.1" : { "UNNAMED_9_LUMEXRGBLED_I92_BLUEK_CPLD" : { "D4_CPLD.3" : { "D4_CPLD.1" : { "CPLD_P3R3V" : {} }, "D4_CPLD.4" : { "UNNAMED_9_LUMEXRGBLED_I92_GREENK_CPLD" : { "R25_CPLD.1" : { "R25_CPLD.2" : { "RGB_LED_GREEN<0>_CPLD" : { "U1_CPLD.E8" : {} } } } } }, "D4_CPLD.2" : { "UNNAMED_9_LUMEXRGBLED_I92_REDK_CPLD" : { "R24_CPLD.1" : { "R24_CPLD.2" : { "RGB_LED_RED<0>_CPLD" : { "U1_CPLD.E9" : {} } } } } } } } } }, "U1_CPLD.E6" : {} }, "C3_DDR4_DQ<48>_XF" : { "J4_XF.119" : {}, "U1_XF.D19" : {} }, "C2_DDR4_DQ<2>_XF" : { "J3_XF.12" : {}, "U1_XF.U49" : {} }, "UNNAMED_20_FERRITEBEAD_I56_B" : { "FB7.2" : { "FB7.1" : { "P12V_MAIN" : {} } }, "P4.2" : {} }, "PCIE1_TXP<3>_XF" : { "J1_P1_XF.B18" : {}, "C30_XF.2" : { "C30_XF.1" : { "AC_PCIE1_TXP<3>_XF" : { "U1_XF.AP9" : {} } } } }, "UNNAMED_8_LT3071_I30_MARGA_FL" : { "R44_FL_XF.2" : { "R44_FL_XF.1" : { "UNNAMED_8_BYPASSCAPNPOL_I25_B_FL" : { "R38_FL_XF.2" : { "R38_FL_XF.1" : { "DAC_AVTT_LIN_XF" : { "R36_FL_XF.1" : { "R36_FL_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I25_B_FL" : { "C22_FL_XF.2" : { "C22_FL_XF.1" : { "GND" : {} } }, "R42_FL_XF.1" : { "R42_FL_XF.2" : { "UNNAMED_6_LT3071_I30_MARGA_FL" : { "U2_FL_XF.22" : {} } } } } } }, "R37_FL_XF.1" : { "R37_FL_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I25_B_FL" : { "R43_FL_XF.1" : { "R43_FL_XF.2" : { "UNNAMED_7_LT3071_I30_MARGA_FL" : { "U4_FL_XF.22" : {} } } }, "C24_FL_XF.2" : { "C24_FL_XF.1" : { "GND" : {} } } } } }, "R29_FL_XF.1" : { "R29_FL_XF.2" : { "UNNAMED_5_BYPASSCAPNPOL_I25_B_FL" : { "R31_FL_XF.1" : { "R31_FL_XF.2" : { "UNNAMED_5_LT3071_I30_MARGA_FL" : { "U1_FL_XF.22" : {} } } }, "C20_FL_XF.2" : { "C20_FL_XF.1" : { "GND" : {} } } } } }, "U1_SP_XF.58" : {} } } }, "C25_FL_XF.2" : { "C25_FL_XF.1" : { "GND" : {} } } } } }, "U5_FL_XF.22" : {} }, "C1_DDR4_DQ<12>_XF" : { "J2_XF.14" : {}, "U1_XF.BR53" : {} }, "AC_E1S1_PET_N<3>_XF" : { "C134_XF.1" : { "C134_XF.2" : { "E1S1_PET_N<3>_XF" : { "J1_E1_XF.B26" : {} } } }, "U1_XF.L10" : {} }, "E1S3_PET_N<1>_XF" : { "J1_E3_XF.B20" : {}, "C313_XF.2" : { "C313_XF.1" : { "AC_E1S3_PET_N<1>_XF" : { "U1_XF.AH8" : {} } } } }, "DDR4_SYS_CLK_P<0>_XF" : { "U6_XF.16" : {}, "C360_XF.1" : { "C360_XF.2" : { "C0_SYS_CLK_P_XF" : { "U1_XF.BY20" : {}, "R33_XF.2" : { "R33_XF.1" : { "PWR_SDIMM_VDD_XF" : {} } }, "R236_XF.1" : { "R236_XF.2" : { "GND" : {} } } } } } }, "C0_DDR4_DQ<21>_XF" : { "J1_XF.170" : {}, "U1_XF.BT18" : {} }, "UNNAMED_7_LT3071_I30_MARGA_FL" : { "U4_FL_XF.22" : {}, "R43_FL_XF.2" : { "R43_FL_XF.1" : { "UNNAMED_7_BYPASSCAPNPOL_I25_B_FL" : { "C24_FL_XF.2" : { "C24_FL_XF.1" : { "GND" : {} } }, "R37_FL_XF.2" : { "R37_FL_XF.1" : { "DAC_AVTT_LIN_XF" : { "R29_FL_XF.1" : { "R29_FL_XF.2" : { "UNNAMED_5_BYPASSCAPNPOL_I25_B_FL" : { "R31_FL_XF.1" : { "R31_FL_XF.2" : { "UNNAMED_5_LT3071_I30_MARGA_FL" : { "U1_FL_XF.22" : {} } } }, "C20_FL_XF.2" : { "C20_FL_XF.1" : { "GND" : {} } } } } }, "U1_SP_XF.58" : {}, "R36_FL_XF.1" : { "R36_FL_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I25_B_FL" : { "R42_FL_XF.1" : { "R42_FL_XF.2" : { "UNNAMED_6_LT3071_I30_MARGA_FL" : { "U2_FL_XF.22" : {} } } }, "C22_FL_XF.2" : { "C22_FL_XF.1" : { "GND" : {} } } } } }, "R38_FL_XF.1" : { "R38_FL_XF.2" : { "UNNAMED_8_BYPASSCAPNPOL_I25_B_FL" : { "C25_FL_XF.2" : { "C25_FL_XF.1" : { "GND" : {} } }, "R44_FL_XF.1" : { "R44_FL_XF.2" : { "UNNAMED_8_LT3071_I30_MARGA_FL" : { "U5_FL_XF.22" : {} } } } } } } } } } } } } }, "UNNAMED_3_RESISTOR_I58_A" : { "R50.1" : { "R50.2" : { "FP_FAULT_LED_N<1>" : { "U1_CPLD.J16" : {} } } }, "FPNL_CONN.8" : {} }, "VS_VCCINT_P_SP" : { "PM4_SP_XF.E8" : { "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "PM5_SP_XF.E6" : { "PM5_SP_XF.G7" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.H8" : { "INTVCC_4650_TR_SP" : { "C32_SP_XF.1" : { "C32_SP_XF.2" : { "GND" : {} } } } }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.G2" : { "SW1_4650_TR_SP" : {} }, "PM5_SP_XF.E8" : { "INTVCC_4650_TR_SP" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L4" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.J3" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.C7" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.L6" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.L5" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.J4" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.L3" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.G8" : { "UNNAMED_5_LTM4650FIXED_I78_PGOOD2_SP" : {} }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J6" : { "TS_LT4650_TR_SP" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.D6" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L10" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K11" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.J2" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L8" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.K9" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.G6" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.G4" : { "PHASMD_4650_TR_SP" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.M11" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C6" : { "FSET_4650_TR_SP" : { "R9_SP_XF.2" : { "R9_SP_XF.1" : { "SGND_PM5_SP" : {} } } } }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J10" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.L7" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C30_SP_XF.1" : { "C30_SP_XF.2" : { "SGND_PM5_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M9" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.L2" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K3" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.G9" : { "UNNAMED_5_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M4" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.F4" : { "UNNAMED_5_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM5_SP_XF.G11" : { "SW2_4650_TR_SP" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.M6" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.F6" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.M5" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.E9" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.M3" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.K4" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M10" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.J9" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.M8" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.J11" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.K2" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.K10" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.L11" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.M7" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.F7" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.M2" : { "P12V_4650_TR_SP" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.L9" : { "P12V_4650_TR_SP" : {} } }, "C71_SP_XF.2" : { "C71_SP_XF.1" : { "SGND_PM4_SP" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G12" : { "GND" : {} } } }, "C0_DDR4_DQ<50>_XF" : { "J1_XF.126" : {}, "U1_XF.BH22" : {} }, "UNNAMED_17_RESISTOR_I59_A_XF" : { "R111_XF.2" : { "R111_XF.1" : { "GND" : {} } }, "R110_XF.2" : { "R110_XF.1" : { "VMON_AVTT_RLC_LIN_XF" : { "R56_FL_XF.2" : { "R56_FL_XF.1" : { "VS_AVTT_RLC_LIN_FL" : { "U1_FL_XF.19" : {}, "NS3_FL_XF.2" : { "NS3_FL_XF.1" : { "PWR_AVTT_RLC_XF" : {} } } } } } } } }, "R80_XF.1" : { "R80_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I57_A_XF" : { "U1_XF.CC36" : {}, "C140_XF.1" : { "C140_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I57_B_XF" : { "U1_XF.CC37" : {}, "R81_XF.2" : { "R81_XF.1" : { "UNNAMED_17_RESISTOR_I60_A_XF" : { "R112_XF.2" : { "R112_XF.1" : { "GND" : {} } }, "R113_XF.2" : { "R113_XF.1" : { "GND" : {} } } } } } } } } } } } }, "FPGA_PROG_F_1" : { "U1_CPLD.G2" : {}, "U1_XF.AK18" : {} }, "C1_DDR4_DQ<58>_XF" : { "J2_XF.137" : {}, "U1_XF.BM54" : {} }, "C1_DDR4_BA<0>_XF" : { "U1_XF.BY50" : {}, "J2_XF.81" : {} }, "UNNAMED_3_LTC2975_I168_VINISN2975_SP" : { "U1_SP_XF.56" : {}, "R42_SP_XF.2" : { "R42_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I177_A_SP" : { "C63_SP_XF.1" : { "C63_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.9" : {}, "R40_SP_XF.2" : { "R40_SP_XF.1" : { "P12V_MAIN" : {} } } } } } }, "UNNAMED_7_LTM4671_I37_TRACKSS1_SP" : { "PM1_SP_XF.G7" : { "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {}, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} } } }, "C2_DDR4_CKE<1>_XF" : { "U1_XF.M54" : {}, "J3_XF.203" : {} }, "UNNAMED_8_BYPASSCAPNPOL_I25_B_FL" : { "R38_FL_XF.2" : { "R38_FL_XF.1" : { "DAC_AVTT_LIN_XF" : { "R29_FL_XF.1" : { "R29_FL_XF.2" : { "UNNAMED_5_BYPASSCAPNPOL_I25_B_FL" : { "R31_FL_XF.1" : { "R31_FL_XF.2" : { "UNNAMED_5_LT3071_I30_MARGA_FL" : { "U1_FL_XF.22" : {} } } }, "C20_FL_XF.2" : { "C20_FL_XF.1" : { "GND" : {} } } } } }, "U1_SP_XF.58" : {}, "R37_FL_XF.1" : { "R37_FL_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I25_B_FL" : { "R43_FL_XF.1" : { "R43_FL_XF.2" : { "UNNAMED_7_LT3071_I30_MARGA_FL" : { "U4_FL_XF.22" : {} } } }, "C24_FL_XF.2" : { "C24_FL_XF.1" : { "GND" : {} } } } } }, "R36_FL_XF.1" : { "R36_FL_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I25_B_FL" : { "R42_FL_XF.1" : { "R42_FL_XF.2" : { "UNNAMED_6_LT3071_I30_MARGA_FL" : { "U2_FL_XF.22" : {} } } }, "C22_FL_XF.2" : { "C22_FL_XF.1" : { "GND" : {} } } } } } } } }, "C25_FL_XF.2" : { "C25_FL_XF.1" : { "GND" : {} } }, "R44_FL_XF.1" : { "R44_FL_XF.2" : { "UNNAMED_8_LT3071_I30_MARGA_FL" : { "U5_FL_XF.22" : {} } } } }, "FPGA_P1R8V_TDO" : { "U1_CPLD.H6" : {}, "R41_XF.2" : { "R41_XF.1" : { "UNNAMED_18_RESISTOR_I22_A_XF" : { "U1_XF.AN18" : {} } } } }, "SI5341_FDEC" : { "U1_CPLD.F4" : {}, "U1.25" : {} }, "C0_DDR4_DQ<64>_XF" : { "J1_XF.49" : {}, "U1_XF.BT27" : {} }, "VS_AVTT_RUC_LIN_FL" : { "U5_FL_XF.19" : {}, "R57_FL_XF.1" : { "R57_FL_XF.2" : { "VMON_AVTT_RUC_LIN_XF" : { "R106_XF.1" : { "R106_XF.2" : { "UNNAMED_17_RESISTOR_I61_A_XF" : { "R107_XF.2" : { "R107_XF.1" : { "GND" : {} } }, "R97_XF.1" : { "R97_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I58_A_XF" : { "U1_XF.BV36" : {}, "C146_XF.1" : { "C146_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I58_B_XF" : { "U1_XF.BW36" : {}, "R98_XF.2" : { "R98_XF.1" : { "UNNAMED_17_RESISTOR_I95_B_XF" : { "R109_XF.2" : { "R109_XF.1" : { "GND" : {} } }, "R108_XF.2" : { "R108_XF.1" : { "GND" : {} } } } } } } } } } } } } } } } } }, "NS9_FL_XF.2" : { "NS9_FL_XF.1" : { "PWR_AVTT_RUC_XF" : {} } } }, "BASE_3R3V_SDA_2" : { "U11.14" : {}, "Q4.3" : { "Q4.1" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "R5.2" : { "R5.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R3.1" : { "R3.2" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "Q3.1" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.3" : { "BASE_3R3V_SCL_2" : { "U12.6" : {}, "R34.2" : { "R34.1" : { "P3R3V" : {} } }, "Q1.3" : { "Q1.1" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "R32.2" : { "R32.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R31.1" : { "R31.2" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "Q2.1" : { "Q2.3" : { "BASE_3R3V_SDA_2" : {} }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } } } } } } } } } }, "Q1.2" : { "FPGA_1R8V_SCL" : { "R33.1" : { "R33.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U11.13" : {}, "U1_CPLD.A9" : {} } } } } } } } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } }, "PCIE1_RXP<2>_XF" : { "J1_P1_XF.A15" : {}, "U1_XF.AP4" : {} }, "E1S3_FPGA_REFCLK_P<0>_XF" : { "R204_XF.1" : { "R204_XF.2" : { "E1S3_FPGA_REFCLK_N<0>_XF" : {} } }, "C19_E3_XF.2" : { "C19_E3_XF.1" : { "AC_FPGA_CLK_REF_P<0>_2" : { "U1_E3_XF.22" : {} } } }, "U1_XF.AG15" : {}, "R203_XF.1" : { "R203_XF.2" : { "GND" : {} } }, "R192_XF.2" : { "R192_XF.1" : { "PWR_FPGA_3R3V" : {} } } }, "OCL_REF_CLK_P<0>" : { "U1.42" : {}, "R279_XF.1" : { "R279_XF.2" : { "GND" : {} } }, "U7_XF.5" : {}, "R275_XF.2" : { "R275_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R280_XF.1" : { "R280_XF.2" : { "OCL_REF_CLK_N<0>" : {} } } }, "UNNAMED_4_MAX116XXQSOP16_I97_AIN5" : { "C43.1" : { "C43.2" : { "GND" : {} } }, "R54.1" : { "R54.2" : { "VMON_NDIMM_VPP_SW" : { "R123_SP_XF.2" : { "R123_SP_XF.1" : { "PWR_NDIMM_VPP_XF" : {} } } } } }, "R76.1" : { "R76.2" : { "GND" : {} } }, "U11.10" : {} }, "OCL2_PER_P<1>_XF" : { "J1_O2_XF.A6" : {}, "U1_XF.BL6" : {} }, "C3_DDR4_DQ<1>_XF" : { "U1_XF.L16" : {}, "J4_XF.150" : {} }, "AC_E1S2_PET_N<6>_XF" : { "C157_XF.1" : { "C157_XF.2" : { "E1S2_PET_N<6>_XF" : { "J1_E2_XF.B36" : {} } } }, "U1_XF.AA10" : {} }, "OCL0_PET_N<1>_XF" : { "C260_XF.2" : { "C260_XF.1" : { "AC_OCL0_PET_N<1>_XF" : { "U1_XF.CC6" : {} } } }, "J1_O0_XF.B7" : {} }, "UNNAMED_4_RESISTOR_I12_B_SP" : { "R11_SP_XF.1" : { "R11_SP_XF.2" : { "VFB_4650_SP" : { "PM4_SP_XF.D5" : { "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } } } }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} } } } } } }, "AC_PCIE1_TXP<6>_XF" : { "C27_XF.1" : { "C27_XF.2" : { "PCIE1_TXP<6>_XF" : { "J2_P1_XF.B15" : {} } } }, "U1_XF.AT9" : {} }, "UNNAMED_4_BYPASSCAPNPOL_I23_B_FL" : { "R21_FL_XF.2" : { "R21_FL_XF.1" : { "DAC_AVCC_LIN_XF" : { "R11_FL_XF.1" : { "R11_FL_XF.2" : { "UNNAMED_3_BYPASSCAPNPOL_I31_B_FL" : { "R12_FL_XF.1" : { "R12_FL_XF.2" : { "UNNAMED_3_LT3071_I32_MARGA_FL" : { "U3_FL_XF.22" : {} } } }, "C66_FL_XF.2" : { "C66_FL_XF.1" : { "GND" : {} } } } } }, "R93_FL_XF.1" : { "R93_FL_XF.2" : { "UNNAMED_12_BYPASSCAPNPOL_I23_B_FL" : { "R94_FL_XF.1" : { "R94_FL_XF.2" : { "UNNAMED_12_LT3071_I30_MARGA_FL" : { "U10_FL_XF.22" : {} } } }, "C94_FL_XF.2" : { "C94_FL_XF.1" : { "GND" : {} } } } } }, "U1_SP_XF.57" : {} } } }, "R22_FL_XF.1" : { "R22_FL_XF.2" : { "UNNAMED_4_LT3071_I30_MARGA_FL" : { "U6_FL_XF.22" : {} } } }, "C5_FL_XF.2" : { "C5_FL_XF.1" : { "GND" : {} } } }, "UNNAMED_17_RESISTOR_I202_A_XF" : { "R23_XF.1" : { "R23_XF.2" : { "UNNAMED_17_RESISTOR_I199_A_XF" : { "R26_XF.1" : { "R26_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I198_B_XF" : { "C315_XF.2" : { "C315_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I198_A_XF" : { "U1_XF.BW39" : {}, "R25_XF.2" : { "R25_XF.1" : { "UNNAMED_17_RESISTOR_I196_A_XF" : { "R17_XF.2" : { "R17_XF.1" : { "UNNAMED_17_RESISTOR_I201_A_XF" : { "R10_XF.2" : { "R10_XF.1" : { "GND" : {} } } } } }, "R14_XF.2" : { "R14_XF.1" : { "IMON_VCCAUX_LIN_XF" : { "IMON_VCCAUX_TP_FL_XF.1" : {}, "R90_FL_XF.1" : { "R90_FL_XF.2" : { "UNNAMED_9_LT3071_I30_IMON_FL" : { "U7_FL_XF.21" : {}, "IMON_VCCAUX_A_TP_FL_XF.1" : {} } } }, "R113_FL_XF.1" : { "R113_FL_XF.2" : { "UNNAMED_9_LT3071_I66_IMON_FL" : { "IMON_VCCAUX_B_TP_FL_XF.1" : {}, "U11_FL_XF.21" : {} } } } } } } } } } } } }, "U1_XF.BW40" : {} } } }, "R21_XF.2" : { "R21_XF.1" : { "GND" : {} } } } } }, "R13_XF.2" : { "R13_XF.1" : { "GND" : {} } } }, "UNNAMED_21_RESISTOR_I39_B_XF" : { "U1_XF.BV49" : {}, "R32_XF.2" : { "R32_XF.1" : { "GND" : {} } } }, "C0_DDR4_DQ<34>_XF" : { "J1_XF.104" : {}, "U1_XF.BK22" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I216_A_XF" : { "R68_XF.1" : { "R68_XF.2" : { "UNNAMED_17_RESISTOR_I214_B_XF" : { "R39_XF.1" : { "R39_XF.2" : { "VMON_AVCC_RUC_LIN_XF" : { "R102_FL_XF.2" : { "R102_FL_XF.1" : { "VS_AVCC_RUC_LIN_FL" : { "U10_FL_XF.19" : {}, "NS1_FL_XF.2" : { "NS1_FL_XF.1" : { "PWR_AVCC_RUC_XF" : {} } } } } } } } }, "R62_XF.1" : { "R62_XF.2" : { "GND" : {} } } } } }, "C316_XF.1" : { "C316_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I216_B_XF" : { "R69_XF.1" : { "R69_XF.2" : { "UNNAMED_17_RESISTOR_I215_B_XF" : { "R63_XF.1" : { "R63_XF.2" : { "GND" : {} } }, "R70_XF.1" : { "R70_XF.2" : { "GND" : {} } } } } }, "U1_XF.CB40" : {} } } }, "U1_XF.CA40" : {} }, "AC_E1S2_PET_P<7>_XF" : { "C148_XF.1" : { "C148_XF.2" : { "E1S2_PET_P<7>_XF" : { "J1_E2_XF.B40" : {} } } }, "U1_XF.Y9" : {} }, "DIMM_VTT_3VFLT_ND" : { "FB6_ND_XF.2" : { "FB6_ND_XF.1" : { "P3R3V" : {} } }, "R66_ND_XF.2" : { "R66_ND_XF.1" : { "UNNAMED_4_RESISTOR_I17_A_ND" : { "U2_ND_XF.7" : {} } } }, "U2_ND_XF.10" : {}, "C43_ND_XF.1" : { "C43_ND_XF.2" : { "GND" : {} } } }, "POK_OD_AVCC_RUC_LIN" : { "R92_FL_XF.2" : { "R92_FL_XF.1" : { "UNNAMED_12_LT3071_I30_PWRGD_FL" : { "U10_FL_XF.2" : {} } } }, "U1_CPLD.R10" : {} }, "UNNAMED_5_CAPACITOR_I148_A_SP" : { "R15_SP_XF.1" : { "R15_SP_XF.2" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } } } } } }, "C1_DDR4_DQ<17>_XF" : { "J2_XF.172" : {}, "U1_XF.BT55" : {} }, "OCL1_PER_P<0>_XF" : { "J1_O1_XF.A3" : {}, "U1_XF.BU6" : {} }, "PCIE0_RXN<0>_XF" : { "J1_P0_XF.A4" : {}, "U1_XF.AV3" : {} }, "C3_DDR4_CS_N<3>_XF" : { "U1_XF.J21" : {}, "J4_XF.237" : {} }, "E1S2_FPGA_REFCLK_N<0>_XF" : { "R189_XF.2" : { "R189_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_XF.W14" : {}, "R199_XF.1" : { "R199_XF.2" : { "GND" : {} } }, "C23_E2_XF.2" : { "C23_E2_XF.1" : { "AC_FPGA_CLK_REF_N<0>_3" : { "U1_E2_XF.23" : {} } } }, "R198_XF.2" : { "R198_XF.1" : { "E1S2_FPGA_REFCLK_P<0>_XF" : {} } } }, "C3_DDR4_DQ<25>_XF" : { "U1_XF.H22" : {}, "J4_XF.183" : {} }, "C1_DDR4_CS_N<0>_XF" : { "U1_XF.BY52" : {}, "J2_XF.84" : {} }, "UNNAMED_7_LTM4671_I36_COMP3A_SP" : { "PM1_SP_XF.N9" : { "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {} } }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} } } }, "C3_RDIMM_DQS_C<17>_XF" : { "J4_XF.52" : {}, "U1_XF.H19" : {} }, "C2_DDR4_ADR<7>_XF" : { "J3_XF.211" : {}, "U1_XF.M56" : {} }, "UNNAMED_5_LT3071_I30_VIOC_FL" : { "U1_FL_XF.1" : {}, "C29_FL_XF.1" : { "C29_FL_XF.2" : { "GND" : {} } } }, "E1S3_PER_N<0>_XF" : { "U1_XF.AJ5" : {}, "J1_E3_XF.A17" : {} }, "C3_DDR4_ADR<15>_XF" : { "U1_XF.P22" : {}, "J4_XF.86" : {} }, "BOARD_CFG_SW<1>" : { "S1.4" : { "S1.3" : { "BOARD_CFG_SW<2>" : { "U1_XF.BY35" : {}, "U1_CPLD.N3" : {} } }, "S1.5" : { "GND" : {} }, "S1.6" : { "BOARD_CFG_SW<3>" : { "U1_CPLD.M2" : {}, "U1_XF.CB34" : {} } }, "S1.2" : { "GND" : {} }, "S1.1" : { "BOARD_CFG_SW<0>" : { "U1_CPLD.P2" : {}, "U1_XF.CB35" : {} } } }, "U1_CPLD.R1" : {}, "U1_XF.CA36" : {} }, "C0_DDR4_DQ<70>_XF" : { "J1_XF.54" : {}, "U1_XF.BV27" : {} }, "UNNAMED_3_LTM4675_I40_GPIO1F_ND" : { "PM4_ND_XF.F2" : { "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "C2_RDIMM_DQS_C<10>_XF" : { "J3_XF.19" : {}, "U1_XF.N51" : {} }, "VMON_RS_RLC_MGTVCCAUX" : { "R47.2" : { "R47.1" : { "UNNAMED_4_MAX116XXQSOP16_I97_AIN1" : { "U11.6" : {}, "R30.1" : { "R30.2" : { "GND" : {} } }, "C48.1" : { "C48.2" : { "GND" : {} } } } } }, "R85_FL_XF.2" : { "R85_FL_XF.1" : { "PWR_RS_RLC_MGTVCCAUX_XF" : {} } } }, "UNNAMED_4_PI6CB33401_I37_SADRTRI_E3" : { "U1_E3_XF.32" : {}, "R12_E3_XF.2" : { "R12_E3_XF.1" : { "GND" : {} } } }, "FPGA_DCM_LOCK_F" : { "U1_CPLD.H4" : {}, "U1_XF.BV39" : {} }, "CLKIN_N_E1" : { "R15_E1_XF.2" : { "R15_E1_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R17_E1_XF.2" : { "R17_E1_XF.1" : { "CLKIN_P_E1" : {} } }, "R18_E1_XF.1" : { "R18_E1_XF.2" : { "GND" : {} } }, "C17_E1_XF.2" : { "C17_E1_XF.1" : { "E1S_REF_CLK_N<1>" : { "U1.30" : {} } } }, "U1_E1_XF.6" : {} }, "C3_DDR4_DQ<44>_XF" : { "U1_XF.B23" : {}, "J4_XF.106" : {} }, "AC_PCIE1_TXN<2>_XF" : { "C47_XF.1" : { "C47_XF.2" : { "PCIE1_TXN<2>_XF" : { "J1_P1_XF.B16" : {} } } }, "U1_XF.AN10" : {} }, "C1_DDR4_CS_N<1>_XF" : { "U1_XF.CB56" : {}, "J2_XF.89" : {} }, "C0_DDR4_ODT<1>_XF" : { "U1_XF.BY17" : {}, "J1_XF.91" : {} }, "C2_DDR4_ADR<13>_XF" : { "U1_XF.G58" : {}, "J3_XF.232" : {} }, "UNNAMED_22_RESISTOR_I37_B_XF" : { "U1_XF.J27" : {}, "R53_XF.2" : { "R53_XF.1" : { "GND" : {} } } }, "C1_DDR4_ADR<14>_XF" : { "J2_XF.228" : {}, "U1_XF.BY57" : {} }, "C1_DDR4_DQ<23>_XF" : { "J2_XF.177" : {}, "U1_XF.BP57" : {} }, "UNNAMED_6_BYPASSCAPNPOL_I25_B_FL" : { "R42_FL_XF.1" : { "R42_FL_XF.2" : { "UNNAMED_6_LT3071_I30_MARGA_FL" : { "U2_FL_XF.22" : {} } } }, "R36_FL_XF.2" : { "R36_FL_XF.1" : { "DAC_AVTT_LIN_XF" : { "R37_FL_XF.1" : { "R37_FL_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I25_B_FL" : { "C24_FL_XF.2" : { "C24_FL_XF.1" : { "GND" : {} } }, "R43_FL_XF.1" : { "R43_FL_XF.2" : { "UNNAMED_7_LT3071_I30_MARGA_FL" : { "U4_FL_XF.22" : {} } } } } } }, "R29_FL_XF.1" : { "R29_FL_XF.2" : { "UNNAMED_5_BYPASSCAPNPOL_I25_B_FL" : { "R31_FL_XF.1" : { "R31_FL_XF.2" : { "UNNAMED_5_LT3071_I30_MARGA_FL" : { "U1_FL_XF.22" : {} } } }, "C20_FL_XF.2" : { "C20_FL_XF.1" : { "GND" : {} } } } } }, "U1_SP_XF.58" : {}, "R38_FL_XF.1" : { "R38_FL_XF.2" : { "UNNAMED_8_BYPASSCAPNPOL_I25_B_FL" : { "R44_FL_XF.1" : { "R44_FL_XF.2" : { "UNNAMED_8_LT3071_I30_MARGA_FL" : { "U5_FL_XF.22" : {} } } }, "C25_FL_XF.2" : { "C25_FL_XF.1" : { "GND" : {} } } } } } } } }, "C22_FL_XF.2" : { "C22_FL_XF.1" : { "GND" : {} } } }, "BOARD_CFG_SW<0>" : { "S1.1" : { "S1.3" : { "BOARD_CFG_SW<2>" : { "U1_XF.BY35" : {}, "U1_CPLD.N3" : {} } }, "S1.5" : { "GND" : {} }, "S1.2" : { "GND" : {} }, "S1.6" : { "BOARD_CFG_SW<3>" : { "U1_XF.CB34" : {}, "U1_CPLD.M2" : {} } }, "S1.4" : { "BOARD_CFG_SW<1>" : { "U1_XF.CA36" : {}, "U1_CPLD.R1" : {} } } }, "U1_CPLD.P2" : {}, "U1_XF.CB35" : {} }, "VS_AVTT_RLC_LIN_FL" : { "NS3_FL_XF.2" : { "NS3_FL_XF.1" : { "PWR_AVTT_RLC_XF" : {} } }, "U1_FL_XF.19" : {}, "R56_FL_XF.1" : { "R56_FL_XF.2" : { "VMON_AVTT_RLC_LIN_XF" : { "R110_XF.1" : { "R110_XF.2" : { "UNNAMED_17_RESISTOR_I59_A_XF" : { "R80_XF.1" : { "R80_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I57_A_XF" : { "C140_XF.1" : { "C140_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I57_B_XF" : { "U1_XF.CC37" : {}, "R81_XF.2" : { "R81_XF.1" : { "UNNAMED_17_RESISTOR_I60_A_XF" : { "R113_XF.2" : { "R113_XF.1" : { "GND" : {} } }, "R112_XF.2" : { "R112_XF.1" : { "GND" : {} } } } } } } } }, "U1_XF.CC36" : {} } } }, "R111_XF.2" : { "R111_XF.1" : { "GND" : {} } } } } } } } } }, "UNNAMED_17_RESISTOR_I105_B_XF" : { "R136_XF.2" : { "R136_XF.1" : { "UNNAMED_17_RESISTOR_I104_A_XF" : { "R135_XF.1" : { "R135_XF.2" : { "GND" : {} } }, "R128_XF.2" : { "R128_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I107_B_XF" : { "C267_XF.2" : { "C267_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I107_A_XF" : { "R127_XF.1" : { "R127_XF.2" : { "UNNAMED_17_RESISTOR_I101_A_XF" : { "R134_XF.1" : { "R134_XF.2" : { "UNNAMED_17_RESISTOR_I101_B_XF" : { "R120_XF.1" : { "R120_XF.2" : { "GND" : {} } } } } }, "R133_XF.1" : { "R133_XF.2" : { "IMON_AVTT_LIN_XF" : { "R24_FL_XF.2" : { "R24_FL_XF.1" : { "UNNAMED_5_LT3071_I30_IMON_FL" : { "U1_FL_XF.21" : {} } } }, "R25_FL_XF.2" : { "R25_FL_XF.1" : { "UNNAMED_6_LT3071_I30_IMON_FL" : { "U2_FL_XF.21" : {} } } }, "R82_FL_XF.2" : { "R82_FL_XF.1" : { "UNNAMED_8_LT3071_I30_IMON_FL" : { "R26_FL_XF.2" : { "R26_FL_XF.1" : { "GND" : {} } }, "U5_FL_XF.21" : {} } } }, "R64_FL_XF.2" : { "R64_FL_XF.1" : { "UNNAMED_7_LT3071_I30_IMON_FL" : { "U4_FL_XF.21" : {} } } } } } } } } }, "U1_XF.CB33" : {} } } }, "U1_XF.CC33" : {} } } } } } }, "R121_XF.1" : { "R121_XF.2" : { "GND" : {} } } }, "C0_DDR4_DQ<7>_XF" : { "U1_XF.BY23" : {}, "J1_XF.155" : {} }, "JT_FPGA_TDO" : { "U1_CPLD.A12" : {}, "J5.9" : {} }, "OCL_REF_CLK_P<1>" : { "R282_XF.1" : { "R282_XF.2" : { "GND" : {} } }, "U5_XF.5" : {}, "R277_XF.2" : { "R277_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1.45" : {}, "R283_XF.1" : { "R283_XF.2" : { "OCL_REF_CLK_N<1>" : {} } } }, "UNNAMED_6_RESISTOR_I435_B_SP" : { "R84_SP_XF.1" : { "R84_SP_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "PM2_SP_XF.E6" : { "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.F10" : { "UNNAMED_6_RESISTOR_I435_B_SP" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} } }, "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "R79_SP_XF.2" : { "R79_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } }, "C2_DDR4_RESET_N_XF" : { "U1_XF.K55" : {}, "J3_XF.58" : {} }, "C3_DDR4_DQ<62>_XF" : { "J4_XF.135" : {}, "U1_XF.A15" : {} }, "C2_DDR4_DQ<71>_XF" : { "U1_XF.B58" : {}, "J3_XF.199" : {} }, "UNNAMED_4_BYPASSCAPNPOL_I101_B" : { "R71.2" : { "R71.1" : { "GND" : {} } }, "U11.3" : {}, "R70.2" : { "R70.1" : { "VMON_SP_9" : { "ADC_SPARE.1" : {} } } }, "C52.2" : { "C52.1" : { "GND" : {} } } }, "LTC2975_AUXFAULT_F" : { "U1_CPLD.R14" : {}, "U1_SP_XF.7" : {} }, "MGTRREF_RS_XF" : { "U1_XF.BV12" : {}, "R270_XF.1" : { "R270_XF.2" : { "PWR_AVTT_RS_XF" : {} } } }, "UNNAMED_10_LTM4650FIXED_I151_MODEPLLIN_SP" : { "R27_SP_XF.2" : { "R27_SP_XF.1" : { "INTVCC_4650_BL_SP" : { "C80_SP_XF.1" : { "C80_SP_XF.2" : { "GND" : {} } }, "R7_SP_XF.1" : { "R7_SP_XF.2" : { "PHASMD_4650_BL_SP" : { "R24_SP_XF.2" : { "R24_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "PM3_SP_XF.G4" : { "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "PM4_SP_XF.E6" : { "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H8" : { "INTVCC_4650_BL_SP" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.E8" : { "INTVCC_4650_BL_SP" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G3" : { "GND" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.F4" : { "UNNAMED_10_LTM4650FIXED_I151_MODEPLLIN_SP" : {} }, "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.G1" : { "GND" : {} } } } } } } } }, "R28_SP_XF.2" : { "R28_SP_XF.1" : { "SGND_PM3_SP" : {} } } }, "AC_PCIE_X1_REFN_XF" : { "C289_XF.2" : { "C289_XF.1" : { "PCIE_X1_REFN_XF" : { "J1_PX1_XF.A14" : {} } } }, "U1_XF.BG14" : {} }, "AC_PCIE0_TXN<1>_XF" : { "U1_XF.AV8" : {}, "C85_XF.1" : { "C85_XF.2" : { "PCIE0_TXN<1>_XF" : { "J1_P0_XF.B7" : {} } } } }, "PCIE_X1_CLKREQ_XF" : { "J1_PX1_XF.B12" : {}, "R285_XF.2" : { "R285_XF.1" : { "P3R3V" : {} } }, "U1_XF.BF17" : {} }, "C2_DDR4_ODT<0>_XF" : { "U1_XF.H58" : {}, "J3_XF.87" : {} }, "UNNAMED_7_LTM4671_I87_TRACKSS0_SP" : { "C104_SP_XF.2" : { "C104_SP_XF.1" : { "PM1_SP_AGND_SP" : {} } }, "PM1_SP_XF.F9" : { "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {} } }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, 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"PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} } } }, "C3_DDR4_DQ<32>_XF" : { "U1_XF.A26" : {}, "J4_XF.97" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I198_A_XF" : { "R25_XF.2" : { "R25_XF.1" : { "UNNAMED_17_RESISTOR_I196_A_XF" : { "R17_XF.2" : { "R17_XF.1" : { "UNNAMED_17_RESISTOR_I201_A_XF" : { "R10_XF.2" : { "R10_XF.1" : { "GND" : {} } } } } }, "R14_XF.2" : { "R14_XF.1" : { "IMON_VCCAUX_LIN_XF" : { "R90_FL_XF.1" : { "R90_FL_XF.2" : { "UNNAMED_9_LT3071_I30_IMON_FL" : { "U7_FL_XF.21" : {}, "IMON_VCCAUX_A_TP_FL_XF.1" : {} } } }, "IMON_VCCAUX_TP_FL_XF.1" : {}, "R113_FL_XF.1" : { "R113_FL_XF.2" : { "UNNAMED_9_LT3071_I66_IMON_FL" : { "U11_FL_XF.21" : {}, "IMON_VCCAUX_B_TP_FL_XF.1" : {} } } } } } } } } }, "U1_XF.BW39" : {}, "C315_XF.1" : { "C315_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I198_B_XF" : { "R26_XF.2" : { "R26_XF.1" : { "UNNAMED_17_RESISTOR_I199_A_XF" : { "R21_XF.2" : { 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"PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} } } } } }, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} } } }, "E1S1_PER_N<1>_XF" : { "U1_XF.N5" : {}, "J1_E1_XF.A20" : {} }, "UNNAMED_22_RESISTOR_I43_B_XF" : { "R58_XF.2" : { "R58_XF.1" : { "GND" : {} } }, "U1_XF.BT21" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I50_B_XF" : { "U1_XF.CB39" : {}, "R79_XF.2" : { "R79_XF.1" : { "UNNAMED_17_RESISTOR_I56_A_XF" : { "R67_XF.2" : { "R67_XF.1" : { "GND" : {} } }, "R104_XF.2" : { "R104_XF.1" : { "GND" : {} } } } } }, "C139_XF.2" : { "C139_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I50_A_XF" : { "R78_XF.2" : { "R78_XF.1" : { "UNNAMED_17_RESISTOR_I55_A_XF" : { "R102_XF.2" : { "R102_XF.1" : { "VMON_AVCC_SW_XF" : { "R100_SP_XF.2" : { "R100_SP_XF.1" : { "PWR_AVCC_SW_XF" : {} } } } } }, "R103_XF.2" : { "R103_XF.1" : { "GND" : {} } } } } }, "U1_XF.CB38" : {} } } } }, "PCIE1_RXN<2>_XF" : { "U1_XF.AP3" : {}, "J1_P1_XF.A16" : {} }, "VDDO1" : { "FB2.2" : { "FB2.1" : { "CPLD_P1R8V_1" : {} } }, "U1.26" : {}, "C17.1" : { "C17.2" : { "GND" : {} } } }, "UNNAMED_9_LT3071_I30_VIOC_FL" : { "U7_FL_XF.1" : {}, "C72_FL_XF.1" : { "C72_FL_XF.2" : { "GND" : {} } } }, "UNNAMED_21_RESISTOR_I40_B_XF" : { "U1_XF.BW51" : {}, "R31_XF.2" : { "R31_XF.1" : { "GND" : {} } } }, "FAN_PWM_OD" : { "R55.1" : { "R55.2" : { "UNNAMED_20_NMOSFETVMT3_I16_G" : { "Q8.1" : { "Q8.2" : { "GND" : {} }, "Q8.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I25_P4" : { "P3.4" : {} } } } } } }, "U1_CPLD.J12" : {}, "R56.1" : { "R56.2" : { "UNNAMED_20_NMOSFETVMT3_I8_G" : { "Q9.1" : { "Q9.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I27_P4" : { "P5.4" : {} } }, "Q9.2" : { "GND" : {} } } } } }, "R39.1" : { "R39.2" : { "UNNAMED_20_NMOSFETVMT3_I20_G" : { "Q6.1" : { "Q6.2" : { "GND" : {} }, "Q6.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I30_P4" : { "P2.4" : {} } } } } } }, "R42.1" : { "R42.2" : { "UNNAMED_20_NMOSFETVMT3_I12_G" : { "Q7.1" : { "Q7.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I26_P4" : { "P4.4" : {} } }, "Q7.2" : { "GND" : {} } } } } } }, "C1_RDIMM_DQS_C<3>_XF" : { "U1_XF.CA61" : {}, "J2_XF.185" : {} }, "OCL3_PER_P<1>_XF" : { "J1_O3_XF.A6" : {}, "U1_XF.BJ2" : {} }, "AC_PCIE0_TXN<0>_XF" : { "U1_XF.AU10" : {}, "C86_XF.1" : { "C86_XF.2" : { "PCIE0_TXN<0>_XF" : { "J1_P0_XF.B4" : {} } } } }, "E1S2_FPGA_REFCLK_P<0>_XF" : { "R198_XF.1" : { "R198_XF.2" : { "E1S2_FPGA_REFCLK_N<0>_XF" : {} } }, "C19_E2_XF.2" : { "C19_E2_XF.1" : { "AC_FPGA_CLK_REF_P<0>_3" : { "U1_E2_XF.22" : {} } } }, "U1_XF.W15" : {}, "R188_XF.2" : { "R188_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R197_XF.1" : { "R197_XF.2" : { "GND" : {} } } }, "UNNAMED_4_LT3071_I30_PWRGD_FL" : { "U6_FL_XF.2" : {}, "R2_FL_XF.1" : { "R2_FL_XF.2" : { "POK_OD_AVCC_RN_LIN" : { "U1_CPLD.P10" : {} } } } }, "AC_CONN_CLK_REFN<1>_3" : { "C24_E2_XF.1" : { "C24_E2_XF.2" : { "CONN_CLK_REFN<1>_E2" : { "J1_E2_XF.A14" : {} } } }, "U1_E2_XF.18" : {} }, "UNNAMED_6_LTM4671_I457_TRACKSS1_SP" : { "PM2_SP_XF.G7" : { "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : {} } } } }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} } } }, "UNNAMED_6_LT3071_I30_V00_FL" : { "U2_FL_XF.23" : {}, "R52_FL_XF.1" : { "R52_FL_XF.2" : { "P3R3V" : {} } }, "R14_FL_XF.2" : { "R14_FL_XF.1" : { "GND" : {} } } }, "UNNAMED_6_RESISTOR_I222_A_SP" : { "R109_SP_XF.1" : { "R109_SP_XF.2" : { "UNNAMED_6_LTM4671_I456_FB3_SP" : { "R8_SP_XF.2" : { "R8_SP_XF.1" : { "UNNAMED_6_RESISTOR_I409_A_SP" : { "R41_SP_XF.2" : { "R41_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "PM2_SP_XF.N10" : { "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : {} } }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} } } } } } }, "C1_DDR4_ADR<17>_XF" : { "J2_XF.234" : {} }, "E1S0_PET_P<0>_XF" : { "C109_XF.2" : { "C109_XF.1" : { "AC_E1S0_PET_P<0>_XF" : { "U1_XF.C7" : {} } } }, "J1_E0_XF.B18" : {} }, "E1S1_3R3V_PERST_CLKREQ_F<1>_XF" : { "U1_XF.AE18" : {}, "R7_E1_XF.2" : { "R7_E1_XF.1" : { "P3R3V" : {} } }, "J1_E1_XF.A11" : {} }, "SDIMM_I2C_ASEL_RESISTOR_XF" : { "PM4_SD_XF.G2" : { "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } }, "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "DN2_DP<3>_SP" : { "PM2_SP_XF.W6" : { "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : { "U11.12" : {}, "R74.2" : { "R74.1" : { "GND" : {} } }, "C33.2" : { "C33.1" : { "GND" : {} } } } } } } }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.E6" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } } } }, "C2_DDR4_DQ<51>_XF" : { "J3_XF.271" : {}, "U1_XF.H47" : {} }, "UNNAMED_9_LT3071_I30_SENSE_FL" : { "NS7_FL_XF.2" : { "NS7_FL_XF.1" : { "PWR_VCCAUX_A_FL" : {} } }, "U7_FL_XF.19" : {} }, "C3_DDR4_VREFCA_1_XF" : { "C228_XF.1" : { "C228_XF.2" : { "GND" : {} } }, "C229_XF.1" : { "C229_XF.2" : { "GND" : {} } }, "R261_XF.1" : { "R261_XF.2" : { "GND" : {} } }, "J4_XF.146" : {}, "R260_XF.1" : { "R260_XF.2" : { "PWR_NDIMM_VDD_XF" : {} } } }, "C0_RDIMM_DQS_C<13>_XF" : { "J1_XF.100" : {}, "U1_XF.BN24" : {} }, "C2_RDIMM_DQS_T<12>_XF" : { "J3_XF.40" : {}, "U1_XF.K53" : {} }, "E1S1_3R3V_DUALPORTEN_F_XF" : { "J1_E1_XF.B9" : {}, "U1_XF.AH19" : {} }, "C2_DDR4_DQ<46>_XF" : { "U1_XF.C54" : {}, "J3_XF.113" : {} }, "VMON_CPLD_P3R3V_SW" : { "R14_MP.2" : { "R14_MP.1" : { "CPLD_P3R3V" : {} } }, "R68.1" : { "R68.2" : { "UNNAMED_4_BYPASSCAPNPOL_I103_B" : { "R21.2" : { "R21.1" : { "GND" : {} } }, "U11.2" : {}, "C51.2" : { "C51.1" : { "GND" : {} } } } } } }, "UNNAMED_20_MLXKK1004PINBOSS_I27_P4" : { "Q9.3" : { "Q9.1" : { "UNNAMED_20_NMOSFETVMT3_I8_G" : { "R56.2" : { "R56.1" : { "FAN_PWM_OD" : { "U1_CPLD.J12" : {}, "R55.1" : { "R55.2" : { "UNNAMED_20_NMOSFETVMT3_I16_G" : { "Q8.1" : { "Q8.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I25_P4" : { "P3.4" : {} } }, "Q8.2" : { "GND" : {} } } } } }, "R39.1" : { "R39.2" : { "UNNAMED_20_NMOSFETVMT3_I20_G" : { "Q6.1" : { "Q6.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I30_P4" : { "P2.4" : {} } }, "Q6.2" : { "GND" : {} } } } } }, "R42.1" : { "R42.2" : { "UNNAMED_20_NMOSFETVMT3_I12_G" : { "Q7.1" : { "Q7.2" : { "GND" : {} }, "Q7.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I26_P4" : { "P4.4" : {} } } } } } } } } } } }, "Q9.2" : { "GND" : {} } }, "P5.4" : {} }, "UNNAMED_18_RESISTOR_I52_A_XF" : { "U1_XF.AT17" : {}, "R140_XF.1" : { "R140_XF.2" : { "GND" : {} } } }, "C0_DDR4_DQ<5>_XF" : { "J1_XF.148" : {}, "U1_XF.CC24" : {} }, "C0_DDR4_CKE<0>_XF" : { "J1_XF.60" : {}, "U1_XF.BU21" : {} }, "C2_DDR4_DQ<63>_XF" : { "J3_XF.280" : {}, "U1_XF.N48" : {} }, "XTAL_SHLD" : { "X1.2" : { "X1.3" : { "SI5341_XTAL_B" : { "TP19.1" : {}, "U1.9" : {} } }, "X1.1" : { "SI5341_XTAL_A" : { "U1.8" : {}, "XA.1" : {} } } }, "U1.7" : {}, "X1.4" : {}, "U1.10" : {} }, "C0_SYS_CLK_N_XF" : { "C361_XF.2" : { "C361_XF.1" : { "DDR4_SYS_CLK_N<0>_XF" : { "U6_XF.15" : {} } } }, "R237_XF.1" : { "R237_XF.2" : { "GND" : {} } }, "R235_XF.2" : { "R235_XF.1" : { "PWR_SDIMM_VDD_XF" : {} } }, "U1_XF.BY19" : {}, "R238_XF.2" : { "R238_XF.1" : { "C0_SYS_CLK_P_XF" : {} } } }, "UNNAMED_17_BYPASSCAPNPOL_I48_B_XF" : { "C138_XF.2" : { "C138_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I48_A_XF" : { "U1_XF.AM25" : {}, "R76_XF.2" : { "R76_XF.1" : { "UNNAMED_17_RESISTOR_I51_A_XF" : { "R2_XF.2" : { "R2_XF.1" : { "GND" : {} } }, "R1_XF.2" : { "R1_XF.1" : { "VMON_AVCC_RN_LIN_XF" : { "R84_FL_XF.2" : { "R84_FL_XF.1" : { "VS_AVCC_RN_LIN_FL" : { "U6_FL_XF.19" : {}, "NS4_FL_XF.2" : { "NS4_FL_XF.1" : { "PWR_AVCC_RN_XF" : {} } } } } } } } } } } } } } }, "R77_XF.2" : { "R77_XF.1" : { "UNNAMED_17_RESISTOR_I52_A_XF" : { "R3_XF.2" : { "R3_XF.1" : { "GND" : {} } }, "R4_XF.2" : { "R4_XF.1" : { "GND" : {} } } } } }, "U1_XF.AN24" : {} }, "C0_DDR4_DQ<42>_XF" : { "U1_XF.BN28" : {}, "J1_XF.115" : {} }, "UNNAMED_3_RESISTOR_I59_A" : { "R53.1" : { "R53.2" : { "FP_FAULT_LED_N<2>" : { "U1_CPLD.H16" : {} } } }, "FPNL_CONN.10" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I58_B_XF" : { "U1_XF.BW36" : {}, "C146_XF.2" : { "C146_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I58_A_XF" : { "U1_XF.BV36" : {}, "R97_XF.2" : { "R97_XF.1" : { "UNNAMED_17_RESISTOR_I61_A_XF" : { "R107_XF.2" : { "R107_XF.1" : { "GND" : {} } }, "R106_XF.2" : { "R106_XF.1" : { "VMON_AVTT_RUC_LIN_XF" : { "R57_FL_XF.2" : { "R57_FL_XF.1" : { "VS_AVTT_RUC_LIN_FL" : { "U5_FL_XF.19" : {}, "NS9_FL_XF.2" : { "NS9_FL_XF.1" : { "PWR_AVTT_RUC_XF" : {} } } } } } } } } } } } } } }, "R98_XF.2" : { "R98_XF.1" : { "UNNAMED_17_RESISTOR_I95_B_XF" : { "R109_XF.2" : { "R109_XF.1" : { "GND" : {} } }, "R108_XF.2" : { "R108_XF.1" : { "GND" : {} } } } } } }, "C2_DDR4_DQ<33>_XF" : { "J3_XF.242" : {}, "U1_XF.A56" : {} }, "UNNAMED_12_EMC1428_I42_TRIPSET_SP" : { "R125_SP_XF.2" : { "R125_SP_XF.1" : { "GND" : {} } }, "U4_SP_XF.5" : {} }, "AC_E1S2_PET_P<5>_XF" : { "U1_XF.AB9" : {}, "C150_XF.1" : { "C150_XF.2" : { "E1S2_PET_P<5>_XF" : { "J1_E2_XF.B34" : {} } } } }, "PCIE0_RXP<0>_XF" : { "U1_XF.AV4" : {}, "J1_P0_XF.A3" : {} }, "E1S3_FPGA_REFCLK_N<0>_XF" : { "R204_XF.2" : { "R204_XF.1" : { "E1S3_FPGA_REFCLK_P<0>_XF" : {} } }, "C23_E3_XF.2" : { "C23_E3_XF.1" : { "AC_FPGA_CLK_REF_N<0>_2" : { "U1_E3_XF.23" : {} } } }, "R205_XF.1" : { "R205_XF.2" : { "GND" : {} } }, "R193_XF.2" : { "R193_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_XF.AG14" : {} }, "E1S1_PET_N<4>_XF" : { "C133_XF.2" : { "C133_XF.1" : { "AC_E1S1_PET_N<4>_XF" : { "U1_XF.U6" : {} } } }, "J1_E1_XF.B30" : {} }, "E1S2_PER_N<0>_XF" : { "J1_E2_XF.A17" : {}, "U1_XF.AA5" : {} }, "DP2_DN<3>_SP" : { "PM2_SP_XF.W7" : { "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : { "U11.12" : {}, "R74.2" : { "R74.1" : { "GND" : {} } }, "C33.2" : { "C33.1" : { "GND" : {} } } } } } } }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.E6" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} } } }, "C1_RDIMM_DQS_C<7>_XF" : { "J2_XF.277" : {}, "U1_XF.BK55" : {} }, "C0_DDR4_BA<1>_XF" : { "U1_XF.CA15" : {}, "J1_XF.224" : {} }, "C2_RDIMM_DQS_C<14>_XF" : { "J3_XF.111" : {}, "U1_XF.E53" : {} }, "C3_DDR4_DQ<10>_XF" : { "J4_XF.23" : {}, "U1_XF.J26" : {} }, "C1_RDIMM_DQS_T<16>_XF" : { "J2_XF.132" : {}, "U1_XF.BM53" : {} }, "C1_DDR4_DQ<59>_XF" : { "J2_XF.282" : {}, "U1_XF.BN54" : {} }, "DDR4_REF_CLK_P" : { "U6_XF.6" : {}, "U1.24" : {}, "R8_XF.1" : { "R8_XF.2" : { "DDR4_REF_CLK_N" : {} } } }, "ENB3V_SEQ_J_CPLD" : { "R8_CPLD.1" : { "R8_CPLD.2" : { "GND" : {} } }, "U1_CPLD.L15" : {} }, "C2_RDIMM_DQS_C<2>_XF" : { "U1_XF.F63" : {}, "J3_XF.174" : {} }, "FPGA_CFG_DONE_1" : { "R38_XF.2" : { "R38_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_CPLD.H1" : {}, "U1_XF.AL18" : {} }, "E1S1_PET_N<0>_XF" : { "J1_E1_XF.B17" : {}, "C137_XF.2" : { "C137_XF.1" : { "AC_E1S1_PET_N<0>_XF" : { "U1_XF.P8" : {} } } } }, "PCIE0_TXP<4>_XF" : { "C37_XF.2" : { "C37_XF.1" : { "AC_PCIE0_TXP<4>_XF" : { "U1_XF.AY9" : {} } } }, "J2_P0_XF.B3" : {} }, "AC_E1S2_PET_P<1>_XF" : { "C154_XF.1" : { "C154_XF.2" : { "E1S2_PET_P<1>_XF" : { "J1_E2_XF.B21" : {} } } }, "U1_XF.W7" : {} }, "C3_DDR4_DQ<49>_XF" : { "J4_XF.264" : {}, "U1_XF.D20" : {} }, "AC_PCIE0_TXP<4>_XF" : { "C37_XF.1" : { "C37_XF.2" : { "PCIE0_TXP<4>_XF" : { "J2_P0_XF.B3" : {} } } }, "U1_XF.AY9" : {} }, "UNNAMED_4_BYPASSCAPNPOL_I99_B" : { "U11.4" : {}, "R72.2" : { "R72.1" : { "TS_LTM4671_CMN<1>" : { "PM1_SP_XF.K8" : { "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} } } } } } } }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} } } } } } }, "E1S2_PER_N<4>_XF" : { "J1_E2_XF.A30" : {}, "U1_XF.AD3" : {} }, "DIMM_VTT_3VFLT_SD" : { "R66_SD_XF.2" : { "R66_SD_XF.1" : { "UNNAMED_4_RESISTOR_I17_A_SD" : { "U2_SD_XF.7" : {} } } }, "FB6_SD_XF.2" : { "FB6_SD_XF.1" : { "P3R3V" : {} } }, "U2_SD_XF.10" : {}, "C43_SD_XF.1" : { "C43_SD_XF.2" : { "GND" : {} } } }, "C3_DDR4_DQ<37>_XF" : { "U1_XF.B25" : {}, "J4_XF.240" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I152_A_SP" : { "R34_SP_XF.1" : { "R34_SP_XF.2" : { "VS_AVCC_LIN_P_XF" : { "U3_FL_XF.19" : {}, "NS2_FL_XF.2" : { "NS2_FL_XF.1" : { "PWR_AVCC_RS_RLC_XF" : {} } } } } }, "U1_SP_XF.61" : {}, "C17_SP_XF.1" : { "C17_SP_XF.2" : { "GND" : {} } } }, "OCL3_PET_P<0>_XF" : { "J1_O3_XF.B3" : {}, "C257_XF.2" : { "C257_XF.1" : { "AC_OCL3_PET_P<0>_XF" : { "U1_XF.BJ11" : {} } } } }, "C3_RDIMM_DQS_T<13>_XF" : { "J4_XF.99" : {}, "U1_XF.C28" : {} }, "PWR_AVTT_RN_XF" : { "U1_XF.F11" : {}, "R269_XF.2" : { "R269_XF.1" : { "MGTRREF_RN_XF" : { "U1_XF.R14" : {} } } }, "U4_FL_XF.17" : {}, "U1_XF.D11" : {}, "U1_XF.G9" : {}, "U1_XF.T11" : {}, "U1_XF.L9" : {}, "U1_XF.R9" : {}, "C33_FL_XF.1" : { "C33_FL_XF.2" : { "GND" : {} } }, "U1_XF.J9" : {}, "C332_XF.1" : { "C332_XF.2" : { "GND" : {} } }, "C331_XF.1" : { "C331_XF.2" : { "GND" : {} } }, "U1_XF.R15" : {}, "U1_XF.N9" : {}, "U1_XF.K11" : {}, "U1_XF.M11" : {}, "C196_XF.1" : { "C196_XF.2" : { "GND" : {} } }, "NS8_FL_XF.1" : { "NS8_FL_XF.2" : { "VS_AVTT_LIN_P_XF" : {} } }, "C195_XF.1" : { "C195_XF.2" : { "GND" : {} } }, "U1_XF.E9" : {}, "U1_XF.P11" : {}, "U4_FL_XF.16" : {}, "C329_XF.1" : { "C329_XF.2" : { "GND" : {} } }, "U4_FL_XF.15" : {}, "U1_XF.H11" : {}, "C330_XF.1" : { "C330_XF.2" : { "GND" : {} } }, "C63_FL_XF.1" : { "C63_FL_XF.2" : { "GND" : {} } }, "C57_FL_XF.1" : { "C57_FL_XF.2" : { "GND" : {} } }, "C60_FL_XF.1" : { "C60_FL_XF.2" : { "GND" : {} } }, "U4_FL_XF.18" : {}, "U1_XF.C9" : {} }, "E1S1_3R3V_SMB_RST_F_XF" : { "R5_E1_XF.2" : { "R5_E1_XF.1" : { "P3R3V" : {} } }, "U1_XF.AH18" : {}, "J1_E1_XF.A9" : {} }, "MFG_E3" : { "J1_E3_XF.B7" : {} }, "C3_DDR4_DQ<67>_XF" : { "U1_XF.G19" : {}, "J4_XF.201" : {} }, "C1_DDR4_SA<0>_XF" : { "J2_XF.139" : {}, "R22_XF.2" : { "R22_XF.1" : { "GND" : {} } } }, "BP_TYPE_P1" : { "J1_P1_XF.B9" : {} }, "C1_DDR4_CK_C<0>_XF" : { "J2_XF.75" : {}, "U1_XF.CC49" : {} }, "SDIMM_VTT_BNC_XF" : { "R105_XF.2" : { "R105_XF.1" : { "PWR_SDIMM_VTT_XF" : {} } }, "J12_XF.C" : {} }, "UNNAMED_4_MAX116XXQSOP16_I97_AIN4" : { "U11.9" : {}, "R94.1" : { "R94.2" : { "VMON_SDIMM_VTT_LIN" : { "R4_SD_XF.2" : { "R4_SD_XF.1" : { "VS_DIMM_VTT_LIN_SD" : { "U2_SD_XF.5" : {}, "NS3_SD_XF.2" : { "NS3_SD_XF.1" : { "PWR_SDIMM_VTT_XF" : {} } } } } } } } }, "C45.1" : { "C45.2" : { "GND" : {} } } }, "E1S0_PET_P<4>_XF" : { "C105_XF.2" : { "C105_XF.1" : { "AC_E1S0_PET_P<4>_XF" : { "U1_XF.F9" : {} } } }, "J1_E0_XF.B31" : {} }, "CPLD_FPGA_SSTAT_CLK" : { "U1_XF.BW34" : {}, "U1_CPLD.K6" : {} }, "AC_E1S3_PET_N<2>_XF" : { "U1_XF.AG10" : {}, "C312_XF.1" : { "C312_XF.2" : { "E1S3_PET_N<2>_XF" : { "J1_E3_XF.B23" : {} } } } }, "UNNAMED_20_MLXKK1004PINBOSS_I30_P4" : { "P2.4" : {}, "Q6.3" : { "Q6.1" : { "UNNAMED_20_NMOSFETVMT3_I20_G" : { "R39.2" : { "R39.1" : { "FAN_PWM_OD" : { "R42.1" : { "R42.2" : { "UNNAMED_20_NMOSFETVMT3_I12_G" : { "Q7.1" : { "Q7.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I26_P4" : { "P4.4" : {} } }, "Q7.2" : { "GND" : {} } } } } }, "R56.1" : { "R56.2" : { "UNNAMED_20_NMOSFETVMT3_I8_G" : { "Q9.1" : { "Q9.2" : { "GND" : {} }, "Q9.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I27_P4" : { "P5.4" : {} } } } } } }, "U1_CPLD.J12" : {}, "R55.1" : { "R55.2" : { "UNNAMED_20_NMOSFETVMT3_I16_G" : { "Q8.1" : { "Q8.2" : { "GND" : {} }, "Q8.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I25_P4" : { "P3.4" : {} } } } } } } } } } } }, "Q6.2" : { "GND" : {} } } }, "UNNAMED_21_RESISTOR_I30_B_XF" : { "U1_XF.BK49" : {}, "R27_XF.2" : { "R27_XF.1" : { "GND" : {} } } }, "C2_DDR4_DQ<20>_XF" : { "U1_XF.G61" : {}, "J3_XF.25" : {} }, "POK_OD_VCCAUX_B_LIN" : { "U1_CPLD.N9" : {}, "R104_FL_XF.2" : { "R104_FL_XF.1" : { "UNNAMED_9_LT3071_I66_PWRGD_FL" : { "U11_FL_XF.2" : {} } } } }, "OCL2_FPGA_REFCLK_P_XF" : { "C358_XF.2" : { "C358_XF.1" : { "AC_OCL2_FPGA_REFCLK_P_XF" : { "U5_XF.22" : {} } } }, "R214_XF.2" : { "R214_XF.1" : { "P3R3V" : {} } }, "R225_XF.1" : { "R225_XF.2" : { "OCL2_FPGA_REFCLK_N_XF" : {} } }, "U1_XF.BL15" : {}, "R224_XF.1" : { "R224_XF.2" : { "GND" : {} } } }, "AC_OCL0_PET_P<1>_XF" : { "U1_XF.CC7" : {}, "C179_XF.1" : { "C179_XF.2" : { "OCL0_PET_P<1>_XF" : { "J1_O0_XF.B6" : {} } } } }, "PCIE1_TXN<3>_XF" : { "C46_XF.2" : { "C46_XF.1" : { "AC_PCIE1_TXN<3>_XF" : { "U1_XF.AP8" : {} } } }, "J1_P1_XF.B19" : {} }, "UNNAMED_21_RESISTOR_I26_B_XF" : { "R44_XF.2" : { "R44_XF.1" : { "GND" : {} } }, "U1_XF.D60" : {} }, "PRSNT_F_P1" : { "J1_P1_XF.A13" : {}, "J2_P1_XF.A13" : {} }, "C1_DDR4_DQ<6>_XF" : { "U1_XF.BL50" : {}, "J2_XF.10" : {} }, "C1_RDIMM_DQS_T<11>_XF" : { "U1_XF.BP55" : {}, "J2_XF.29" : {} }, "E1S1_3R3V_PRSNT_F<1>_XF" : { "U1_XF.AE19" : {}, "J1_E1_XF.B42" : {} }, "AC_OCL1_PET_N<2>_XF" : { "U1_XF.BW10" : {}, "C271_XF.1" : { "C271_XF.2" : { "OCL1_PET_N<2>_XF" : { "J1_O1_XF.B16" : {} } } } }, "POK_OD_SPARE_SW_XF" : { "PM1_SP_XF.R7" : { "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} } } } } }, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} } } }, "TSE2002_EVENT_OD_F" : { "U12.7" : {}, "U1_CPLD.T6" : {} }, "C1_RDIMM_DQS_C<9>_XF" : { "J2_XF.8" : {}, "U1_XF.BP51" : {} }, "E1S2_PET_N<1>_XF" : { "J1_E2_XF.B20" : {}, "C172_XF.2" : { "C172_XF.1" : { "AC_E1S2_PET_N<1>_XF" : { "U1_XF.W6" : {} } } } }, "C2_RDIMM_DQS_C<4>_XF" : { "J3_XF.244" : {}, "U1_XF.E57" : {} }, "C0_DDR4_DQ<47>_XF" : { "U1_XF.BM25" : {}, "J1_XF.258" : {} }, "UNNAMED_22_RESISTOR_I46_B_XF" : { "R59_XF.2" : { "R59_XF.1" : { "GND" : {} } }, "U1_XF.CA17" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I46_B_XF" : { "C147_XF.2" : { "C147_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I46_A_XF" : { "U1_XF.BY33" : {}, "R99_XF.1" : { "R99_XF.2" : { "UNNAMED_17_RESISTOR_I40_A_XF" : { "R93_XF.1" : { "R93_XF.2" : { "VMON_AVTT_RS_LIN_XF" : { "R137_XF.2" : { "R137_XF.1" : { "UNNAMED_17_RESISTOR_I110_A_XF" : { "R138_XF.1" : { "R138_XF.2" : { "GND" : {} } }, "R129_XF.2" : { "R129_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I116_A_XF" : { "C268_XF.1" : { "C268_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I116_B_XF" : { "R130_XF.1" : { "R130_XF.2" : { "UNNAMED_17_RESISTOR_I113_A_XF" : { "R139_XF.1" : { "R139_XF.2" : { "GND" : {} } }, "R141_XF.1" : { "R141_XF.2" : { "GND" : {} } } } } }, "U1_XF.BW32" : {} } } }, "U1_XF.BW31" : {} } } } } } }, "R4_FL_XF.2" : { "R4_FL_XF.1" : { "VS_AVTT_RS_LIN_FL" : { "U2_FL_XF.19" : {}, "NS5_FL_XF.2" : { "NS5_FL_XF.1" : { "PWR_AVTT_RS_XF" : {} } } } } } } } }, "R94_XF.1" : { "R94_XF.2" : { "GND" : {} } } } } } } } }, "R100_XF.1" : { "R100_XF.2" : { "UNNAMED_17_RESISTOR_I41_A_XF" : { "R95_XF.1" : { "R95_XF.2" : { "GND" : {} } }, "R96_XF.1" : { "R96_XF.2" : { "GND" : {} } } } } }, "U1_XF.CA33" : {} }, "AC_CONN_CLK_REFP<0>" : { "U1_E1_XF.13" : {}, "C21_E1_XF.1" : { "C21_E1_XF.2" : { "CONN_CLK_REFP<0>_E1" : { "J1_E1_XF.B15" : {} } } } }, "C0_DDR4_DQ<39>_XF" : { "J1_XF.247" : {}, "U1_XF.BN22" : {} }, "UNNAMED_17_RESISTOR_I9_B" : { "U12.1" : {}, "R104.2" : { "R104.1" : { "P3R3V" : {} } } }, "UNNAMED_4_BYPASSCAPNPOL_I48_B" : { "R51.2" : { "R51.1" : { "TS_LTM4671_CMN<0>" : { "PM2_SP_XF.K8" : { "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "C81_SP_XF.2" : {} } }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} } } } } } }, "UNNAMED_4_BYPASSCAPNPOL_I105_B" : { "C50.2" : { "C50.1" : { "GND" : {} } }, "R59.2" : { "R59.1" : { "VMON_CPLD_P1R8V_SW" : { "R11_MP.2" : { "R11_MP.1" : { "CPLD_P1R8V_1" : {} } } } } }, "R26.2" : { "R26.1" : { "GND" : {} } }, "U11.1" : {} }, "FPGA_1R8V_SDA" : { "Q2.2" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : {} }, "Q2.3" : { "BASE_3R3V_SDA_2" : { "Q4.3" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.1" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "R5.2" : { "R5.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R3.1" : { "R3.2" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "Q3.1" : { "Q3.3" : { "BASE_3R3V_SCL_2" : { "U12.6" : {}, "U11.13" : {}, "Q1.3" : { "Q1.2" : { "FPGA_1R8V_SCL" : { "R33.1" : { "R33.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q1.1" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "R32.2" : { "R32.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R31.1" : { "R31.2" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : {} } } } } } } } }, "R34.2" : { "R34.1" : { "P3R3V" : {} } }, "U1_CPLD.A9" : {} } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } } } } } } } } }, "U11.14" : {} } } }, "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } }, "C0_DDR4_DQ<69>_XF" : { "J1_XF.192" : {}, "U1_XF.BU26" : {} }, "E1S0_PER_P<1>_XF" : { "J1_E0_XF.A21" : {}, "U1_XF.E6" : {} }, "OCL3_FPGA_REFCLK_N_XF" : { "C385_XF.2" : { "C385_XF.1" : { "AC_OCL3_FPGA_REFCLK_N_XF" : { "U5_XF.28" : {} } } }, "R228_XF.2" : { "R228_XF.1" : { "OCL3_FPGA_REFCLK_P_XF" : {} } }, "U1_XF.BJ14" : {}, "R217_XF.2" : { "R217_XF.1" : { "P3R3V" : {} } }, "R229_XF.1" : { "R229_XF.2" : { "GND" : {} } } }, "UNNAMED_9_LT3071_I30_V00_FL" : { "U7_FL_XF.23" : {}, "R68_FL_XF.1" : { "R68_FL_XF.2" : { "P3R3V" : {} } }, "R80_FL_XF.2" : { "R80_FL_XF.1" : { "GND" : {} } } }, "PWR_VCCINT_XF" : { "U1_XF.AV33" : {}, "PM3_SP_XF.C1" : {}, "C52_XF.1" : { "C52_XF.2" : { "GND" : {} } }, "PM4_SP_XF.C12" : {}, "PM3_SP_XF.A4" : {}, "U1_XF.AD39" : {}, "U1_XF.BD27" : {}, "U1_XF.V33" : {}, "U1_XF.Y29" : {}, "U1_XF.W36" : {}, "PM5_SP_XF.A5" : {}, "U1_XF.AT23" : {}, "U1_XF.AF33" : {}, "U1_XF.Y31" : {}, "U1_XF.AW32" : {}, "U1_XF.AW40" : {}, "C241_XF.1" : { "C241_XF.2" : { "GND" : {} } }, "C302_XF.2" : { "C302_XF.1" : { "GND" : {} } }, "C72_SP_XF.1" : { "C72_SP_XF.2" : { "GND" : {} } }, "U1_XF.BC34" : {}, "U1_XF.BF35" : {}, "C252_XF.1" : { "C252_XF.2" : { "GND" : {} } }, "PM4_SP_XF.B12" : {}, "U1_XF.AJ26" : {}, "U1_XF.BD31" : {}, "C245_XF.1" : { "C245_XF.2" : { "GND" : {} } }, "C69_XF.1" : { "C69_XF.2" : { "GND" : {} } }, "C96_XF.1" : { "C96_XF.2" : { "GND" : {} } }, "PM3_SP_XF.B1" : {}, "U1_XF.AA28" : {}, "U1_XF.BE24" : {}, "U1_XF.AV31" : {}, "U1_XF.AA34" : {}, "C61_XF.1" : { "C61_XF.2" : { "GND" : {} } }, "U1_XF.BE38" : {}, "PM3_SP_XF.A8" : {}, "PM5_SP_XF.B9" : {}, "C325_XF.1" : { "C325_XF.2" : { "GND" : {} } }, "U1_XF.BC28" : {}, "U1_XF.AT21" : {}, "U1_XF.AG20" : {}, "C308_XF.2" : { "C308_XF.1" : { "GND" : {} } }, "U1_XF.AN40" : {}, "PM7_SP_XF.A12" : {}, "C67_XF.1" : { "C67_XF.2" : { "GND" : {} } }, "C321_XF.1" : { "C321_XF.2" : { "GND" : {} } }, "U1_XF.AF31" : {}, "C264_XF.1" : { "C264_XF.2" : { "GND" : {} } }, "U1_XF.AD35" : {}, "U1_XF.BF39" : {}, "PM3_SP_XF.A2" : {}, "U1_XF.AF27" : {}, "C2_SP_XF.1" : { "C2_SP_XF.2" : { "GND" : {} } }, "C21_XF.1" : { "C21_XF.2" : { "GND" : {} } }, "U1_XF.AL26" : {}, "C10_XF.1" : { "C10_XF.2" : { "GND" : {} } }, "U1_XF.AR26" : {}, "U1_XF.BD33" : {}, "PM5_SP_XF.C9" : {}, "PM5_SP_XF.A10" : {}, "C374_XF.2" : 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"GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E6" : { "UNNAMED_7_LTM4671_I87_PHMODE0_SP" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : {} } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} } } } } }, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.E7" : { "UNNAMED_7_BYPASSCAPNPOL_I44_B_SP" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} } } } } } } } } }, "VDDO6" : { "R14.2" : { "R14.1" : { "CPLD_P1R8V_1" : {} } }, "U1.43" : {}, "C11.1" : { "C11.2" : { "GND" : {} } } }, "UNNAMED_17_BYPASSCAPNPOL_I57_A_XF" : { "C140_XF.1" : { "C140_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I57_B_XF" : { "R81_XF.2" : { "R81_XF.1" : { "UNNAMED_17_RESISTOR_I60_A_XF" : { "R112_XF.2" : { "R112_XF.1" : { "GND" : {} } }, "R113_XF.2" : { "R113_XF.1" : { "GND" : {} } } } } }, "U1_XF.CC37" : {} } } }, "U1_XF.CC36" : {}, "R80_XF.2" : { "R80_XF.1" : { "UNNAMED_17_RESISTOR_I59_A_XF" : { "R111_XF.2" : { "R111_XF.1" : { "GND" : {} } }, "R110_XF.2" : { "R110_XF.1" : { "VMON_AVTT_RLC_LIN_XF" : { "R56_FL_XF.2" : { "R56_FL_XF.1" : { "VS_AVTT_RLC_LIN_FL" : { "NS3_FL_XF.2" : { "NS3_FL_XF.1" : { "PWR_AVTT_RLC_XF" : {} } }, "U1_FL_XF.19" : {} } } } } } } } } } }, "C3_DDR4_SA<1>_XF" : { "R266_XF.2" : { "R266_XF.1" : { "P3R3V" : {} } }, "J4_XF.140" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I116_B_XF" : { "C268_XF.2" : { "C268_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I116_A_XF" : { "U1_XF.BW31" : {}, "R129_XF.1" : { "R129_XF.2" : { "UNNAMED_17_RESISTOR_I110_A_XF" : { "R137_XF.1" : { "R137_XF.2" : { "VMON_AVTT_RS_LIN_XF" : { "R4_FL_XF.2" : { "R4_FL_XF.1" : { "VS_AVTT_RS_LIN_FL" : { "U2_FL_XF.19" : {}, "NS5_FL_XF.2" : { "NS5_FL_XF.1" : { "PWR_AVTT_RS_XF" : {} } } } } }, "R93_XF.2" : { "R93_XF.1" : { "UNNAMED_17_RESISTOR_I40_A_XF" : { "R99_XF.2" : { "R99_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I46_A_XF" : { "U1_XF.BY33" : {}, "C147_XF.1" : { "C147_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I46_B_XF" : { "R100_XF.1" : { "R100_XF.2" : { "UNNAMED_17_RESISTOR_I41_A_XF" : { "R95_XF.1" : { "R95_XF.2" : { "GND" : {} } }, "R96_XF.1" : { "R96_XF.2" : { "GND" : {} } } } } }, "U1_XF.CA33" : {} } } } } } }, "R94_XF.1" : { "R94_XF.2" : { "GND" : {} } } } } } } } }, "R138_XF.1" : { "R138_XF.2" : { "GND" : {} } } } } } } } }, "R130_XF.1" : { "R130_XF.2" : { "UNNAMED_17_RESISTOR_I113_A_XF" : { "R139_XF.1" : { "R139_XF.2" : { "GND" : {} } }, "R141_XF.1" : { "R141_XF.2" : { "GND" : {} } } } } }, "U1_XF.BW32" : {} }, "UNNAMED_9_LT3071_I66_MARGA_FL" : { "U11_FL_XF.22" : {}, "R112_FL_XF.2" : { "R112_FL_XF.1" : { "UNNAMED_9_BYPASSCAPNPOL_I59_B_FL" : { "C104_FL_XF.2" : { "C104_FL_XF.1" : { "GND" : {} } }, "R108_FL_XF.2" : { "R108_FL_XF.1" : { "DAC_VCCAUX_LIN_XF" : { "R77_FL_XF.1" : { "R77_FL_XF.2" : { "UNNAMED_9_BYPASSCAPNPOL_I25_B_FL" : { "C75_FL_XF.2" : { "C75_FL_XF.1" : { "GND" : {} } }, "R81_FL_XF.1" : { "R81_FL_XF.2" : { "UNNAMED_9_LT3071_I30_MARGA_FL" : { "U7_FL_XF.22" : {} } } } } } }, "U1_SP_XF.54" : {} } } } } } } }, "C3_DDR4_ADR<6>_XF" : { "J4_XF.69" : {}, "U1_XF.R28" : {} }, "AC_PCIE0_TXP<2>_XF" : { "U1_XF.AV13" : {}, "C39_XF.1" : { "C39_XF.2" : { "PCIE0_TXP<2>_XF" : { "J1_P0_XF.B15" : {} } } } }, "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "PM4_SP_XF.E5" : { "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G9" : { "UNNAMED_4_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } } } }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } } }, "E1S0_PER_P<7>_XF" : { "J1_E0_XF.A40" : {}, "U1_XF.G2" : {} }, "VS_AVCC_RUC_LIN_FL" : { "R102_FL_XF.1" : { "R102_FL_XF.2" : { "VMON_AVCC_RUC_LIN_XF" : { "R39_XF.2" : { "R39_XF.1" : { "UNNAMED_17_RESISTOR_I214_B_XF" : { "R62_XF.1" : { "R62_XF.2" : { "GND" : {} } }, "R68_XF.2" : { "R68_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I216_A_XF" : { "U1_XF.CA40" : {}, "C316_XF.1" : { "C316_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I216_B_XF" : { "U1_XF.CB40" : {}, "R69_XF.1" : { "R69_XF.2" : { "UNNAMED_17_RESISTOR_I215_B_XF" : { "R63_XF.1" : { "R63_XF.2" : { "GND" : {} } }, "R70_XF.1" : { "R70_XF.2" : { "GND" : {} } } } } } } } } } } } } } } } } }, "NS1_FL_XF.2" : { "NS1_FL_XF.1" : { "PWR_AVCC_RUC_XF" : {} } }, "U10_FL_XF.19" : {} }, "TS_1428_SPARE_P_SP" : { "U4_SP_XF.15" : {}, "TS_SP_P_SP_XF.1" : {} }, "UNNAMED_7_RESISTOR_I68_A_SP" : { "R74_SP_XF.1" : { "R74_SP_XF.2" : { "UNNAMED_7_LTM4671_I39_FB2_SP" : { "PM1_SP_XF.M9" : { "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {}, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} } } } } } }, "E1S3_PER_N<6>_XF" : { "U1_XF.AL1" : {}, "J1_E3_XF.A36" : {} }, "UNNAMED_4_BYPASSCAPNPOL_I13_B_ND" : { "C32_ND_XF.2" : { "C32_ND_XF.1" : { "GND" : {} } }, "U2_ND_XF.6" : {} }, "PCIE0_TXN<6>_XF" : { "C51_XF.2" : { "C51_XF.1" : { "AC_PCIE0_TXN<6>_XF" : { "U1_XF.BB8" : {} } } }, "J2_P0_XF.B16" : {} }, "DDR4_REF_CLK_N" : { "R8_XF.2" : { "R8_XF.1" : { "DDR4_REF_CLK_P" : {} } }, "U1.23" : {}, "U6_XF.7" : {} }, "E1S_REF_CLK_N<0>" : { "C17_E0_XF.1" : { "C17_E0_XF.2" : { "CLKIN_N_E0" : { "R15_E0_XF.2" : { "R15_E0_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R18_E0_XF.1" : { "R18_E0_XF.2" : { "GND" : {} } }, "U1_E0_XF.6" : {} } } }, "U1.27" : {} }, "AC_E1S0_PET_N<7>_XF" : { "C118_XF.1" : { "C118_XF.2" : { "E1S0_PET_N<7>_XF" : { "J1_E0_XF.B39" : {} } } }, "U1_XF.C10" : {} }, "UNNAMED_29_PI6CB33401_I89_SDATA_XF" : { "U7_XF.10" : {}, "R88_XF.2" : { "R88_XF.1" : { "PWR_FPGA_3R3V" : {} } } }, "UNNAMED_10_RESISTOR_I155_A" : { "U1.47" : {}, "R43.1" : { "R43.2" : { "SI5341_LOL_N" : { "U1_CPLD.D2" : {} } } } }, "UNNAMED_17_RESISTOR_I121_A_XF" : { "R131_XF.1" : { "R131_XF.2" : { "UNNAMED_17_RESISTOR_I119_A_XF" : { "R143_XF.1" : { "R143_XF.2" : { "GND" : {} } }, "R142_XF.1" : { "R142_XF.2" : { "VMON_AVTT_SW_XF" : { "R99_SP_XF.2" : { "R99_SP_XF.1" : { "PWR_AVTT_SW_XF" : {} } } } } } } } }, "C269_XF.1" : { "C269_XF.2" : { "UNNAMED_17_RESISTOR_I124_A_XF" : { "R132_XF.1" : { "R132_XF.2" : { "UNNAMED_17_RESISTOR_I122_A_XF" : { "R144_XF.1" : { "R144_XF.2" : { "GND" : {} } }, "R145_XF.1" : { "R145_XF.2" : { "GND" : {} } } } } }, "U1_XF.BY30" : {} } } }, "U1_XF.BY29" : {} }, "C2_RDIMM_DQS_T<10>_XF" : { "J3_XF.18" : {}, "U1_XF.P51" : {} }, "FPGA_CFG_MODE<2>_1" : { "U1_XF.AK17" : {}, "U1_CPLD.J3" : {} }, "AC_E1S0_PET_P<6>_XF" : { "C103_XF.1" : { "C103_XF.2" : { "E1S0_PET_P<6>_XF" : { "J1_E0_XF.B37" : {} } } }, "U1_XF.D9" : {} }, "PCIE1_RXN<5>_XF" : { "J2_P1_XF.A7" : {}, "U1_XF.AT3" : {} }, "C3_DDR4_DQ<38>_XF" : { "J4_XF.102" : {}, "U1_XF.A27" : {} }, "E1S2_PET_N<5>_XF" : { "C168_XF.2" : { "C168_XF.1" : { "AC_E1S2_PET_N<5>_XF" : { "U1_XF.AB8" : {} } } }, "J1_E2_XF.B33" : {} }, "IS_VCCINTUL_SW_N_SP" : { "C127_SP_XF.1" : { "C127_SP_XF.2" : { "GND" : {} } }, "R49_SP_XF.2" : { "R49_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I146_A_SP" : { "C28_SP_XF.1" : { "C28_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.44" : {} } } }, "R127_SP_XF.1" : { "R127_SP_XF.2" : { "P3R3V" : {} } }, "R128_SP_XF.2" : { "R128_SP_XF.1" : { "GND" : {} } } }, "OCL0_PET_P<2>_XF" : { "C177_XF.2" : { "C177_XF.1" : { "AC_OCL0_PET_P<2>_XF" : { "U1_XF.CB9" : {} } } }, "J1_O0_XF.B15" : {} }, "C0_DDR4_ADR<3>_XF" : { "J1_XF.71" : {}, "U1_XF.CB15" : {} }, "E1S3_3R3V_SDA_XF" : { "R4_E3_XF.2" : { "R4_E3_XF.1" : { "P3R3V" : {} } }, "R209_XF.2" : { "R209_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_XF.U20" : {}, "J1_E3_XF.A8" : {} }, "INTVCC_4650_BL_SP" : { "R7_SP_XF.1" : { "R7_SP_XF.2" : { "PHASMD_4650_BL_SP" : { "R24_SP_XF.2" : { "R24_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "PM3_SP_XF.G4" : { "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H8" : { "INTVCC_4650_BL_SP" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.E8" : { "INTVCC_4650_BL_SP" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G3" : { "GND" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} } } } } }, "C80_SP_XF.1" : { "C80_SP_XF.2" : { "GND" : {} } } }, "AC_OCL3_CONN_REFCLK_N_XF" : { "C387_XF.1" : { "C387_XF.2" : { "OCL3_CONN_REFCLK_N_XF" : { "J1_O3_XF.B13" : {} } } }, "U5_XF.18" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I49_B_XF" : { "R83_XF.2" : { "R83_XF.1" : { "UNNAMED_17_RESISTOR_I54_A_XF" : { "R75_XF.2" : { "R75_XF.1" : { "UNNAMED_17_RESISTOR_I187_B_XF" : { "R119_XF.2" : { "R119_XF.1" : { "GND" : {} } } } } }, "R74_XF.2" : { "R74_XF.1" : { "GND" : {} } } } } }, "C141_XF.2" : { "C141_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I49_A_XF" : { "U1_XF.BY38" : {}, "R82_XF.2" : { "R82_XF.1" : { "UNNAMED_17_RESISTOR_I53_A_XF" : { "R72_XF.2" : { "R72_XF.1" : { "IMON_AVCC_LIN_XF" : { "R15_FL_XF.2" : { "R15_FL_XF.1" : { "UNNAMED_4_LT3071_I30_IMON_FL" : { "U6_FL_XF.21" : {} } } }, "R91_FL_XF.2" : { "R91_FL_XF.1" : { "UNNAMED_12_LT3071_I30_IMON_FL" : { "U10_FL_XF.21" : {} } } }, "R7_FL_XF.2" : { "R7_FL_XF.1" : { "UNNAMED_3_LT3071_I32_IMON_FL" : { "U3_FL_XF.21" : {} } } } } } }, "R73_XF.2" : { "R73_XF.1" : { "UNNAMED_17_RESISTOR_I188_B_XF" : { "R118_XF.2" : { "R118_XF.1" : { "GND" : {} } } } } } } } } } } }, "U1_XF.CA38" : {} }, "UNNAMED_3_LTM4675_I40_VOUT0CFG_ND" : { "PM4_ND_XF.G3" : { "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } }, "U1_CPLD.C9" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } }, "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "OCL0_3R3V_CKEN_F<1>_XF" : { "U1_XF.BJ19" : {}, "U7_XF.12" : {} }, "C3_RDIMM_DQS_T<17>_XF" : { "U1_XF.J20" : {}, "J4_XF.51" : {} }, "AC_PCIE0_TXN<6>_XF" : { "U1_XF.BB8" : {}, "C51_XF.1" : { "C51_XF.2" : { "PCIE0_TXN<6>_XF" : { "J2_P0_XF.B16" : {} } } } }, "C3_DDR4_DQ<68>_XF" : { "J4_XF.47" : {}, "U1_XF.G15" : {} }, "E1S0_PER_P<5>_XF" : { "U1_XF.H4" : {}, "J1_E0_XF.A34" : {} }, "AC_CONN_CLK_REFP<0>_3" : { "U1_E2_XF.13" : {}, "C21_E2_XF.1" : { "C21_E2_XF.2" : { "CONN_CLK_REFP<0>_E2" : { "J1_E2_XF.B15" : {} } } } }, "UNNAMED_5_LT3071_I30_V02_FL" : { "R73_FL_XF.1" : { "R73_FL_XF.2" : { "P3R3V" : {} } }, "R33_FL_XF.2" : { "R33_FL_XF.1" : { "GND" : {} } }, "U1_FL_XF.25" : {} }, "AC_OCL2_FPGA_REFCLK_P_XF" : { "U5_XF.22" : {}, "C358_XF.1" : { "C358_XF.2" : { "OCL2_FPGA_REFCLK_P_XF" : { "R214_XF.2" : { "R214_XF.1" : { "P3R3V" : {} } }, "R224_XF.1" : { "R224_XF.2" : { "GND" : {} } }, "U1_XF.BL15" : {} } } } }, "PCIE0_RXP<1>_XF" : { "U1_XF.AW2" : {}, "J1_P0_XF.A6" : {} }, "OCL2_PER_N<2>_XF" : { "J1_O2_XF.A16" : {}, "U1_XF.BL1" : {} }, "UNNAMED_8_ACS711_I102_VIOUT_SP" : { "R131_SP_XF.2" : { "R131_SP_XF.1" : { "IS_VCCINTUL_SW_P_SP" : { "C129_SP_XF.1" : { "C129_SP_XF.2" : { "GND" : {} } }, "R50_SP_XF.2" : { "R50_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I147_A_SP" : { "U1_SP_XF.43" : {}, "C34_SP_XF.1" : { "C34_SP_XF.2" : { "GND" : {} } } } } }, "R132_SP_XF.2" : { "R132_SP_XF.1" : { "GND" : {} } } } } }, "U5_SP_XF.11" : {} }, "E1S0_3R3V_PERST_F<0>_XF" : { "U1_XF.Y17" : {}, "J1_E0_XF.B10" : {} }, "UNNAMED_4_LED_I22_C_MP" : { "U2_MP.14" : {}, "D1_MP.1" : { "D1_MP.2" : { "UNNAMED_4_LED_I22_A_MP" : { "R8_MP.2" : { "R8_MP.1" : { "P5VSB" : {} } } } } } }, "STAT_LED_ON_F<3>_CPLD" : { "D5_CPLD.1" : { "D5_CPLD.2" : { "UNNAMED_9_LED_I13_A_CPLD" : { "R116_CPLD.1" : { "R116_CPLD.2" : { "CPLD_P3R3V" : {} } } } } }, "U1_CPLD.D7" : {} }, "UNNAMED_9_ACS711_I5_VIOUT_SP" : { "R193_SP_XF.2" : { "R193_SP_XF.1" : { "IS_VCCINTUR_SW_P_SP" : { "R46_SP_XF.2" : { "R46_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I143_A_SP" : { "C25_SP_XF.1" : { "C25_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.47" : {} } } }, "C182_SP_XF.1" : { "C182_SP_XF.2" : { "GND" : {} } }, "R194_SP_XF.2" : { "R194_SP_XF.1" : { "GND" : {} } } } } }, "U2_SP_XF.11" : {} }, "CPLD_SEL_CFG_FLASH" : { "U4_XF.7" : {}, "R114_XF.1" : { "R114_XF.2" : { "UNNAMED_15_NMOSFETVMT3_I42_G_XF" : { "Q1_XF.1" : { "Q1_XF.3" : { "UNNAMED_15_MAX4641_I1_IN2_XF" : { "R116_XF.1" : { "R116_XF.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U4_XF.3" : {} } }, "Q1_XF.2" : { "GND" : {} } } } } }, "U1_CPLD.J4" : {} }, "UNNAMED_4_RESISTOR_I7_A_SD" : { "U2_SD_XF.9" : {}, "R61_SD_XF.1" : { "R61_SD_XF.2" : { "POK_OD_SDIMM_VTT_LIN" : { "U1_CPLD.T7" : {} } } } }, "PCIE1_TXP<7>_XF" : { "C26_XF.2" : { "C26_XF.1" : { "AC_PCIE1_TXP<7>_XF" : { "U1_XF.AT13" : {} } } }, "J2_P1_XF.B18" : {} }, "PCIE_X1_WAKE_F_XF" : { "U1_XF.BD19" : {}, "J1_PX1_XF.B11" : {} }, "PWR_RN_RUC_MGTVCCAUX_XF" : { "U1_XF.T15" : {}, "C91_XF.1" : { "C91_XF.2" : { "GND" : {} } }, "U8_FL_XF.1" : {}, "C84_FL_XF.2" : { "C84_FL_XF.1" : { "UNNAMED_10_RESISTOR_I75_A_FL" : {} } }, "U1_XF.AK15" : {}, "R86_FL_XF.2" : { "R86_FL_XF.1" : { "UNNAMED_10_RESISTOR_I75_A_FL" : {} } }, "U1_XF.P15" : {}, "R83_FL_XF.1" : { "R83_FL_XF.2" : { "VMON_RN_RUC_MGTVCCAUX" : { "R46.2" : { "R46.1" : { "UNNAMED_4_MAX116XXQSOP16_I97_AIN2" : {} } } } } }, "C474_XF.1" : { "C474_XF.2" : { "GND" : {} } }, "U1_XF.AM15" : {}, "C92_XF.1" : { "C92_XF.2" : { "GND" : {} } }, "C82_FL_XF.1" : { "C82_FL_XF.2" : { "GND" : {} } }, "C473_XF.1" : { "C473_XF.2" : { "GND" : {} } } }, "OCL0_3R3V_SDA_XF" : { "U1_XF.BL18" : {}, "R231_XF.2" : { "R231_XF.1" : { "P3R3V" : {} } }, "J1_O0_XF.A10" : {} }, "UNNAMED_3_LTM4675_I40_RUN0_SD" : { "PM4_SD_XF.F3" : { "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U1_CPLD.C9" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "E1S3_PET_P<2>_XF" : { "C340_XF.2" : { "C340_XF.1" : { "AC_E1S3_PET_P<2>_XF" : { "U1_XF.AG11" : {} } } }, "J1_E3_XF.B24" : {} }, "MGTRREF_RN_XF" : { "R269_XF.1" : { "R269_XF.2" : { "PWR_AVTT_RN_XF" : {} } }, "U1_XF.R14" : {} }, "AC_CONN_CLK_REFN<1>" : { "U1_E1_XF.18" : {}, "C24_E1_XF.1" : { "C24_E1_XF.2" : { "CONN_CLK_REFN<1>_E1" : { "J1_E1_XF.A14" : {} } } } }, "E1S3_3R3V_CKEN_F<1>_XF" : { "U1_XF.R18" : {}, "U1_E3_XF.19" : {} }, "GNDADC_XF" : { "U1_XF.AL24" : {}, "C143_XF.2" : { "C143_XF.1" : { "VCCADC_XF" : { "R84_XF.2" : { "R84_XF.1" : { "VREF_P1R25V_XF" : { "U9_XF.4" : {}, "U1_XF.AN25" : {}, "U9_XF.3" : {} } } }, "FB2_XF.1" : { "FB2_XF.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.AL25" : {} } } }, "C142_XF.2" : { "C142_XF.1" : { "VREF_P1R25V_XF" : {} } }, "R85_XF.2" : { "R85_XF.1" : { "VREF_P1R25V_RET_XF" : { "U1_XF.AM24" : {} } } }, "U9_XF.5" : {}, "FB1_XF.1" : { "FB1_XF.2" : { "GND" : {} } } }, "OCL1_PET_N<2>_XF" : { "C271_XF.2" : { "C271_XF.1" : { "AC_OCL1_PET_N<2>_XF" : { "U1_XF.BW10" : {} } } }, "J1_O1_XF.B16" : {} }, "C3_DDR4_ODT<1>_XF" : { "J4_XF.91" : {}, "U1_XF.K22" : {} }, "UNNAMED_6_RESISTOR_I441_A_SP" : { "R85_SP_XF.1" : { "R85_SP_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I402_B_SP" : { "R94_SP_XF.2" : { "R94_SP_XF.1" : { "UNNAMED_6_LTM4671_I456_MODECLKIN3_SP" : { "PM2_SP_XF.R8" : { "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.P8" : { "UNNAMED_6_RESISTOR_I441_A_SP" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R11" : { "UNNAMED_6_BYPASSCAPNPOL_I402_B_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} } } } } }, "C83_SP_XF.2" : { "C83_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } } }, "JTAG_CTL_TCK" : { "U1_XF.CA32" : {}, "U1_CPLD.F1" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I146_A_SP" : { "R49_SP_XF.1" : { "R49_SP_XF.2" : { "IS_VCCINTUL_SW_N_SP" : { "R128_SP_XF.2" : { "R128_SP_XF.1" : { "GND" : {} } }, "R127_SP_XF.1" : { "R127_SP_XF.2" : { "P3R3V" : {} } }, "C127_SP_XF.1" : { "C127_SP_XF.2" : { "GND" : {} } } } } }, "U1_SP_XF.44" : {}, "C28_SP_XF.1" : { "C28_SP_XF.2" : { "GND" : {} } } }, "C0_DDR4_DQ<44>_XF" : { "U1_XF.BP24" : {}, "J1_XF.106" : {} }, "C3_DDR4_DQ<70>_XF" : { "U1_XF.G16" : {}, "J4_XF.54" : {} }, "UNNAMED_5_BYPASSCAPNPOL_I25_B_FL" : { "R31_FL_XF.1" : { "R31_FL_XF.2" : { "UNNAMED_5_LT3071_I30_MARGA_FL" : { "U1_FL_XF.22" : {} } } }, "R29_FL_XF.2" : { "R29_FL_XF.1" : { "DAC_AVTT_LIN_XF" : { "R38_FL_XF.1" : { "R38_FL_XF.2" : { "UNNAMED_8_BYPASSCAPNPOL_I25_B_FL" : { "C25_FL_XF.2" : { "C25_FL_XF.1" : { "GND" : {} } }, "R44_FL_XF.1" : { "R44_FL_XF.2" : { "UNNAMED_8_LT3071_I30_MARGA_FL" : { "U5_FL_XF.22" : {} } } } } } }, "R36_FL_XF.1" : { "R36_FL_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I25_B_FL" : { "R42_FL_XF.1" : { "R42_FL_XF.2" : { "UNNAMED_6_LT3071_I30_MARGA_FL" : { "U2_FL_XF.22" : {} } } }, "C22_FL_XF.2" : { "C22_FL_XF.1" : { "GND" : {} } } } } }, "R37_FL_XF.1" : { "R37_FL_XF.2" : { "UNNAMED_7_BYPASSCAPNPOL_I25_B_FL" : { "C24_FL_XF.2" : { "C24_FL_XF.1" : { "GND" : {} } }, "R43_FL_XF.1" : { "R43_FL_XF.2" : { "UNNAMED_7_LT3071_I30_MARGA_FL" : { "U4_FL_XF.22" : {} } } } } } }, "U1_SP_XF.58" : {} } } }, "C20_FL_XF.2" : { "C20_FL_XF.1" : { "GND" : {} } } }, "E1S1_PER_N<5>_XF" : { "U1_XF.U1" : {}, "J1_E1_XF.A33" : {} }, "C0_DDR4_ADR<15>_XF" : { "J1_XF.86" : {}, "U1_XF.BR20" : {} }, "C0_DDR4_DQ<25>_XF" : { "J1_XF.183" : {}, "U1_XF.BV22" : {} }, "C0_RDIMM_DQS_C<17>_XF" : { "J1_XF.52" : {}, "U1_XF.BW26" : {} }, "AC_OCL1_PET_P<3>_XF" : { "U1_XF.BV9" : {}, "C181_XF.1" : { "C181_XF.2" : { "OCL1_PET_P<3>_XF" : { "J1_O1_XF.B18" : {} } } } }, "PHASMD_4650_BL_SP" : { "R7_SP_XF.2" : { "R7_SP_XF.1" : { "INTVCC_4650_BL_SP" : { "R27_SP_XF.1" : { "R27_SP_XF.2" : { "UNNAMED_10_LTM4650FIXED_I151_MODEPLLIN_SP" : { "R28_SP_XF.2" : { "R28_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R32_SP_XF.2" : { "R32_SP_XF.1" : { "CKO_LTM4650_PM4_SP" : { "R33_SP_XF.2" : { "R33_SP_XF.1" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : { "PM4_SP_XF.G5" : { "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} } } } } } } } } } } }, "C80_SP_XF.1" : { "C80_SP_XF.2" : { "GND" : {} } } } } }, "R24_SP_XF.2" : { "R24_SP_XF.1" : { "SGND_PM3_SP" : {} } } }, "UNNAMED_6_LTM4671_I456_CLKOUT3_SP" : { "PM2_SP_XF.P6" : { "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : {} } } } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} } } }, "UNNAMED_4_PI6CB33401_I37_BWSELTRI_E3" : { "U1_E3_XF.1" : {}, "R10_E3_XF.2" : { "R10_E3_XF.1" : { "GND" : {} } } }, "OCL0_3R3V_BP_TYPE_XF" : { "U1_XF.BJ20" : {}, "J1_O0_XF.B9" : {} }, "PWR_VCCAUX_B_FL" : { "C108_FL_XF.1" : { "C108_FL_XF.2" : { "GND" : {} } }, "C107_FL_XF.1" : { "C107_FL_XF.2" : { "GND" : {} } }, "U11_FL_XF.18" : {}, "R115_FL_XF.1" : { "R115_FL_XF.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U11_FL_XF.17" : {}, "U11_FL_XF.16" : {}, "C105_FL_XF.1" : { "C105_FL_XF.2" : { "GND" : {} } }, "NS11_FL_XF.1" : { "NS11_FL_XF.2" : { "UNNAMED_9_LT3071_I66_SENSE_FL" : { "U11_FL_XF.19" : {} } } }, "U11_FL_XF.15" : {}, "C106_FL_XF.1" : { "C106_FL_XF.2" : { "GND" : {} } } }, "C0_DDR4_CS_N<3>_XF" : { "J1_XF.237" : {}, "U1_XF.CC16" : {} }, "ENB3V_SEQ_G_CPLD" : { "R10_CPLD.1" : { "R10_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N15" : {} }, "AC_E1S3_PET_P<3>_XF" : { "U1_XF.AF13" : {}, "C311_XF.1" : { "C311_XF.2" : { "E1S3_PET_P<3>_XF" : { "J1_E3_XF.B27" : {} } } } }, "OCL1_3R3V_SCL_XF" : { "J1_O1_XF.A9" : {}, "R232_XF.2" : { "R232_XF.1" : { "P3R3V" : {} } }, "U1_XF.BK20" : {} }, "CPLD_TMS_PIN_CPLD" : { "U1_CPLD.B8" : {}, "R19_CPLD.2" : { "R19_CPLD.1" : { "UNNAMED_8_1G97_I17_Y_CPLD" : { "U2_CPLD.4" : {} } } } }, "POK_OD_VCCINT_TLSW_P<1>" : { "U1_CPLD.R11" : {}, "R67_SP_XF.2" : { "R67_SP_XF.1" : { "UNNAMED_4_LTM4650FIXED_I78_PGOOD2_SP" : { "PM4_SP_XF.G8" : { "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } } } }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} } } } } } }, "C2_DDR4_DQ<11>_XF" : { "J3_XF.168" : {}, "U1_XF.P49" : {} }, "UNNAMED_7_SM050TP_I155_1_CPLD" : { "U1_CPLD.E15" : {}, "TP10_CPLD.1" : {} }, "PWR_NDIMM_VPP_XF" : { "C194_XF.1" : { "C194_XF.2" : { "GND" : {} } }, "C224_XF.2" : { "C224_XF.1" : { "GND" : {} } }, "PM1_SP_XF.H2" : {}, "R123_SP_XF.1" : { "R123_SP_XF.2" : { "VMON_NDIMM_VPP_SW" : { "R54.2" : { "R54.1" : { "UNNAMED_4_MAX116XXQSOP16_I97_AIN5" : {} } } } } }, "J4_XF.288" : {}, "C193_XF.2" : { "C193_XF.1" : { "GND" : {} } }, "J4_XF.287" : {}, "PM1_SP_XF.J4" : {}, "PM1_SP_XF.H1" : {}, "PM1_SP_XF.H3" : {}, "PM1_SP_XF.J10" : {}, "J3_XF.286" : {}, "C227_XF.1" : { "C227_XF.2" : { "GND" : {} } }, "J4_XF.142" : {}, "C120_SP_XF.1" : { "C120_SP_XF.2" : { "GND" : {} } }, "J4_XF.143" : {}, "PM1_SP_XF.J2" : {}, "J3_XF.143" : {}, "C112_SP_XF.1" : { "C112_SP_XF.2" : { "GND" : {} } }, "J3_XF.142" : {}, "PM1_SP_XF.H4" : {}, "C223_XF.2" : { "C223_XF.1" : { "GND" : {} } }, "J4_XF.286" : {}, "C192_XF.2" : { "C192_XF.1" : { "GND" : {} } }, "C198_XF.1" : { "C198_XF.2" : { "GND" : {} } }, "J3_XF.288" : {}, "J3_XF.287" : {}, "C116_SP_XF.1" : { "C116_SP_XF.2" : { "GND" : {} } }, "C197_XF.1" : { "C197_XF.2" : { "GND" : {} } }, "C226_XF.1" : { "C226_XF.2" : { "GND" : {} } }, "PM1_SP_XF.J1" : {}, "PM1_SP_XF.J3" : {}, "C225_XF.1" : { "C225_XF.2" : { "GND" : {} } } }, "UNNAMED_9_ACS711_I28_VIOUT_SP" : { "U3_SP_XF.11" : {}, "R195_SP_XF.2" : { "R195_SP_XF.1" : { "IS_VCCINTLR_SW_P_SP" : { "C183_SP_XF.1" : { "C183_SP_XF.2" : { "GND" : {} } }, "R48_SP_XF.2" : { "R48_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I145_A_SP" : { "C27_SP_XF.1" : { "C27_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.45" : {} } } }, "R196_SP_XF.2" : { "R196_SP_XF.1" : { "GND" : {} } } } } } }, "UNNAMED_4_PI6CB33401_I37_SDATA_E3" : { "R9_E3_XF.2" : { "R9_E3_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E3_XF.10" : {} }, "OCL0_PER_N<3>_XF" : { "U1_XF.BV3" : {}, "J1_O0_XF.A19" : {} }, "C3_DDR4_DQ<34>_XF" : { "J4_XF.104" : {}, "U1_XF.D26" : {} }, "C0_DDR4_DQ<1>_XF" : { "J1_XF.150" : {}, "U1_XF.BW25" : {} }, "UNNAMED_3_LT3071_I32_V01_FL" : { "U3_FL_XF.24" : {}, "R71_FL_XF.2" : { "R71_FL_XF.1" : { "GND" : {} } }, "R46_FL_XF.1" : { "R46_FL_XF.2" : { "P3R3V" : {} } } }, "AC_OCL2_PET_N<0>_XF" : { "U1_XF.BN10" : {}, "C277_XF.1" : { "C277_XF.2" : { "OCL2_PET_N<0>_XF" : { "J1_O2_XF.B4" : {} } } } }, "E1S3_3R3V_LED_XF" : { "U1_XF.U18" : {}, "J1_E3_XF.A10" : {}, "R6_E3_XF.2" : { "R6_E3_XF.1" : { "P3R3V" : {} } } }, "FPGA_CPLD_DCLK_1" : { "U1_CPLD.C8" : {}, "U1_XF.BN29" : {} }, "C1_DDR4_ADR<1>_XF" : { "U1_XF.CB54" : {}, "J2_XF.72" : {} }, "C2_DDR4_SA<2>_XF" : { "R6_XF.2" : { "R6_XF.1" : { "P3R3V" : {} } }, "J3_XF.238" : {} }, "C2_DDR4_ADR<9>_XF" : { "U1_XF.K59" : {}, "J3_XF.66" : {} }, "ENB3V_SEQ_H_CPLD" : { "U1_CPLD.P16" : {}, "R9_CPLD.1" : { "R9_CPLD.2" : { "GND" : {} } } }, "UNNAMED_20_NMOSFETVMT3_I12_G" : { "R42.2" : { "R42.1" : { "FAN_PWM_OD" : { "R55.1" : { "R55.2" : { "UNNAMED_20_NMOSFETVMT3_I16_G" : { "Q8.1" : { "Q8.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I25_P4" : { "P3.4" : {} } }, "Q8.2" : { "GND" : {} } } } } }, "U1_CPLD.J12" : {}, "R56.1" : { "R56.2" : { "UNNAMED_20_NMOSFETVMT3_I8_G" : { "Q9.1" : { "Q9.2" : { "GND" : {} }, "Q9.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I27_P4" : { "P5.4" : {} } } } } } }, "R39.1" : { "R39.2" : { "UNNAMED_20_NMOSFETVMT3_I20_G" : { "Q6.1" : { "Q6.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I30_P4" : { "P2.4" : {} } }, "Q6.2" : { "GND" : {} } } } } } } } }, "Q7.1" : { "Q7.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I26_P4" : { "P4.4" : {} } }, "Q7.2" : { "GND" : {} } } }, "OCL2_PET_P<3>_XF" : { "J1_O2_XF.B18" : {}, "C233_XF.2" : { "C233_XF.1" : { "AC_OCL2_PET_P<3>_XF" : { "U1_XF.BK9" : {} } } } }, "C3_DDR4_DQ<64>_XF" : { "J4_XF.49" : {}, "U1_XF.F16" : {} }, "REF/BYP_FL" : { "C102_FL_XF.1" : { "C102_FL_XF.2" : { "GND" : {} } }, "C73_FL_XF.1" : { "C73_FL_XF.2" : { "GND" : {} } }, "U11_FL_XF.3" : {}, "U7_FL_XF.3" : {} }, "AC_PCIE1_TXN<7>_XF" : { "U1_XF.AT12" : {}, "C42_XF.1" : { "C42_XF.2" : { "PCIE1_TXN<7>_XF" : { "J2_P1_XF.B19" : {} } } } }, "AC_E1S0_PET_N<0>_XF" : { "U1_XF.C6" : {}, "C129_XF.1" : { "C129_XF.2" : { "E1S0_PET_N<0>_XF" : { "J1_E0_XF.B17" : {} } } } }, "CLKIN_P_E1" : { "C16_E1_XF.2" : { "C16_E1_XF.1" : { "E1S_REF_CLK_P<1>" : { "U1.31" : {} } } }, "R16_E1_XF.1" : { "R16_E1_XF.2" : { "GND" : {} } }, "R14_E1_XF.2" : { "R14_E1_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E1_XF.5" : {}, "R17_E1_XF.1" : { "R17_E1_XF.2" : { "CLKIN_N_E1" : {} } } }, "C1_DDR4_DQ<26>_XF" : { "U1_XF.BW62" : {}, "J2_XF.45" : {} }, "E1S1_PER_N<7>_XF" : { "U1_XF.R1" : {}, "J1_E1_XF.A39" : {} }, "C1_DDR4_DQ<19>_XF" : { "J2_XF.179" : {}, "U1_XF.BU56" : {} }, "UNNAMED_5_LT3071_I30_V01_FL" : { "R3_FL_XF.1" : { "R3_FL_XF.2" : { "P3R3V" : {} } }, "R5_FL_XF.2" : { "R5_FL_XF.1" : { "GND" : {} } }, "U1_FL_XF.24" : {} }, "C3_DDR4_DQ<50>_XF" : { "J4_XF.126" : {}, "U1_XF.D15" : {} }, "VDD_VS_N_SD" : { "PM4_SD_XF.E7" : { "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } }, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } 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"PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.D8" : { "NC" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.H5" : { "NC" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.F7" : { "NC" : {} }, "PM4_ND_XF.E5" : { "CKI_LTM4675_ND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.E3" : { "NDIMM_LTM4675_ALERT_OD_F_1" : { "U1_CPLD.M6" : {} } } }, "J2_XF.285" : {}, "J1_XF.285" : {}, "J4_XF.285" : {}, "U1_CPLD.C9" : {}, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "U1_XF.BW29" : {}, "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } } } } } } } } } } }, "U12.6" : {}, "U1_CPLD.A9" : {} } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } } } }, "E1S_REF_CLK_P<3>" : { "C16_E3_XF.1" : { "C16_E3_XF.2" : { "CLKIN_P_E3" : { "R14_E3_XF.2" : { "R14_E3_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_E3_XF.5" : {}, "R16_E3_XF.1" : { "R16_E3_XF.2" : { "GND" : {} } } } } }, "U1.38" : {} }, "C2_DDR4_VREFCA_1_XF" : { "R254_XF.1" : { "R254_XF.2" : { "GND" : {} } }, "J3_XF.146" : {}, "R253_XF.1" : { "R253_XF.2" : { "PWR_NDIMM_VDD_XF" : {} } }, "C199_XF.1" : { "C199_XF.2" : { "GND" : {} } }, "C200_XF.1" : { "C200_XF.2" : { "GND" : {} } } }, "UNNAMED_17_RESISTOR_I55_A_XF" : { "R102_XF.2" : { "R102_XF.1" : { "VMON_AVCC_SW_XF" : { "R100_SP_XF.2" : { "R100_SP_XF.1" : { "PWR_AVCC_SW_XF" : {} } } } } }, "R78_XF.1" : { "R78_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I50_A_XF" : { "U1_XF.CB38" : {}, "C139_XF.1" : { "C139_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I50_B_XF" : { "R79_XF.2" : { "R79_XF.1" : { "UNNAMED_17_RESISTOR_I56_A_XF" : { "R67_XF.2" : { "R67_XF.1" : { "GND" : {} } }, "R104_XF.2" : { "R104_XF.1" : { "GND" : {} } } } } }, "U1_XF.CB39" : {} } } } } } }, "R103_XF.2" : { "R103_XF.1" : { "GND" : {} } } }, "PCIE0_REFN_XF" : { "R2_P0_XF.2" : { "R2_P0_XF.1" : { "UNNAMED_3_OCULINKX4CONN_I86_REFCLKN_P0" : { "J1_P0_XF.B13" : {} } } }, "C288_XF.1" : { "C288_XF.2" : { "AC_PCIE0_REFN_XF" : { "U1_XF.BB12" : {} } } } }, "AC_E1S3_PET_P<6>_XF" : { "U1_XF.AK9" : {}, "C234_XF.1" : { "C234_XF.2" : { "E1S3_PET_P<6>_XF" : { "J1_E3_XF.B37" : {} } } } }, "OCL3_PET_N<3>_XF" : { "C278_XF.2" : { "C278_XF.1" : { "AC_OCL3_PET_N<3>_XF" : { "U1_XF.BG6" : {} } } }, "J1_O3_XF.B19" : {} }, "OCL3_CONN_REFCLK_N_XF" : { "J1_O3_XF.B13" : {}, "C387_XF.2" : { "C387_XF.1" : { "AC_OCL3_CONN_REFCLK_N_XF" : { "U5_XF.18" : {} } } } }, "C2_DDR4_DQ<10>_XF" : { "U1_XF.R48" : {}, "J3_XF.23" : {} }, "AC_OCL0_CONN_REFCLK_N_XF" : { "U7_XF.14" : {}, "C384_XF.1" : { "C384_XF.2" : { "OCL0_CONN_REFCLK_N_XF" : { "J1_O0_XF.B13" : {} } } } }, "C3_RDIMM_DQS_C<14>_XF" : { "U1_XF.A22" : {}, "J4_XF.111" : {} }, "UNNAMED_11_RESISTOR_I769_B_XF" : { "R154_XF.2" : { "R154_XF.1" : { "PCIE0_RST_F" : { "U1_CPLD.G13" : {} } } }, "U1_XF.BK34" : {}, "R155_XF.2" : { "R155_XF.1" : { "GND" : {} } } }, "CONN_CLK_REFN<1>_E2" : { "J1_E2_XF.A14" : {}, "C24_E2_XF.2" : { "C24_E2_XF.1" : { "AC_CONN_CLK_REFN<1>_3" : { "U1_E2_XF.18" : {} } } } }, "C1_DDR4_DQ<65>_XF" : { "J2_XF.194" : {}, "U1_XF.BU60" : {} }, "UNNAMED_3_LTM4675_I40_COMP1A_ND" : { "PM4_ND_XF.H6" : { "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U1_CPLD.C9" : {} } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } } } }, "PM4_ND_XF.D6" : { "UNNAMED_3_LTM4675_I40_COMP0B_ND" : {} }, "PM4_ND_XF.J6" : { "UNNAMED_3_LTM4675_I40_COMP0B_ND" : {} } }, "R109_ND_XF.2" : { "R109_ND_XF.1" : { "UNNAMED_3_LTM4675_I40_COMP0B_ND" : {} } } }, "C0_DDR4_ADR<8>_XF" : { "U1_XF.BW20" : {}, "J1_XF.68" : {} }, "E1S1_PET_P<3>_XF" : { "J1_E1_XF.B27" : {}, "C114_XF.2" : { "C114_XF.1" : { "AC_E1S1_PET_P<3>_XF" : { "U1_XF.L11" : {} } } } }, "C3_DDR4_DQ<33>_XF" : { "U1_XF.A25" : {}, "J4_XF.242" : {} }, "C1_DDR4_ADR<0>_XF" : { "U1_XF.CA52" : {}, "J2_XF.79" : {} }, "VMON_VCCAUX_SW" : { "R121_SP_XF.2" : { "R121_SP_XF.1" : { "PWR_VCCAUX_SW_XF" : {} } }, "R48.2" : { "R48.1" : { "UNNAMED_4_MAX116XXQSOP16_I97_AIN0" : { "R36.1" : { "R36.2" : { "GND" : {} } }, "U11.5" : {}, "C49.1" : { "C49.2" : { "GND" : {} } } } } } }, "AC_E1S3_PET_N<7>_XF" : { "C174_XF.1" : { "C174_XF.2" : { "E1S3_PET_N<7>_XF" : { "J1_E3_XF.B39" : {} } } }, "U1_XF.AJ10" : {} }, "UNNAMED_17_RESISTOR_I124_A_XF" : { "R132_XF.1" : { "R132_XF.2" : { "UNNAMED_17_RESISTOR_I122_A_XF" : { "R144_XF.1" : { "R144_XF.2" : { "GND" : {} } }, "R145_XF.1" : { "R145_XF.2" : { "GND" : {} } } } } }, "U1_XF.BY30" : {}, "C269_XF.2" : { "C269_XF.1" : { "UNNAMED_17_RESISTOR_I121_A_XF" : { "R131_XF.1" : { "R131_XF.2" : { "UNNAMED_17_RESISTOR_I119_A_XF" : { "R143_XF.1" : { "R143_XF.2" : { "GND" : {} } }, "R142_XF.1" : { "R142_XF.2" : { "VMON_AVTT_SW_XF" : { "R99_SP_XF.2" : { "R99_SP_XF.1" : { "PWR_AVTT_SW_XF" : {} } } } } } } } }, "U1_XF.BY29" : {} } } } }, "C1_DDR4_BG<1>_XF" : { "U1_XF.CC52" : {}, "J2_XF.207" : {} }, "E1S0_3R3V_PWRDIS_XF" : { "J1_E0_XF.B12" : {}, "U1_XF.AA18" : {} }, "C2_DDR4_DQ<49>_XF" : { "J3_XF.264" : {}, "U1_XF.G50" : {} }, "E1S3_PET_P<7>_XF" : { "J1_E3_XF.B40" : {}, "C235_XF.2" : { "C235_XF.1" : { "AC_E1S3_PET_P<7>_XF" : { "U1_XF.AJ11" : {} } } } }, "UNNAMED_8_LT3071_I30_IMON_FL" : { "R82_FL_XF.1" : { "R82_FL_XF.2" : { "IMON_AVTT_LIN_XF" : { "R25_FL_XF.2" : { "R25_FL_XF.1" : { "UNNAMED_6_LT3071_I30_IMON_FL" : { "U2_FL_XF.21" : {} } } }, "R64_FL_XF.2" : { "R64_FL_XF.1" : { "UNNAMED_7_LT3071_I30_IMON_FL" : { "U4_FL_XF.21" : {} } } }, "R24_FL_XF.2" : { "R24_FL_XF.1" : { "UNNAMED_5_LT3071_I30_IMON_FL" : { "U1_FL_XF.21" : {} } } }, "R133_XF.2" : { "R133_XF.1" : { "UNNAMED_17_RESISTOR_I101_A_XF" : { "R127_XF.2" : { "R127_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I107_A_XF" : { "U1_XF.CB33" : {}, "C267_XF.1" : { "C267_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I107_B_XF" : { "R128_XF.1" : { "R128_XF.2" : { "UNNAMED_17_RESISTOR_I104_A_XF" : { "R135_XF.1" : { "R135_XF.2" : { "GND" : {} } }, "R136_XF.1" : { "R136_XF.2" : { "UNNAMED_17_RESISTOR_I105_B_XF" : { "R121_XF.1" : { "R121_XF.2" : { "GND" : {} } } } } } } } }, "U1_XF.CC33" : {} } } } } } }, "R134_XF.1" : { "R134_XF.2" : { "UNNAMED_17_RESISTOR_I101_B_XF" : { "R120_XF.1" : { "R120_XF.2" : { "GND" : {} } } } } } } } } } } }, "R26_FL_XF.2" : { "R26_FL_XF.1" : { "GND" : {} } }, "U5_FL_XF.21" : {} }, "AC_PCIE1_REFP_XF" : { "C230_XF.2" : { "C230_XF.1" : { "PCIE1_REFP_XF" : { "R1_P1_XF.2" : { "R1_P1_XF.1" : { "UNNAMED_3_OCULINKX4CONN_I86_REFCLKP_P1" : { "J1_P1_XF.B12" : {} } } } } } }, "U1_XF.AU15" : {} }, "C2_DDR4_DQ<37>_XF" : { "J3_XF.240" : {}, "U1_XF.C56" : {} }, "E1S2_PER_P<3>_XF" : { "J1_E2_XF.A27" : {}, "U1_XF.W2" : {} }, "E1S0_PET_N<6>_XF" : { "C119_XF.2" : { "C119_XF.1" : { "AC_E1S0_PET_N<6>_XF" : { "U1_XF.D8" : {} } } }, "J1_E0_XF.B36" : {} }, "C2_RDIMM_DQS_T<13>_XF" : { "U1_XF.E55" : {}, "J3_XF.99" : {} }, "VDDO4" : { "R12.2" : { "R12.1" : { "CPLD_P1R8V_1" : {} } }, "C7.1" : { "C7.2" : { "GND" : {} } }, "U1.36" : {} }, "C3_RDIMM_DQS_C<2>_XF" : { "J4_XF.174" : {}, "U1_XF.G28" : {} }, "UNNAMED_7_RESISTOR_I53_A_SP" : { "R71_SP_XF.1" : { "R71_SP_XF.2" : { "UNNAMED_7_LTM4671_I36_FB3_SP" : { "PM1_SP_XF.N10" : { "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} } } } } } } }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} } } } } } }, "UNNAMED_4_BYPASSCAPNPOL_I13_B_SD" : { "U2_SD_XF.6" : {}, "C32_SD_XF.2" : { "C32_SD_XF.1" : { "GND" : {} } } }, "JT_CPLD_INST_F" : { "U4_CPLD.6" : {}, "J5.18" : {}, "R88.2" : { "R88.1" : { "CPLD_P1R8V_1" : {} } }, "U2_CPLD.6" : {}, "U3_CPLD.6" : {} }, "AC_PCIE0_TXP<0>_XF" : { "C41_XF.1" : { "C41_XF.2" : { "PCIE0_TXP<0>_XF" : { "J1_P0_XF.B3" : {} } } }, "U1_XF.AU11" : {} }, "C0_DDR4_PARITY_XF" : { "J1_XF.222" : {}, "U1_XF.CB20" : {} }, "C0_RDIMM_DQS_C<12>_XF" : { "U1_XF.BU23" : {}, "J1_XF.41" : {} }, "DDR4_SYS_CLK_P<3>_XF" : { "C366_XF.1" : { "C366_XF.2" : { "C3_SYS_CLK_P_XF" : { "R257_XF.2" : { "R257_XF.1" : { "PWR_NDIMM_VDD_XF" : {} } }, "R258_XF.1" : { "R258_XF.2" : { "GND" : {} } }, "U1_XF.P25" : {} } } }, "U6_XF.10" : {} }, "PWR_SPARE_SW_XF" : { "C115_SP_XF.1" : { "C115_SP_XF.2" : { "GND" : {} } }, "PM1_SP_XF.W2" : {}, "C119_SP_XF.1" : { "C119_SP_XF.2" : { "GND" : {} } }, "PWR_SPARE_SW_XF.1" : {}, "PM1_SP_XF.U3" : {}, "PM1_SP_XF.R2" : {}, "PM1_SP_XF.T3" : {}, "PM1_SP_XF.T1" : {}, "PM1_SP_XF.U1" : {}, "PM1_SP_XF.V2" : {}, "C111_SP_XF.1" : { "C111_SP_XF.2" : { "GND" : {} } }, "PM1_SP_XF.R1" : {}, "R122_SP_XF.1" : { "R122_SP_XF.2" : { "VMON_SPARE_SW_XF" : { "VMON_SPARE_SW_XF.1" : {} } } }, "PM1_SP_XF.V3" : {}, "PM1_SP_XF.V1" : {}, "PM1_SP_XF.U2" : {}, "PM1_SP_XF.T2" : {}, "PM1_SP_XF.W3" : {}, "PM1_SP_XF.N11" : {}, "PM1_SP_XF.W1" : {} }, "CPLD_PWR_ALERT_OD_F" : { "U1_CPLD.N6" : {}, "J5.1" : {} }, "C3_DDR4_DQ<20>_XF" : { "J4_XF.25" : {}, "U1_XF.F28" : {} }, "PWR_AVTT_SW_XF" : { "PM2_SP_XF.R2" : {}, "U2_FL_XF.6" : {}, "C28_FL_XF.1" : { "C28_FL_XF.2" : { "GND" : {} } }, "U1_FL_XF.8" : {}, "C93_SP_XF.1" : { "C93_SP_XF.2" : { "GND" : {} } }, "PM2_SP_XF.W2" : {}, "C46_FL_XF.1" : { "C46_FL_XF.2" : { "GND" : {} } }, "C88_SP_XF.1" : { "C88_SP_XF.2" : { "GND" : {} } }, "C51_FL_XF.1" : { "C51_FL_XF.2" : { "GND" : {} } }, "C89_SP_XF.1" : { "C89_SP_XF.2" : { "GND" : {} } }, "PM2_SP_XF.B2" : {}, "PM2_SP_XF.A2" : {}, "PM2_SP_XF.E2" : {}, "C47_FL_XF.1" : { "C47_FL_XF.2" : { "GND" : {} } }, "U1_FL_XF.5" : {}, "PM2_SP_XF.U2" : {}, "PM2_SP_XF.G8" : {}, "PM2_SP_XF.C2" : {}, "U5_FL_XF.5" : {}, "PM2_SP_XF.D1" : {}, "U4_FL_XF.8" : {}, "PM2_SP_XF.D3" : {}, "C23_FL_XF.1" : { "C23_FL_XF.2" : { "GND" : {} } }, "U2_FL_XF.7" : {}, "C30_FL_XF.1" : { "C30_FL_XF.2" : { "GND" : {} } }, "PM2_SP_XF.T2" : {}, "U4_FL_XF.5" : {}, "PM2_SP_XF.V1" : {}, "U5_FL_XF.8" : {}, "PM2_SP_XF.V3" : {}, "PM2_SP_XF.U1" : {}, "C43_FL_XF.1" : { "C43_FL_XF.2" : { "GND" : {} } }, "PM2_SP_XF.E1" : {}, "C96_SP_XF.1" : { "C96_SP_XF.2" : { "GND" : {} } }, "PM2_SP_XF.U3" : {}, "U2_FL_XF.8" : {}, "PM2_SP_XF.A3" : {}, "PM2_SP_XF.B1" : {}, "U1_FL_XF.6" : {}, "U5_FL_XF.7" : {}, "PM2_SP_XF.B3" : {}, "PM2_SP_XF.A1" : {}, "PM2_SP_XF.W1" : {}, "C97_SP_XF.1" : { "C97_SP_XF.2" : { "GND" : {} } }, "U2_FL_XF.5" : {}, "C50_FL_XF.1" : { "C50_FL_XF.2" : { "GND" : {} } }, "C92_SP_XF.1" : { "C92_SP_XF.2" : { "GND" : {} } }, "PM2_SP_XF.W3" : {}, "U4_FL_XF.7" : {}, "PM2_SP_XF.R1" : {}, "PM2_SP_XF.V2" : {}, "C26_FL_XF.1" : { "C26_FL_XF.2" : { "GND" : {} } }, "PM2_SP_XF.T1" : {}, "PM2_SP_XF.T3" : {}, "C48_FL_XF.1" : { "C48_FL_XF.2" : { "GND" : {} } }, "R99_SP_XF.1" : { "R99_SP_XF.2" : { "VMON_AVTT_SW_XF" : { "R142_XF.2" : { "R142_XF.1" : { "UNNAMED_17_RESISTOR_I119_A_XF" : {} } } } } }, "U4_FL_XF.6" : {}, "PM2_SP_XF.D2" : {}, "PM2_SP_XF.C1" : {}, "PM2_SP_XF.C3" : {}, "U5_FL_XF.6" : {}, "C55_FL_XF.1" : { "C55_FL_XF.2" : { "GND" : {} } }, "C49_FL_XF.1" : { "C49_FL_XF.2" : { "GND" : {} } }, "U1_FL_XF.7" : {} }, "UNNAMED_17_RESISTOR_I196_A_XF" : { "R14_XF.2" : { "R14_XF.1" : { "IMON_VCCAUX_LIN_XF" : { "R90_FL_XF.1" : { "R90_FL_XF.2" : { "UNNAMED_9_LT3071_I30_IMON_FL" : { "IMON_VCCAUX_A_TP_FL_XF.1" : {}, "U7_FL_XF.21" : {} } } }, "IMON_VCCAUX_TP_FL_XF.1" : {}, "R113_FL_XF.1" : { "R113_FL_XF.2" : { "UNNAMED_9_LT3071_I66_IMON_FL" : { "IMON_VCCAUX_B_TP_FL_XF.1" : {}, "U11_FL_XF.21" : {} } } } } } }, "R25_XF.1" : { "R25_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I198_A_XF" : { "U1_XF.BW39" : {}, "C315_XF.1" : { "C315_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I198_B_XF" : { "U1_XF.BW40" : {}, "R26_XF.2" : { "R26_XF.1" : { "UNNAMED_17_RESISTOR_I199_A_XF" : { "R21_XF.2" : { "R21_XF.1" : { "GND" : {} } }, "R23_XF.2" : { "R23_XF.1" : { "UNNAMED_17_RESISTOR_I202_A_XF" : { "R13_XF.2" : { "R13_XF.1" : { "GND" : {} } } } } } } } } } } } } } }, "R17_XF.2" : { "R17_XF.1" : { "UNNAMED_17_RESISTOR_I201_A_XF" : { "R10_XF.2" : { "R10_XF.1" : { "GND" : {} } } } } } }, "ID_LED_N" : { "U1_CPLD.H13" : {}, "FPNL_CONN.6" : {} }, "AC_OCL1_PET_N<0>_XF" : { "U1_XF.CA6" : {}, "C273_XF.1" : { "C273_XF.2" : { "OCL1_PET_N<0>_XF" : { "J1_O1_XF.B4" : {} } } } }, "OCL3_3R3V_PERST_F_XF" : { "U1_XF.BB19" : {}, "J1_O3_XF.A12" : {} }, "PCIE1_TXP<2>_XF" : { "C31_XF.2" : { "C31_XF.1" : { "AC_PCIE1_TXP<2>_XF" : { "U1_XF.AN11" : {} } } }, "J1_P1_XF.B15" : {} }, "VMON_AVCC_SW_XF" : { "R100_SP_XF.2" : { "R100_SP_XF.1" : { "PWR_AVCC_SW_XF" : {} } }, "R102_XF.1" : { "R102_XF.2" : { "UNNAMED_17_RESISTOR_I55_A_XF" : { "R78_XF.1" : { "R78_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I50_A_XF" : { "U1_XF.CB38" : {}, "C139_XF.1" : { "C139_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I50_B_XF" : { "R79_XF.2" : { "R79_XF.1" : { "UNNAMED_17_RESISTOR_I56_A_XF" : { "R67_XF.2" : { "R67_XF.1" : { "GND" : {} } }, "R104_XF.2" : { "R104_XF.1" : { "GND" : {} } } } } }, "U1_XF.CB39" : {} } } } } } }, "R103_XF.2" : { "R103_XF.1" : { "GND" : {} } } } } } }, "RFU_<1>_E2" : { "J1_E2_XF.A42" : {} }, "C1_DDR4_DQ<56>_XF" : { "J2_XF.130" : {}, "U1_XF.BM55" : {} }, "UNNAMED_29_PI6CB33401_I63_OE2F_XF" : { "U5_XF.24" : {}, "R9_XF.2" : { "R9_XF.1" : { "GND" : {} } }, "U5_XF.29" : {} }, "VREF_P1R25V_XF" : { "U9_XF.4" : {}, "R84_XF.1" : { "R84_XF.2" : { "VCCADC_XF" : { "U1_XF.AL25" : {}, "FB2_XF.1" : { "FB2_XF.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "C143_XF.1" : { "C143_XF.2" : { "GNDADC_XF" : {} } } } } }, "U1_XF.AN25" : {}, "C142_XF.1" : { "C142_XF.2" : { "GNDADC_XF" : {} } }, "U9_XF.3" : {} }, "AC_PCIE0_TXP<1>_XF" : { "U1_XF.AV9" : {}, "C40_XF.1" : { "C40_XF.2" : { "PCIE0_TXP<1>_XF" : { "J1_P0_XF.B6" : {} } } } }, "UNNAMED_4_BYPASSCAPNPOL_I51_B" : { "C42.2" : { "C42.1" : { "GND" : {} } }, "U11.11" : {}, "R75.2" : { "R75.1" : { "GND" : {} } }, "R52.2" : { "R52.1" : { "VMON_SDIMM_VPP_SW" : { "R124_SP_XF.2" : { "R124_SP_XF.1" : { "PWR_SDIMM_VPP_XF" : {} } } } } } }, "E1S2_PER_P<6>_XF" : { "J1_E2_XF.A37" : {}, "U1_XF.AC2" : {} }, "E1S0_PET_N<3>_XF" : { "J1_E0_XF.B26" : {}, "C126_XF.2" : { "C126_XF.1" : { "AC_E1S0_PET_N<3>_XF" : { "U1_XF.A6" : {} } } } }, "C2_DDR4_DQ<67>_XF" : { "U1_XF.C57" : {}, "J3_XF.201" : {} }, "C1_DDR4_DQ<41>_XF" : { "J2_XF.253" : {}, "U1_XF.BK62" : {} }, "SW1_4650_BR_SP" : { "PM7_SP_XF.G2" : { "PM7_SP_XF.H6" : { "GND" : {} }, "PM7_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM7_SP_XF.J7" : { "NC" : {} }, "PM7_SP_XF.H4" : { "GND" : {} }, "PM7_SP_XF.D2" : { "GND" : {} }, "PM7_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C5" : { "NC" : {} }, "PM7_SP_XF.B6" : { "GND" : {} }, "PM7_SP_XF.E4" : { "GND" : {} }, "PM7_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G3" : { "GND" : {} }, "PM7_SP_XF.G6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F11" : { "GND" : {} }, "PM7_SP_XF.J8" : { "GND" : {} }, "PM7_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H5" : { "GND" : {} }, "PM7_SP_XF.H3" : { "GND" : {} }, "PM7_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM7_SP_XF.E3" : { "GND" : {} }, "PM7_SP_XF.D10" : { "GND" : {} }, "PM7_SP_XF.G7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K1" : { "GND" : {} }, "PM7_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H10" : { "GND" : {} }, "PM7_SP_XF.J5" : { "GND" : {} }, "PM7_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E10" : { "GND" : {} }, "PM7_SP_XF.D3" : { "GND" : {} }, "PM7_SP_XF.C7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F12" : { "GND" : {} }, "PM7_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.M12" : { "GND" : {} }, "PM7_SP_XF.H7" : { "GND" : {} }, "PM7_SP_XF.F1" : { "GND" : {} }, "PM7_SP_XF.E2" : { "GND" : {} }, "PM7_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.H2" : { "GND" : {} }, "PM7_SP_XF.M1" : { "GND" : {} }, "PM7_SP_XF.D4" : { "GND" : {} }, "PM7_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } } } }, "PM7_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B7" : { "GND" : {} }, "PM7_SP_XF.D6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.G10" : { "GND" : {} }, "PM7_SP_XF.C8" : { "NC" : {} }, "PM7_SP_XF.K12" : { "GND" : {} }, "PM7_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E12" : { "GND" : {} }, "PM7_SP_XF.H12" : { "GND" : {} }, "PM7_SP_XF.D9" : { "GND" : {} }, "PM7_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A6" : { "GND" : {} }, "PM7_SP_XF.F10" : { "GND" : {} }, "PM7_SP_XF.K7" : { "GND" : {} }, "PM7_SP_XF.D11" : { "GND" : {} }, "PM7_SP_XF.G1" : { "GND" : {} }, "PM7_SP_XF.F8" : { "NC" : {} }, "PM7_SP_XF.G12" : { "GND" : {} }, "PM7_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E1" : { "GND" : {} }, "PM7_SP_XF.F2" : { "GND" : {} }, "PM7_SP_XF.K8" : { "GND" : {} }, "PM7_SP_XF.H1" : { "GND" : {} }, "PM7_SP_XF.F7" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.K5" : { "GND" : {} }, "PM7_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.D1" : { "GND" : {} }, "PM7_SP_XF.J1" : { "GND" : {} }, "PM7_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.F6" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.L12" : { "GND" : {} }, "PM7_SP_XF.E9" : { "SGND_PM7_SP" : {} }, "PM7_SP_XF.F3" : { "GND" : {} }, "PM7_SP_XF.H9" : { "GND" : {} }, "PM7_SP_XF.L1" : { "GND" : {} }, "PM7_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.A7" : { "GND" : {} }, "PM7_SP_XF.D12" : { "GND" : {} }, "PM7_SP_XF.J12" : { "GND" : {} }, "PM7_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.E11" : { "GND" : {} }, "PM7_SP_XF.H11" : { "GND" : {} }, "PM7_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM7_SP_XF.K6" : { "GND" : {} } } }, "POK_OD_VCCINT_BLSW_P<0>" : { "R29_SP_XF.2" : { "R29_SP_XF.1" : { "UNNAMED_10_LTM4650FIXED_I151_PGOOD1_SP" : { "PM3_SP_XF.G9" : { "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } } } }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.G3" : { "GND" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} } } } } }, "U1_CPLD.P11" : {} }, "C0_RDIMM_DQS_T<14>_XF" : { "J1_XF.110" : {}, "U1_XF.BL28" : {} }, "UNNAMED_6_RESISTOR_I463_A_SP" : { "R54_SP_XF.1" : { "R54_SP_XF.2" : { "UNNAMED_6_LTM4671_I457_FB1_SP" : { "PM2_SP_XF.H9" : { "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : {} } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N16" : {} } }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} } } } } } }, "C3_RDIMM_DQS_C<4>_XF" : { "U1_XF.C26" : {}, "J4_XF.244" : {} }, "PSU_1R8V_SDA" : { "U1_XF.CA37" : {}, "R19.1" : { "R19.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "Q11.2" : { "Q11.3" : { "PSU_3R3V_SDA" : {} }, "Q11.1" : { "UNNAMED_12_NMOSFETVMT3_I12_G" : { "R7.2" : { "R7.1" : { "UNNAMED_12_RESISTOR_I13_A" : { "R1.2" : { "R1.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "R4.2" : { "R4.1" : { "DIS_1R8V_I2C_XLAT_F" : { "U1_CPLD.H3" : {}, "R58.1" : { "R58.2" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } } }, "U11.13" : {} } } } } } } } } } } } }, "R8.1" : { "R8.2" : { "UNNAMED_12_NMOSFETVMT3_I4_G" : { "Q10.1" : { "Q10.3" : { "PSU_3R3V_SCL" : { "R25.2" : { "R25.1" : { "P3R3V" : {} } }, "J4.1" : {} } }, "Q10.2" : { "PSU_1R8V_SCL" : { "R9.1" : { "R9.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.CA35" : {} } } } } } } } } } } } } }, "UNNAMED_4_BYPASSCAPNPOL_I12_B_MP" : { "U2_MP.10" : {}, "L2_MP.1" : { "L2_MP.2" : { "CPLD_P3R3V" : {} } }, "U2_MP.12" : {}, "U2_MP.11" : {}, "C11_MP.2" : { "C11_MP.1" : { "UNNAMED_4_BYPASSCAPNPOL_I12_A_MP" : { "U2_MP.13" : {} } } } }, "AC_OCL2_PET_P<3>_XF" : { "U1_XF.BK9" : {}, "C233_XF.1" : { "C233_XF.2" : { "OCL2_PET_P<3>_XF" : { "J1_O2_XF.B18" : {} } } } }, "C0_SYS_CLK_P_XF" : { "R33_XF.2" : { "R33_XF.1" : { "PWR_SDIMM_VDD_XF" : {} } }, "C360_XF.2" : { "C360_XF.1" : { "DDR4_SYS_CLK_P<0>_XF" : { "U6_XF.16" : {} } } }, "U1_XF.BY20" : {}, "R236_XF.1" : { "R236_XF.2" : { "GND" : {} } }, "R238_XF.1" : { "R238_XF.2" : { "C0_SYS_CLK_N_XF" : {} } } }, "DAC_VCCAUX_LIN_XF" : { "R108_FL_XF.1" : { "R108_FL_XF.2" : { "UNNAMED_9_BYPASSCAPNPOL_I59_B_FL" : { "C104_FL_XF.2" : { "C104_FL_XF.1" : { "GND" : {} } }, "R112_FL_XF.1" : { "R112_FL_XF.2" : { "UNNAMED_9_LT3071_I66_MARGA_FL" : { "U11_FL_XF.22" : {} } } } } } }, "R77_FL_XF.1" : { "R77_FL_XF.2" : { "UNNAMED_9_BYPASSCAPNPOL_I25_B_FL" : { "C75_FL_XF.2" : { "C75_FL_XF.1" : { "GND" : {} } }, "R81_FL_XF.1" : { "R81_FL_XF.2" : { "UNNAMED_9_LT3071_I30_MARGA_FL" : { "U7_FL_XF.22" : {} } } } } } }, "U1_SP_XF.54" : {} }, "TDO_JTAG_CTL" : { "U1_XF.CB31" : {}, "U1_CPLD.E1" : {} }, "SW1_4650_TL_SP" : { "PM4_SP_XF.G2" : { "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G9" : { "UNNAMED_4_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} } } }, "E1S3_PET_P<5>_XF" : { "J1_E3_XF.B34" : {}, "C327_XF.2" : { "C327_XF.1" : { "AC_E1S3_PET_P<5>_XF" : { "U1_XF.AK13" : {} } } } }, "AC_E1S3_PET_N<0>_XF" : { "C314_XF.1" : { "C314_XF.2" : { "E1S3_PET_N<0>_XF" : { "J1_E3_XF.B17" : {} } } }, "U1_XF.AH12" : {} }, "OCL3_PER_P<2>_XF" : { "U1_XF.BH4" : {}, "J1_O3_XF.A15" : {} }, "E1S2_3R3V_CKEN_F<0>_XF" : { "U1_XF.M18" : {}, "U1_E2_XF.12" : {} }, "UNNAMED_12_LT3071_I30_V00_FL" : { "R100_FL_XF.2" : { "R100_FL_XF.1" : { "GND" : {} } }, "R95_FL_XF.1" : { "R95_FL_XF.2" : { "P3R3V" : {} } }, "U10_FL_XF.23" : {} }, "C2_DDR4_DQ<9>_XF" : { "J3_XF.161" : {}, "U1_XF.R49" : {} }, "C0_DDR4_DQ<55>_XF" : { "J1_XF.269" : {}, "U1_XF.BK24" : {} }, "PCIE0_TXN<0>_XF" : { "C86_XF.2" : { "C86_XF.1" : { "AC_PCIE0_TXN<0>_XF" : { "U1_XF.AU10" : {} } } }, "J1_P0_XF.B4" : {} }, "UNNAMED_6_LTM4671_I456_FB3_SP" : { "PM2_SP_XF.N10" : { "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : {} } } } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} } }, "R109_SP_XF.2" : { "R109_SP_XF.1" : { "UNNAMED_6_RESISTOR_I222_A_SP" : { "R97_SP_XF.2" : { "R97_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "R8_SP_XF.2" : { "R8_SP_XF.1" : { "UNNAMED_6_RESISTOR_I409_A_SP" : { "R41_SP_XF.2" : { "R41_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } } }, "C0_DDR4_ADR<4>_XF" : { "J1_XF.214" : {}, "U1_XF.CA20" : {} }, "E1S1_PER_N<2>_XF" : { "U1_XF.N1" : {}, "J1_E1_XF.A23" : {} }, "AC_E1S0_PET_P<3>_XF" : { "C106_XF.1" : { "C106_XF.2" : { "E1S0_PET_P<3>_XF" : { "J1_E0_XF.B27" : {} } } }, "U1_XF.A7" : {} }, "UNNAMED_4_BYPASSCAPNPOL_I12_A_MP" : { "C11_MP.1" : { "C11_MP.2" : { "UNNAMED_4_BYPASSCAPNPOL_I12_B_MP" : { "U2_MP.11" : {}, "L2_MP.1" : { "L2_MP.2" : { "CPLD_P3R3V" : {} } }, "U2_MP.10" : {}, "U2_MP.12" : {} } } }, "U2_MP.13" : {} }, "FSET_4650_TR_SP" : { "PM5_SP_XF.C6" : { "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.G6" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D6" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } } } }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.G7" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.C7" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.F7" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.E9" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.F6" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} } }, "R9_SP_XF.2" : { "R9_SP_XF.1" : { "SGND_PM5_SP" : {} } } }, "SI5334_TP_CLK_N<3>" : { "U1.58" : {}, "SI5334_TP_N.1" : {} }, "C0_DDR4_DQ<2>_XF" : { "U1_XF.BY25" : {}, "J1_XF.12" : {} }, "C0_DDR4_ADR<2>_XF" : { "J1_XF.216" : {}, "U1_XF.CB21" : {} }, "C3_DDR4_BG<0>_XF" : { "U1_XF.U25" : {}, "J4_XF.63" : {} }, "UNNAMED_3_LTM4675_I40_WP_SD" : { "PM4_SD_XF.K4" : { "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "PS_ON_N" : { "Q5.3" : { "Q5.2" : { "GND" : {} }, "Q5.1" : { "UNNAMED_19_NMOSFETVMT3_I39_G" : { "R57.1" : { "R57.2" : { "PSU_PWR_ON" : { "U1_CPLD.P7" : {}, "R61.1" : { "R61.2" : { "GND" : {} } } } } } } } }, "J3.16" : {} }, "CFG_FLASH_RST_F" : { "R37_XF.2" : { "R37_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_CPLD.D3" : {}, "U2_XF.A4" : {}, "R34_XF.2" : { "R34_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U3_XF.A4" : {} }, "UNNAMED_15_MAX4641_I1_IN2_XF" : { "Q1_XF.3" : { "Q1_XF.2" : { "GND" : {} }, "Q1_XF.1" : { "UNNAMED_15_NMOSFETVMT3_I42_G_XF" : { "R114_XF.2" : { "R114_XF.1" : { "CPLD_SEL_CFG_FLASH" : { "U1_CPLD.J4" : {}, "U4_XF.7" : {} } } } } } }, "U4_XF.3" : {}, "R116_XF.1" : { "R116_XF.2" : { "FPGA_VCCAUX_P1R8V" : {} } } }, "UNNAMED_10_RESISTOR_I69_B" : { "R112.2" : { "R112.1" : { "BASE_1R8V_SDA" : { "Q4.2" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "U11.14" : {} } }, "Q4.1" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "R5.2" : { "R5.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R3.1" : { "R3.2" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "Q3.1" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.3" : { "BASE_3R3V_SCL_2" : { "U1_CPLD.A9" : {}, "U12.6" : {}, "U11.13" : {}, "R34.2" : { "R34.1" : { "P3R3V" : {} } }, "Q1.3" : { "Q1.1" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "R32.2" : { "R32.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R31.1" : { "R31.2" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "Q2.1" : { "Q2.3" : { "BASE_3R3V_SDA_2" : {} } } } } } } } } } }, "Q1.2" : { "FPGA_1R8V_SCL" : { "R33.1" : { "R33.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } } } } } } } } } } } } } } } } }, "U1.18" : {} }, "OCL2_PET_N<0>_XF" : { "J1_O2_XF.B4" : {}, "C277_XF.2" : { "C277_XF.1" : { "AC_OCL2_PET_N<0>_XF" : { "U1_XF.BN10" : {} } } } }, "C2_DDR4_DQ<21>_XF" : { "J3_XF.170" : {}, "U1_XF.E60" : {} }, "UNNAMED_3_LTM4675_I40_FSWPHCFG_SD" : { "PM4_SD_XF.H2" : { "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "AC_E1S0_PET_N<4>_XF" : { "C125_XF.1" : { "C125_XF.2" : { "E1S0_PET_N<4>_XF" : { "J1_E0_XF.B30" : {} } } }, "U1_XF.F8" : {} }, "VFB_4650_SP" : { "PM4_SP_XF.D5" : { "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} } }, "R11_SP_XF.2" : { "R11_SP_XF.1" : { "UNNAMED_4_RESISTOR_I12_B_SP" : { "R12_SP_XF.2" : { "R12_SP_XF.1" : { "SGND_PM4_SP" : {} } } } } } }, "AC_E1S1_PET_P<5>_XF" : { "U1_XF.T9" : {}, "C112_XF.1" : { "C112_XF.2" : { "E1S1_PET_P<5>_XF" : { "J1_E1_XF.B34" : {} } } } }, "UNNAMED_3_LTM4675_I40_WP_ND" : { "PM4_ND_XF.K4" : { "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U1_CPLD.C9" : {} } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } } } }, "E1S3_PER_P<4>_XF" : { "J1_E3_XF.A31" : {}, "U1_XF.AM4" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I143_A_SP" : { "C25_SP_XF.1" : { "C25_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.47" : {}, "R46_SP_XF.1" : { "R46_SP_XF.2" : { "IS_VCCINTUR_SW_P_SP" : { "C182_SP_XF.1" : { "C182_SP_XF.2" : { "GND" : {} } }, "R194_SP_XF.2" : { "R194_SP_XF.1" : { "GND" : {} } }, "R193_SP_XF.1" : { "R193_SP_XF.2" : { "UNNAMED_9_ACS711_I5_VIOUT_SP" : { "U2_SP_XF.11" : {} } } } } } } }, "C1_DDR4_ACT_N_XF" : { "U1_XF.BY53" : {}, "J2_XF.62" : {} }, "C1_DDR4_DQ<29>_XF" : { "J2_XF.181" : {}, "U1_XF.CB59" : {} }, "E1S_REF_CLK_N<2>" : { "C17_E2_XF.1" : { "C17_E2_XF.2" : { "CLKIN_N_E2" : { "U1_E2_XF.6" : {}, "R15_E2_XF.2" : { "R15_E2_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R18_E2_XF.1" : { "R18_E2_XF.2" : { "GND" : {} } } } } }, "U1.34" : {} }, "DIS_1R8V_I2C_XLAT_F" : { "U1_CPLD.H3" : {}, "R58.1" : { "R58.2" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U11.14" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : {} } }, "U1_CPLD.C9" : {}, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } } } } } } } } } } } }, "U11.13" : {} } } } } } } } } } }, "FPGA_CPLD_SSTAT" : { "U1_CPLD.K1" : {}, "U1_XF.CC32" : {} }, "C1_DDR4_DQ<16>_XF" : { "J2_XF.27" : {}, "U1_XF.BT56" : {} }, "UNNAMED_17_RESISTOR_I95_B_XF" : { "R108_XF.2" : { "R108_XF.1" : { "GND" : {} } }, "R109_XF.2" : { "R109_XF.1" : { "GND" : {} } }, "R98_XF.1" : { "R98_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I58_B_XF" : { "C146_XF.2" : { "C146_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I58_A_XF" : { "U1_XF.BV36" : {}, "R97_XF.2" : { "R97_XF.1" : { "UNNAMED_17_RESISTOR_I61_A_XF" : { "R106_XF.2" : { "R106_XF.1" : { "VMON_AVTT_RUC_LIN_XF" : { "R57_FL_XF.2" : { "R57_FL_XF.1" : { "VS_AVTT_RUC_LIN_FL" : { "NS9_FL_XF.2" : { "NS9_FL_XF.1" : { "PWR_AVTT_RUC_XF" : {} } }, "U5_FL_XF.19" : {} } } } } } }, "R107_XF.2" : { "R107_XF.1" : { "GND" : {} } } } } } } } }, "U1_XF.BW36" : {} } } } }, "OCL0_PER_P<0>_XF" : { "J1_O0_XF.A3" : {}, "U1_XF.BY4" : {} }, "AC_FPGA_CLK_REF_P<1>_1" : { "C18_E0_XF.1" : { "C18_E0_XF.2" : { "E1S0_FPGA_REFCLK_P<1>_XF" : { "R161_XF.2" : { "R161_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R170_XF.1" : { "R170_XF.2" : { "GND" : {} } }, "U1_XF.H13" : {} } } }, "U1_E0_XF.27" : {} }, "C2_DDR4_ADR<6>_XF" : { "J3_XF.69" : {}, "U1_XF.M61" : {} }, "C2_DDR4_SA<1>_XF" : { "R264_XF.2" : { "R264_XF.1" : { "GND" : {} } }, "J3_XF.140" : {} }, "E1S0_3R3V_PERST_CLKREQ_F<1>_XF" : { "U1_XF.Y18" : {}, "R7_E0_XF.2" : { "R7_E0_XF.1" : { "P3R3V" : {} } }, "J1_E0_XF.A11" : {} }, "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.2" : { "FPGA_1R8V_SCL" : { "R33.1" : { "R33.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } } } } } } } } } } } }, "U11.13" : {} }, "FPGA_CFG_MODE<0>_1" : { "U1_CPLD.H2" : {}, "U1_XF.AH17" : {} }, "AC_PCIE1_TXP<7>_XF" : { "U1_XF.AT13" : {}, "C26_XF.1" : { "C26_XF.2" : { "PCIE1_TXP<7>_XF" : { "J2_P1_XF.B18" : {} } } } }, "UNNAMED_3_LT3071_I32_IMON_FL" : { "R7_FL_XF.1" : { "R7_FL_XF.2" : { "IMON_AVCC_LIN_XF" : { "R72_XF.1" : { "R72_XF.2" : { "UNNAMED_17_RESISTOR_I53_A_XF" : { "R73_XF.2" : { "R73_XF.1" : { "UNNAMED_17_RESISTOR_I188_B_XF" : { "R118_XF.2" : { "R118_XF.1" : { "GND" : {} } } } } }, "R82_XF.1" : { "R82_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_A_XF" : { "C141_XF.1" : { "C141_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_B_XF" : { "U1_XF.CA38" : {}, "R83_XF.2" : { "R83_XF.1" : { "UNNAMED_17_RESISTOR_I54_A_XF" : { "R75_XF.2" : { "R75_XF.1" : { "UNNAMED_17_RESISTOR_I187_B_XF" : { "R119_XF.2" : { "R119_XF.1" : { "GND" : {} } } } } }, "R74_XF.2" : { "R74_XF.1" : { "GND" : {} } } } } } } } }, "U1_XF.BY38" : {} } } } } } }, "R15_FL_XF.2" : { "R15_FL_XF.1" : { "UNNAMED_4_LT3071_I30_IMON_FL" : { "U6_FL_XF.21" : {} } } }, "R91_FL_XF.2" : { "R91_FL_XF.1" : { "UNNAMED_12_LT3071_I30_IMON_FL" : { "U10_FL_XF.21" : {} } } } } } }, "U3_FL_XF.21" : {} }, "C1_RDIMM_DQS_T<1>_XF" : { "J2_XF.164" : {}, "U1_XF.BT50" : {} }, "C2_DDR4_DQ<38>_XF" : { "U1_XF.B56" : {}, "J3_XF.102" : {} }, "OCL1_PET_N<1>_XF" : { "J1_O1_XF.B7" : {}, "C272_XF.2" : { "C272_XF.1" : { "AC_OCL1_PET_N<1>_XF" : { "U1_XF.BY8" : {} } } } }, "UNNAMED_3_BYPASSCAPNPOL_I27_A_SP" : { "U1_SP_XF.48" : {}, "C65_SP_XF.1" : { "C65_SP_XF.2" : { "GND" : {} } }, "R45_SP_XF.1" : { "R45_SP_XF.2" : { "IS_VCCINTUR_SW_N_SP" : { "R189_SP_XF.1" : { "R189_SP_XF.2" : { "P3R3V" : {} } }, "C180_SP_XF.1" : { "C180_SP_XF.2" : { "GND" : {} } }, "R190_SP_XF.2" : { "R190_SP_XF.1" : { "GND" : {} } } } } } }, "IS_VCCINTLL_SW_P_SP" : { "R134_SP_XF.2" : { "R134_SP_XF.1" : { "GND" : {} } }, "C130_SP_XF.1" : { "C130_SP_XF.2" : { "GND" : {} } }, "R52_SP_XF.2" : { "R52_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I149_A_SP" : { "U1_SP_XF.41" : {}, "C40_SP_XF.1" : { "C40_SP_XF.2" : { "GND" : {} } } } } }, "R133_SP_XF.1" : { "R133_SP_XF.2" : { "UNNAMED_8_ACS711_I94_VIOUT_SP" : { "U6_SP_XF.11" : {} } } } }, "PWR_VCCAUX_SW_XF" : { "PM1_SP_XF.B2" : {}, "C110_SP_XF.1" : { "C110_SP_XF.2" : { "GND" : {} } }, "C118_SP_XF.2" : { "C118_SP_XF.1" : { "GND" : {} } }, "C81_FL_XF.2" : { "C81_FL_XF.1" : { "GND" : {} } }, "PM1_SP_XF.A2" : {}, "C80_FL_XF.2" : { "C80_FL_XF.1" : { "GND" : {} } }, "PM1_SP_XF.G8" : {}, "U7_FL_XF.6" : {}, "U7_FL_XF.8" : {}, "PM1_SP_XF.E2" : {}, "C100_FL_XF.1" : { "C100_FL_XF.2" : { "GND" : {} } }, "C99_FL_XF.1" : { "C99_FL_XF.2" : { "GND" : {} } }, "PM1_SP_XF.E1" : {}, "C98_FL_XF.1" : { "C98_FL_XF.2" : { "GND" : {} } }, "U11_FL_XF.6" : {}, "U11_FL_XF.5" : {}, "U11_FL_XF.8" : {}, "U7_FL_XF.5" : {}, "PM1_SP_XF.A3" : {}, "PM1_SP_XF.B1" : {}, "U9_FL_XF.8" : {}, "PM1_SP_XF.A1" : {}, "PM1_SP_XF.B3" : {}, "R66_FL_XF.1" : { "R66_FL_XF.2" : { "UNNAMED_10_RESISTOR_I152_B_FL" : { "U9_FL_XF.5" : {} } } }, "PM1_SP_XF.C1" : {}, "PM1_SP_XF.D2" : {}, "C71_FL_XF.1" : { "C71_FL_XF.2" : { "GND" : {} } }, "R121_SP_XF.1" : { "R121_SP_XF.2" : { "VMON_VCCAUX_SW" : { "R48.2" : { "R48.1" : { "UNNAMED_4_MAX116XXQSOP16_I97_AIN0" : {} } } } } }, "U11_FL_XF.7" : {}, "PM1_SP_XF.C3" : {}, "C70_FL_XF.1" : { "C70_FL_XF.2" : { "GND" : {} } }, "R8_FL_XF.1" : { "R8_FL_XF.2" : { "UNNAMED_10_RESISTOR_I87_B_FL" : { "U8_FL_XF.5" : {} } } }, "C114_SP_XF.1" : { "C114_SP_XF.2" : { "GND" : {} } }, "U7_FL_XF.7" : {}, "PM1_SP_XF.C2" : {}, "PM1_SP_XF.D1" : {}, "PM1_SP_XF.D3" : {}, "C69_FL_XF.1" : { "C69_FL_XF.2" : { "GND" : {} } }, "U8_FL_XF.8" : {} }, "UNNAMED_7_BYPASSCAPNPOL_I55_B_SP" : { "R116_SP_XF.2" : { "R116_SP_XF.1" : { "UNNAMED_7_LTM4671_I36_MODECLKIN3_SP" : { "PM1_SP_XF.R8" : { "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : {} } } } } } } } } } } }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} } } } } } } }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.R11" : { "UNNAMED_7_BYPASSCAPNPOL_I55_B_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} } } } } } }, "VS_DIMM_VTT_LIN_ND" : { "NS3_ND_XF.2" : { "NS3_ND_XF.1" : { "PWR_NDIMM_VTT_XF" : {} } }, "U2_ND_XF.5" : {}, "R4_ND_XF.1" : { "R4_ND_XF.2" : { "VMON_NDIMM_VTT_LIN" : { "R45.2" : { "R45.1" : { "UNNAMED_4_MAX116XXQSOP16_I97_AIN3" : { "C46.1" : { "C46.2" : { "GND" : {} } }, "U11.8" : {} } } } } } } }, "UNNAMED_12_NMOSFETVMT3_I4_G" : { "R8.2" : { "R8.1" : { "UNNAMED_12_RESISTOR_I13_A" : { "R7.1" : { "R7.2" : { "UNNAMED_12_NMOSFETVMT3_I12_G" : { "Q11.1" : { "Q11.2" : { "PSU_1R8V_SDA" : { "U1_XF.CA37" : {}, "R19.1" : { "R19.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q11.3" : { "PSU_3R3V_SDA" : { "R24.2" : { "R24.1" : { "P3R3V" : {} } }, "J4.2" : {} } } } } } }, "R4.2" : { "R4.1" : { "DIS_1R8V_I2C_XLAT_F" : { "U1_CPLD.H3" : {}, "R58.1" : { "R58.2" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { 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"GND" : {} } } } } }, "U1_CPLD.M14" : {} } }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} } }, "U1_CPLD.N8" : {} }, "E1S3_PET_P<1>_XF" : { "C341_XF.2" : { "C341_XF.1" : { "AC_E1S3_PET_P<1>_XF" : { "U1_XF.AH9" : {} } } }, "J1_E3_XF.B21" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I33_A_FL" : { "U3_FL_XF.3" : {}, "C18_FL_XF.1" : { "C18_FL_XF.2" : { "GND" : {} } } }, "UNNAMED_10_RESISTOR_I134_B" : { "R10.2" : { "R10.1" : { "GND" : {} } }, "U1.19" : {} }, "UNNAMED_4_LED_I22_A_MP" : { "R8_MP.2" : { "R8_MP.1" : { "P5VSB" : {} } }, "D1_MP.2" : { "D1_MP.1" : { "UNNAMED_4_LED_I22_C_MP" : { "U2_MP.14" : {} } } } }, "CPLD_SELF_TDI_CPLD" : { "U3_CPLD.3" : {}, "U1_CPLD.A15" : {} }, "C0_DDR4_DQ<15>_XF" : { "J1_XF.166" : {}, "U1_XF.CC27" : {} }, "C2_RDIMM_DQS_T<17>_XF" : { "J3_XF.51" : {}, "U1_XF.F58" : {} }, "P5V" : { "J3.21" : {}, "P5V_TP.1" : {}, "C36.1" : { "C36.2" : { "GND" : {} } }, "J3.6" : {}, "J3.4" : {}, "J3.23" : {}, "J3.22" : {} }, "UNNAMED_17_RESISTOR_I101_A_XF" : { "R133_XF.1" : { "R133_XF.2" : { "IMON_AVTT_LIN_XF" : { "R64_FL_XF.2" : { "R64_FL_XF.1" : { "UNNAMED_7_LT3071_I30_IMON_FL" : { "U4_FL_XF.21" : {} } } }, "R82_FL_XF.2" : { "R82_FL_XF.1" : { "UNNAMED_8_LT3071_I30_IMON_FL" : { "U5_FL_XF.21" : {}, "R26_FL_XF.2" : { "R26_FL_XF.1" : { "GND" : {} } } } } }, "R25_FL_XF.2" : { "R25_FL_XF.1" : { "UNNAMED_6_LT3071_I30_IMON_FL" : { "U2_FL_XF.21" : {} } } }, "R24_FL_XF.2" : { "R24_FL_XF.1" : { "UNNAMED_5_LT3071_I30_IMON_FL" : { "U1_FL_XF.21" : {} } } } } } }, "R127_XF.2" : { "R127_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I107_A_XF" : { "U1_XF.CB33" : {}, "C267_XF.1" : { "C267_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I107_B_XF" : { "U1_XF.CC33" : {}, "R128_XF.1" : { "R128_XF.2" : { "UNNAMED_17_RESISTOR_I104_A_XF" : { "R135_XF.1" : { "R135_XF.2" : { "GND" : {} } }, "R136_XF.1" : { "R136_XF.2" : { "UNNAMED_17_RESISTOR_I105_B_XF" : { "R121_XF.1" : { "R121_XF.2" : { "GND" : {} } } } } } } } } } } } } } }, "R134_XF.1" : { "R134_XF.2" : { "UNNAMED_17_RESISTOR_I101_B_XF" : { "R120_XF.1" : { "R120_XF.2" : { "GND" : {} } } } } } }, "C1_RDIMM_DQS_T<0>_XF" : { "U1_XF.BM49" : {}, "J2_XF.153" : {} }, "C2_DDR4_DQ<68>_XF" : { "J3_XF.47" : {}, "U1_XF.D59" : {} }, "UNNAMED_6_TIMINGCAPNPOL_I426_B_SP" : { "PM2_SP_XF.P9" : { "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : {} } } } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} } }, "C84_SP_XF.2" : { "C84_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } }, "C82_SP_XF.2" : { "C82_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } }, "AC_E1S0_PET_N<2>_XF" : { "U1_XF.A10" : {}, "C127_XF.1" : { "C127_XF.2" : { "E1S0_PET_N<2>_XF" : { "J1_E0_XF.B23" : {} } } } }, "AC_PCIE0_TXN<2>_XF" : { "C84_XF.1" : { "C84_XF.2" : { "PCIE0_TXN<2>_XF" : { "J1_P0_XF.B16" : {} } } }, "U1_XF.AV12" : {} }, "UNNAMED_4_RESISTOR_I14_A_ND" : { "U2_ND_XF.1" : {}, "C31_ND_XF.1" : { "C31_ND_XF.2" : { "GND" : {} } }, "R62_ND_XF.2" : { "R62_ND_XF.1" : { "GND" : {} } }, "R68_ND_XF.1" : { "R68_ND_XF.2" : { "PWR_NDIMM_VDD_XF" : {} } } }, "C0_DDR4_ADR<13>_XF" : { "J1_XF.232" : {}, "U1_XF.BW15" : {} }, "C2_DDR4_ODT<1>_XF" : { "J3_XF.91" : {}, "U1_XF.H56" : {} }, "UNNAMED_7_SM050TP_I157_1_CPLD" : { "U1_CPLD.D15" : {}, "TP9_CPLD.1" : {} }, "C0_RDIMM_DQS_C<10>_XF" : { "U1_XF.CB25" : {}, "J1_XF.19" : {} }, "OCL0_PET_P<1>_XF" : { "J1_O0_XF.B6" : {}, "C179_XF.2" : { "C179_XF.1" : { "AC_OCL0_PET_P<1>_XF" : { "U1_XF.CC7" : {} } } } }, "AC_OCL3_PET_P<1>_XF" : { "U1_XF.BH9" : {}, "C256_XF.1" : { "C256_XF.2" : { "OCL3_PET_P<1>_XF" : { "J1_O3_XF.B6" : {} } } } }, "PCIE1_RESET_3V_F" : { "J1_P1_XF.A12" : {}, "U1_CPLD.F16" : {} }, "VDD_VS_N_ND" : { "PM4_ND_XF.E7" : { "PM4_ND_XF.D4" : { "BASE_3R3V_SDA_2" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } } } }, "UNNAMED_20_NMOSFETVMT3_I20_G" : { "R39.2" : { "R39.1" : { "FAN_PWM_OD" : { "R56.1" : { "R56.2" : { "UNNAMED_20_NMOSFETVMT3_I8_G" : { "Q9.1" : { "Q9.2" : { "GND" : {} }, "Q9.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I27_P4" : { "P5.4" : {} } } } } } }, "R42.1" : { "R42.2" : { "UNNAMED_20_NMOSFETVMT3_I12_G" : { "Q7.1" : { "Q7.2" : { "GND" : {} }, "Q7.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I26_P4" : { "P4.4" : {} } } } } } }, "R55.1" : { "R55.2" : { "UNNAMED_20_NMOSFETVMT3_I16_G" : { "Q8.1" : { "Q8.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I25_P4" : { "P3.4" : {} } }, "Q8.2" : { "GND" : {} } } } } }, "U1_CPLD.J12" : {} } } }, "Q6.1" : { "Q6.2" : { "GND" : {} }, "Q6.3" : { "UNNAMED_20_MLXKK1004PINBOSS_I30_P4" : { "P2.4" : {} } } } }, "VS_AVTT_LIN_N_XF" : { "R35_SP_XF.2" : { "R35_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I151_A_SP" : { "C23_SP_XF.1" : { "C23_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.50" : {} } } }, "NS10_FL_XF.2" : { "NS10_FL_XF.1" : { "GND" : {} } } }, "UNNAMED_10_RESISTOR_I133_B" : { "U1.17" : {}, "R11.2" : { "R11.1" : { "GND" : {} } } }, "UNNAMED_6_LT3071_I30_V02_FL" : { "U2_FL_XF.25" : {}, "R49_FL_XF.2" : { "R49_FL_XF.1" : { "GND" : {} } }, "R74_FL_XF.1" : { "R74_FL_XF.2" : { "P3R3V" : {} } } }, "UNNAMED_4_LT3071_I30_VIOC_FL" : { "U6_FL_XF.1" : {}, "C16_FL_XF.1" : { "C16_FL_XF.2" : { "GND" : {} } } }, "OCL0_3R3V_CPRSNT_F_XF" : { "U1_XF.BL17" : {}, "J1_O0_XF.A13" : {} }, "UNNAMED_17_BYPASSCAPNPOL_I216_B_XF" : { "R69_XF.1" : { "R69_XF.2" : { "UNNAMED_17_RESISTOR_I215_B_XF" : { "R63_XF.1" : { "R63_XF.2" : { "GND" : {} } }, "R70_XF.1" : { "R70_XF.2" : { "GND" : {} } } } } }, "C316_XF.2" : { "C316_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I216_A_XF" : { "R68_XF.1" : { "R68_XF.2" : { "UNNAMED_17_RESISTOR_I214_B_XF" : { "R62_XF.1" : { "R62_XF.2" : { "GND" : {} } }, "R39_XF.1" : { "R39_XF.2" : { "VMON_AVCC_RUC_LIN_XF" : { "R102_FL_XF.2" : { "R102_FL_XF.1" : { "VS_AVCC_RUC_LIN_FL" : { "U10_FL_XF.19" : {}, "NS1_FL_XF.2" : { "NS1_FL_XF.1" : { "PWR_AVCC_RUC_XF" : {} } } } } } } } } } } }, "U1_XF.CA40" : {} } } }, "U1_XF.CB40" : {} }, "JT_FPGA_TCK" : { "R60.2" : { "R60.1" : { "GND" : {} } }, "J5.3" : {}, "U1_CPLD.A14" : {} }, "UNNAMED_6_LTM4671_I457_FREQ12_SP" : { "PM2_SP_XF.K10" : { "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : {} } } } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} } } }, "DDR4_SYS_CLK_N<3>_XF" : { "U6_XF.9" : {}, "C367_XF.1" : { "C367_XF.2" : { "C3_SYS_CLK_N_XF" : { "R256_XF.2" : { "R256_XF.1" : { "PWR_NDIMM_VDD_XF" : {} } }, "U1_XF.P24" : {}, "R165_XF.1" : { "R165_XF.2" : { "GND" : {} } } } } } }, "AC_OCL2_PET_N<2>_XF" : { "U1_XF.BL10" : {}, "C275_XF.1" : { "C275_XF.2" : { "OCL2_PET_N<2>_XF" : { "J1_O2_XF.B16" : {} } } } }, "E1S0_3R3V_PRSNT_F<0>_XF" : { "R8_E0_XF.2" : { "R8_E0_XF.1" : { "P3R3V" : {} } }, "J1_E0_XF.A12" : {}, "U1_XF.W19" : {} }, "POK_OD_NDIMM_VTT_LIN" : { "U1_CPLD.T8" : {}, "R61_ND_XF.2" : { "R61_ND_XF.1" : { "UNNAMED_4_RESISTOR_I7_A_ND" : { "U2_ND_XF.9" : {} } } } }, "OCL2_PER_N<1>_XF" : { "U1_XF.BL5" : {}, "J1_O2_XF.A7" : {} }, "C2_DDR4_DQ<70>_XF" : { "J3_XF.54" : {}, "U1_XF.A58" : {} }, "C0_DDR4_ADR<7>_XF" : { "U1_XF.CC21" : {}, "J1_XF.211" : {} }, "DAC_VCCINT_SP" : { "R3_SP_XF.1" : { "R3_SP_XF.2" : { "UNNAMED_4_CAPACITOR_I64_B_SP" : { "R61_SP_XF.1" : { "R61_SP_XF.2" : { "VFB_4650_SP" : { "R11_SP_XF.2" : { "R11_SP_XF.1" : { "UNNAMED_4_RESISTOR_I12_B_SP" : { "R12_SP_XF.2" : { "R12_SP_XF.1" : { "SGND_PM4_SP" : {} } } } } }, "PM4_SP_XF.D5" : { "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} } } } } }, "C4_SP_XF.2" : { "C4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } } } }, "UNNAMED_5_BYPASSCAPNPOL_I31_A_FL" : { "U1_FL_XF.3" : {}, "C31_FL_XF.1" : { "C31_FL_XF.2" : { "GND" : {} } } }, "UNNAMED_9_LED_I15_A_CPLD" : { "R117_CPLD.1" : { "R117_CPLD.2" : { "CPLD_P3R3V" : {} } }, "D6_CPLD.2" : { "D6_CPLD.1" : { "STAT_LED_ON_F<2>_CPLD" : { "U1_CPLD.D6" : {} } } } }, "C2_DDR4_DQ<34>_XF" : { "U1_XF.F56" : {}, "J3_XF.104" : {} }, "UNNAMED_17_RESISTOR_I61_A_XF" : { "R107_XF.2" : { "R107_XF.1" : { "GND" : {} } }, "R97_XF.1" : { "R97_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I58_A_XF" : { "C146_XF.1" : { "C146_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I58_B_XF" : { "U1_XF.BW36" : {}, "R98_XF.2" : { "R98_XF.1" : { "UNNAMED_17_RESISTOR_I95_B_XF" : { "R108_XF.2" : { "R108_XF.1" : { "GND" : {} } }, "R109_XF.2" : { "R109_XF.1" : { "GND" : {} } } } } } } } }, "U1_XF.BV36" : {} } } }, "R106_XF.2" : { "R106_XF.1" : { "VMON_AVTT_RUC_LIN_XF" : { "R57_FL_XF.2" : { "R57_FL_XF.1" : { "VS_AVTT_RUC_LIN_FL" : { "U5_FL_XF.19" : {}, "NS9_FL_XF.2" : { "NS9_FL_XF.1" : { "PWR_AVTT_RUC_XF" : {} } } } } } } } } }, "UNNAMED_22_RESISTOR_I61_B_XF" : { "R160_XF.2" : { "R160_XF.1" : { "GND" : {} } }, "U1_XF.CC31" : {} }, "UNNAMED_7_LTM4671_I87_FB0_SP" : { "R69_SP_XF.2" : { "R69_SP_XF.1" : { "UNNAMED_7_RESISTOR_I42_A_SP" : { "R58_SP_XF.2" : { "R58_SP_XF.1" : { "PM1_SP_AGND_SP" : {} } } } } }, "PM1_SP_XF.G9" : { "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {} } }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} } } }, "C1_RDIMM_DQS_T<15>_XF" : { "U1_XF.BL57" : {}, "J2_XF.121" : {} }, "AC_FPGA_CLK_REF_N<0>" : { "C23_E1_XF.1" : { "C23_E1_XF.2" : { "E1S1_FPGA_REFCLK_N<0>_XF" : { "U1_XF.P12" : {}, "R169_XF.2" : { "R169_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R181_XF.1" : { "R181_XF.2" : { "GND" : {} } } } } }, "U1_E1_XF.23" : {} }, "PCIE1_TXP<5>_XF" : { "J2_P1_XF.B6" : {}, "C28_XF.2" : { "C28_XF.1" : { "AC_PCIE1_TXP<5>_XF" : { "U1_XF.AR11" : {} } } } }, "AC_PCIE0_TXP<6>_XF" : { "U1_XF.BB9" : {}, "C35_XF.1" : { "C35_XF.2" : { "PCIE0_TXP<6>_XF" : { "J2_P0_XF.B15" : {} } } } }, "FSET_4650_TL_SP" : { "PM4_SP_XF.C6" : { "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } } } }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G9" : { "UNNAMED_4_LTM4650FIXED_I78_PGOOD1_SP" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} } }, "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } }, "UNNAMED_17_RESISTOR_I101_B_XF" : { "R134_XF.2" : { "R134_XF.1" : { "UNNAMED_17_RESISTOR_I101_A_XF" : { "R133_XF.1" : { "R133_XF.2" : { "IMON_AVTT_LIN_XF" : { "R64_FL_XF.2" : { "R64_FL_XF.1" : { "UNNAMED_7_LT3071_I30_IMON_FL" : { "U4_FL_XF.21" : {} } } }, "R25_FL_XF.2" : { "R25_FL_XF.1" : { "UNNAMED_6_LT3071_I30_IMON_FL" : { "U2_FL_XF.21" : {} } } }, "R82_FL_XF.2" : { "R82_FL_XF.1" : { "UNNAMED_8_LT3071_I30_IMON_FL" : { "R26_FL_XF.2" : { "R26_FL_XF.1" : { "GND" : {} } }, "U5_FL_XF.21" : {} } } }, "R24_FL_XF.2" : { "R24_FL_XF.1" : { "UNNAMED_5_LT3071_I30_IMON_FL" : { "U1_FL_XF.21" : {} } } } } } }, "R127_XF.2" : { "R127_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I107_A_XF" : { "C267_XF.1" : { "C267_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I107_B_XF" : { "U1_XF.CC33" : {}, "R128_XF.1" : { "R128_XF.2" : { "UNNAMED_17_RESISTOR_I104_A_XF" : { "R136_XF.1" : { "R136_XF.2" : { "UNNAMED_17_RESISTOR_I105_B_XF" : { "R121_XF.1" : { "R121_XF.2" : { "GND" : {} } } } } }, "R135_XF.1" : { "R135_XF.2" : { "GND" : {} } } } } } } } }, "U1_XF.CB33" : {} } } } } } }, "R120_XF.1" : { "R120_XF.2" : { "GND" : {} } } }, "FP_INTRUSION_N" : { "FPNL_CONN.20" : {}, "U1_CPLD.K16" : {} }, "C3_DDR4_DQ<11>_XF" : { "J4_XF.168" : {}, "U1_XF.J25" : {} }, "PCIE0_RXP<6>_XF" : { "U1_XF.BB4" : {}, "J2_P0_XF.A15" : {} }, "PCIE1_RXN<7>_XF" : { "U1_XF.AU5" : {}, "J2_P1_XF.A19" : {} }, "OCL1_PER_N<0>_XF" : { "U1_XF.BU5" : {}, "J1_O1_XF.A4" : {} }, "C2_DDR4_DQ<50>_XF" : { "J3_XF.126" : {}, "U1_XF.J47" : {} }, "C1_RDIMM_DQS_C<5>_XF" : { "U1_XF.BM61" : {}, "J2_XF.255" : {} }, "C3_DDR4_SA<2>_XF" : { "R265_XF.2" : { "R265_XF.1" : { "P3R3V" : {} } }, "J4_XF.238" : {} }, "PWR_VCCAUX_A_FL" : { "U7_FL_XF.17" : {}, "C79_FL_XF.1" : { "C79_FL_XF.2" : { "GND" : {} } }, "R114_FL_XF.2" : { "R114_FL_XF.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "C77_FL_XF.1" : { "C77_FL_XF.2" : { "GND" : {} } }, "U7_FL_XF.15" : {}, "U7_FL_XF.16" : {}, "C78_FL_XF.1" : { "C78_FL_XF.2" : { "GND" : {} } }, "C76_FL_XF.1" : { "C76_FL_XF.2" : { "GND" : {} } }, "NS7_FL_XF.1" : { "NS7_FL_XF.2" : { "UNNAMED_9_LT3071_I30_SENSE_FL" : { "U7_FL_XF.19" : {} } } }, "U7_FL_XF.18" : {} }, "AC_E1S1_PET_P<1>_XF" : { "C116_XF.1" : { "C116_XF.2" : { "E1S1_PET_P<1>_XF" : { "J1_E1_XF.B21" : {} } } }, "U1_XF.N11" : {} }, "UNNAMED_8_LT3071_I30_PWRGD_FL" : { "R20_FL_XF.1" : { "R20_FL_XF.2" : { "POK_OD_AVTT_RUC_LIN" : { "U1_CPLD.M9" : {} } } }, "U5_FL_XF.2" : {} }, "PCIE0_TXN<1>_XF" : { "J1_P0_XF.B7" : {}, "C85_XF.2" : { "C85_XF.1" : { "AC_PCIE0_TXN<1>_XF" : { "U1_XF.AV8" : {} } } } }, "VDDO8" : { "U1.52" : {}, "R16.2" : { "R16.1" : { "CPLD_P1R8V_1" : {} } }, "C18.1" : { "C18.2" : { "GND" : {} } } }, "POK_OD_AVTT_RN_LIN" : { "U1_CPLD.T10" : {}, "R19_FL_XF.2" : { "R19_FL_XF.1" : { "UNNAMED_7_LT3071_I30_PWRGD_FL" : { "U4_FL_XF.2" : {} } } } }, "C3_DDR4_ADR<9>_XF" : { "U1_XF.U28" : {}, "J4_XF.66" : {} }, "C0_DDR4_CKE<1>_XF" : { "U1_XF.BT20" : {}, "J1_XF.203" : {} }, "C2_DDR4_DQ<64>_XF" : { "U1_XF.C59" : {}, "J3_XF.49" : {} }, "E1S3_PER_P<0>_XF" : { "U1_XF.AJ6" : {}, "J1_E3_XF.A18" : {} }, "CONN_CLK_REFN<0>_E3" : { "J1_E3_XF.B14" : {}, "C25_E3_XF.2" : { "C25_E3_XF.1" : { "AC_CONN_CLK_REFN<0>_2" : { "U1_E3_XF.14" : {} } } } }, "UNNAMED_3_OCULINKX4CONN_I86_REFCLKP_P0" : { "R1_P0_XF.1" : { "R1_P0_XF.2" : { "PCIE0_REFP_XF" : { "C100_XF.1" : { "C100_XF.2" : { "AC_PCIE0_REFP_XF" : { "U1_XF.BB13" : {} } } } } } }, "J1_P0_XF.B12" : {} }, "VMON_SPARE_SW_XF" : { "R122_SP_XF.2" : { "R122_SP_XF.1" : { "PWR_SPARE_SW_XF" : { "PM1_SP_XF.U1" : {}, "PM1_SP_XF.V2" : {}, "PM1_SP_XF.T1" : {}, "PM1_SP_XF.T3" : {}, "PM1_SP_XF.R2" : {}, "PM1_SP_XF.U3" : {}, "PWR_SPARE_SW_XF.1" : {}, "C119_SP_XF.1" : { "C119_SP_XF.2" : { "GND" : {} } }, "PM1_SP_XF.W2" : {}, "C115_SP_XF.1" : { "C115_SP_XF.2" : { "GND" : {} } }, "PM1_SP_XF.W1" : {}, "PM1_SP_XF.W3" : {}, "PM1_SP_XF.N11" : {}, "PM1_SP_XF.T2" : {}, "PM1_SP_XF.U2" : {}, "PM1_SP_XF.V1" : {}, "PM1_SP_XF.V3" : {}, "C111_SP_XF.1" : { "C111_SP_XF.2" : { "GND" : {} } }, "PM1_SP_XF.R1" : {} } } }, "VMON_SPARE_SW_XF.1" : {} }, "LTC2975_ALERT_OD_F" : { "U1_SP_XF.31" : {}, "U1_CPLD.P13" : {} }, "E1S1_PER_P<1>_XF" : { "J1_E1_XF.A21" : {}, "U1_XF.N6" : {} }, "C2_DDR4_DQ<42>_XF" : { "J3_XF.115" : {}, "U1_XF.B53" : {} }, "UNNAMED_3_LT3071_I32_VIOC_FL" : { "C17_FL_XF.1" : { "C17_FL_XF.2" : { "GND" : {} } }, "U3_FL_XF.1" : {} }, "C2_SYS_CLK_N_XF" : { "R252_XF.1" : { "R252_XF.2" : { "GND" : {} } }, "U1_XF.J60" : {}, "R248_XF.2" : { "R248_XF.1" : { "PWR_NDIMM_VDD_XF" : {} } }, "C365_XF.2" : { "C365_XF.1" : { "DDR4_SYS_CLK_N<2>_XF" : { "U6_XF.11" : {} } } }, "R251_XF.2" : { "R251_XF.1" : { "C2_SYS_CLK_P_XF" : {} } } }, "C3_DDR4_ADR<8>_XF" : { "U1_XF.R25" : {}, "J4_XF.68" : {} }, "AC_E1S2_PET_N<3>_XF" : { "U1_XF.U10" : {}, "C170_XF.1" : { "C170_XF.2" : { "E1S2_PET_N<3>_XF" : { "J1_E2_XF.B26" : {} } } } }, "C0_DDR4_DQ<33>_XF" : { "J1_XF.242" : {}, "U1_XF.BL22" : {} }, "OCL3_PER_N<1>_XF" : { "J1_O3_XF.A7" : {}, "U1_XF.BJ1" : {} }, "C0_RDIMM_DQS_C<14>_XF" : { "J1_XF.111" : {}, "U1_XF.BL27" : {} }, "C2_DDR4_BA<1>_XF" : { "J3_XF.224" : {}, "U1_XF.J62" : {} }, "POK_OD_AVCC_RS_RLC_LIN" : { "R70_FL_XF.2" : { "R70_FL_XF.1" : { "UNNAMED_3_LT3071_I32_PWRGD_FL" : { "U3_FL_XF.2" : {} } } }, "U1_CPLD.N10" : {} }, "AC_CONN_CLK_REFP<1>" : { "U1_E1_XF.17" : {}, "C20_E1_XF.1" : { "C20_E1_XF.2" : { "CONN_CLK_REFP<1>_E1" : { "J1_E1_XF.A15" : {} } } } }, "UNNAMED_21_RESISTOR_I33_B_XF" : { "U1_XF.BR50" : {}, "R29_XF.2" : { "R29_XF.1" : { "GND" : {} } } }, "UNNAMED_17_BYPASSCAPNPOL_I50_A_XF" : { "R78_XF.2" : { "R78_XF.1" : { "UNNAMED_17_RESISTOR_I55_A_XF" : { "R103_XF.2" : { "R103_XF.1" : { "GND" : {} } }, "R102_XF.2" : { "R102_XF.1" : { "VMON_AVCC_SW_XF" : { "R100_SP_XF.2" : { "R100_SP_XF.1" : { "PWR_AVCC_SW_XF" : {} } } } } } } } }, "U1_XF.CB38" : {}, "C139_XF.1" : { "C139_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I50_B_XF" : { "R79_XF.2" : { "R79_XF.1" : { "UNNAMED_17_RESISTOR_I56_A_XF" : { "R104_XF.2" : { "R104_XF.1" : { "GND" : {} } }, "R67_XF.2" : { "R67_XF.1" : { "GND" : {} } } } } }, "U1_XF.CB39" : {} } } } }, "AC_OCL3_PET_P<0>_XF" : { "C257_XF.1" : { "C257_XF.2" : { "OCL3_PET_P<0>_XF" : { "J1_O3_XF.B3" : {} } } }, "U1_XF.BJ11" : {} }, "C0_DDR4_DQ<51>_XF" : { "U1_XF.BH24" : {}, "J1_XF.271" : {} }, "PWR_RS_RLC_MGTVCCAUX_XF" : { "U1_XF.BK15" : {}, "U1_XF.AT15" : {}, "C85_FL_XF.2" : { "C85_FL_XF.1" : { "UNNAMED_10_RESISTOR_I143_A_FL" : {} } }, "R85_FL_XF.1" : { "R85_FL_XF.2" : { "VMON_RS_RLC_MGTVCCAUX" : { "R47.2" : { "R47.1" : { "UNNAMED_4_MAX116XXQSOP16_I97_AIN1" : {} } } } } }, "R88_FL_XF.2" : { "R88_FL_XF.1" : { "UNNAMED_10_RESISTOR_I143_A_FL" : {} } }, "C475_XF.1" : { "C475_XF.2" : { "GND" : {} } }, "C83_FL_XF.1" : { "C83_FL_XF.2" : { "GND" : {} } }, "U9_FL_XF.1" : {}, "C93_XF.1" : { "C93_XF.2" : { "GND" : {} } }, "U1_XF.BH15" : {}, "U1_XF.AP15" : {}, "C452_XF.1" : { "C452_XF.2" : { "GND" : {} } }, "C476_XF.1" : { "C476_XF.2" : { "GND" : {} } } }, "C2_RDIMM_DQS_C<13>_XF" : { "J3_XF.100" : {}, "U1_XF.D55" : {} }, "E1S0_3R3V_PRSNT_F<1>_XF" : { "U1_XF.Y19" : {}, "J1_E0_XF.B42" : {} }, "C3_DDR4_CK_T<0>_XF" : { "J4_XF.74" : {}, "U1_XF.N27" : {} }, "UNNAMED_13_NMOSFETVMT3_I99_G" : { "Q2.1" : { "Q2.3" : { "BASE_3R3V_SDA_2" : { "U11.14" : {}, "Q4.3" : { "Q4.1" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "R5.2" : { "R5.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R3.1" : { "R3.2" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "Q3.1" : { "Q3.3" : { "BASE_3R3V_SCL_2" : { "U12.6" : {}, "R34.2" : { "R34.1" : { "P3R3V" : {} } }, "Q1.3" : { "Q1.1" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "R32.2" : { "R32.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R27.2" : { "R27.1" : { "FPGA_VCCAUX_P1R8V" : {} } }, "R58.2" : { "R58.1" : { "DIS_1R8V_I2C_XLAT_F" : { "U1_CPLD.H3" : {} } } }, "R31.1" : { "R31.2" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : {} } } } } } } }, "Q1.2" : { "FPGA_1R8V_SCL" : { "R33.1" : { "R33.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "U11.13" : {}, "U1_CPLD.A9" : {} } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } } } } } } } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } }, "C2_DDR4_DQ<5>_XF" : { "J3_XF.148" : {}, "U1_XF.U46" : {} }, "C2_DDR4_CKE<0>_XF" : { "U1_XF.L55" : {}, "J3_XF.60" : {} }, "C0_DDR4_DQ<63>_XF" : { "U1_XF.BG26" : {}, "J1_XF.280" : {} }, "UNNAMED_7_LTM4671_I39_TRACKSS2_SP" : { "PM1_SP_XF.N7" : { "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "U1_CPLD.M14" : {}, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } } }, "U11.13" : {} } }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} } } } } }, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } }, "U1_CPLD.R16" : {} } }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} } } }, "C0_DDR4_DQ<46>_XF" : { "J1_XF.113" : {}, "U1_XF.BM26" : {} }, "C0_RDIMM_DQS_T<12>_XF" : { "J1_XF.40" : {}, "U1_XF.BU24" : {} }, "AC_OCL0_PET_N<3>_XF" : { "U1_XF.CA10" : {}, "C258_XF.1" : { "C258_XF.2" : { "OCL0_PET_N<3>_XF" : { "J1_O0_XF.B19" : {} } } } }, "C3_RDIMM_DQS_T<2>_XF" : { "J4_XF.175" : {}, "U1_XF.H28" : {} }, "BOARD_CFG_SW<2>" : { "U1_CPLD.N3" : {}, "S1.3" : { "S1.4" : { "BOARD_CFG_SW<1>" : { "U1_XF.CA36" : {}, "U1_CPLD.R1" : {} } }, "S1.1" : { "BOARD_CFG_SW<0>" : { "U1_XF.CB35" : {}, "U1_CPLD.P2" : {} } }, "S1.5" : { "GND" : {} }, "S1.6" : { "BOARD_CFG_SW<3>" : { "U1_XF.CB34" : {}, "U1_CPLD.M2" : {} } }, "S1.2" : { "GND" : {} } }, "U1_XF.BY35" : {} }, "C3_DDR4_DQ<43>_XF" : { "U1_XF.C23" : {}, "J4_XF.260" : {} }, "E1S1_PET_P<4>_XF" : { "J1_E1_XF.B31" : {}, "C113_XF.2" : { "C113_XF.1" : { "AC_E1S1_PET_P<4>_XF" : { "U1_XF.U7" : {} } } } }, "CJTAG_REF" : { "J5.12" : {}, "C14.2" : { "C14.1" : { "GND" : {} } }, "R40.2" : { "R40.1" : { "CPLD_P1R8V_1" : {} } } }, "UNNAMED_6_LTM4671_I456_COMP3A_SP" : { "PM2_SP_XF.N9" : { "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : { "R51.2" : { "UNNAMED_4_BYPASSCAPNPOL_I48_B" : {} } } } }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C4" : { "GND" : {} } } }, "PCIE1_RXP<7>_XF" : { "J2_P1_XF.A18" : {}, "U1_XF.AU6" : {} }, "C3_DDR4_DQ<66>_XF" : { "J4_XF.56" : {}, "U1_XF.G18" : {} }, "C0_DDR4_ODT<0>_XF" : { "J1_XF.87" : {}, "U1_XF.BY18" : {} }, "C1_DDR4_DQ<24>_XF" : { "U1_XF.BW61" : {}, "J2_XF.38" : {} }, "E1S2_PER_P<0>_XF" : { "U1_XF.AA6" : {}, "J1_E2_XF.A18" : {} }, "UNNAMED_9_LT3071_I66_PWRGD_FL" : { "R104_FL_XF.1" : { "R104_FL_XF.2" : { "POK_OD_VCCAUX_B_LIN" : { "U1_CPLD.N9" : {} } } }, "U11_FL_XF.2" : {} }, "PCIE0_TXP<1>_XF" : { "J1_P0_XF.B6" : {}, "C40_XF.2" : { "C40_XF.1" : { "AC_PCIE0_TXP<1>_XF" : { "U1_XF.AV9" : {} } } } }, "UNNAMED_9_LT3071_I30_V02_FL" : { "U7_FL_XF.25" : {}, "R78_FL_XF.2" : { "R78_FL_XF.1" : { "GND" : {} } }, "R65_FL_XF.1" : { "R65_FL_XF.2" : { "P3R3V" : {} } } }, "UNNAMED_7_SM050TP_I161_1_CPLD" : { "U1_CPLD.R5" : {}, "TP12_CPLD.1" : {} }, "AC_FPGA_CLK_REF_N<1>" : { "U1_E1_XF.28" : {}, "C22_E1_XF.1" : { "C22_E1_XF.2" : { "E1S1_FPGA_REFCLK_N<1>_XF" : { "R167_XF.2" : { "R167_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_XF.U14" : {}, "R178_XF.1" : { "R178_XF.2" : { "GND" : {} } } } } } }, "AC_PCIE1_TXN<0>_XF" : { "U1_XF.AM8" : {}, "C49_XF.1" : { "C49_XF.2" : { "PCIE1_TXN<0>_XF" : { "J1_P1_XF.B4" : {} } } } }, "UNNAMED_12_NMOSFETVMT3_I12_G" : { "R7.2" : { "R7.1" : { "UNNAMED_12_RESISTOR_I13_A" : { "R8.1" : { "R8.2" : { "UNNAMED_12_NMOSFETVMT3_I4_G" : { "Q10.1" : { "Q10.3" : { "PSU_3R3V_SCL" : { "R25.2" : { "R25.1" : { "P3R3V" : {} } }, "J4.1" : {} } }, "Q10.2" : { "PSU_1R8V_SCL" : { "U1_XF.CA35" : {}, "R9.1" : { "R9.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } } } } }, "R4.2" : { "R4.1" : { "DIS_1R8V_I2C_XLAT_F" : { "U1_CPLD.H3" : {}, "R58.1" : { "R58.2" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : { "U11.13" : {}, "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } } } } } } } } } } } } } }, "R1.2" : { "R1.1" : { "FPGA_VCCAUX_P1R8V" : {} } } } } }, "Q11.1" : { "Q11.2" : { "PSU_1R8V_SDA" : { "R19.1" : { "R19.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.CA37" : {} } }, "Q11.3" : { "PSU_3R3V_SDA" : { "J4.2" : {}, "R24.2" : { "R24.1" : { "P3R3V" : {} } } } } } }, "PCIE1_TXN<5>_XF" : { "C44_XF.2" : { "C44_XF.1" : { "AC_PCIE1_TXN<5>_XF" : { "U1_XF.AR10" : {} } } }, "J2_P1_XF.B7" : {} }, "E1S0_PET_N<0>_XF" : { "J1_E0_XF.B17" : {}, "C129_XF.2" : { "C129_XF.1" : { "AC_E1S0_PET_N<0>_XF" : { "U1_XF.C6" : {} } } } }, "UNNAMED_4_PI6CB33401_I37_SADRTRI_E1" : { "R12_E1_XF.2" : { "R12_E1_XF.1" : { "GND" : {} } }, "U1_E1_XF.32" : {} }, "C0_DDR4_RESET_N_XF" : { "J1_XF.58" : {}, "U1_XF.BV17" : {} }, "AC_E1S1_PET_P<0>_XF" : { "U1_XF.P9" : {}, "C117_XF.1" : { "C117_XF.2" : { "E1S1_PET_P<0>_XF" : { "J1_E1_XF.B18" : {} } } } }, "PWR_AVCC_RN_XF" : { "U1_XF.G13" : {}, "NS4_FL_XF.1" : { "NS4_FL_XF.2" : { "VS_AVCC_RN_LIN_FL" : {} } }, "U6_FL_XF.15" : {}, "U6_FL_XF.16" : {}, "U1_XF.L13" : {}, "U1_XF.R13" : {}, "U6_FL_XF.18" : {}, "C12_FL_XF.1" : { "C12_FL_XF.2" : { "GND" : {} } }, "U1_XF.E13" : {}, "U1_XF.J13" : {}, "U6_FL_XF.17" : {}, "C477_XF.1" : { "C477_XF.2" : { "GND" : {} } }, "C478_XF.1" : { "C478_XF.2" : { "GND" : {} } }, "C55_XF.1" : { "C55_XF.2" : { "GND" : {} } }, "U1_XF.U13" : {}, "C14_FL_XF.1" : { "C14_FL_XF.2" : { "GND" : {} } }, "C9_FL_XF.1" : { "C9_FL_XF.2" : { "GND" : {} } }, "U1_XF.C13" : {}, "C53_XF.1" : { "C53_XF.2" : { "GND" : {} } }, "U1_XF.N13" : {}, "C8_FL_XF.1" : { "C8_FL_XF.2" : { "GND" : {} } } }, "C2_DDR4_DQ<7>_XF" : { "J3_XF.155" : {}, "U1_XF.U50" : {} }, "C3_RDIMM_DQS_T<4>_XF" : { "J4_XF.245" : {}, "U1_XF.C27" : {} }, "PCIE0_CLKREQ_XF" : { "U1_XF.BC17" : {} }, "JT_FPGA_TMS" : { "U1_CPLD.A11" : {}, "R63.1" : { "R63.2" : { "CPLD_P1R8V_1" : {} } }, "J5.2" : {} }, "CONN_CLK_REFN<1>_E3" : { "C24_E3_XF.2" : { "C24_E3_XF.1" : { "AC_CONN_CLK_REFN<1>_2" : { "U1_E3_XF.18" : {} } } }, "J1_E3_XF.A14" : {} }, "UNNAMED_4_RESISTOR_I2_B_MP" : { "R9_MP.2" : { "R9_MP.1" : { "UNNAMED_4_RESISTOR_I2_A_MP" : { "U2_MP.7" : {} } } }, "C12_MP.1" : { "C12_MP.2" : { "GND" : {} } } }, "C3_DDR4_DQ<36>_XF" : { "U1_XF.B26" : {}, "J4_XF.95" : {} }, "PCIE0_RXN<6>_XF" : { "J2_P0_XF.A16" : {}, "U1_XF.BB3" : {} }, "E1S0_3R3V_SMB_RST_F_XF" : { "J1_E0_XF.A9" : {}, "U1_XF.AB18" : {}, "R5_E0_XF.2" : { "R5_E0_XF.1" : { "P3R3V" : {} } } }, "C1_DDR4_CS_N<2>_XF" : { "U1_XF.CA57" : {}, "J2_XF.93" : {} }, "C1_DDR4_DQ<45>_XF" : { "U1_XF.BN62" : {}, "J2_XF.251" : {} }, "FPGA_1R8V_SCL" : { "Q1.2" : { "Q1.3" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } }, "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.3" : { "BASE_3R3V_SDA_2" : { "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } }, "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : {} } } } } } } } }, "R2.2" : { "R2.1" : { "P3R3V" : {} } } } }, "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } } } } } } } } } } } }, "U11.13" : {} } }, "Q1.1" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : {} } }, "R33.1" : { "R33.2" : { "FPGA_VCCAUX_P1R8V" : {} } } }, "C0_DDR4_DQ<71>_XF" : { "U1_XF.BT26" : {}, "J1_XF.199" : {} }, "AC_PCIE1_TXN<1>_XF" : { "C48_XF.1" : { "C48_XF.2" : { "PCIE1_TXN<1>_XF" : { "J1_P1_XF.B7" : {} } } }, "U1_XF.AM12" : {} }, "E1S0_PET_N<4>_XF" : { "C125_XF.2" : { "C125_XF.1" : { "AC_E1S0_PET_N<4>_XF" : { "U1_XF.F8" : {} } } }, "J1_E0_XF.B30" : {} }, "FAN_TACH_OD<2>" : { "U1_CPLD.G11" : {}, "P4.3" : {} }, "C1_DDR4_DQ<31>_XF" : { "J2_XF.188" : {}, "U1_XF.BW59" : {} }, "C2_DDR4_DQ<69>_XF" : { "J3_XF.192" : {}, "U1_XF.E59" : {} }, "C1_RDIMM_DQS_C<6>_XF" : { "U1_XF.BN57" : {}, "J2_XF.266" : {} }, "C3_DDR4_ADR<4>_XF" : { "U1_XF.P27" : {}, "J4_XF.214" : {} }, "UNNAMED_8_LT3071_I30_V01_FL" : { "R41_FL_XF.1" : { "R41_FL_XF.2" : { "P3R3V" : {} } }, "U5_FL_XF.24" : {}, "R63_FL_XF.2" : { "R63_FL_XF.1" : { "GND" : {} } } }, "UNNAMED_3_RESISTOR_I28_A_MP" : { "R10_MP.1" : { "R10_MP.2" : { "UNNAMED_3_RESISTOR_I28_B_MP" : { "U1_MP.8" : {} } } }, "R1_MP.2" : { "R1_MP.1" : { "GND" : {} } } }, "C3_DDR4_DQ<55>_XF" : { "U1_XF.E17" : {}, "J4_XF.269" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I28_A_SD" : { "R111_SD_XF.1" : { "R111_SD_XF.2" : { "UNNAMED_3_LTM4675_I40_COMP0B_SD" : {} } }, "C81_SD_XF.1" : { "C81_SD_XF.2" : { "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF" : {} } } }, "UNNAMED_3_BYPASSCAPNPOL_I28_A_ND" : { "R111_ND_XF.1" : { "R111_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_COMP0B_ND" : {} } }, "C81_ND_XF.1" : { "C81_ND_XF.2" : { "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF" : {} } } }, "SGND_PM5_SP" : { "R9_SP_XF.1" : { "R9_SP_XF.2" : { "FSET_4650_TR_SP" : { "PM5_SP_XF.C6" : { "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D6" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.G7" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.C7" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.G6" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.E9" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.F6" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.F7" : { "SGND_PM5_SP" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} } } } } } }, "UNNAMED_22_RESISTOR_I41_B_XF" : { "U1_XF.BR24" : {}, "R54_XF.2" : { "R54_XF.1" : { "GND" : {} } } }, "UNNAMED_18_RESISTOR_I22_A_XF" : { "U1_XF.AN18" : {}, "R41_XF.1" : { "R41_XF.2" : { "FPGA_P1R8V_TDO" : { "U1_CPLD.H6" : {} } } } }, "AC_FPGA_CLK_REF_P<0>_1" : { "C19_E0_XF.1" : { "C19_E0_XF.2" : { "E1S0_FPGA_REFCLK_P<0>_XF" : { "R163_XF.2" : { "R163_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R173_XF.1" : { "R173_XF.2" : { "GND" : {} } }, "U1_XF.D13" : {} } } }, "U1_E0_XF.22" : {} }, "E1S1_PET_P<0>_XF" : { "J1_E1_XF.B18" : {}, "C117_XF.2" : { "C117_XF.1" : { "AC_E1S1_PET_P<0>_XF" : { "U1_XF.P9" : {} } } } }, "C1_DDR4_DQ<53>_XF" : { "U1_XF.BM59" : {}, "J2_XF.262" : {} }, "P12V_4650_URIGHT_SP" : { "U2_SP_XF.3_4" : {}, "F5_SP_XF.1" : { "F5_SP_XF.2" : { "P12V_4650_TR_SP" : {} } }, "C43_SP_XF.1" : { "C43_SP_XF.2" : { "GND" : {} } } }, "UNNAMED_7_LTM4671_I36_PHMODE3_SP" : { "PM1_SP_XF.R6" : { "PM1_SP_XF.B10" : { "GND" : {} }, "PM1_SP_XF.U10" : { "GND" : {} }, "PM1_SP_XF.C7" : { "GND" : {} }, "PM1_SP_XF.D5" : { "GND" : {} }, "PM1_SP_XF.W8" : { "GND" : {} }, "PM1_SP_XF.B8" : { "GND" : {} }, "PM1_SP_XF.U8" : { "GND" : {} }, "PM1_SP_XF.G2" : { "GND" : {} }, "PM1_SP_XF.W10" : { "GND" : {} }, "PM1_SP_XF.K1" : { "GND" : {} }, "PM1_SP_XF.P11" : { "GND" : {} }, "PM1_SP_XF.A11" : { "GND" : {} }, "PM1_SP_XF.C8" : { "GND" : {} }, "PM1_SP_XF.W7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.G10" : { "GND" : {} }, "PM1_SP_XF.A9" : { "GND" : {} }, "PM1_SP_XF.D6" : { "GND" : {} }, "PM1_SP_XF.B7" : { "GND" : {} }, "PM1_SP_XF.D4" : { "GND" : {} }, "PM1_SP_XF.U7" : { "GND" : {} }, "PM1_SP_XF.C10" : { "GND" : {} }, "PM1_SP_XF.F1" : { "GND" : {} }, "PM1_SP_XF.H7" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.L8" : { "ENB3V_SEQ_E" : { "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } }, "R1_ND_XF.1" : { "R1_ND_XF.2" : { "UNNAMED_3_LTM4675_I40_RUN0_ND" : { "PM4_ND_XF.F3" : { "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.C7" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.H1" : { "GND" : {} }, "PM4_ND_XF.M2" : { "GND" : {} }, "PM4_ND_XF.C4" : { "GND" : {} }, "PM4_ND_XF.L2" : { "GND" : {} }, "PM4_ND_XF.K8" : { "GND" : {} }, "PM4_ND_XF.M7" : { "GND" : {} }, "PM4_ND_XF.E1" : { "GND" : {} }, "PM4_ND_XF.L7" : { "GND" : {} }, "PM4_ND_XF.C6" : { "GND" : {} }, "PM4_ND_XF.B5" : { "GND" : {} }, "PM4_ND_XF.B3" : { "GND" : {} }, "PM4_ND_XF.A3" : { "GND" : {} }, "PM4_ND_XF.A5" : { "GND" : {} }, "PM4_ND_XF.J8" : { "GND" : {} }, "PM4_ND_XF.F8" : { "GND" : {} }, "PM4_ND_XF.G1" : { "GND" : {} }, "PM4_ND_XF.K2" : { "GND" : {} }, "PM4_ND_XF.M8" : { "GND" : {} }, "PM4_ND_XF.K7" : { "GND" : {} }, "PM4_ND_XF.J2" : { "GND" : {} }, "PM4_ND_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : {} } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_ND_XF.B6" : { "GND" : {} }, "PM4_ND_XF.C5" : { "GND" : {} }, "PM4_ND_XF.A6" : { "GND" : {} }, "PM4_ND_XF.D2" : { "GND" : {} }, "PM4_ND_XF.B4" : { "GND" : {} }, "PM4_ND_XF.A4" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {} } }, "PM1_SP_XF.V9" : { "GND" : {} }, "PM1_SP_XF.G3" : { "GND" : {} }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} } } }, "C1_DDR4_ADR<16>_XF" : { "J2_XF.82" : {}, "U1_XF.BW50" : {} }, "FPGA_CFG_MODE<1>_1" : { "U1_XF.AJ17" : {}, "U1_CPLD.G1" : {} }, "C2_DDR4_DQ<39>_XF" : { "J3_XF.247" : {}, "U1_XF.B55" : {} }, "AVCC_S_BNC_XF" : { "J9_XF.C" : {}, "R146_XF.2" : { "R146_XF.1" : { "PWR_AVCC_RS_RLC_XF" : {} } } }, "OCL3_PET_N<0>_XF" : { "C281_XF.2" : { "C281_XF.1" : { "AC_OCL3_PET_N<0>_XF" : { "U1_XF.BJ10" : {} } } }, "J1_O3_XF.B4" : {} }, "C1_DDR4_ALERT_N_XF" : { "U1_XF.CB58" : {}, "R241_XF.2" : { "R241_XF.1" : { "PWR_SDIMM_VDD_XF" : {} } }, "J2_XF.208" : {} }, "C3_SYS_CLK_P_XF" : { "R257_XF.2" : { "R257_XF.1" : { "PWR_NDIMM_VDD_XF" : {} } }, "C366_XF.2" : { "C366_XF.1" : { "DDR4_SYS_CLK_P<3>_XF" : { "U6_XF.10" : {} } } }, "R259_XF.1" : { "R259_XF.2" : { "C3_SYS_CLK_N_XF" : {} } }, "U1_XF.P25" : {}, "R258_XF.1" : { "R258_XF.2" : { "GND" : {} } } }, "C2_DDR4_DQ<47>_XF" : { "J3_XF.258" : {}, "U1_XF.C53" : {} }, "E1S2_PER_P<4>_XF" : { "U1_XF.AD4" : {}, "J1_E2_XF.A31" : {} }, "C0_RDIMM_DQS_C<4>_XF" : { "U1_XF.BM21" : {}, "J1_XF.244" : {} }, "POK_OD_AVCC_RN_LIN" : { "R2_FL_XF.2" : { "R2_FL_XF.1" : { "UNNAMED_4_LT3071_I30_PWRGD_FL" : { "U6_FL_XF.2" : {} } } }, "U1_CPLD.P10" : {} }, "UNNAMED_4_RESISTOR_I14_A_SD" : { "C31_SD_XF.1" : { "C31_SD_XF.2" : { "GND" : {} } }, "R62_SD_XF.2" : { "R62_SD_XF.1" : { "GND" : {} } }, "U2_SD_XF.1" : {}, "R68_SD_XF.1" : { "R68_SD_XF.2" : { "PWR_SDIMM_VDD_XF" : {} } } }, "C1_DDR4_DQ<61>_XF" : { "J2_XF.273" : {}, "U1_XF.BK53" : {} }, "AC_E1S1_PET_P<7>_XF" : { "U1_XF.R7" : {}, "C110_XF.1" : { "C110_XF.2" : { "E1S1_PET_P<7>_XF" : { "J1_E1_XF.B40" : {} } } } }, "E1S0_PER_N<1>_XF" : { "J1_E0_XF.A20" : {}, "U1_XF.E5" : {} }, "C3_RDIMM_DQS_T<14>_XF" : { "J4_XF.110" : {}, "U1_XF.A23" : {} }, "VMON_AVTT_SW_XF" : { "R99_SP_XF.2" : { "R99_SP_XF.1" : { "PWR_AVTT_SW_XF" : {} } }, "R142_XF.2" : { "R142_XF.1" : { "UNNAMED_17_RESISTOR_I119_A_XF" : { "R143_XF.1" : { "R143_XF.2" : { "GND" : {} } }, "R131_XF.2" : { "R131_XF.1" : { "UNNAMED_17_RESISTOR_I121_A_XF" : { "C269_XF.1" : { "C269_XF.2" : { "UNNAMED_17_RESISTOR_I124_A_XF" : { "R132_XF.1" : { "R132_XF.2" : { "UNNAMED_17_RESISTOR_I122_A_XF" : { "R145_XF.1" : { "R145_XF.2" : { "GND" : {} } }, "R144_XF.1" : { "R144_XF.2" : { "GND" : {} } } } } }, "U1_XF.BY30" : {} } } }, "U1_XF.BY29" : {} } } } } } } }, "IS_VCCINTUL_SW_P_SP" : { "C129_SP_XF.1" : { "C129_SP_XF.2" : { "GND" : {} } }, "R50_SP_XF.2" : { "R50_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I147_A_SP" : { "C34_SP_XF.1" : { "C34_SP_XF.2" : { "GND" : {} } }, "U1_SP_XF.43" : {} } } }, "R131_SP_XF.1" : { "R131_SP_XF.2" : { "UNNAMED_8_ACS711_I102_VIOUT_SP" : { "U5_SP_XF.11" : {} } } }, "R132_SP_XF.2" : { "R132_SP_XF.1" : { "GND" : {} } } }, "C1_DDR4_DQ<28>_XF" : { "J2_XF.36" : {}, "U1_XF.CB60" : {} }, "C0_DDR4_DQ<20>_XF" : { "U1_XF.BR18" : {}, "J1_XF.25" : {} }, "AC_E1S1_PET_N<6>_XF" : { "C131_XF.1" : { "C131_XF.2" : { "E1S1_PET_N<6>_XF" : { "J1_E1_XF.B36" : {} } } }, "U1_XF.R10" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I177_A_SP" : { "R40_SP_XF.2" : { "R40_SP_XF.1" : { "P12V_MAIN" : {} } }, "U1_SP_XF.9" : {}, "R42_SP_XF.1" : { "R42_SP_XF.2" : { "UNNAMED_3_LTC2975_I168_VINISN2975_SP" : { "U1_SP_XF.56" : {} } } }, "R14_SP_XF.1" : { "R14_SP_XF.2" : { "UNNAMED_3_LTC2975_I168_VINISP2975_SP" : { "U1_SP_XF.55" : {} } } }, "C63_SP_XF.1" : { "C63_SP_XF.2" : { "GND" : {} } } }, "RGB_LED_BLUE<2>_CPLD" : { "R20_CPLD.2" : { "R20_CPLD.1" : { "UNNAMED_9_LUMEXRGBLED_I90_BLUEK_CPLD" : { "D2_CPLD.3" : { "D2_CPLD.2" : { "UNNAMED_9_LUMEXRGBLED_I90_REDK_CPLD" : { "R4_CPLD.1" : { "R4_CPLD.2" : { "RGB_LED_RED<2>_CPLD" : { "U1_CPLD.D9" : {} } } } } }, "D2_CPLD.4" : { "UNNAMED_9_LUMEXRGBLED_I90_GREENK_CPLD" : { "R5_CPLD.1" : { "R5_CPLD.2" : { "RGB_LED_GREEN<2>_CPLD" : { "U1_CPLD.A8" : {} } } } } }, "D2_CPLD.1" : { "CPLD_P3R3V" : {} } } } } }, "U1_CPLD.B7" : {} }, "C1_RDIMM_DQS_C<8>_XF" : { "U1_XF.BV59" : {}, "J2_XF.196" : {} }, "UNNAMED_4_PI6CB33401_I37_PDF_E2" : { "R13_E2_XF.2" : { "R13_E2_XF.1" : { "GND" : {} } }, "U1_E2_XF.31" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I148_A_SP" : { "U1_SP_XF.42" : {}, "R51_SP_XF.1" : { "R51_SP_XF.2" : { "IS_VCCINTLL_SW_N_SP" : { "R129_SP_XF.1" : { "R129_SP_XF.2" : { "P3R3V" : {} } }, "C128_SP_XF.1" : { "C128_SP_XF.2" : { "GND" : {} } }, "R130_SP_XF.2" : { "R130_SP_XF.1" : { "GND" : {} } } } } }, "C39_SP_XF.1" : { "C39_SP_XF.2" : { "GND" : {} } } }, "DIMM_EVENT_OD_F<1>" : { "J2_XF.78" : {}, "U1_CPLD.K12" : {} }, "C0_RDIMM_DQS_C<2>_XF" : { "J1_XF.174" : {}, "U1_XF.BT15" : {} }, "UNNAMED_17_RESISTOR_I187_B_XF" : { "R75_XF.1" : { "R75_XF.2" : { "UNNAMED_17_RESISTOR_I54_A_XF" : { "R83_XF.1" : { "R83_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I49_B_XF" : { "C141_XF.2" : { "C141_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I49_A_XF" : { "R82_XF.2" : { "R82_XF.1" : { "UNNAMED_17_RESISTOR_I53_A_XF" : { "R73_XF.2" : { "R73_XF.1" : { "UNNAMED_17_RESISTOR_I188_B_XF" : { "R118_XF.2" : { "R118_XF.1" : { "GND" : {} } } } } }, "R72_XF.2" : { "R72_XF.1" : { "IMON_AVCC_LIN_XF" : { "R15_FL_XF.2" : { "R15_FL_XF.1" : { "UNNAMED_4_LT3071_I30_IMON_FL" : { "U6_FL_XF.21" : {} } } }, "R91_FL_XF.2" : { "R91_FL_XF.1" : { "UNNAMED_12_LT3071_I30_IMON_FL" : { "U10_FL_XF.21" : {} } } }, "R7_FL_XF.2" : { "R7_FL_XF.1" : { "UNNAMED_3_LT3071_I32_IMON_FL" : { "U3_FL_XF.21" : {} } } } } } } } } }, "U1_XF.BY38" : {} } } }, "U1_XF.CA38" : {} } } }, "R74_XF.2" : { "R74_XF.1" : { "GND" : {} } } } } }, "R119_XF.2" : { "R119_XF.1" : { "GND" : {} } } }, "C3_DDR4_PARITY_XF" : { "J4_XF.222" : {}, "U1_XF.R24" : {} }, "UNNAMED_4_PI6CB33401_I37_SDATA_E2" : { "U1_E2_XF.10" : {}, "R9_E2_XF.2" : { "R9_E2_XF.1" : { "PWR_FPGA_3R3V" : {} } } }, "C3_RDIMM_DQS_C<12>_XF" : { "J4_XF.41" : {}, "U1_XF.F23" : {} }, "AC_CONN_CLK_REFN<0>_3" : { "U1_E2_XF.14" : {}, "C25_E2_XF.1" : { "C25_E2_XF.2" : { "CONN_CLK_REFN<0>_E2" : { "J1_E2_XF.B14" : {} } } } }, "AC_PCIE1_TXP<4>_XF" : { "C29_XF.1" : { "C29_XF.2" : { "PCIE1_TXP<4>_XF" : { "J2_P1_XF.B3" : {} } } }, "U1_XF.AP13" : {} }, "E1S2_PET_P<1>_XF" : { "J1_E2_XF.B21" : {}, "C154_XF.2" : { "C154_XF.1" : { "AC_E1S2_PET_P<1>_XF" : { "U1_XF.W7" : {} } } } }, "OCL2_3R3V_PERST_F_XF" : { "U1_XF.AY17" : {}, "J1_O2_XF.A12" : {} }, "PCIE1_TXN<2>_XF" : { "J1_P1_XF.B16" : {}, "C47_XF.2" : { "C47_XF.1" : { "AC_PCIE1_TXN<2>_XF" : { "U1_XF.AN10" : {} } } } }, "VCCINT_BNC_XF" : { "R71_XF.2" : { "R71_XF.1" : { "PWR_VCCINT_XF" : {} } }, "J8_XF.C" : {} }, "UNNAMED_17_RESISTOR_I56_A_XF" : { "R104_XF.2" : { "R104_XF.1" : { "GND" : {} } }, "R79_XF.1" : { "R79_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I50_B_XF" : { "C139_XF.2" : { "C139_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I50_A_XF" : { "R78_XF.2" : { "R78_XF.1" : { "UNNAMED_17_RESISTOR_I55_A_XF" : { "R103_XF.2" : { "R103_XF.1" : { "GND" : {} } }, "R102_XF.2" : { "R102_XF.1" : { "VMON_AVCC_SW_XF" : { "R100_SP_XF.2" : { "R100_SP_XF.1" : { "PWR_AVCC_SW_XF" : {} } } } } } } } }, "U1_XF.CB38" : {} } } }, "U1_XF.CB39" : {} } } }, "R67_XF.2" : { "R67_XF.1" : { "GND" : {} } } }, "AC_PCIE1_TXN<6>_XF" : { "U1_XF.AT8" : {}, "C43_XF.1" : { "C43_XF.2" : { "PCIE1_TXN<6>_XF" : { "J2_P1_XF.B16" : {} } } } }, "CKO_LTM4650_PM4_SP" : { "R32_SP_XF.1" : { "R32_SP_XF.2" : { "UNNAMED_10_LTM4650FIXED_I151_MODEPLLIN_SP" : { "R27_SP_XF.2" : { "R27_SP_XF.1" : { "INTVCC_4650_BL_SP" : { "R7_SP_XF.1" : { "R7_SP_XF.2" : { "PHASMD_4650_BL_SP" : { "PM3_SP_XF.G4" : { "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.F4" : { "UNNAMED_10_LTM4650FIXED_I151_MODEPLLIN_SP" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.G3" : { "GND" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.E8" : { "INTVCC_4650_BL_SP" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.H8" : { "INTVCC_4650_BL_SP" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } } } }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} } }, "R24_SP_XF.2" : { "R24_SP_XF.1" : { "SGND_PM3_SP" : {} } } } } }, "C80_SP_XF.1" : { "C80_SP_XF.2" : { "GND" : {} } } } } }, "R28_SP_XF.2" : { "R28_SP_XF.1" : { "SGND_PM3_SP" : {} } } } } } }, "C3_DDR4_DQ<15>_XF" : { "J4_XF.166" : {}, "U1_XF.K25" : {} }, "SP_ENB3V_SEQ_M_CPLD" : { "U1_CPLD.L13" : {}, "R2_CPLD.1" : { "R2_CPLD.2" : { "GND" : {} } } }, "E1S3_PER_P<6>_XF" : { "J1_E3_XF.A37" : {}, "U1_XF.AL2" : {} }, "UNNAMED_11_LTM4650FIXED_I150_RUN1_SP" : { "R78_SP_XF.2" : { "R78_SP_XF.1" : { "ENB3V_SEQ_A" : { "R16_SP_XF.1" : { "R16_SP_XF.2" : { "UNNAMED_10_LTM4650FIXED_I151_RUN1_SP" : { "PM3_SP_XF.F5" : { "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} } } } }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.G3" : { "GND" : {} } } } } }, "R16_CPLD.1" : { "R16_CPLD.2" : { "GND" : {} } }, "U1_CPLD.P15" : {} } } } }, "C1_DDR4_DQ<27>_XF" : { "J2_XF.190" : {}, "U1_XF.BY60" : {} }, "UNNAMED_10_RESISTOR_I152_B_FL" : { "U9_FL_XF.5" : {}, "R66_FL_XF.2" : { "R66_FL_XF.1" : { "PWR_VCCAUX_SW_XF" : {} } } }, "E1S0_PER_N<7>_XF" : { "U1_XF.G1" : {}, "J1_E0_XF.A39" : {} }, "VCCADC_XF" : { "C143_XF.1" : { "C143_XF.2" : { "GNDADC_XF" : {} } }, "R84_XF.2" : { "R84_XF.1" : { "VREF_P1R25V_XF" : { "U1_XF.AN25" : {}, "U9_XF.3" : {}, "C142_XF.1" : { "C142_XF.2" : { "GNDADC_XF" : {} } }, "U9_XF.4" : {} } } }, "FB2_XF.1" : { "FB2_XF.2" : { "FPGA_VCCAUX_P1R8V" : {} } }, "U1_XF.AL25" : {} }, "INTVCC_4650_TR_SP" : { "C32_SP_XF.1" : { "C32_SP_XF.2" : { "GND" : {} } }, "PM5_SP_XF.E8" : { "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } } } }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.F10" : { "GND" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} } } }, "OCL0_3R3V_SCL_XF" : { "U1_XF.BM19" : {}, "R230_XF.2" : { "R230_XF.1" : { "P3R3V" : {} } }, "J1_O0_XF.A9" : {} }, "P12V_4650_TR_SP" : { "PM5_SP_XF.J3" : {}, "PM5_SP_XF.M4" : {}, "PM5_SP_XF.L4" : {}, "PM5_SP_XF.L6" : {}, "PM5_SP_XF.M6" : {}, "C10_SP_XF.1" : { "C10_SP_XF.2" : { "GND" : {} } }, "PM5_SP_XF.M8" : {}, "PM5_SP_XF.L8" : {}, "PM5_SP_XF.K2" : {}, "PM5_SP_XF.K9" : {}, "PM5_SP_XF.J11" : {}, "C31_SP_XF.1" : { "C31_SP_XF.2" : { "GND" : {} } }, "PM5_SP_XF.K3" : {}, "PM5_SP_XF.M10" : {}, "PM5_SP_XF.L10" : {}, "PM5_SP_XF.J2" : {}, "PM5_SP_XF.J9" : {}, "PM5_SP_XF.K11" : {}, "PM5_SP_XF.K4" : {}, "F5_SP_XF.2" : { "F5_SP_XF.1" : { "P12V_4650_URIGHT_SP" : {} } }, "PM5_SP_XF.M7" : {}, "PM5_SP_XF.L7" : {}, "PM5_SP_XF.J10" : {}, "PM5_SP_XF.L9" : {}, "PM5_SP_XF.M2" : {}, "PM5_SP_XF.M9" : {}, "PM5_SP_XF.L2" : {}, "PM5_SP_XF.M3" : {}, "PM5_SP_XF.L3" : {}, "PM5_SP_XF.M5" : {}, "PM5_SP_XF.J4" : {}, "PM5_SP_XF.L5" : {}, "C29_SP_XF.1" : { "C29_SP_XF.2" : { "GND" : {} } }, "PM5_SP_XF.K10" : {}, "PM5_SP_XF.L11" : {}, "PM5_SP_XF.M11" : {} }, "E1S2_PET_P<7>_XF" : { "J1_E2_XF.B40" : {}, "C148_XF.2" : { "C148_XF.1" : { "AC_E1S2_PET_P<7>_XF" : { "U1_XF.Y9" : {} } } } }, "C0_RDIMM_DQS_T<10>_XF" : { "J1_XF.18" : {}, "U1_XF.CB26" : {} }, "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "R87_SP_XF.1" : { "R87_SP_XF.2" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "R84_SP_XF.2" : { "R84_SP_XF.1" : { "UNNAMED_6_RESISTOR_I435_B_SP" : { "PM2_SP_XF.F10" : { "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } }, "U1_CPLD.N14" : {} } }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.E6" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.A11" : { "GND" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } } }, "R79_SP_XF.2" : { "R79_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } }, "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } }, "UNNAMED_5_LT3071_I30_PWRGD_FL" : { "U1_FL_XF.2" : {}, "R10_FL_XF.1" : { "R10_FL_XF.2" : { "POK_OD_AVTT_RLC_LIN" : { "U1_CPLD.L10" : {} } } } }, "UNNAMED_7_SM050TP_I160_1_CPLD" : { "U1_CPLD.T3" : {}, "TP15_CPLD.1" : {} }, "C1_DDR4_DQ<13>_XF" : { "J2_XF.159" : {}, "U1_XF.BR52" : {} }, "E1S3_PER_P<3>_XF" : { "U1_XF.AG6" : {}, "J1_E3_XF.A27" : {} }, "VS_AVCC_LIN_N_XF" : { "R30_SP_XF.2" : { "R30_SP_XF.1" : { "UNNAMED_3_BYPASSCAPNPOL_I153_A_SP" : { "U1_SP_XF.62" : {}, "C16_SP_XF.1" : { "C16_SP_XF.2" : { "GND" : {} } } } } }, "NS6_FL_XF.2" : { "NS6_FL_XF.1" : { "GND" : {} } } }, "AC_OCL1_PET_N<1>_XF" : { "U1_XF.BY8" : {}, "C272_XF.1" : { "C272_XF.2" : { "OCL1_PET_N<1>_XF" : { "J1_O1_XF.B7" : {} } } } }, "UNNAMED_9_LUMEXRGBLED_I92_BLUEK_CPLD" : { "R26_CPLD.1" : { "R26_CPLD.2" : { "RGB_LED_BLUE<0>_CPLD" : { "U1_CPLD.E6" : {} } } }, "D4_CPLD.3" : { "D4_CPLD.1" : { "CPLD_P3R3V" : {} }, "D4_CPLD.2" : { "UNNAMED_9_LUMEXRGBLED_I92_REDK_CPLD" : { "R24_CPLD.1" : { "R24_CPLD.2" : { "RGB_LED_RED<0>_CPLD" : { "U1_CPLD.E9" : {} } } } } }, "D4_CPLD.4" : { "UNNAMED_9_LUMEXRGBLED_I92_GREENK_CPLD" : { "R25_CPLD.1" : { "R25_CPLD.2" : { "RGB_LED_GREEN<0>_CPLD" : { "U1_CPLD.E8" : {} } } } } } } }, "OCL1_PER_N<3>_XF" : { "J1_O1_XF.A19" : {}, "U1_XF.BR5" : {} }, "C2_DDR4_ADR<3>_XF" : { "U1_XF.L61" : {}, "J3_XF.71" : {} }, "RFU_<1>_E0" : { "J1_E0_XF.A42" : {} }, "AC_OCL0_PET_P<2>_XF" : { "C177_XF.1" : { "C177_XF.2" : { "OCL0_PET_P<2>_XF" : { "J1_O0_XF.B15" : {} } } }, "U1_XF.CB9" : {} }, "E1S3_3R3V_CKEN_F<0>_XF" : { "U1_XF.R17" : {}, "U1_E3_XF.12" : {} }, "AC_CONN_CLK_REFN<0>" : { "U1_E1_XF.14" : {}, "C25_E1_XF.1" : { "C25_E1_XF.2" : { "CONN_CLK_REFN<0>_E1" : { "J1_E1_XF.B14" : {} } } } }, "OCL2_PER_P<2>_XF" : { "J1_O2_XF.A15" : {}, "U1_XF.BL2" : {} }, "E1S0_PER_N<5>_XF" : { "U1_XF.H3" : {}, "J1_E0_XF.A33" : {} }, "AC_PCIE1_TXP<2>_XF" : { "C31_XF.1" : { "C31_XF.2" : { "PCIE1_TXP<2>_XF" : { "J1_P1_XF.B15" : {} } } }, "U1_XF.AN11" : {} }, "NC_BR_2_SP" : {}, "AC_E1S3_PET_N<1>_XF" : { "C313_XF.1" : { "C313_XF.2" : { "E1S3_PET_N<1>_XF" : { "J1_E3_XF.B20" : {} } } }, "U1_XF.AH8" : {} }, "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : { "C81_SP_XF.2" : { "C81_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } }, "R87_SP_XF.2" : { "R87_SP_XF.1" : { "UNNAMED_6_LTM4671_I516_PHMODE0_SP" : { "PM2_SP_XF.E6" : { "PM2_SP_XF.N5" : { "GND" : {} }, "PM2_SP_XF.D9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J9" : { "GND" : {} }, "PM2_SP_XF.P3" : { "GND" : {} }, "PM2_SP_XF.T1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K7" : { "GND" : {} }, "PM2_SP_XF.M8" : { "POK_OD_AVCC_SW_P<1>" : { "U1_CPLD.M10" : {} } }, "PM2_SP_XF.G1" : { "GND" : {} }, "PM2_SP_XF.V7" : { "GND" : {} }, "PM2_SP_XF.W1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.V10" : { "GND" : {} }, "PM2_SP_XF.L11" : { "GND" : {} }, "PM2_SP_XF.A5" : { "GND" : {} }, "PM2_SP_XF.F7" : { "GND" : {} }, "PM2_SP_XF.M2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P4" : { "GND" : {} }, "PM2_SP_XF.K5" : { "GND" : {} }, "PM2_SP_XF.V5" : { "GND" : {} }, "PM2_SP_XF.P2" : { "GND" : {} }, "PM2_SP_XF.C9" : { "GND" : {} }, "PM2_SP_XF.T11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.M4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.M6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.A10" : { "GND" : {} }, "PM2_SP_XF.W11" : { "GND" : {} }, "PM2_SP_XF.U9" : { "GND" : {} }, "PM2_SP_XF.M3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.F5" : { "GND" : {} }, "PM2_SP_XF.L1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B9" : { "GND" : {} }, "PM2_SP_XF.A7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.R9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.H6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J7" : { "GND" : {} }, "PM2_SP_XF.H4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.P1" : { "GND" : {} }, "PM2_SP_XF.C5" : { "GND" : {} }, "PM2_SP_XF.D7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.L8" : { "ENB3V_SEQ_C" : { "U1_CPLD.N16" : {}, "R14_CPLD.1" : { "R14_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.V9" : { "GND" : {} }, "PM2_SP_XF.G3" : { "GND" : {} }, "PM2_SP_XF.T3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W4" : { "GND" : {} }, "PM2_SP_XF.R5" : { "GND" : {} }, "PM2_SP_XF.G6" : { "GND" : {} }, "PM2_SP_XF.T6" : { "GND" : {} }, "PM2_SP_XF.G4" : { "GND" : {} }, "PM2_SP_XF.T4" : { "GND" : {} }, "PM2_SP_XF.W3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B5" : { "GND" : {} }, "PM2_SP_XF.H3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.E5" : { "GND" : {} }, "PM2_SP_XF.L2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.D10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U5" : { "GND" : {} }, "PM2_SP_XF.P11" : { "GND" : {} }, "PM2_SP_XF.H8" : { "POK_OD_AVCC_SW_P<0>" : { "U1_CPLD.N11" : {} } }, "PM2_SP_XF.T2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.G2" : { "GND" : {} }, "PM2_SP_XF.R10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.L4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.J5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U10" : { "GND" : {} }, "PM2_SP_XF.C7" : { "GND" : {} }, "PM2_SP_XF.D5" : { "GND" : {} }, "PM2_SP_XF.W8" : { "GND" : {} }, "PM2_SP_XF.L6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B10" : { "GND" : {} }, "PM2_SP_XF.L3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.G8" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U7" : { "GND" : {} }, "PM2_SP_XF.C10" : { "GND" : {} }, "PM2_SP_XF.T8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.E7" : { "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP" : {} }, "PM2_SP_XF.M1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.B7" : { "GND" : {} }, "PM2_SP_XF.A9" : { "GND" : {} }, "PM2_SP_XF.W2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.R7" : { "POK_OD_AVTT_SW_P<1>" : { "U1_CPLD.M11" : {} } }, "PM2_SP_XF.N3" : { "GND" : {} }, "PM2_SP_XF.A4" : { "GND" : {} }, "PM2_SP_XF.C1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A6" : { "DN2_DP<3>_SP" : {} }, "PM2_SP_XF.M10" : { "GND" : {} }, "PM2_SP_XF.P5" : { "GND" : {} }, "PM2_SP_XF.D11" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K2" : { "GND" : {} }, "PM2_SP_XF.F8" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.R1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.N4" : { "GND" : {} }, "PM2_SP_XF.B1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F2" : { "GND" : {} }, "PM2_SP_XF.N6" : { "GND" : {} }, "PM2_SP_XF.M7" : { "GND" : {} }, "PM2_SP_XF.U1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.K8" : { "TS_LTM4671_CMN<0>" : { "R51.1" : {} } }, "PM2_SP_XF.V8" : { "GND" : {} }, "PM2_SP_XF.K3" : { "GND" : {} }, "PM2_SP_XF.C11" : { "GND" : {} }, "PM2_SP_XF.T9" : { "P12V_MAIN" : {} }, "PM2_SP_XF.V3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A8" : { "GND" : {} }, "PM2_SP_XF.D1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.P7" : { "ENB3V_SEQ_D" : { "U1_CPLD.N14" : {}, "R13_CPLD.1" : { "R13_CPLD.2" : { "GND" : {} } } } }, "PM2_SP_XF.F4" : { "GND" : {} }, "PM2_SP_XF.J1" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.N2" : { "GND" : {} }, "PM2_SP_XF.F6" : { "GND" : {} }, "PM2_SP_XF.M5" : { "GND" : {} }, "PM2_SP_XF.F3" : { "GND" : {} }, "PM2_SP_XF.P10" : { "PM2_VOSNS03_N_SP" : {} }, "PM2_SP_XF.A2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.W9" : { "GND" : {} }, "PM2_SP_XF.U11" : { "GND" : {} }, "PM2_SP_XF.K4" : { "GND" : {} }, "PM2_SP_XF.E11" : { "POK_OD_AVTT_SW_P<0>" : { "U1_CPLD.R9" : {} } }, "PM2_SP_XF.V4" : { "GND" : {} }, "PM2_SP_XF.K6" : { "GND" : {} }, "PM2_SP_XF.B11" : { "GND" : {} }, "PM2_SP_XF.V6" : { "GND" : {} }, "PM2_SP_XF.U6" : { "GND" : {} }, "PM2_SP_XF.B4" : { "GND" : {} }, "PM2_SP_XF.N1" : { "GND" : {} }, "PM2_SP_XF.D2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.L10" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.V11" : { "GND" : {} }, "PM2_SP_XF.B6" : { "GND" : {} }, "PM2_SP_XF.K11" : { "GND" : {} }, "PM2_SP_XF.E4" : { "GND" : {} }, "PM2_SP_XF.J2" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U4" : { "GND" : {} }, "PM2_SP_XF.R4" : { "GND" : {} }, "PM2_SP_XF.G5" : { "GND" : {} }, "PM2_SP_XF.T5" : { "GND" : {} }, "PM2_SP_XF.R3" : { "GND" : {} }, "PM2_SP_XF.F11" : { "ENB3V_SEQ_D" : {} }, "PM2_SP_XF.J8" : { "ENB3V_SEQ_C" : {} }, "PM2_SP_XF.D8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W5" : { "GND" : {} }, "PM2_SP_XF.A1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.B3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C6" : { "GND" : {} }, "PM2_SP_XF.L7" : { "GND" : {} }, "PM2_SP_XF.H5" : { "GND" : {} }, "PM2_SP_XF.U3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.C4" : { "GND" : {} }, "PM2_SP_XF.E3" : { "GND" : {} }, "PM2_SP_XF.V1" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E8" : { "P12V_MAIN" : {} }, "PM2_SP_XF.T7" : { "P12V_MAIN" : {} }, "PM2_SP_XF.U8" : { "GND" : {} }, "PM2_SP_XF.W10" : { "GND" : {} }, "PM2_SP_XF.K1" : { "GND" : {} }, "PM2_SP_XF.N11" : { "NC" : {} }, "PM2_SP_XF.B8" : { "GND" : {} }, "PM2_SP_XF.J3" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.C2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D3" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.U2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.E2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.F1" : { "GND" : {} }, "PM2_SP_XF.L5" : { "P12V_MAIN" : {} }, "PM2_SP_XF.J4" : { "PWR_AVCC_SW_XF" : {} }, "PM2_SP_XF.H7" : { "GND" : {} }, "PM2_SP_XF.D4" : { "GND" : {} }, "PM2_SP_XF.J6" : { "P12V_MAIN" : {} }, "PM2_SP_XF.B2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.D6" : { "GND" : {} }, "PM2_SP_XF.G10" : { "GND" : {} }, "PM2_SP_XF.C8" : { "GND" : {} }, "PM2_SP_XF.T10" : { "P12V_MAIN" : {} }, "PM2_SP_XF.W7" : { "DP2_DN<3>_SP" : {} }, "PM2_SP_XF.R2" : { "PWR_AVTT_SW_XF" : {} }, "PM2_SP_XF.A11" : { "GND" : {} } }, "R76_SP_XF.2" : { "R76_SP_XF.1" : { "PM2_SP_AGND_SP" : {} } } } } } }, "OCL1_3R3V_BP_TYPE_XF" : { "J1_O1_XF.B9" : {}, "U1_XF.BK18" : {} }, "UNNAMED_3_BYPASSCAPNPOL_I7_A_MP" : { "U1_MP.13" : {}, "C3_MP.1" : { "C3_MP.2" : { "UNNAMED_3_BYPASSCAPNPOL_I7_B_MP" : { "U1_MP.11" : {}, "U1_MP.10" : {}, "L1_MP.1" : { "L1_MP.2" : { "CPLD_P1R8V_1" : {} } }, "U1_MP.12" : {} } } } }, "C1_RDIMM_DQS_T<5>_XF" : { "U1_XF.BL61" : {}, "J2_XF.256" : {} }, "PCIE0_TXP<0>_XF" : { "C41_XF.2" : { "C41_XF.1" : { "AC_PCIE0_TXP<0>_XF" : { "U1_XF.AU11" : {} } } }, "J1_P0_XF.B3" : {} }, "PWR_SDIMM_VTT_XF" : { "NS3_SD_XF.1" : { "NS3_SD_XF.2" : { "VS_DIMM_VTT_LIN_SD" : {} } }, "C38_SD_XF.1" : { "C38_SD_XF.2" : { "GND" : {} } }, "J2_XF.77" : {}, "J2_XF.221" : {}, "U2_SD_XF.3" : {}, "J1_XF.221" : {}, "C36_SD_XF.1" : { "C36_SD_XF.2" : { "GND" : {} } }, "C44_SD_XF.1" : { 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"PM4_ND_XF.D5" : { "GND" : {} }, "PM4_ND_XF.M4" : { "GND" : {} }, "PM4_ND_XF.L4" : { "GND" : {} }, "PM4_ND_XF.C2" : { "GND" : {} }, "PM4_ND_XF.L6" : { "GND" : {} }, "PM4_ND_XF.M6" : { "GND" : {} }, "PM4_ND_XF.G9" : { "GND" : {} }, "PM4_ND_XF.H8" : { "GND" : {} }, "PM4_ND_XF.K5" : { "GND" : {} }, "PM4_ND_XF.A8" : { "GND" : {} }, "PM4_ND_XF.C8" : { "GND" : {} }, "PM4_ND_XF.K6" : { "GND" : {} }, "PM4_ND_XF.H9" : { "GND" : {} }, "PM4_ND_XF.M3" : { "GND" : {} }, "PM4_ND_XF.G8" : { "GND" : {} }, "PM4_ND_XF.L3" : { "GND" : {} }, "PM4_ND_XF.E9" : { "GND" : {} }, "PM4_ND_XF.M5" : { "GND" : {} }, "PM4_ND_XF.F1" : { "GND" : {} }, "PM4_ND_XF.L5" : { "GND" : {} }, "PM4_ND_XF.B7" : { "GND" : {} }, "PM4_ND_XF.A2" : { "GND" : {} }, "PM4_ND_XF.B2" : { "GND" : {} }, "PM4_ND_XF.A7" : { "GND" : {} } } } } }, "U1_CPLD.M14" : {}, "R12_CPLD.1" : { "R12_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.G5" : { "GND" : {} }, "PM1_SP_XF.W4" : { "GND" : {} }, "PM1_SP_XF.T5" : { "GND" : {} }, "PM1_SP_XF.R4" : { "GND" : {} }, "PM1_SP_XF.W6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.V11" : { "GND" : {} }, "PM1_SP_XF.P1" : { "GND" : {} }, "PM1_SP_XF.J7" : { "GND" : {} }, "PM1_SP_XF.U4" : { "GND" : {} }, "PM1_SP_XF.K11" : { "GND" : {} }, "PM1_SP_XF.B6" : { "GND" : {} }, "PM1_SP_XF.E4" : { "GND" : {} }, "PM1_SP_XF.C5" : { "GND" : {} }, "PM1_SP_XF.B4" : { "GND" : {} }, "PM1_SP_XF.N1" : { "GND" : {} }, "PM1_SP_XF.U6" : { "GND" : {} }, "PM1_SP_XF.H5" : { "GND" : {} }, "PM1_SP_XF.L7" : { "GND" : {} }, "PM1_SP_XF.U5" : { "GND" : {} }, "PM1_SP_XF.E3" : { "GND" : {} }, "PM1_SP_XF.E5" : { "GND" : {} }, "PM1_SP_XF.C4" : { "GND" : {} }, "PM1_SP_XF.B5" : { "GND" : {} }, "PM1_SP_XF.C6" : { "GND" : {} }, "PM1_SP_XF.J8" : { "ENB3V_SEQ_E" : {} }, "PM1_SP_XF.G4" : { "GND" : {} }, "PM1_SP_XF.F11" : { "ENB3V_SEQ_B" : { "U1_CPLD.R16" : {}, "R15_CPLD.1" : { "R15_CPLD.2" : { "GND" : {} } } } }, "PM1_SP_XF.W5" : { "GND" : {} }, "PM1_SP_XF.T4" : { "GND" : {} }, "PM1_SP_XF.G6" : { "GND" : {} }, "PM1_SP_XF.R3" : { "GND" : {} }, "PM1_SP_XF.R5" : { "GND" : {} }, "PM1_SP_XF.T6" : { "GND" : {} }, "PM1_SP_XF.A10" : { "GND" : {} }, "PM1_SP_XF.F6" : { "GND" : {} }, "PM1_SP_XF.N2" : { "GND" : {} }, "PM1_SP_XF.C9" : { "GND" : {} }, "PM1_SP_XF.P2" : { "GND" : {} }, "PM1_SP_XF.F4" : { "GND" : {} }, "PM1_SP_XF.A8" : { "GND" : {} }, "PM1_SP_XF.C11" : { "GND" : {} }, "PM1_SP_XF.K5" : { "GND" : {} }, "PM1_SP_XF.K3" : { "GND" : {} }, "PM1_SP_XF.V5" : { "GND" : {} }, "PM1_SP_XF.K6" : { "GND" : {} }, "PM1_SP_XF.B11" : { "GND" : {} }, "PM1_SP_XF.V6" : { "GND" : {} }, "PM1_SP_XF.K4" : { "GND" : {} }, "PM1_SP_XF.U11" : { "GND" : {} }, "PM1_SP_XF.W9" : { "GND" : {} }, "PM1_SP_XF.V4" : { "GND" : {} }, "PM1_SP_XF.A7" : { "DP4_DN<5>_SP" : {} }, "PM1_SP_XF.B9" : { "GND" : {} }, "PM1_SP_XF.M5" : { "GND" : {} }, "PM1_SP_XF.U9" : { "GND" : {} }, "PM1_SP_XF.W11" : { "GND" : {} }, "PM1_SP_XF.F5" : { "GND" : {} }, "PM1_SP_XF.F3" : { "GND" : {} }, "PM1_SP_XF.K7" : { "GND" : {} }, "PM1_SP_XF.V7" : { "GND" : {} }, "PM1_SP_XF.K2" : { "GND" : {} }, "PM1_SP_XF.G1" : { "GND" : {} }, "PM1_SP_XF.M10" : { "GND" : {} }, "PM1_SP_XF.A6" : { "DN4_DP<5>_SP" : {} }, "PM1_SP_XF.P5" : { "GND" : {} }, "PM1_SP_XF.P3" : { "GND" : {} }, "PM1_SP_XF.J9" : { "GND" : {} }, "PM1_SP_XF.N5" : { "GND" : {} }, "PM1_SP_XF.N3" : { "GND" : {} }, "PM1_SP_XF.A4" : { "GND" : {} }, "PM1_SP_XF.M7" : { "GND" : {} }, "PM1_SP_XF.F2" : { "GND" : {} }, "PM1_SP_XF.N6" : { "GND" : {} }, "PM1_SP_XF.P4" : { "GND" : {} }, "PM1_SP_XF.V8" : { "GND" : {} }, "PM1_SP_XF.F7" : { "GND" : {} }, "PM1_SP_XF.N4" : { "GND" : {} }, "PM1_SP_XF.A5" : { "GND" : {} }, "PM1_SP_XF.L11" : { "GND" : {} }, "PM1_SP_XF.V10" : { "GND" : {} } } }, "UNNAMED_4_MAX116XXQSOP16_I97_AIN2" : { "U11.7" : {}, "R46.1" : { "R46.2" : { "VMON_RN_RUC_MGTVCCAUX" : { "R83_FL_XF.2" : { "R83_FL_XF.1" : { "PWR_RN_RUC_MGTVCCAUX_XF" : {} } } } } }, "C47.1" : { "C47.2" : { "GND" : {} } }, "R28.1" : { "R28.2" : { "GND" : {} } } }, "AC_E1S3_PET_N<5>_XF" : { "U1_XF.AK12" : {}, "C326_XF.1" : { "C326_XF.2" : { "E1S3_PET_N<5>_XF" : { "J1_E3_XF.B33" : {} } } } }, "FPGA_ERR_VIS<2>_1" : { "U1_CPLD.K3" : {}, "U1_XF.CC38" : {} }, "C1_DDR4_DQ<22>_XF" : { "U1_XF.BP56" : {}, "J2_XF.32" : {} }, "OCL2_3R3V_CWAKE_F_XF" : { "J1_O2_XF.B10" : {}, "U1_XF.AV19" : {} }, "FP_HDD_LED_N" : { "FPNL_CONN.9" : {}, "U1_CPLD.J14" : {} }, "E1S3_PET_N<2>_XF" : { "J1_E3_XF.B23" : {}, "C312_XF.2" : { "C312_XF.1" : { "AC_E1S3_PET_N<2>_XF" : { "U1_XF.AG10" : {} } } } }, "OCL1_3R3V_CKEN_F<1>_XF" : { "U7_XF.19" : {}, "U1_XF.BL20" : {} }, "C2_DDR4_DQ<1>_XF" : { "U1_XF.U48" : {}, "J3_XF.150" : {} }, "UNNAMED_22_RESISTOR_I39_B_XF" : { "U1_XF.M26" : {}, "R51_XF.2" : { "R51_XF.1" : { "GND" : {} } } }, "FPGA_CPLD_DVAL_1" : { "U1_XF.BU34" : {}, "U1_CPLD.D11" : {} }, "P12V_FUSED_4675_SD" : { "F7_SD_XF.2" : { "F7_SD_XF.1" : { "P12V_MAIN" : {} } }, "C2_SD_XF.1" : { "C2_SD_XF.2" : { "GND" : {} } }, "PM4_SD_XF.L9" : {}, "C7_SD_XF.1" : { "C7_SD_XF.2" : { "GND" : {} } }, "PM4_SD_XF.M9" : {}, "PM4_SD_XF.K9" : {}, "C68_SD_XF.2" : { "C68_SD_XF.1" : { "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF" : {} } }, "PM4_SD_XF.F9" : {}, "PM4_SD_XF.C9" : {}, "PM4_SD_XF.A9" : {}, "PM4_SD_XF.J9" : {}, "PM4_SD_XF.D9" : {}, "PM4_SD_XF.B9" : {}, "C67_SD_XF.2" : { "C67_SD_XF.1" : { "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF" : {} } }, "C66_SD_XF.1" : { "C66_SD_XF.2" : { "GND" : {} } }, "C10_SD_XF.1" : { "C10_SD_XF.2" : { "GND" : {} } } }, "OCL1_PET_P<2>_XF" : { "J1_O1_XF.B15" : {}, "C182_XF.2" : { "C182_XF.1" : { "AC_OCL1_PET_P<2>_XF" : { "U1_XF.BW11" : {} } } } }, "PCIE0_RXP<4>_XF" : { "U1_XF.BA2" : {}, "J2_P0_XF.A3" : {} }, "UNNAMED_11_CAPACITOR_I148_A_SP" : { "R112_SP_XF.1" : { "R112_SP_XF.2" : { "CMP_4650_SP" : { "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} } } } } } }, "C3_DDR4_ADR<7>_XF" : { "U1_XF.T28" : {}, "J4_XF.211" : {} }, "OCL2_CONN_REFCLK_N_XF" : { "C388_XF.2" : { "C388_XF.1" : { "AC_OCL2_CONN_REFCLK_N_XF" : { "U5_XF.14" : {} } } }, "J1_O2_XF.B13" : {} }, "PHASMD_4650_TR_SP" : { "PM5_SP_XF.G4" : { "PM5_SP_XF.G10" : { "GND" : {} }, "PM5_SP_XF.C8" : { "NC" : {} }, "PM5_SP_XF.K12" : { "GND" : {} }, "PM5_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H7" : { "GND" : {} }, "PM5_SP_XF.F1" : { "GND" : {} }, "PM5_SP_XF.E2" : { "GND" : {} }, "PM5_SP_XF.M1" : { "GND" : {} }, "PM5_SP_XF.H2" : { "GND" : {} }, "PM5_SP_XF.D4" : { "GND" : {} }, "PM5_SP_XF.E7" : { "CMP_4650_SP" : { "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } } } }, "PM5_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B7" : { "GND" : {} }, "PM5_SP_XF.J5" : { "GND" : {} }, "PM5_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H10" : { "GND" : {} }, "PM5_SP_XF.E10" : { "GND" : {} }, "PM5_SP_XF.D3" : { "GND" : {} }, "PM5_SP_XF.F12" : { "GND" : {} }, "PM5_SP_XF.M12" : { "GND" : {} }, "PM5_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K1" : { "GND" : {} }, "PM5_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.H3" : { "GND" : {} }, "PM5_SP_XF.H5" : { "GND" : {} }, "PM5_SP_XF.E3" : { "GND" : {} }, "PM5_SP_XF.D10" : { "GND" : {} }, "PM5_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.J8" : { "GND" : {} }, "PM5_SP_XF.F11" : { "GND" : {} }, "PM5_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM5_SP_XF.G3" : { "GND" : {} }, "PM5_SP_XF.G5" : { "NC" : {} }, "PM5_SP_XF.H6" : { "GND" : {} }, "PM5_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM5_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J7" : { "NC" : {} }, "PM5_SP_XF.H4" : { "GND" : {} }, "PM5_SP_XF.D2" : { "GND" : {} }, "PM5_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E4" : { "GND" : {} }, "PM5_SP_XF.B6" : { "GND" : {} }, "PM5_SP_XF.C5" : { "NC" : {} }, "PM5_SP_XF.E11" : { "GND" : {} }, "PM5_SP_XF.H11" : { "GND" : {} }, "PM5_SP_XF.K6" : { "GND" : {} }, "PM5_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L1" : { "GND" : {} }, "PM5_SP_XF.H9" : { "GND" : {} }, "PM5_SP_XF.F3" : { "GND" : {} }, "PM5_SP_XF.A7" : { "GND" : {} }, "PM5_SP_XF.D12" : { "GND" : {} }, "PM5_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.J12" : { "GND" : {} }, "PM5_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.D1" : { "GND" : {} }, "PM5_SP_XF.J1" : { "GND" : {} }, "PM5_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.L12" : { "GND" : {} }, "PM5_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K5" : { "GND" : {} }, "PM5_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.K8" : { "GND" : {} }, "PM5_SP_XF.E1" : { "GND" : {} }, "PM5_SP_XF.F2" : { "GND" : {} }, "PM5_SP_XF.H1" : { "GND" : {} }, "PM5_SP_XF.G12" : { "GND" : {} }, "PM5_SP_XF.K7" : { "GND" : {} }, "PM5_SP_XF.D11" : { "GND" : {} }, "PM5_SP_XF.F8" : { "NC" : {} }, "PM5_SP_XF.G1" : { "GND" : {} }, "PM5_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.E12" : { "GND" : {} }, "PM5_SP_XF.H12" : { "GND" : {} }, "PM5_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.A6" : { "GND" : {} }, "PM5_SP_XF.D9" : { "GND" : {} }, "PM5_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM5_SP_XF.F10" : { "GND" : {} } } }, "OCL2_PET_N<3>_XF" : { "C274_XF.2" : { "C274_XF.1" : { "AC_OCL2_PET_N<3>_XF" : { "U1_XF.BK8" : {} } } }, "J1_O2_XF.B19" : {} }, "C2_DDR4_ADR<15>_XF" : { "U1_XF.G59" : {}, "J3_XF.86" : {} }, "AC_OCL3_CONN_REFCLK_P_XF" : { "C359_XF.1" : { "C359_XF.2" : { "OCL3_CONN_REFCLK_P_XF" : { "J1_O3_XF.B12" : {} } } }, "U5_XF.17" : {} }, "UNNAMED_22_RESISTOR_I48_B_XF" : { "R57_XF.2" : { "R57_XF.1" : { "GND" : {} } }, "U1_XF.BV29" : {} }, "UNNAMED_10_LTM4650FIXED_I151_PGOOD1_SP" : { "R29_SP_XF.1" : { "R29_SP_XF.2" : { "POK_OD_VCCINT_BLSW_P<0>" : { "U1_CPLD.P11" : {} } } }, "PM3_SP_XF.G9" : { "PM3_SP_XF.G12" : { "GND" : {} }, "PM3_SP_XF.E1" : { "GND" : {} }, "PM3_SP_XF.F2" : { "GND" : {} }, "PM3_SP_XF.K8" : { "GND" : {} }, "PM3_SP_XF.F7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H1" : { "GND" : {} }, "PM3_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D9" : { "GND" : {} }, "PM3_SP_XF.A6" : { "GND" : {} }, "PM3_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F10" : { "GND" : {} }, "PM3_SP_XF.E12" : { "GND" : {} }, "PM3_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H12" : { "GND" : {} }, "PM3_SP_XF.D11" : { "GND" : {} }, "PM3_SP_XF.K7" : { "GND" : {} }, "PM3_SP_XF.G1" : { "GND" : {} }, "PM3_SP_XF.F8" : { "NC" : {} }, "PM3_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D12" : { "GND" : {} }, "PM3_SP_XF.A7" : { "GND" : {} }, "PM3_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J12" : { "GND" : {} }, "PM3_SP_XF.E9" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.F3" : { "GND" : {} }, "PM3_SP_XF.L1" : { "GND" : {} }, "PM3_SP_XF.H9" : { "GND" : {} }, "PM3_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K6" : { "GND" : {} }, "PM3_SP_XF.E11" : { "GND" : {} }, "PM3_SP_XF.H11" : { "GND" : {} }, "PM3_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K5" : { "GND" : {} }, "PM3_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.L12" : { "GND" : {} }, "PM3_SP_XF.D1" : { "GND" : {} }, "PM3_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J1" : { "GND" : {} }, "PM3_SP_XF.F11" : { "GND" : {} }, "PM3_SP_XF.J8" : { "GND" : {} }, "PM3_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.G6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.H5" : { "GND" : {} }, "PM3_SP_XF.H3" : { "GND" : {} }, "PM3_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E5" : { "SS_LTM4650_SP" : {} }, "PM3_SP_XF.E3" : { "GND" : {} }, "PM3_SP_XF.D10" : { "GND" : {} }, "PM3_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.D2" : { "GND" : {} }, "PM3_SP_XF.H4" : { "GND" : {} }, "PM3_SP_XF.J7" : { "NC" : {} }, "PM3_SP_XF.B6" : { "GND" : {} }, "PM3_SP_XF.E4" : { "GND" : {} }, "PM3_SP_XF.C5" : { "NC" : {} }, "PM3_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H6" : { "GND" : {} }, "PM3_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E6" : { "CMP_4650_SP" : {} }, "PM3_SP_XF.G3" : { "GND" : {} }, "PM3_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.B7" : { "GND" : {} }, "PM3_SP_XF.D6" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.F1" : { "GND" : {} }, "PM3_SP_XF.E2" : { "GND" : {} }, "PM3_SP_XF.H7" : { "GND" : {} }, "PM3_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "PM4_SP_XF.E6" : { "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.F4" : { "UNNAMED_4_LTM4650FIXED_I78_MODEPLLIN_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C6" : { "FSET_4650_TL_SP" : { "R4_SP_XF.2" : { "R4_SP_XF.1" : { "SGND_PM4_SP" : {} } } } }, "PM4_SP_XF.B3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D10" : { "GND" : {} }, "PM4_SP_XF.E3" : { "GND" : {} }, "PM4_SP_XF.C4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.E5" : { "SS_LTM4650_SP" : { "C6_SP_XF.1" : { "C6_SP_XF.2" : { "SGND_PM4_SP" : {} } }, "C186_SP_XF.1" : { "C186_SP_XF.2" : { "SGND_PM7_SP" : {} } }, "C76_SP_XF.1" : { "C76_SP_XF.2" : { "SGND_PM3_SP" : {} } } } }, "PM4_SP_XF.L2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H3" : { "GND" : {} }, "PM4_SP_XF.J10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H5" : { "GND" : {} }, "PM4_SP_XF.L7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.D8" : { "SS_LTM4650_SP" : {} }, "PM4_SP_XF.M11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J8" : { "GND" : {} }, "PM4_SP_XF.G4" : { "PHASMD_4650_TL_SP" : {} }, "PM4_SP_XF.F11" : { "GND" : {} }, "PM4_SP_XF.K9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G3" : { "GND" : {} }, "PM4_SP_XF.L8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G5" : { "UNNAMED_4_LTM4650FIXED_I78_CLKOUT_SP" : {} }, "PM4_SP_XF.B4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H6" : { "GND" : {} }, "PM4_SP_XF.C3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B6" : { "GND" : {} }, "PM4_SP_XF.E4" : { "GND" : {} }, "PM4_SP_XF.C5" : { "NC" : {} }, "PM4_SP_XF.L10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H4" : { "GND" : {} }, "PM4_SP_XF.J7" : { "NC" : {} }, "PM4_SP_XF.D2" : { "GND" : {} }, "PM4_SP_XF.C8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.G10" : { "GND" : {} }, "PM4_SP_XF.K12" : { "GND" : {} }, "PM4_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } } } }, "PM3_SP_XF.D4" : { "GND" : {} }, "PM3_SP_XF.M1" : { "GND" : {} }, "PM3_SP_XF.H2" : { "GND" : {} }, "PM3_SP_XF.A11" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.K12" : { "GND" : {} }, "PM3_SP_XF.G10" : { "GND" : {} }, "PM3_SP_XF.C8" : { "NC" : {} }, "PM3_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.G7" : { "SGND_PM3_SP" : {} }, "PM3_SP_XF.K1" : { "GND" : {} }, "PM3_SP_XF.F12" : { "GND" : {} }, "PM3_SP_XF.M12" : { "GND" : {} }, "PM3_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.H10" : { "GND" : {} }, "PM3_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM3_SP_XF.J5" : { "GND" : {} }, "PM3_SP_XF.E10" : { "GND" : {} }, "PM3_SP_XF.D3" : { "GND" : {} }, "PM3_SP_XF.C7" : { "SGND_PM3_SP" : {} } } }, "C1_DDR4_ADR<11>_XF" : { "J2_XF.210" : {}, "U1_XF.CB51" : {} }, "UNNAMED_22_RESISTOR_I40_B_XF" : { "R55_XF.2" : { "R55_XF.1" : { "GND" : {} } }, "U1_XF.BR25" : {} }, "C2_DDR4_CS_N<3>_XF" : { "J3_XF.237" : {}, "U1_XF.J56" : {} }, "C1_RDIMM_DQS_C<0>_XF" : { "U1_XF.BM50" : {}, "J2_XF.152" : {} }, "C2_DDR4_DQ<25>_XF" : { "U1_XF.L53" : {}, "J3_XF.183" : {} }, "E1S1_PER_P<7>_XF" : { "U1_XF.R2" : {}, "J1_E1_XF.A40" : {} }, "GND" : { "J1_XF.189" : {}, "U1_XF.BP15" : {}, "C4_XF.1" : { "C4_XF.2" : { "PWR_VCCINT_XF" : {} } }, "PM5_SP_XF.A7" : {}, "PM4_SP_XF.H11" : {}, "C466_XF.2" : { "C466_XF.1" : { "PWR_AVCC_RS_RLC_XF" : {} } }, "U1_XF.M7" : {}, "PM4_SD_XF.H9" : {}, "PM4_SD_XF.K6" : {}, "PM4_ND_XF.M7" : {}, "J1_E2_XF.A29" : {}, "PM1_SP_XF.W4" : {}, "J1_PX1_XF.B18" : {}, "R111_FL_XF.1" : { "R111_FL_XF.2" : { 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"GND" : {} }, "PM4_SP_XF.L5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E2" : { "GND" : {} }, "PM4_SP_XF.F1" : { "GND" : {} }, "PM4_SP_XF.J4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H7" : { "GND" : {} }, "PM4_SP_XF.L3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E7" : { "CMP_4650_SP" : { "C79_SP_XF.2" : { "C79_SP_XF.1" : { "SGND_PM3_SP" : {} } }, "R13_SP_XF.2" : { "R13_SP_XF.1" : { "UNNAMED_4_CAPACITOR_I11_A_SP" : { "C20_SP_XF.1" : { "C20_SP_XF.2" : { "SGND_PM4_SP" : {} } } } } }, "R112_SP_XF.2" : { "R112_SP_XF.1" : { "UNNAMED_11_CAPACITOR_I148_A_SP" : { "C195_SP_XF.1" : { "C195_SP_XF.2" : { "SGND_PM7_SP" : {} } } } } }, "C200_SP_XF.2" : { "C200_SP_XF.1" : { "SGND_PM7_SP" : {} } }, "R10_SP_XF.2" : { "R10_SP_XF.1" : { "UNNAMED_10_CAPACITOR_I11_A_SP" : { "C56_SP_XF.1" : { "C56_SP_XF.2" : { "SGND_PM3_SP" : {} } } } } } } }, "PM4_SP_XF.D4" : { "GND" : {} }, "PM4_SP_XF.M1" : { "GND" : {} }, "PM4_SP_XF.H2" : { "GND" : {} }, "PM4_SP_XF.C10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J6" : { "TS_LT4650_TL_SP" : {} }, "PM4_SP_XF.B2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.B7" : { "GND" : {} }, "PM4_SP_XF.C2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.J5" : { "GND" : {} }, "PM4_SP_XF.H10" : { "GND" : {} }, "PM4_SP_XF.J3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.E10" : { "GND" : {} }, "PM4_SP_XF.D3" : { "GND" : {} }, "PM4_SP_XF.F12" : { "GND" : {} }, "PM4_SP_XF.L6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.B10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M12" : { "GND" : {} }, "PM4_SP_XF.G7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.H8" : { "INTVCC_4650_TL_SP" : { "C9_SP_XF.1" : { "C9_SP_XF.2" : { "GND" : {} } } } }, "PM4_SP_XF.K1" : { "GND" : {} }, "PM4_SP_XF.G2" : { "SW1_4650_TL_SP" : {} }, "PM4_SP_XF.B8" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.B1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A3" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.C12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.A5" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K8" : { "GND" : {} }, "PM4_SP_XF.F2" : { "GND" : {} }, "PM4_SP_XF.E1" : { "GND" : {} }, "PM4_SP_XF.M7" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.F7" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.M2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H1" : { "GND" : {} }, "PM4_SP_XF.G12" : { "GND" : {} }, "PM4_SP_XF.K10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M8" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K7" : { "GND" : {} }, "PM4_SP_XF.D11" : { "GND" : {} }, "PM4_SP_XF.F8" : { "UNNAMED_4_CAPACITOR_I132_A_SP" : {} }, "PM4_SP_XF.J11" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.K2" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.G1" : { "GND" : {} }, "PM4_SP_XF.E12" : { "GND" : {} }, "PM4_SP_XF.A4" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.H12" : { "GND" : {} }, "PM4_SP_XF.A6" : { "GND" : {} }, "PM4_SP_XF.B12" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M10" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C1" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D9" : { "GND" : {} }, "PM4_SP_XF.F10" : { "GND" : {} }, "PM4_SP_XF.J9" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.E11" : { "GND" : {} }, "PM4_SP_XF.K4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.H11" : { "GND" : {} }, "PM4_SP_XF.K6" : { "GND" : {} }, "PM4_SP_XF.B11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.M5" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.M3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.L1" : { "GND" : {} }, "PM4_SP_XF.H9" : { "GND" : {} }, "PM4_SP_XF.F3" : { "GND" : {} }, "PM4_SP_XF.D12" : { "GND" : {} }, "PM4_SP_XF.A7" : { "GND" : {} }, "PM4_SP_XF.B9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.J12" : { "GND" : {} }, "PM4_SP_XF.A2" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.D1" : { "GND" : {} }, "PM4_SP_XF.M4" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.C9" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.G11" : { "SW2_4650_TL_SP" : {} }, "PM4_SP_XF.J1" : { "GND" : {} }, "PM4_SP_XF.M6" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A10" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.L12" : { "GND" : {} }, "PM4_SP_XF.F6" : { "SGND_PM4_SP" : {} }, "PM4_SP_XF.C11" : { "PWR_VCCINT_XF" : {} }, "PM4_SP_XF.K5" : { "GND" : {} }, "PM4_SP_XF.K3" : { "P12V_4650_TL_SP" : {} }, "PM4_SP_XF.A8" : { "PWR_VCCINT_XF" : {} } } } } } }, "C2_RDIMM_DQS_C<17>_XF" : { "U1_XF.E58" : {}, "J3_XF.52" : {} }, "NC_BL_2_SP" : {}, "CONN_CLK_REFN<0>_E2" : { "J1_E2_XF.B14" : {}, "C25_E2_XF.2" : { "C25_E2_XF.1" : { "AC_CONN_CLK_REFN<0>_3" : { "U1_E2_XF.14" : {} } } } }, "UNNAMED_9_LUMEXRGBLED_I91_REDK_CPLD" : { "R21_CPLD.1" : { "R21_CPLD.2" : { "RGB_LED_RED<1>_CPLD" : { "U1_CPLD.D8" : {} } } }, "D3_CPLD.2" : { "D3_CPLD.3" : { "UNNAMED_9_LUMEXRGBLED_I91_BLUEK_CPLD" : { "R23_CPLD.1" : { "R23_CPLD.2" : { "RGB_LED_BLUE<1>_CPLD" : { "U1_CPLD.C7" : {} } } } } }, "D3_CPLD.1" : { "CPLD_P3R3V" : {} }, "D3_CPLD.4" : { "UNNAMED_9_LUMEXRGBLED_I91_GREENK_CPLD" : { "R22_CPLD.1" : { "R22_CPLD.2" : { "RGB_LED_GREEN<1>_CPLD" : { "U1_CPLD.F7" : {} } } } } } } }, "C1_RDIMM_DQS_C<1>_XF" : { "J2_XF.163" : {}, "U1_XF.BT51" : {} }, "UNNAMED_3_LTC2975_I168_WDIRESETF_SP" : { "R39_SP_XF.2" : { "R39_SP_XF.1" : { "P3R3V" : {} } }, "U1_SP_XF.24" : {} }, "P12V_4650_TL_SP" : { "PM4_SP_XF.J10" : {}, "PM4_SP_XF.M7" : {}, "PM4_SP_XF.L7" : {}, "PM4_SP_XF.L9" : {}, "PM4_SP_XF.M2" : {}, "PM4_SP_XF.M9" : {}, "PM4_SP_XF.L2" : {}, "PM4_SP_XF.K4" : {}, "F4_SP_XF.2" : { "F4_SP_XF.1" : { "P12V_4650_ULEFT_SP" : {} } }, "PM4_SP_XF.K10" : {}, "PM4_SP_XF.L11" : {}, "PM4_SP_XF.M11" : {}, "PM4_SP_XF.M5" : {}, "PM4_SP_XF.J4" : {}, "PM4_SP_XF.L5" : {}, "PM4_SP_XF.M3" : {}, "PM4_SP_XF.L3" : {}, "C5_SP_XF.1" : { "C5_SP_XF.2" : { "GND" : {} } }, "PM4_SP_XF.M8" : {}, "PM4_SP_XF.L8" : {}, "PM4_SP_XF.L6" : {}, "PM4_SP_XF.M6" : {}, "C7_SP_XF.1" : { "C7_SP_XF.2" : { "GND" : {} } }, "PM4_SP_XF.K2" : {}, "PM4_SP_XF.K9" : {}, "PM4_SP_XF.J11" : {}, "PM4_SP_XF.M4" : {}, "PM4_SP_XF.L4" : {}, "PM4_SP_XF.J3" : {}, "PM4_SP_XF.M10" : {}, "PM4_SP_XF.L10" : {}, "C3_SP_XF.1" : { "C3_SP_XF.2" : { "GND" : {} } }, "PM4_SP_XF.J2" : {}, "PM4_SP_XF.J9" : {}, "PM4_SP_XF.K11" : {}, "PM4_SP_XF.K3" : {} }, "AC_E1S2_PET_P<4>_XF" : { "U1_XF.AC11" : {}, "C151_XF.1" : { "C151_XF.2" : { "E1S2_PET_P<4>_XF" : { "J1_E2_XF.B31" : {} } } } }, "UNNAMED_20_FERRITEBEAD_I72_A" : { "Q14.3" : { "Q14.1" : { "UNNAMED_20_NMOSFETVMT3_I61_G" : { "R83.2" : { "R83.1" : { "ENB3V_SEQ_K" : { "U1_CPLD.M16" : {}, "R7_CPLD.1" : { "R7_CPLD.2" : { "GND" : {} } }, "R80.2" : { "R80.1" : { "GND" : {} } } } } } } }, "Q14.2" : { "UNNAMED_20_NMOSFETVMT3_I61_S" : { "R81.2" : { "R81.1" : { "GND" : {} } } } } }, "FB9.1" : { "FB9.2" : { "UNNAMED_20_FERRITEBEAD_I72_B" : { "P6.2" : {} } } }, "R82.2" : { "R82.1" : { "P5VSB" : {} } } }, "UNNAMED_17_RESISTOR_I110_A_XF" : { "R129_XF.2" : { "R129_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I116_A_XF" : { "C268_XF.1" : { "C268_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I116_B_XF" : { "U1_XF.BW32" : {}, "R130_XF.1" : { "R130_XF.2" : { "UNNAMED_17_RESISTOR_I113_A_XF" : { "R139_XF.1" : { "R139_XF.2" : { "GND" : {} } }, "R141_XF.1" : { "R141_XF.2" : { "GND" : {} } } } } } } } }, "U1_XF.BW31" : {} } } }, "R138_XF.1" : { "R138_XF.2" : { "GND" : {} } }, "R137_XF.1" : { "R137_XF.2" : { "VMON_AVTT_RS_LIN_XF" : { "R93_XF.2" : { "R93_XF.1" : { "UNNAMED_17_RESISTOR_I40_A_XF" : { "R94_XF.1" : { "R94_XF.2" : { "GND" : {} } }, "R99_XF.2" : { "R99_XF.1" : { "UNNAMED_17_BYPASSCAPNPOL_I46_A_XF" : { "C147_XF.1" : { "C147_XF.2" : { "UNNAMED_17_BYPASSCAPNPOL_I46_B_XF" : { "U1_XF.CA33" : {}, "R100_XF.1" : { "R100_XF.2" : { "UNNAMED_17_RESISTOR_I41_A_XF" : { "R96_XF.1" : { "R96_XF.2" : { "GND" : {} } }, "R95_XF.1" : { "R95_XF.2" : { "GND" : {} } } } } } } } }, "U1_XF.BY33" : {} } } } } } }, "R4_FL_XF.2" : { "R4_FL_XF.1" : { "VS_AVTT_RS_LIN_FL" : { "U2_FL_XF.19" : {}, "NS5_FL_XF.2" : { "NS5_FL_XF.1" : { "PWR_AVTT_RS_XF" : {} } } } } } } } } }, "C3_RDIMM_DQS_C<10>_XF" : { "J4_XF.19" : {}, "U1_XF.K27" : {} }, "E1S3_3R3V_SCL_XF" : { "R3_E3_XF.2" : { "R3_E3_XF.1" : { "P3R3V" : {} } }, "R208_XF.2" : { "R208_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "U1_XF.U21" : {}, "J1_E3_XF.A7" : {} }, "PCIE1_RXN<3>_XF" : { "U1_XF.AR1" : {}, "J1_P1_XF.A19" : {} }, "P12V_4650_LRIGHT_SP" : { "F16_SP_XF.1" : { "F16_SP_XF.2" : { "P12V_4650_BR_SP" : {} } }, "U3_SP_XF.3_4" : {}, "C161_SP_XF.1" : { "C161_SP_XF.2" : { "GND" : {} } } }, "C2_DDR4_DQ<44>_XF" : { "U1_XF.E54" : {}, "J3_XF.106" : {} }, "C1_DDR4_ADR<10>_XF" : { "J2_XF.225" : {}, "U1_XF.CB55" : {} }, "UNNAMED_3_DIODESOD923F_I70_A_SD" : { "PM4_SD_XF.E2" : { "PM4_SD_XF.E4" : { "BASE_3R3V_SCL_2" : { "Q3.3" : { "Q3.1" : { "UNNAMED_13_NMOSFETVMT3_I33_G" : { "R3.2" : { "R3.1" : { "UNNAMED_13_RESISTOR_I34_A" : { "R5.1" : { "R5.2" : { "UNNAMED_13_NMOSFETVMT3_I35_G" : { "Q4.1" : { "Q4.2" : { "BASE_1R8V_SDA" : { "R112.1" : { "R112.2" : { "UNNAMED_10_RESISTOR_I69_B" : { "U1.18" : {} } } } } }, "Q4.3" : { "BASE_3R3V_SDA_2" : { "R2.2" : { "R2.1" : { "P3R3V" : {} } }, "U11.14" : {}, "R113.1" : { "R113.2" : { "UNNAMED_17_RESISTOR_I1_B" : { "U12.5" : {} } } }, "U1_CPLD.C9" : {}, "Q2.3" : { "Q2.1" : { "UNNAMED_13_NMOSFETVMT3_I99_G" : { "R31.2" : { "R31.1" : { "UNNAMED_13_RESISTOR_I101_A" : { "R32.1" : { "R32.2" : { "UNNAMED_13_NMOSFETVMT3_I100_G" : { "Q1.1" : { "Q1.3" : { "BASE_3R3V_SCL_2" : {} } } } } } } } } } }, "Q2.2" : { "FPGA_1R8V_SDA" : { "R35.1" : { "R35.2" : { "FPGA_VCCAUX_P1R8V" : {} } } } } } } } } } } } } } } } }, "Q3.2" : { "BASE_1R8V_SCL" : { "U1.16" : {} } } }, "U11.13" : {} } }, "PM4_SD_XF.D4" : { "BASE_3R3V_SDA_2" : {} } } }, "E1S0_FPGA_REFCLK_P<1>_XF" : { "C18_E0_XF.2" : { "C18_E0_XF.1" : { "AC_FPGA_CLK_REF_P<1>_1" : { "U1_E0_XF.27" : {} } } }, "R171_XF.1" : { "R171_XF.2" : { "E1S0_FPGA_REFCLK_N<1>_XF" : {} } }, "R161_XF.2" : { "R161_XF.1" : { "PWR_FPGA_3R3V" : {} } }, "R170_XF.1" : { "R170_XF.2" : { "GND" : {} } }, "U1_XF.H13" : {} }, "OCL0_PER_P<3>_XF" : { "U1_XF.BV4" : {}, "J1_O0_XF.A18" : {} }, "C3_DDR4_ADR<13>_XF" : { "U1_XF.L22" : {}, "J4_XF.232" : {} }, "AC_OCL2_FPGA_REFCLK_N_XF" : { "U5_XF.23" : {}, "C386_XF.1" : { "C386_XF.2" : { "OCL2_FPGA_REFCLK_N_XF" : { "R215_XF.2" : { "R215_XF.1" : { "P3R3V" : {} } }, "U1_XF.BL14" : {}, "R226_XF.1" : { "R226_XF.2" : { "GND" : {} } } } } } } }, "part_info" : { "400-000010-010" : { "part_type" : "resistor", "part_number" : "400-000010-010", "part_name" : "RESISTOR", "mfg_pn" : null, "mfg_name" : null }, "402-000010-016" : { "mfg_name" : null, "mfg_pn" : null, "part_name" : "BYPASS_CAP_NPOL", "part_number" : "402-000010-016", "part_type" : "capacitor" }, "450-000057-001" : { "part_type" : "ic", "mfg_name" : null, "part_name" : "LT3071", "mfg_pn" : null, "part_number" : "450-000057-001" }, "400-000015-016" : { "mfg_name" : null, "part_number" : "400-000015-016", "part_name" : "RESISTOR", "mfg_pn" : null, "part_type" : "resistor" }, "402-000010-005" : { "part_number" : "402-000010-005", "part_name" : "BYPASS_CAP_NPOL", "mfg_pn" : null, "mfg_name" : null, "part_type" : "capacitor" }, "402-000010-043" : { "part_type" : "capacitor", "mfg_name" : null, "part_number" : "402-000010-043", "mfg_pn" : null, "part_name" : "BYPASS_CAP_NPOL" }, "HOLE_RING" : { "mfg_name" : null, "part_number" : "HOLE_RING", "part_name" : "HOLE_RING", "mfg_pn" : null, "part_type" : "" }, "404-000007-001" : { "part_type" : "diode", "mfg_pn" : null, "part_name" : "DIODE_SOD923F", "part_number" : "404-000007-001", "mfg_name" : null }, "402-000050-015" : { "part_number" : "402-000050-015", "mfg_pn" : null, "part_name" : "TIMING_CAP_NPOL", "mfg_name" : null, "part_type" : "capacitor" }, "410-000324-001" : { "mfg_pn" : null, "part_name" : "OCULINK_X4_CONN", "part_number" : "410-000324-001", "mfg_name" : null, "part_type" : "connector" }, "400-000010-084" : { "part_type" : "resistor", "part_number" : "400-000010-084", "part_name" : "RESISTOR", "mfg_pn" : null, "mfg_name" : null }, "450-000333-001" : { "part_name" : "MAX116XX_QSOP16", "mfg_pn" : null, "part_number" : "450-000333-001", "mfg_name" : null, "part_type" : "ic" }, "402-000500-005" : { "part_type" : "capacitor", "part_number" : "402-000500-005", "mfg_pn" : null, "part_name" : "BYPASS_CAP_POL", "mfg_name" : null }, "400-000010-061" : { "part_name" : "RESISTOR", "mfg_pn" : null, "part_number" : "400-000010-061", "mfg_name" : null, "part_type" : "resistor" }, "402-000020-003" : { "part_type" : "capacitor", "mfg_name" : null, "mfg_pn" : null, "part_name" : "BYPASS_CAP_NPOL", "part_number" : "402-000020-003" }, "400-000010-080" : { "mfg_pn" : null, "part_name" : "RESISTOR", "part_number" : "400-000010-080", "mfg_name" : null, "part_type" : "resistor" }, "400-000010-116" : { "part_number" : "400-000010-116", "part_name" : "RESISTOR", "mfg_pn" : null, "mfg_name" : null, "part_type" : "resistor" }, "402-000015-007" : { "mfg_pn" : null, "part_name" : "BYPASS_CAP_NPOL", "part_number" : "402-000015-007", "mfg_name" : null, "part_type" : "capacitor" }, "401-000001-002" : { "part_name" : "FERRITE_BEAD", "mfg_pn" : null, "part_number" : "401-000001-002", "mfg_name" : null, "part_type" : "inductor" }, "400-000010-007" : { "mfg_pn" : null, "part_name" : "RESISTOR", "part_number" : "400-000010-007", "mfg_name" : null, "part_type" : "resistor" }, "410-000105-001" : { "part_type" : "connector", "mfg_name" : null, "part_name" : "ATX_POWER_24PIN", "mfg_pn" : null, "part_number" : "410-000105-001" }, "402-000202-005" : { "part_type" : "capacitor", "mfg_name" : null, "part_number" : "402-000202-005", "mfg_pn" : null, "part_name" : "CAPACITOR" }, "450-000340-001" : { "part_type" : "ic", "mfg_name" : null, "mfg_pn" : null, "part_name" : "XC2_VU19P_FPGA", "part_number" : "450-000340-001" }, "400-000010-002" : { "part_type" : "resistor", "mfg_name" : null, "part_number" : "400-000010-002", "mfg_pn" : null, "part_name" : "RESISTOR" }, "TP_020_VIA" : { "part_name" : "TP_020_VIA", "mfg_pn" : null, "part_number" : "TP_020_VIA", "mfg_name" : null, "part_type" : "" }, "400-000010-136" : { "part_type" : "resistor", "mfg_name" : null, "part_name" : "RESISTOR", "mfg_pn" : null, "part_number" : "400-000010-136" }, "401-000302-001" : { "part_number" : "401-000302-001", "part_name" : "INDUCTOR", "mfg_pn" : null, "mfg_name" : null, "part_type" : "inductor" }, "405-000003-001" : { "part_name" : "P_MOSFET_8PIN", "mfg_pn" : null, "part_number" : "405-000003-001", "mfg_name" : null, "part_type" : "transistor" }, "400-000010-108" : { "mfg_name" : null, "mfg_pn" : null, "part_name" : "RESISTOR", "part_number" : "400-000010-108", "part_type" : "resistor" }, "402-000500-008" : { "mfg_pn" : null, "part_name" : "BYPASS_CAP_POL_3T", "part_number" : "402-000500-008", "mfg_name" : null, "part_type" : "capacitor" }, "400-000010-120" : { "mfg_name" : null, "part_name" : "RESISTOR", "mfg_pn" : null, "part_number" : "400-000010-120", "part_type" : "resistor" }, "402-000010-003" : { "part_type" : "capacitor", "part_number" : "402-000010-003", "part_name" : "BYPASS_CAP_NPOL", "mfg_pn" : null, "mfg_name" : null }, "400-000010-157" : { "mfg_name" : null, "part_name" : "RESISTOR", "mfg_pn" : null, "part_number" : "400-000010-157", "part_type" : "resistor" }, "400-000015-024" : { "part_type" : "resistor", "mfg_name" : null, "part_number" : "400-000015-024", "mfg_pn" : null, "part_name" : "RESISTOR" }, "ROHS_SYMBOL" : { "part_number" : "ROHS_SYMBOL", "part_name" : "ROHS_SYMBOL", "mfg_pn" : null, "mfg_name" : null, "part_type" : "" }, "452-000302-001" : { "mfg_pn" : null, "part_name" : "XTAL_4P", "part_number" : "452-000302-001", "mfg_name" : null, "part_type" : "xtal" }, "410-000328-001" : { "part_number" : "410-000328-001", "part_name" : "AMPH_PCIEX1_36P_CONN", "mfg_pn" : null, "mfg_name" : null, "part_type" : "connector" }, "403-000007-001" : { "part_type" : "fuse", "part_number" : "403-000007-001", "part_name" : "FUSE", "mfg_pn" : null, "mfg_name" : null }, "462-000308-002" : { "mfg_name" : null, "mfg_pn" : null, "part_name" : "LTM4650_FIXED", "part_number" : "462-000308-002", "part_type" : "" }, "410-000321-001" : { "part_number" : "410-000321-001", "part_name" : "PSU_COMM", "mfg_pn" : null, "mfg_name" : null, "part_type" : "connector" }, "FIDUCIAL" : { "part_type" : "", "mfg_name" : null, "part_number" : "FIDUCIAL", "part_name" : "FIDUCIAL", "mfg_pn" : null }, "400-000010-075" : { "part_type" : "resistor", "part_number" : "400-000010-075", "mfg_pn" : null, "part_name" : "RESISTOR", "mfg_name" : null }, "410-000327-001" : { "part_type" : "connector", "part_number" : "410-000327-001", "part_name" : "XC200_FPNL_2X12_HDR", "mfg_pn" : null, "mfg_name" : null }, "450-000345-001" : { "part_type" : "ic", "mfg_name" : null, "part_number" : "450-000345-001", "part_name" : "PI6CB33401", "mfg_pn" : null }, "400-000010-049" : { "part_type" : "resistor", "part_name" : "RESISTOR", "mfg_pn" : null, "part_number" : "400-000010-049", "mfg_name" : null }, "400-000010-097" : { "mfg_name" : null, "part_number" : "400-000010-097", "part_name" : "RESISTOR", "mfg_pn" : null, "part_type" : "resistor" }, "450-000011-002" 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"capacitor" }, "402-000010-014" : { "part_type" : "capacitor", "mfg_name" : null, "part_name" : "BYPASS_CAP_NPOL", "mfg_pn" : null, "part_number" : "402-000010-014" }, "402-000202-002" : { "part_type" : "capacitor", "part_number" : "402-000202-002", "part_name" : "CAPACITOR", "mfg_pn" : null, "mfg_name" : null }, "410-000317-001" : { "part_type" : "connector", "mfg_name" : null, "part_number" : "410-000317-001", "part_name" : "SFFTA1009", "mfg_pn" : null }, "410-000047-001" : { "mfg_name" : null, "part_name" : "ATX_12V_8PIN", "mfg_pn" : null, "part_number" : "410-000047-001", "part_type" : "connector" }, "450-000313-001" : { "part_number" : "450-000313-001", "part_name" : "XC200_CPLD", "mfg_pn" : null, "mfg_name" : null, "part_type" : "ic" }, "462-000309-001" : { "mfg_name" : null, "part_name" : "LTM4671", "mfg_pn" : null, "part_number" : "462-000309-001", "part_type" : "" }, "410-000322-001" : { "part_name" : "MLX_KK100_4PIN_BOSS", "mfg_pn" : null, "part_number" : "410-000322-001", "mfg_name" : null, "part_type" : "connector" }, "400-000010-009" : { "part_name" : "RESISTOR", "mfg_pn" : null, "part_number" : "400-000010-009", "mfg_name" : null, "part_type" : "resistor" }, "400-000010-066" : { "part_type" : "resistor", "part_name" : "RESISTOR", "mfg_pn" : null, "part_number" : "400-000010-066", "mfg_name" : null }, "402-000015-008" : { "mfg_name" : null, "part_number" : "402-000015-008", "part_name" : "BYPASS_CAP_NPOL", "mfg_pn" : null, "part_type" : "capacitor" }, "403-000006-003" : { "mfg_name" : null, "mfg_pn" : null, "part_name" : "FUSE", "part_number" : "403-000006-003", "part_type" : "fuse" }, "402-000010-034" : { "part_type" : "capacitor", "part_number" : "402-000010-034", "mfg_pn" : null, "part_name" : "BYPASS_CAP_NPOL", "mfg_name" : null }, "400-000010-003" : { "part_type" : "resistor", "mfg_name" : null, "mfg_pn" : null, "part_name" : "RESISTOR", "part_number" : "400-000010-003" }, "402-000010-026" : { "part_type" : "capacitor", "mfg_name" : null, "part_number" : "402-000010-026", "mfg_pn" : null, "part_name" : "BYPASS_CAP_NPOL" }, "400-000015-034" : { "part_type" : "resistor", "part_number" : "400-000015-034", "mfg_pn" : null, "part_name" : "RESISTOR", "mfg_name" : null }, "400-000010-020" : { "part_type" : "resistor", "mfg_name" : null, "part_number" : "400-000010-020", "mfg_pn" : null, "part_name" : "RESISTOR" }, "450-000302-001" : { "part_type" : "ic", "part_number" : "450-000302-001", "part_name" : "LTC2975", "mfg_pn" : null, "mfg_name" : null }, "400-000018-017" : { "part_number" : "400-000018-017", "part_name" : "RESISTOR", "mfg_pn" : null, "mfg_name" : null, "part_type" : "resistor" }, "401-000001-003" : { "part_type" : "inductor", "mfg_pn" : null, "part_name" : "FERRITE_BEAD", "part_number" : "401-000001-003", "mfg_name" : null }, "404-000001-001" : { "part_type" : "led", "mfg_name" : null, "mfg_pn" : null, "part_name" : "LED", "part_number" : "404-000001-001" }, "402-000010-011" : { "part_type" : "capacitor", "mfg_name" : null, "mfg_pn" : null, "part_name" : "BYPASS_CAP_NPOL", "part_number" : "402-000010-011" }, "402-000015-001" : { "mfg_name" : null, "part_name" : "BYPASS_CAP_NPOL", "mfg_pn" : null, "part_number" : "402-000015-001", "part_type" : "capacitor" }, "400-000010-001" : { "part_type" : "resistor", "part_name" : "RESISTOR", "mfg_pn" : null, "part_number" : "400-000010-001", "mfg_name" : null }, "406-000001-001" : { "part_type" : "", "mfg_pn" : null, "part_name" : "SW_4P_SPST_NO", "part_number" : "406-000001-001", "mfg_name" : null }, "402-000050-003" : { "mfg_name" : null, "part_number" : "402-000050-003", "mfg_pn" : null, "part_name" : "TIMING_CAP_NPOL", "part_type" : "capacitor" }, "402-000050-020" : { "mfg_name" : null, "part_name" : "TIMING_CAP_NPOL", "mfg_pn" : null, "part_number" : "402-000050-020", "part_type" : "capacitor" }, "402-000010-035" : { "mfg_name" : null, "part_number" : "402-000010-035", "mfg_pn" : null, "part_name" : "AC_COUPLING_CAP", "part_type" : "capacitor" }, "450-000162-001" : { "part_number" : "450-000162-001", "mfg_pn" : null, "part_name" : "ACS711", "mfg_name" : null, "part_type" : "ic" }, "402-000010-018" : { "part_type" : "capacitor", "mfg_pn" : null, "part_name" : "BYPASS_CAP_NPOL", "part_number" : "402-000010-018", "mfg_name" : null }, "404-000001-008" : { "mfg_name" : null, "part_number" : "404-000001-008", "part_name" : "598_BICOLOR_LED", "mfg_pn" : null, "part_type" : "led" }, "SM_020_TP" : { "mfg_pn" : null, "part_name" : "SM_020_TP", "part_number" : "SM_020_TP", "mfg_name" : null, "part_type" : "" }, "404-000001-003" : { "mfg_pn" : null, "part_name" : "LED", "part_number" : "404-000001-003", "mfg_name" : null, "part_type" : "led" }, "SM_050_TP" : { "part_type" : "connector", "mfg_name" : null, "part_name" : "SM_050_TP", "mfg_pn" : null, "part_number" : "SM_050_TP" }, "450-000325-001" : { "mfg_name" : null, "mfg_pn" : null, "part_name" : "MAX4641", "part_number" : "450-000325-001", "part_type" : "ic" }, "400-000015-022" : { "mfg_name" : null, "part_name" : "RESISTOR", "mfg_pn" : null, "part_number" : "400-000015-022", "part_type" : "resistor" }, "450-000094-001" : { "mfg_name" : null, "part_number" : "450-000094-001", "mfg_pn" : null, "part_name" : "TSE2002", "part_type" : "ic" }, "462-000304-001" : { "part_type" : "", "mfg_name" : null, "part_name" : "LTM4675", "mfg_pn" : null, "part_number" : "462-000304-001" }, "400-000015-019" : { "part_name" : "RESISTOR", "mfg_pn" : null, "part_number" : "400-000015-019", "mfg_name" : null, "part_type" : "resistor" }, "400-000015-027" : { "part_type" : "resistor", "mfg_name" : null, "part_number" : "400-000015-027", "mfg_pn" : null, "part_name" : "RESISTOR" }, "402-000010-027" : { "part_type" : "capacitor", "part_number" : "402-000010-027", "mfg_pn" : null, "part_name" : "BYPASS_CAP_NPOL", "mfg_name" : null }, "402-000015-004" : { "mfg_pn" : null, "part_name" : "BYPASS_CAP_NPOL", "part_number" : "402-000015-004", "mfg_name" : null, "part_type" : "capacitor" }, "MICRON_LOGO" : { "mfg_name" : null, "mfg_pn" : null, "part_name" : "MICRON_LOGO", "part_number" : "MICRON_LOGO", "part_type" : "" }, "402-000010-033" : { "part_type" : "capacitor", "part_number" : "402-000010-033", "mfg_pn" : null, "part_name" : "BYPASS_CAP_NPOL", "mfg_name" : null }, "400-000010-004" : { "mfg_name" : null, "mfg_pn" : null, "part_name" : "RESISTOR", "part_number" : "400-000010-004", "part_type" : "resistor" }, "402-000050-021" : { "mfg_name" : null, "mfg_pn" : null, "part_name" : "TIMING_CAP_NPOL", "part_number" : "402-000050-021", "part_type" : "capacitor" }, "402-000200-003" : { "part_type" : "capacitor", "part_number" : "402-000200-003", "part_name" : "CAPACITOR", "mfg_pn" : null, "mfg_name" : null }, "400-000010-028" : { "part_type" : "resistor", "part_number" : "400-000010-028", "part_name" : "RESISTOR", "mfg_pn" : null, "mfg_name" : null }, "402-000010-006" : { "mfg_name" : null, "part_number" : "402-000010-006", "part_name" : "BYPASS_CAP_NPOL", "mfg_pn" : null, "part_type" : "capacitor" }, "400-000015-015" : { "part_type" : "resistor", "mfg_pn" : null, "part_name" : "RESISTOR", "part_number" : "400-000015-015", "mfg_name" : null }, "400-000010-041" : { "part_number" : "400-000010-041", "mfg_pn" : null, "part_name" : "RESISTOR", "mfg_name" : null, "part_type" : "resistor" }, "402-000020-013" : { "part_number" : "402-000020-013", "part_name" : "BYPASS_CAP_NPOL", "mfg_pn" : null, "mfg_name" : null, "part_type" : "capacitor" }, "EXTRA_PROPS" : { "part_type" : "", "part_name" : "EXTRA_PROPS", "mfg_pn" : null, "part_number" : "EXTRA_PROPS", "mfg_name" : null }, "400-000010-133" : { "mfg_pn" : null, "part_name" : "RESISTOR", "part_number" : "400-000010-133", "mfg_name" : null, "part_type" : "resistor" }, "402-000050-016" : { "part_type" : "capacitor", "mfg_name" : null, "mfg_pn" : null, "part_name" : "TIMING_CAP_NPOL", "part_number" : "402-000050-016" }, "405-000010-001" : { "part_type" : "transistor", "part_name" : "N_MOSFET_VMT3", "mfg_pn" : null, "part_number" : "405-000010-001", "mfg_name" : null }, "450-000020-002" : { "mfg_name" : null, "mfg_pn" : null, "part_name" : "TL431_SOT23_5", "part_number" : "450-000020-002", "part_type" : "ic" }, "402-000050-005" : { "mfg_name" : null, "mfg_pn" : null, "part_name" : "TIMING_CAP_NPOL", "part_number" : "402-000050-005", "part_type" : "capacitor" }, "450-000059-001" : { "mfg_name" : null, "part_number" : "450-000059-001", "part_name" : "TPS51200", "mfg_pn" : null, "part_type" : "ic" }, "XXX-XXXXXX-001" : { "mfg_name" : null, "part_name" : "CONVEY_LABEL", "mfg_pn" : null, "part_number" : "XXX-XXXXXX-001", "part_type" : "" }, "400-000010-082" : { "mfg_name" : null, "part_number" : "400-000010-082", "mfg_pn" : null, "part_name" : "RESISTOR", "part_type" : "resistor" }, "450-000308-002" : { "part_type" : "ic", "part_number" : "450-000308-002", "mfg_pn" : null, "part_name" : "SI5341", "mfg_name" : null }, "400-000010-029" : { "part_type" : "resistor", "part_name" : "RESISTOR", "mfg_pn" : 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null, "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3_i81", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3", "page_instance" : "I81" } ], "ohm_resistance" : "4640", "value" : "4.64K", "part_number" : "400-000010-007", "refdes" : "R5_E0_XF", "is_polar_cap" : null, "node_list" : [ "R5_E0_XF.2", "R5_E0_XF.1" ], "voltage" : "50", "do_not_pop" : 0, "description" : "RES,MF,0402,4.64K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "R7_SD_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,3.24K,50V,1/16W,1%,100ppm,Metal Film", "node_list" : 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"top/xc2_fpga_blk/ocl_2x4_pcie_blk", "page" : "page3" } ], "is_cap" : null, "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF" }, "C129_SP_XF" : { "do_not_install" : 0, "description" : "CAP,X7R,0603,25V,0.015uF,Precison Ceramic", "node_list" : [ "C129_SP_XF.2", "C129_SP_XF.1" ], "is_polar_cap" : null, "voltage" : "25", "do_not_pop" : 0, "part_type" : "CAPACITOR", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "page_instance" : "I95", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8_i95", "sym_num" : 1, "phys_page" : "page8", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "path" : 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Switch,1.8-5.5V,8Pin 8UMAX,SPST, NOFF, 4ohm", "do_not_install" : 0, "refdes" : "U4_XF", "value" : null, "part_number" : "450-000325-001", "ohm_resistance" : null, "is_cap" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i1", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "page_instance" : "I1", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "remapped_page" : null, "page" : "page15", "block" : "top/xc2_fpga_blk", "phys_page" : "page15" } ], "part_type" : "IC", "do_not_pop" : 0, "voltage" : "5.5", "node_list" : [ "U4_XF.2", "U4_XF.6", "U4_XF.7", "U4_XF.8", "U4_XF.4", "U4_XF.3", "U4_XF.1", "U4_XF.5" ], "is_polar_cap" : null }, "C6_E0_XF" : { "description" : "CAP,X5R,0603,6.3V,22UF,Bulk Ceramic", "do_not_install" : 0, "marker_data" : [ { "ppath_without_last_instance" : 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"C5_E1_XF.2" ], "do_not_pop" : 0, "voltage" : "6.3", "part_type" : "CAPACITOR", "value" : "100UF", "part_number" : "402-000010-033", "refdes" : "C5_E1_XF", "is_cap" : 1, "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i87", "sym_num" : 1, "page_instance" : "I87", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3" } ], "ohm_resistance" : null, "do_not_install" : 0, "description" : "CAP,X5R,1206,6.3V,100UF,Bulk Ceramic 1.6mm Thk" }, "C34_FL_XF" : { "description" : "CAP,X5R,0402,4V,4.7UF,Bulk Ceramic", "do_not_install" : 0, "part_type" : "CAPACITOR", "refdes" : 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"is_cap" : 1, "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_page" : "page14", "block" : "top/xc2_fpga_blk", "page" : "page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i174", "sym_num" : 1, "page_instance" : "I174", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14" } ], "ohm_resistance" : null, "part_number" : "402-000010-035", "value" : "0.22UF", "refdes" : "C276_XF", "part_type" : "CAPACITOR" }, "R112_FL_XF" : { "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF", "do_not_install" : 0, "part_type" : "RESISTOR", "refdes" : "R112_FL_XF", "value" : "0OHM", "part_number" : "400-000014-011", "ohm_resistance" : "0", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : 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"do_not_install" : 0, "description" : "CONN, HDR, 3PIN, 1X3, 2.5MM, LOCK RAMP" }, "R81_SP_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF", "node_list" : [ "R81_SP_XF.1", "R81_SP_XF.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50", "part_type" : "RESISTOR", "refdes" : "R81_SP_XF", "part_number" : "400-000014-011", "value" : "0OHM", "ohm_resistance" : "0", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i467", "sym_num" : 1, "page_instance" : "I467", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6" } ], "is_cap" : null }, "D3_CPLD" : { "refdes" : "D3_CPLD", "part_number" : "404-000302-001", "value" : null, "ohm_resistance" : null, "is_cap" : null, "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page9", "page_instance" : "I91", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page9_i91", "page" : "page9", "block" : "top/cpld_blk", "phys_page" : "page9", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "remapped_page" : null } ], "part_type" : "LED", "do_not_pop" : 0, "voltage" : "R2.1V,G2.95V,B2.85V", "is_polar_cap" : null, "node_list" : [ "D3_CPLD.1", "D3_CPLD.3", "D3_CPLD.4", "D3_CPLD.2" ], "description" : "LED,SMT,0404,RGB_LED,R30ma_G25ma_B10ma,R2.15V_G2.95V_B1.85V,4 pin 1mmx1mm", "do_not_install" : 0 }, "C415_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "is_polar_cap" : null, "node_list" : [ "C415_XF.2", "C415_XF.1" ], "do_not_pop" : 0, "voltage" : "6.3", "part_type" : "CAPACITOR", "refdes" : "C415_XF", "part_number" : "402-000010-001", "value" : ".22UF", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i176", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I176" } ] }, "C382_XF" : { "voltage" : "2.5", "do_not_pop" : 0, "node_list" : [ "C382_XF.2", "C382_XF.1" ], "is_polar_cap" : null, "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : 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}, "C18_E3_XF" : { "node_list" : [ "C18_E3_XF.1", "C18_E3_XF.2" ], "is_polar_cap" : null, "voltage" : "6.3", "do_not_pop" : 0, "part_type" : "CAPACITOR", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4", "page_instance" : "I48", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4_i48" } ], "refdes" : "C18_E3_XF", "value" : "0.22UF", "part_number" : "402-000010-035", "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling" }, "C214_XF" : { "is_polar_cap" : null, "node_list" : [ "C214_XF.1", "C214_XF.2" ], "do_not_pop" : 0, "voltage" : "4", "part_type" : "CAPACITOR", "value" : "4.7UF", "part_number" : "402-000010-028", "refdes" : "C214_XF", "is_cap" : 1, "marker_data" : [ { "page_instance" : "I163", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i163", "sym_num" : 1, "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10" } ], "ohm_resistance" : null, "do_not_install" : 0, "description" : "CAP,X5R,0402,4V,4.7UF,Bulk Ceramic" }, "C19" : { "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "phys_page" : "page10", "block" : "top", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "page_instance" : "I131", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i131", "sym_num" : 1 } ], "refdes" : "C19", "part_number" : "402-000010-026", "value" : "1UF", "part_type" : "CAPACITOR", "voltage" : "16", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C19.2", "C19.1" ], "description" : "CAP,X5R,0402,16V,1UF,Bulk Ceramic", "do_not_install" : 0 }, "C389_XF" : { "refdes" : "C389_XF", "value" : ".22UF", "part_number" : "402-000010-001", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "phys_page" : "page15", "block" : "top/xc2_fpga_blk", "page" : "page15", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "page_instance" : "I48", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i48", "sym_num" : 1 } ], "part_type" : "CAPACITOR", "do_not_pop" : 0, "voltage" : "6.3", "is_polar_cap" : null, "node_list" : [ "C389_XF.1", "C389_XF.2" ], "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "C460_XF" : { "description" : "CAP,X5R,0402,4V,4.7UF,Bulk Ceramic", "do_not_install" : 0, "is_cap" : 1, "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_page" : "page20", "page" : "page20", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i66", "sym_num" : 1, "page_instance" : "I66", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20" } ], "ohm_resistance" : null, "part_number" : "402-000010-028", "value" : "4.7UF", "refdes" : "C460_XF", "part_type" : "CAPACITOR", "voltage" : "4", "do_not_pop" : 0, "node_list" : [ "C460_XF.2", "C460_XF.1" ], "is_polar_cap" : null }, "R243_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,100,50V,1/16W,1%,100ppm,Metal Film", "voltage" : "50", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "R243_XF.2", "R243_XF.1" ], "ohm_resistance" : "100", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2421", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "page_instance" : "I2421", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "remapped_page" : null, "page" : "page5", "block" : "top/xc2_fpga_blk", "phys_page" : "page5" } ], "is_cap" : null, "refdes" : "R243_XF", "part_number" : "400-000010-004", "value" : "100", "part_type" : "RESISTOR" }, "C484_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "is_polar_cap" : null, "node_list" : [ "C484_XF.2", "C484_XF.1" ], "voltage" : "6.3", "do_not_pop" : 0, "part_type" : "CAPACITOR", "marker_data" : [ { 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1, "ohm_resistance" : null }, "C198_XF" : { "do_not_pop" : 0, "voltage" : "6.3", "node_list" : [ "C198_XF.2", "C198_XF.1" ], "is_polar_cap" : null, "part_number" : "402-000010-001", "value" : ".22UF", "refdes" : "C198_XF", "is_cap" : 1, "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i176", "sym_num" : 1, "page_instance" : "I176", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8" } ], "ohm_resistance" : null, "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling" }, "R108_SD_XF" : { "marker_data" : [ { "page_instance" : "I23", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "ppath" : 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null, "refdes" : "TP2", "is_cap" : null, "marker_data" : [ { "path" : "@top_lib.top(sch_1):page2", "phys_path" : "@top_lib.top(sch_1):page2", "remapped_page" : null, "page" : "page2", "block" : "top", "phys_page" : "page2", "sym_num" : 1, "ppath" : "top/page2_i25", "ppath_without_last_instance" : "top/page2", "page_instance" : "I25" } ], "ohm_resistance" : null, "part_type" : "CONNECTOR", "do_not_install" : 0, "description" : "TestPoint,SMT,RectPad,.090inheight" }, "C301_XF" : { "do_not_install" : 0, "description" : "CAP,X6S,0402,6.3V,10uF,Bulk Ceramic", "is_polar_cap" : null, "node_list" : [ "C301_XF.1", "C301_XF.2" ], "do_not_pop" : 0, "voltage" : "6.3", "part_type" : "CAPACITOR", "refdes" : "C301_XF", "value" : "10UF", "part_number" : "402-000015-008", "ohm_resistance" : null, "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i30", "sym_num" : 1, "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "remapped_page" : null, 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"is_polar_cap" : null, "node_list" : [ "TP4_CPLD.1" ], "description" : "SM_050_TP-SM_050_TP", "do_not_install" : 0 }, "R66_XF" : { "part_type" : "RESISTOR", "ohm_resistance" : "4640", "is_cap" : null, "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i5", "sym_num" : 1, "page_instance" : "I5", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "phys_page" : "page15", "block" : "top/xc2_fpga_blk", "page" : "page15" } ], "refdes" : "R66_XF", "value" : "4.64K", "part_number" : "400-000010-007", "is_polar_cap" : null, "node_list" : [ "R66_XF.2", "R66_XF.1" ], "voltage" : "50", "do_not_pop" : 0, "description" : "RES,MF,0402,4.64K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "R99_XF" : { "part_type" : "RESISTOR", "refdes" : "R99_XF", "value" : "1K", "part_number" : "400-000010-010", "ohm_resistance" : "1000", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i44", "sym_num" : 1, "page_instance" : "I44", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_page" : "page17", "block" : "top/xc2_fpga_blk", "page" : "page17" } ], "is_cap" : null, "node_list" : [ "R99_XF.1", "R99_XF.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50", "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "U5_SP_XF" : { "do_not_install" : 0, "description" : "IC,ISens,Bi-CMOS,3.3V,12Pin QFN,15A Hall Effect Current Monitor", "do_not_pop" : 0, "voltage" : "3.3", "is_polar_cap" : null, "node_list" : [ "U5_SP_XF.5", "U5_SP_XF.6", "U5_SP_XF.7", "U5_SP_XF.8", "U5_SP_XF.9", "U5_SP_XF.10", "U5_SP_XF.12", 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"top/page14_i1/cpld_blk/page7_i127", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I127" } ], "is_cap" : 1, "ohm_resistance" : null, "part_number" : "402-000010-001", "value" : ".22UF", "refdes" : "C3_CPLD", "is_polar_cap" : null, "node_list" : [ "C3_CPLD.2", "C3_CPLD.1" ], "voltage" : "6.3", "do_not_pop" : 0 }, "C52_ND_XF" : { "voltage" : "6.3", "do_not_pop" : 0, "node_list" : [ "C52_ND_XF.2", "C52_ND_XF.1" ], "is_polar_cap" : null, "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "page_instance" : "I10", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i10", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3" } ], "refdes" : "C52_ND_XF", "part_number" : "402-000010-033", "value" : "100UF", "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X5R,1206,6.3V,100UF,Bulk Ceramic 1.6mm Thk" }, "R62_ND_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,10K,50V,1/16W,1%,100ppm,Metal Film", "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R62_ND_XF.1", "R62_ND_XF.2" ], "is_polar_cap" : null, "is_cap" : null, "marker_data" : [ { "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4_i20", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4" } ], "ohm_resistance" : "10000", "value" : "10K", "part_number" : "400-000010-074", "refdes" : "R62_ND_XF", "part_type" : "RESISTOR" }, "C23_E3_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "node_list" : [ "C23_E3_XF.1", "C23_E3_XF.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "6.3", "part_type" : "CAPACITOR", "part_number" : "402-000010-035", "value" : "0.22UF", "refdes" : "C23_E3_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4", "page_instance" : "I51", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4_i51", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "path" : 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"450-000345-001", "node_list" : [ "U1_E1_XF.14", "U1_E1_XF.18", "U1_E1_XF.13", "U1_E1_XF.17", "U1_E1_XF.23", "U1_E1_XF.28", "U1_E1_XF.22", "U1_E1_XF.27", "U1_E1_XF.6", "U1_E1_XF.5", "U1_E1_XF.12", "U1_E1_XF.19", "U1_E1_XF.8", "U1_E1_XF.33", "U1_E1_XF.2", "U1_E1_XF.3", "U1_E1_XF.7", "U1_E1_XF.16", "U1_E1_XF.20", "U1_E1_XF.26", "U1_E1_XF.30", "U1_E1_XF.4", "U1_E1_XF.11", "U1_E1_XF.15", "U1_E1_XF.21", "U1_E1_XF.25", "U1_E1_XF.1", "U1_E1_XF.24", "U1_E1_XF.29", "U1_E1_XF.31", "U1_E1_XF.32", "U1_E1_XF.9", "U1_E1_XF.10" ], "is_polar_cap" : null, "voltage" : "", "do_not_pop" : 0, "description" : "IC,Clock Buff,PCIe Gen1-5, 4-Output, 32-TQFN", "do_not_install" : 0 }, "R21_CPLD" : { "description" : "RES,MF,0402,511,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "part_type" : "RESISTOR", "part_number" : "400-000010-006", "value" : "511", "refdes" : "R21_CPLD", "marker_data" : [ { "page_instance" : "I87", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page9", "ppath" : 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"0.22UF", "refdes" : "C137_XF", "is_polar_cap" : null, "node_list" : [ "C137_XF.1", "C137_XF.2" ], "voltage" : "6.3", "do_not_pop" : 0 }, "C255_XF" : { "value" : "0.22UF", "part_number" : "402-000010-035", "refdes" : "C255_XF", "marker_data" : [ { "page" : "page14", "block" : "top/xc2_fpga_blk", "phys_page" : "page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I147", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i147" } ], "is_cap" : 1, "ohm_resistance" : null, "part_type" : "CAPACITOR", "do_not_pop" : 0, "voltage" : "6.3", "is_polar_cap" : null, "node_list" : [ "C255_XF.1", "C255_XF.2" ], "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "R13_FL_XF" : { "do_not_install" : 0, "description" : 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"R32.2", "R32.1" ], "is_polar_cap" : null, "value" : "1K", "part_number" : "400-000010-010", "refdes" : "R32", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page13_i101", "ppath_without_last_instance" : "top/page13", "page_instance" : "I101", "path" : "@top_lib.top(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page13", "remapped_page" : null, "page" : "page13", "block" : "top", "phys_page" : "page13" } ], "is_cap" : null, "ohm_resistance" : "1000", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film" }, "C41_XF" : { "node_list" : [ "C41_XF.1", "C41_XF.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "6.3", "part_type" : "CAPACITOR", "refdes" : "C41_XF", "value" : "0.22UF", "part_number" : "402-000010-035", "ohm_resistance" : null, "marker_data" : [ { "phys_page" : "page11", "block" : "top/xc2_fpga_blk", "page" : "page11", "remapped_page" : null, "phys_path" : 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"top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i113", "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null } ], "is_cap" : null, "refdes" : "R20_SP_XF", "part_number" : "400-000010-033", "value" : "182", "part_type" : "RESISTOR" }, "C16_E2_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "voltage" : "6.3", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C16_E2_XF.2", "C16_E2_XF.1" ], "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i45", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4", "page_instance" : "I45", "phys_path" : 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: null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4" } ], "is_cap" : null, "ohm_resistance" : "0", "node_list" : [ "R2_FL_XF.2", "R2_FL_XF.1" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50" }, "R92_SP_XF" : { "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page5", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i135", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I135" } ], "is_cap" : null, "ohm_resistance" : "0", "part_number" : "400-000014-011", "value" : "0OHM", "refdes" : "R92_SP_XF", "part_type" : "RESISTOR", "voltage" : "50", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "R92_SP_XF.2", "R92_SP_XF.1" ], "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF", "do_not_install" : 0 }, "R249_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_pop" : 0, "voltage" : "50", "is_polar_cap" : null, "node_list" : [ "R249_XF.2", "R249_XF.1" ], "part_number" : "400-000010-010", "value" : "1K", "refdes" : "R249_XF", "is_cap" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2422", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "page_instance" : "I2422", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page7", "phys_page" : "page7" } ], "ohm_resistance" : "1000", "part_type" : "RESISTOR" }, "R33_SP_XF" : { "is_cap" : null, "marker_data" : [ { "page_instance" : "I119", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i119", "sym_num" : 1, "phys_page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4" } ], "ohm_resistance" : "49.9", "part_number" : "400-000010-003", "value" : "49.9", "refdes" : "R33_SP_XF", "part_type" : "RESISTOR", "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R33_SP_XF.2", "R33_SP_XF.1" ], "is_polar_cap" : null, "description" : "RES,MF,0402,49.9,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "R103" : { "do_not_install" : 0, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF", "do_not_pop" : 0, "voltage" : "50", "is_polar_cap" : null, "node_list" : [ "R103.1", "R103.2" ], "refdes" : "R103", "part_number" : "400-000014-011", "value" : "0OHM", "ohm_resistance" : "0", "is_cap" : null, "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page17", "phys_page" : "page17", "page" : "page17", "block" : "top", "ppath" : "top/page17_i8", "sym_num" : 1, "page_instance" : "I8", "ppath_without_last_instance" : "top/page17" } ], "part_type" : "RESISTOR" }, "R9_SP_XF" : { "do_not_pop" : 0, "voltage" : "50", "node_list" : [ "R9_SP_XF.2", "R9_SP_XF.1" ], "is_polar_cap" : null, "value" : "90.9K", "part_number" : "400-000011-010", "refdes" : "R9_SP_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5", "phys_page" : "page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I36", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i36" } ], "is_cap" : null, "ohm_resistance" : "90900", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0603,90.9K,50V,1/16W,1%,100ppm,Metal Film" }, "C78" : { "description" : "CAP,ALUM_CP,7343,16V,68uf,AlumOrgPoly,0.040 OHM ESR", "do_not_install" : 0, "part_number" : "402-000500-005", "value" : "68UF", "refdes" : "C78", "is_cap" : 1, "marker_data" : [ { "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19", "remapped_page" : null, "page" : "page19", "block" : "top", "phys_page" : "page19", "sym_num" : 1, "ppath" : "top/page19_i91", "ppath_without_last_instance" : "top/page19", "page_instance" : "I91" } ], "ohm_resistance" : null, "part_type" : "CAPACITOR", "do_not_pop" : 0, "voltage" : "16", "is_polar_cap" : null, "node_list" : [ "C78.2", "C78.1" ] }, "C26_SP_XF" : { "description" : "CAP,X5R,0402,50V,2200pF,Bulk Ceramic", "do_not_install" : 0, "is_cap" : 1, "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I144", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i144" } ], "ohm_resistance" : null, "value" : "2200PF", "part_number" : "402-000010-006", "refdes" : "C26_SP_XF", "part_type" : "CAPACITOR", "voltage" : "50", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C26_SP_XF.2", "C26_SP_XF.1" ] }, "R10_E2_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,511,50V,1/16W,1%,100ppm,Metal Film", "node_list" : [ "R10_E2_XF.1", "R10_E2_XF.2" ], "is_polar_cap" : null, "voltage" : "50", "do_not_pop" : 0, "part_type" : "RESISTOR", "ohm_resistance" : "511", "is_cap" : null, "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i34", "sym_num" : 1, "page_instance" : "I34", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8" } ], "refdes" : "R10_E2_XF", "part_number" : "400-000010-006", "value" : "511" }, "C115_XF" : { "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0, "part_type" : "CAPACITOR", "ohm_resistance" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i94", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I94", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "page" : "page12", "block" : "top/xc2_fpga_blk", "phys_page" : "page12" } ], "is_cap" : 1, "refdes" : "C115_XF", "value" : "0.22UF", "part_number" : "402-000010-035", "is_polar_cap" : null, "node_list" : [ "C115_XF.1", "C115_XF.2" ], "voltage" : "6.3", "do_not_pop" : 0 }, "C383_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "is_polar_cap" : null, "node_list" : [ "C383_XF.1", "C383_XF.2" ], "do_not_pop" : 0, "voltage" : "6.3", "part_type" : "CAPACITOR", "refdes" : "C383_XF", "value" : "0.22UF", "part_number" : "402-000010-035", "ohm_resistance" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i160", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "page_instance" : "I160", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null, "page" : "page29", "block" : "top/xc2_fpga_blk", "phys_page" : "page29" } ], "is_cap" : 1 }, "C101_FL_XF" : { "description" : "CAP,X7R,0402,50V,1000pF,Precison Ceramic", "do_not_install" : 0, "part_type" : "CAPACITOR", "refdes" : "C101_FL_XF", "value" : "1000PF", "part_number" : "402-000050-015", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_page" : "page9", "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i69", "sym_num" : 1, "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9" } ], "is_polar_cap" : null, "node_list" : [ "C101_FL_XF.2", "C101_FL_XF.1" ], "do_not_pop" : 0, "voltage" : "50" }, "R223_XF" : { "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "part_type" : "RESISTOR", "part_number" : "400-000010-010", "value" : "1K", "refdes" : "R223_XF", "is_cap" : null, "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_page" : "page14", "block" : "top/xc2_fpga_blk", "page" : "page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i217", "sym_num" : 1, "page_instance" : "I217", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14" } ], "ohm_resistance" : "1000", "is_polar_cap" : null, "node_list" : [ "R223_XF.2", "R223_XF.1" ], "do_not_pop" : 0, "voltage" : "50" }, "R237_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "node_list" : [ "R237_XF.1", "R237_XF.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50", "part_type" : "RESISTOR", "part_number" : "400-000010-010", "value" : "1K", "refdes" : "R237_XF", "marker_data" : [ { "remapped_page" : null, "path" : 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"value" : "1.2K", "part_type" : "RESISTOR", "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R155_XF.1", "R155_XF.2" ], "is_polar_cap" : null, "description" : "RES,MF,0402,1.2K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "C23_FL_XF" : { "description" : "CAP,X5R,1206,10V,47UF,Bulk Ceramic 1.6mm Thk", "do_not_install" : 0, "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i33", "sym_num" : 1, "page_instance" : "I33", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_page" : "page5", "page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1" } ], "refdes" : "C23_FL_XF", "part_number" : "402-000010-032", "value" : "47UF", "part_type" : "CAPACITOR", "voltage" : "10", "do_not_pop" : 0, "node_list" : [ "C23_FL_XF.2", "C23_FL_XF.1" ], "is_polar_cap" : null }, "R170_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "voltage" : "50", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "R170_XF.1", "R170_XF.2" ], "ohm_resistance" : "1000", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i220", "sym_num" : 1, "page_instance" : "I220", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk" } ], "is_cap" : null, "refdes" : "R170_XF", "value" : "1K", "part_number" : "400-000010-010", "part_type" : "RESISTOR" }, "C8_XF" : { "part_type" : "CAPACITOR", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "page_instance" : "I161", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i161", "sym_num" : 1 } ], "refdes" : "C8_XF", "value" : "4.7UF", "part_number" : "402-000010-028", "is_polar_cap" : null, "node_list" : [ "C8_XF.1", "C8_XF.2" ], "voltage" : "4", "do_not_pop" : 0, "description" : "CAP,X5R,0402,4V,4.7UF,Bulk Ceramic", "do_not_install" : 0 }, "C367_XF" : { "voltage" : "6.3", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C367_XF.2", "C367_XF.1" ], "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_path" : 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I45", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i45" } ], "ohm_resistance" : null, "part_number" : "402-000010-025", "value" : "10UF", "refdes" : "C67_SD_XF", "part_type" : "CAPACITOR", "voltage" : "16", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C67_SD_XF.2", "C67_SD_XF.1" ] }, "C78_XF" : { "part_type" : "CAPACITOR", "ohm_resistance" : null, "marker_data" : [ { "page" : "page11", "block" : "top/xc2_fpga_blk", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I626", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i626" } ], "is_cap" : 1, "refdes" : "C78_XF", "value" : "0.22UF", "part_number" : "402-000010-035", "is_polar_cap" : null, "node_list" : [ "C78_XF.1", "C78_XF.2" ], "voltage" : "6.3", "do_not_pop" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "S1" : { "part_number" : "406-000003-001", "value" : null, "refdes" : "S1", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page17", "path" : "@top_lib.top(sch_1):page17", "phys_page" : "page17", "block" : "top", "page" : "page17", "ppath" : "top/page17_i12", "sym_num" : 1, "page_instance" : "I12", "ppath_without_last_instance" : "top/page17" } ], "is_cap" : null, "ohm_resistance" : null, "part_type" : "", "do_not_pop" : 0, "voltage" : "24V", "node_list" : [ "S1.1", "S1.4", "S1.3", "S1.6", "S1.2", "S1.5" ], "is_polar_cap" : null, "description" : "Switch,smt rotary, 6 pin, 0-9,a-f stops,HEX encoded", "do_not_install" : 0 }, "C2" : { "do_not_pop" : 0, "voltage" : "25", "is_polar_cap" : null, "node_list" : [ "C2.2", "C2.3", "C2.4", "C2.1" ], "refdes" : "C2", "part_number" : "402-000041-001", "value" : ".1UF", "ohm_resistance" : null, "marker_data" : [ { "page" : "page10", "block" : "top", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page10", "page_instance" : "I123", "sym_num" : 1, "ppath" : "top/page10_i123" } ], "is_cap" : 1, "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X7R,0805C_4T,25V,.1UF,2A Feed Thru" }, "C36_XF" : { "is_polar_cap" : null, "node_list" : [ "C36_XF.1", "C36_XF.2" ], "do_not_pop" : 0, "voltage" : "6.3", "part_type" : "CAPACITOR", "value" : "0.22UF", "part_number" : "402-000010-035", "refdes" : "C36_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i629", "sym_num" : 1, "page_instance" : "I629", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "remapped_page" : null, "path" : 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: "0", "value" : "0OHM", "part_number" : "400-000014-011", "refdes" : "R1_XF", "do_not_install" : 0, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF" }, "R174_XF" : { "description" : "RES,MF,0402,100,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "part_type" : "RESISTOR", "ohm_resistance" : "100", "is_cap" : null, "marker_data" : [ { "page_instance" : "I230", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i230", "sym_num" : 1, "phys_page" : "page12", "block" : "top/xc2_fpga_blk", "page" : "page12", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12" } ], "refdes" : "R174_XF", "value" : "100", "part_number" : "400-000010-004", "node_list" : [ "R174_XF.2", "R174_XF.1" ], "is_polar_cap" : null, "voltage" : "50", "do_not_pop" : 0 }, "C44_XF" : { "voltage" : "6.3", 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"top/xc2_fpga_blk", "page" : "page22", "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i60", "sym_num" : 1, "page_instance" : "I60", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22" } ], "refdes" : "R159_XF", "value" : "511", "part_number" : "400-000010-006", "part_type" : "RESISTOR", "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R159_XF.1", "R159_XF.2" ], "is_polar_cap" : null }, "R124_XF" : { "do_not_pop" : 0, "voltage" : "50", "is_polar_cap" : null, "node_list" : [ "R124_XF.1", "R124_XF.2" ], "value" : "511", "part_number" : "400-000010-006", "refdes" : "R124_XF", "is_cap" : null, "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "page_instance" : "I87", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i87", "block" : "top/xc2_fpga_blk", "page" : "page29", "phys_page" : "page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null } ], "ohm_resistance" : "511", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,511,50V,1/16W,1%,100ppm,Metal Film" }, "C388_XF" : { "value" : "0.22UF", "part_number" : "402-000010-035", "refdes" : "C388_XF", "is_cap" : 1, "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null, "page" : "page29", "block" : "top/xc2_fpga_blk", "phys_page" : "page29", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i170", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "page_instance" : "I170" } ], "ohm_resistance" : null, "part_type" : "CAPACITOR", "do_not_pop" : 0, "voltage" : "6.3", "is_polar_cap" : null, "node_list" : [ "C388_XF.1", "C388_XF.2" ], "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "C64_SP_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0402,25V,0.01uF,Bulk Ceramic", "is_polar_cap" : null, "node_list" : [ "C64_SP_XF.1", "C64_SP_XF.2" ], "do_not_pop" : 0, "voltage" : "25", "part_type" : "CAPACITOR", "part_number" : "402-000010-005", "value" : "0.01UF", "refdes" : "C64_SP_XF", "is_cap" : 1, "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I51" } ], "ohm_resistance" : null }, "R65_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,4.64K,50V,1/16W,1%,100ppm,Metal Film", "node_list" : [ "R65_XF.1", "R65_XF.2" ], "is_polar_cap" : null, "voltage" : "50", "do_not_pop" : 0, "part_type" : "RESISTOR", "ohm_resistance" : "4640", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i9", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "page_instance" : "I9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "remapped_page" : null, "page" : "page15", "block" : "top/xc2_fpga_blk", "phys_page" : "page15" } ], "is_cap" : null, "refdes" : "R65_XF", "value" : "4.64K", "part_number" : "400-000010-007" }, "C6_E2_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0603,6.3V,22UF,Bulk Ceramic", "is_polar_cap" : null, "node_list" : [ "C6_E2_XF.1", "C6_E2_XF.2" ], "do_not_pop" : 0, "voltage" : "6.3", "part_type" : "CAPACITOR", "value" : "22UF", "part_number" : "402-000010-012", "refdes" : "C6_E2_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i98", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3", "page_instance" : "I98", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "phys_page" : "page3" } ], "is_cap" : 1, "ohm_resistance" : null }, "C55_XF" : { "part_type" : "CAPACITOR", "refdes" : "C55_XF", "part_number" : "402-000010-001", "value" : ".22UF", "ohm_resistance" : null, "marker_data" : [ { "page" : "page20", "block" : "top/xc2_fpga_blk", "phys_page" : "page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I30", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i30" } ], "is_cap" : 1, "is_polar_cap" : null, "node_list" : [ "C55_XF.2", "C55_XF.1" ], "do_not_pop" : 0, "voltage" : "6.3", "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "R54_SP_XF" : { "node_list" : [ "R54_SP_XF.2", "R54_SP_XF.1" ], "is_polar_cap" : null, "voltage" : "25", "do_not_pop" : 0, "part_type" : "RESISTOR", "is_cap" : null, "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I463", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i463", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null } ], "ohm_resistance" : "48700", "value" : "48.7K", "part_number" : "400-000015-027", "refdes" : "R54_SP_XF", "do_not_install" : 0, "description" : "RES,MF,0402,48.7K,25V,1/16W,0.5%,100ppm,Metal Film" }, "R5_E2_XF" : { "description" : "RES,MF,0402,4.64K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "part_type" : "RESISTOR", "is_cap" : null, "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i81", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3", "page_instance" : "I81" } ], "ohm_resistance" : "4640", "part_number" : "400-000010-007", "value" : "4.64K", "refdes" : "R5_E2_XF", "node_list" : [ "R5_E2_XF.2", "R5_E2_XF.1" ], "is_polar_cap" : null, "voltage" : "50", "do_not_pop" : 0 }, "R16_XF" : { "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R16_XF.1", "R16_XF.2" ], "is_polar_cap" : null, "is_cap" : null, "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page18", "phys_page" : "page18", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page18_i32", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page18", "page_instance" : "I32" } ], "ohm_resistance" : "511", "value" : "511", "part_number" : "400-000010-006", "refdes" : "R16_XF", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,511,50V,1/16W,1%,100ppm,Metal Film" }, "R37_SP_XF" : { "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R37_SP_XF.1", "R37_SP_XF.2" ], "is_polar_cap" : null, "ohm_resistance" : "10000", "is_cap" : null, "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "page_instance" : "I63", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i63", "sym_num" : 1 } ], "refdes" : "R37_SP_XF", "value" : "10K", "part_number" : "400-000010-074", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,10K,50V,1/16W,1%,100ppm,Metal Film" }, "C88_XF" : { "do_not_pop" : 0, "voltage" : "6.3", "is_polar_cap" : null, "node_list" : [ "C88_XF.2", "C88_XF.1" ], "refdes" : "C88_XF", "value" : ".22UF", "part_number" : "402-000010-001", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page18_i25", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page18", "page_instance" : "I25", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page18", "phys_page" : "page18" } ], "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling" }, "C10_XF" : { "voltage" : "2.5", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C10_XF.2", "C10_XF.1" ], "ohm_resistance" : null, "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I114", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i114", "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null } ], "is_cap" : 1, "refdes" : "C10_XF", "part_number" : "402-000015-007", "value" : "47UF", "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X6S,0603,2.5V,47uF,Bulk Ceramic" }, "C61" : { "node_list" : [ "C61.2", "C61.1" ], "is_polar_cap" : null, "voltage" : "16", "do_not_pop" : 0, "part_type" : "CAPACITOR", "is_cap" : 1, "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19", "phys_page" : "page19", "page" : "page19", "block" : "top", "ppath" : "top/page19_i96", "sym_num" : 1, "page_instance" : "I96", "ppath_without_last_instance" : "top/page19" } ], "ohm_resistance" : null, "part_number" : "402-000500-005", "value" : "68UF", "refdes" : "C61", "do_not_install" : 0, "description" : "CAP,ALUM_CP,7343,16V,68uf,AlumOrgPoly,0.040 OHM ESR" }, "C311_XF" : { "part_type" : "CAPACITOR", "refdes" : "C311_XF", "part_number" : "402-000010-035", "value" : "0.22UF", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "page" : "page13", "block" : "top/xc2_fpga_blk", "phys_page" : "page13", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i90", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I90" } ], "is_polar_cap" : null, "node_list" : [ "C311_XF.1", "C311_XF.2" ], "do_not_pop" : 0, "voltage" : "6.3", "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "C7_XF" : { "do_not_install" : 0, "description" : "CAP,X6S,0603,2.5V,47uF,Bulk Ceramic", "is_polar_cap" : null, "node_list" : [ "C7_XF.2", "C7_XF.1" ], "voltage" : "2.5", "do_not_pop" : 0, "part_type" : "CAPACITOR", "ohm_resistance" : null, "marker_data" : [ { "page_instance" : "I113", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i113", "sym_num" : 1, "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23" } ], "is_cap" : 1, "refdes" : "C7_XF", "part_number" : "402-000015-007", "value" : "47UF" }, "R124_SP_XF" : { "do_not_pop" : 0, "voltage" : "50", "is_polar_cap" : null, "node_list" : [ "R124_SP_XF.1", "R124_SP_XF.2" ], "refdes" : "R124_SP_XF", "part_number" : "400-000014-011", "value" : "0OHM", "ohm_resistance" : "0", "marker_data" : [ { "phys_page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "page_instance" : "I83", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i83", "sym_num" : 1 } ], "is_cap" : null, "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF" }, "R51" : { "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "part_type" : "RESISTOR", "value" : "1K", "part_number" : "400-000010-010", "refdes" : "R51", "marker_data" : [ { "ppath_without_last_instance" : "top/page4", "page_instance" : "I47", "sym_num" : 1, "ppath" : "top/page4_i47", "page" : "page4", "block" : "top", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page4", "remapped_page" : null } ], "is_cap" : null, "ohm_resistance" : "1000", "node_list" : [ "R51.1", "R51.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50" }, "C47_CPLD" : { "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "do_not_install" : 0, "value" : ".22UF", "part_number" : "402-000010-001", "refdes" : "C47_CPLD", "is_cap" : 1, "marker_data" : [ { "phys_page" : "page7", "block" : "top/cpld_blk", "page" : "page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "page_instance" : "I13", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "ppath" : "top/page14_i1/cpld_blk/page7_i13", "sym_num" : 1 } ], "ohm_resistance" : null, "part_type" : "CAPACITOR", "do_not_pop" : 0, "voltage" : "6.3", "node_list" : [ "C47_CPLD.2", "C47_CPLD.1" ], "is_polar_cap" : null }, "C63_SD_XF" : { "voltage" : "4", "do_not_pop" : 0, "node_list" : [ "C63_SD_XF.2", "C63_SD_XF.1" ], "is_polar_cap" : null, "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "page_instance" : "I11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i11", "sym_num" : 1 } ], "is_cap" : 1, "ohm_resistance" : null, "part_number" : "402-000010-039", "value" : "220UF", "refdes" : "C63_SD_XF", "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X5R,1206,4V,220UF,Bulk Ceramic" }, "C55" : { "node_list" : [ "C55.2", "C55.1" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "25", "part_type" : "CAPACITOR", "refdes" : "C55", "value" : "22UF", "part_number" : "402-000010-041", "ohm_resistance" : null, "marker_data" : [ { "page_instance" : "I45", "ppath_without_last_instance" : "top/page20", "ppath" : "top/page20_i45", "sym_num" : 1, "phys_page" : "page20", "page" : "page20", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page20" } ], "is_cap" : 1, "do_not_install" : 0, "description" : "CAP,X5R,1206,25V,22UF,Bulk Ceramic" }, "C119_SP_XF" : { "description" : "CAP,X5R,1210,6.3V,100UF,Hi-freq Decoupling", "do_not_install" : 0, "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i21", "sym_num" : 1, "page_instance" : "I21", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7" } ], "is_cap" : 1, "ohm_resistance" : null, "part_number" : "402-000010-031", "value" : "100UF", "refdes" : "C119_SP_XF", "part_type" : "CAPACITOR", "voltage" : "6.3", "do_not_pop" : 0, "node_list" : [ "C119_SP_XF.2", "C119_SP_XF.1" ], "is_polar_cap" : null }, "R16" : { "do_not_install" : 0, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF", "node_list" : [ "R16.1", "R16.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50", "part_type" : "RESISTOR", "part_number" : "400-000014-011", "value" : "0OHM", "refdes" : "R16", "marker_data" : [ { "page_instance" : "I139", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i139", "sym_num" : 1, "phys_page" : "page10", "page" : "page10", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10" } ], "is_cap" : null, "ohm_resistance" : "0" }, "R130_SP_XF" : { "refdes" : "R130_SP_XF", "part_number" : "400-000015-037", "value" : "909", "ohm_resistance" : "909", "is_cap" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8_i90", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8", "page_instance" : "I90", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page8", "phys_page" : "page8" } ], "part_type" : "RESISTOR", "do_not_pop" : 0, "voltage" : "25", "is_polar_cap" : null, "node_list" : [ "R130_SP_XF.1", "R130_SP_XF.2" ], "description" : "RES,MF,0402,909,25V,1/16W,0.5%,25ppm,Metal Film", "do_not_install" : 0 }, "M21" : { "do_not_install" : 0, "description" : "RING PATTERN 2.9MM", "is_polar_cap" : null, "node_list" : [ "M21.MTG2", "M21.MTG3", "M21.MTG4", "M21.MTG5" ], "do_not_pop" : 0, "voltage" : "", "part_type" : "", "refdes" : "M21", "part_number" : "HOLE_RING", "value" : null, "ohm_resistance" : null, "is_cap" : null, "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page1", "path" : "@top_lib.top(sch_1):page1", "phys_page" : "page1", "block" : "top", "page" : "page1", "ppath" : "top/page1_i74", "sym_num" : 1, "page_instance" : "I74", "ppath_without_last_instance" : "top/page1" } ] }, "R65" : { "voltage" : "50", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "R65.1", "R65.2" ], "ohm_resistance" : "10000", "is_cap" : null, "marker_data" : [ { "phys_page" : "page15", "page" : "page15", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page15", "page_instance" : "I44", "ppath_without_last_instance" : "top/page15", "ppath" : "top/page15_i44", "sym_num" : 1 } ], "refdes" : "R65", "value" : "10K", "part_number" : "400-000010-074", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,10K,50V,1/16W,1%,100ppm,Metal Film" }, "R130_XF" : { "part_type" : "RESISTOR", "refdes" : "R130_XF", "value" : "1K", "part_number" : "400-000010-010", "ohm_resistance" : "1000", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null, "page" : "page17", "block" : "top/xc2_fpga_blk", "phys_page" : "page17", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i115", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I115" } ], "is_cap" : null, "node_list" : [ "R130_XF.1", "R130_XF.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50", "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "R245_XF" : { "description" : "RES,MF,0402,49.9,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "part_number" : "400-000010-003", "value" : "49.9", "refdes" : "R245_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I147", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i147", "block" : "top/xc2_fpga_blk", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null } ], "is_cap" : null, "ohm_resistance" : "49.9", "part_type" : "RESISTOR", "do_not_pop" : 0, "voltage" : "50", "node_list" : [ "R245_XF.1", "R245_XF.2" ], "is_polar_cap" : null }, "R51_XF" : { "description" : "RES,MF,0402,240,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "ohm_resistance" : "240", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "remapped_page" : null, "page" : "page22", "block" : "top/xc2_fpga_blk", "phys_page" : "page22", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i39", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "page_instance" : "I39" } ], "is_cap" : null, "refdes" : "R51_XF", "value" : "240", "part_number" : "400-000010-090", "part_type" : "RESISTOR", "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R51_XF.1", "R51_XF.2" ], "is_polar_cap" : null }, "C10" : { "part_number" : "402-000010-026", "value" : "1UF", "refdes" : "C10", "is_cap" : 1, "marker_data" : [ { "ppath_without_last_instance" : "top/page10", "page_instance" : "I127", "sym_num" : 1, "ppath" : "top/page10_i127", "block" : "top", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "remapped_page" : null } ], "ohm_resistance" : null, "part_type" : "CAPACITOR", "do_not_pop" : 0, "voltage" : "16", "is_polar_cap" : null, "node_list" : [ "C10.2", "C10.1" ], "description" : "CAP,X5R,0402,16V,1UF,Bulk Ceramic", "do_not_install" : 0 }, "C61_XF" : { "voltage" : "2.5", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C61_XF.2", "C61_XF.1" ], "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i134", "sym_num" : 1, "page_instance" : "I134", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23" } ], "is_cap" : 1, "ohm_resistance" : null, "value" : "47UF", "part_number" : "402-000015-007", "refdes" : "C61_XF", "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X6S,0603,2.5V,47uF,Bulk Ceramic" }, "R228_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,100,50V,1/16W,1%,100ppm,Metal Film", "node_list" : [ "R228_XF.2", "R228_XF.1" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50", "part_type" : "RESISTOR", "value" : "100", "part_number" : "400-000010-004", "refdes" : "R228_XF", "marker_data" : [ { "page_instance" : "I236", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i236", "sym_num" : 1, "phys_page" : "page14", "block" : "top/xc2_fpga_blk", "page" : "page14", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14" } ], "is_cap" : null, "ohm_resistance" : "100" }, "C346_XF" : { "description" : "CAP,X6S,0402,6.3V,10uF,Bulk Ceramic", "do_not_install" : 0, "part_type" : "CAPACITOR", "refdes" : "C346_XF", "part_number" : "402-000015-008", "value" : "10UF", "ohm_resistance" : null, "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I59", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i59" } ], "is_cap" : 1, "node_list" : [ "C346_XF.1", "C346_XF.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "6.3" }, "C119_XF" : { "part_type" : "CAPACITOR", "refdes" : "C119_XF", "part_number" : "402-000010-035", "value" : "0.22UF", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "page" : "page12", "block" : "top/xc2_fpga_blk", "phys_page" : "page12", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i66", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I66" } ], "is_polar_cap" : null, "node_list" : [ "C119_XF.1", "C119_XF.2" ], "do_not_pop" : 0, "voltage" : "6.3", "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "C27_FL_XF" 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"do_not_pop" : 0, "voltage" : "50", "part_type" : "RESISTOR", "refdes" : "R277_XF", "value" : "1K", "part_number" : "400-000010-010", "ohm_resistance" : "1000", "is_cap" : null, "marker_data" : [ { "page_instance" : "I146", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i146", "sym_num" : 1, "phys_page" : "page29", "block" : "top/xc2_fpga_blk", "page" : "page29", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29" } ], "do_not_install" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film" }, "C2_E1_XF" : { "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "do_not_install" : 0, "ohm_resistance" : null, "marker_data" : [ { "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "ppath" : 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"is_cap" : 1, "refdes" : "C224_XF", "value" : ".22UF", "part_number" : "402-000010-001", "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling" }, "R20" : { "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R20.1", "R20.2" ], "is_polar_cap" : null, "ohm_resistance" : "0", "is_cap" : null, "marker_data" : [ { "phys_page" : "page17", "block" : "top", "page" : "page17", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page17", "path" : "@top_lib.top(sch_1):page17", "page_instance" : "I7", "ppath_without_last_instance" : "top/page17", "ppath" : "top/page17_i7", "sym_num" : 1 } ], "refdes" : "R20", "value" : "0OHM", "part_number" : "400-000014-011", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF" }, "C128_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "is_polar_cap" : null, "node_list" : [ "C128_XF.1", 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"top/mgmt_pwr_block", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page18_i1/mgmt_pwr_block/page4_i20", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page4", "page_instance" : "I20" } ], "is_cap" : null, "ohm_resistance" : "82000", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,82.0K,25V,1/16W,0.5%,100ppm,Metal Film" }, "R219_XF" : { "refdes" : "R219_XF", "part_number" : "400-000010-004", "value" : "100", "ohm_resistance" : "100", "is_cap" : null, "marker_data" : [ { "phys_page" : "page14", "block" : "top/xc2_fpga_blk", "page" : "page14", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "page_instance" : "I211", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i211", "sym_num" : 1 } ], "part_type" : "RESISTOR", "do_not_pop" : 0, "voltage" : "50", "node_list" : [ "R219_XF.2", "R219_XF.1" ], "is_polar_cap" : null, "description" : "RES,MF,0402,100,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "C177_XF" : { "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0, "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null, "page" : "page14", "block" : "top/xc2_fpga_blk", "phys_page" : "page14", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i113", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I113" } ], "refdes" : "C177_XF", "value" : "0.22UF", "part_number" : "402-000010-035", "part_type" : "CAPACITOR", "voltage" : "6.3", "do_not_pop" : 0, "node_list" : [ "C177_XF.1", "C177_XF.2" ], "is_polar_cap" : null }, "R17_FL_XF" : { "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "refdes" : "R17_FL_XF", "value" : "1K", "part_number" : "400-000010-010", "ohm_resistance" : "1000", "is_cap" : null, "marker_data" : [ { "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "page_instance" : "I4", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8_i4", "sym_num" : 1 } ], "part_type" : "RESISTOR", "do_not_pop" : 0, "voltage" : "50", "is_polar_cap" : null, "node_list" : [ "R17_FL_XF.1", "R17_FL_XF.2" ] }, "C13_E0_XF" : { "description" : "CAP,X5R,0402,4V,4.7UF,Bulk Ceramic", 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: "402-000010-035", "refdes" : "C230_XF", "is_cap" : 1, "marker_data" : [ { "page_instance" : "I682", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i682", "sym_num" : 1, "phys_page" : "page11", "block" : "top/xc2_fpga_blk", "page" : "page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11" } ], "ohm_resistance" : null, "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling" }, "C5_MP" : { "part_type" : "CAPACITOR", "value" : "22UF", "part_number" : "402-000010-029", "refdes" : "C5_MP", "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page18_i1/mgmt_pwr_block/page3_i19", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page3", "page_instance" : "I19", "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/mgmt_pwr_block", "phys_page" : "page3" } ], "ohm_resistance" : null, "node_list" : [ "C5_MP.1", "C5_MP.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "4", "description" : "CAP,X5R,0603,4V,22UF,Bulk Ceramic", "do_not_install" : 0 }, "C145_XF" : { "refdes" : "C145_XF", "part_number" : "402-000010-001", "value" : ".22UF", "ohm_resistance" : null, "marker_data" : [ { "page_instance" : "I18", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i18", "sym_num" : 1, "phys_page" : "page17", "page" : "page17", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : 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null, "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i171", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I171" } ], "ohm_resistance" : null, "node_list" : [ "C164_XF.2", "C164_XF.1" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "6.3" }, "J1_E1_XF" : { "do_not_install" : 0, "description" : "CONN, EDSFF, 84POS, 2C, VERT, SMT", "voltage" : "", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "J1_E1_XF.B14", "J1_E1_XF.A14", "J1_E1_XF.B15", "J1_E1_XF.A15", "J1_E1_XF.B9", "J1_E1_XF.A10", "J1_E1_XF.A11", "J1_E1_XF.B10", "J1_E1_XF.A12", "J1_E1_XF.B42", "J1_E1_XF.B12", "J1_E1_XF.A7", "J1_E1_XF.A8", "J1_E1_XF.A9", "J1_E1_XF.A17", "J1_E1_XF.A20", "J1_E1_XF.A23", "J1_E1_XF.A26", "J1_E1_XF.A30", "J1_E1_XF.A33", "J1_E1_XF.A36", "J1_E1_XF.A39", "J1_E1_XF.A18", "J1_E1_XF.A21", "J1_E1_XF.A24", "J1_E1_XF.A27", "J1_E1_XF.A31", "J1_E1_XF.A34", "J1_E1_XF.A37", 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i101", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3" } ], "is_cap" : null, "refdes" : "J1_E1_XF", "value" : null, "part_number" : "410-000317-001", "part_type" : "CONNECTOR" }, "C12_XF" : { "do_not_install" : 0, "description" : "CAP,X6S,0603,2.5V,47uF,Bulk Ceramic", "is_polar_cap" : null, "node_list" : [ "C12_XF.2", "C12_XF.1" ], "voltage" : "2.5", "do_not_pop" : 0, "part_type" : "CAPACITOR", "ohm_resistance" : null, "marker_data" : [ { "remapped_page" : null, "phys_path" : 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"top/page14_i1/cpld_blk/page9" } ], "ohm_resistance" : "511", "part_number" : "400-000010-006", "value" : "511", "refdes" : "R4_CPLD", "node_list" : [ "R4_CPLD.2", "R4_CPLD.1" ], "is_polar_cap" : null, "voltage" : "50", "do_not_pop" : 0 }, "TP1" : { "do_not_install" : 0, "description" : "TestPoint,SMT,RectPad,.090inheight", "voltage" : "", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "TP1.1" ], "ohm_resistance" : null, "marker_data" : [ { "path" : "@top_lib.top(sch_1):page2", "phys_path" : "@top_lib.top(sch_1):page2", "remapped_page" : null, "page" : "page2", "block" : "top", "phys_page" : "page2", "sym_num" : 1, "ppath" : "top/page2_i24", "ppath_without_last_instance" : "top/page2", "page_instance" : "I24" } ], "is_cap" : null, "refdes" : "TP1", "part_number" : "410-000021-001", "value" : null, "part_type" : "CONNECTOR" }, "R68_SD_XF" : { "description" : "RES,MF,0402,10K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "part_type" : "RESISTOR", "refdes" : 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"part_number" : "410-000021-001", "value" : null, "part_type" : "CONNECTOR", "do_not_install" : 0, "description" : "TestPoint,SMT,RectPad,.090inheight" }, "C290_XF" : { "is_polar_cap" : null, "node_list" : [ "C290_XF.1", "C290_XF.2" ], "voltage" : "6.3", "do_not_pop" : 0, "part_type" : "CAPACITOR", "ohm_resistance" : null, "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i756", "sym_num" : 1, "page_instance" : "I756", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11" } ], "is_cap" : 1, "refdes" : "C290_XF", "part_number" : "402-000010-035", "value" : "0.22UF", "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling" }, "R81" : { "description" : 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"voltage" : "6.3", "do_not_pop" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "R81_XF" : { "refdes" : "R81_XF", "value" : "1K", "part_number" : "400-000010-010", "ohm_resistance" : "1000", "is_cap" : null, "marker_data" : [ { "page_instance" : "I60", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i60", "sym_num" : 1, "phys_page" : "page17", "page" : "page17", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17" } ], "part_type" : "RESISTOR", "do_not_pop" : 0, "voltage" : "50", "is_polar_cap" : null, "node_list" : [ "R81_XF.2", "R81_XF.1" ], "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "C42" : { "do_not_pop" : 0, "voltage" : "6.3", "node_list" : [ "C42.1", "C42.2" ], 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], "is_polar_cap" : null, "voltage" : "50", "do_not_pop" : 0, "description" : "CAP,X5R,0402,50V,2200pF,Bulk Ceramic", "do_not_install" : 0 }, "C47" : { "node_list" : [ "C47.2", "C47.1" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "6.3", "part_type" : "CAPACITOR", "refdes" : "C47", "part_number" : "402-000010-001", "value" : ".22UF", "ohm_resistance" : null, "marker_data" : [ { "page_instance" : "I69", "ppath_without_last_instance" : "top/page4", "ppath" : "top/page4_i69", "sym_num" : 1, "phys_page" : "page4", "block" : "top", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page4", "path" : "@top_lib.top(sch_1):page4" } ], "is_cap" : 1, "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling" }, "R11_MP" : { "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF", "do_not_install" : 0, "marker_data" : [ { "block" : "top/mgmt_pwr_block", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page3", "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page3", "page_instance" : "I31", "sym_num" : 1, "ppath" : "top/page18_i1/mgmt_pwr_block/page3_i31" } ], "is_cap" : null, "ohm_resistance" : "0", "value" : "0OHM", "part_number" : "400-000014-011", "refdes" : "R11_MP", "part_type" : "RESISTOR", "voltage" : "50", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "R11_MP.1", "R11_MP.2" ] }, "C25_E1_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "voltage" : "6.3", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C25_E1_XF.1", "C25_E1_XF.2" ], "is_cap" : 1, "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "page_instance" : "I47", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i47", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null } ], "ohm_resistance" : null, "value" : "0.22UF", "part_number" : "402-000010-035", "refdes" : "C25_E1_XF", "part_type" : "CAPACITOR" }, "C39_FL_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0402,25V,0.01uF,Bulk Ceramic", "voltage" : "25", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C39_FL_XF.2", "C39_FL_XF.1" ], "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7_i31", "sym_num" : 1, "page_instance" : "I31", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "phys_page" : "page7", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page7" } ], "refdes" : "C39_FL_XF", "value" : "0.01UF", "part_number" : "402-000010-005", "part_type" : "CAPACITOR" }, "C326_XF" : { "part_type" : "CAPACITOR", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "phys_page" : "page13", "block" : "top/xc2_fpga_blk", "page" : "page13", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "page_instance" : "I85", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i85", "sym_num" : 1 } ], "refdes" : "C326_XF", "value" : "0.22UF", "part_number" : "402-000010-035", "node_list" : [ "C326_XF.1", "C326_XF.2" ], "is_polar_cap" : null, "voltage" : "6.3", "do_not_pop" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "C81_FL_XF" : { "part_type" : "CAPACITOR", "ohm_resistance" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page10_i151", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page10", "page_instance" : "I151", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page10", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page10", "phys_page" : "page10" } ], "is_cap" : 1, "refdes" : "C81_FL_XF", "part_number" : "402-000020-001", "value" : ".1UF", "is_polar_cap" : null, "node_list" : [ "C81_FL_XF.1", "C81_FL_XF.2" ], "voltage" : "10", "do_not_pop" : 0, "description" : "CAP,X7R,0603,10V,.1uF,Hi-freq Decoupling", "do_not_install" : 0 }, "R248_XF" : { "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "part_type" : "RESISTOR", "is_cap" : null, "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "page_instance" : "I2418", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2418" } ], "ohm_resistance" : "1000", "part_number" : "400-000010-010", "value" : "1K", "refdes" : "R248_XF", "is_polar_cap" : null, "node_list" : [ "R248_XF.2", "R248_XF.1" ], "voltage" : "50", "do_not_pop" : 0 }, "C456_XF" : { "part_type" : "CAPACITOR", "refdes" : "C456_XF", "value" : ".22UF", "part_number" : "402-000010-001", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "phys_page" : "page20", "block" : "top/xc2_fpga_blk", "page" : "page20", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "page_instance" : "I57", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i57", "sym_num" : 1 } ], "is_polar_cap" : null, "node_list" : [ "C456_XF.2", "C456_XF.1" ], "do_not_pop" : 0, "voltage" : "6.3", "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "R153_XF" : { "do_not_pop" : 0, "voltage" : "50", "node_list" : [ "R153_XF.1", "R153_XF.2" ], "is_polar_cap" : null, "part_number" : "400-000010-006", "value" : "511", "refdes" : "R153_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page29", "phys_page" : "page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "page_instance" : "I78", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i78" } ], "is_cap" : null, "ohm_resistance" : "511", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,511,50V,1/16W,1%,100ppm,Metal Film" }, "R225_XF" : { "description" : "RES,MF,0402,100,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "value" : "100", "part_number" : "400-000010-004", "refdes" : "R225_XF", "is_cap" : null, "marker_data" : [ { "page_instance" : "I230", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i230", "sym_num" : 1, "phys_page" : "page14", "page" : "page14", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14" } ], "ohm_resistance" : "100", "part_type" : "RESISTOR", "do_not_pop" : 0, "voltage" : "50", "is_polar_cap" : null, "node_list" : [ "R225_XF.2", "R225_XF.1" ] }, "Q4" : { "do_not_install" : 0, "description" : "XSTR,N-CHAN MOSFET,3PIN VMT3,300MA,20V,1OHM", "is_polar_cap" : null, "node_list" : [ "Q4.2", "Q4.3", "Q4.1" ], "voltage" : "20", "do_not_pop" : 0, "part_type" : "TRANSISTOR", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page13", "path" : "@top_lib.top(sch_1):page13", "remapped_page" : null, "block" : "top", "page" : "page13", "phys_page" : "page13", "sym_num" : 1, "ppath" : "top/page13_i35", "ppath_without_last_instance" : "top/page13", "page_instance" : "I35" } ], "is_cap" : null, "ohm_resistance" : null, "value" : null, "part_number" : "405-000010-001", "refdes" : "Q4" }, "C10_CPLD" : { "refdes" : "C10_CPLD", "part_number" : "402-000010-001", "value" : ".22UF", "ohm_resistance" : null, "marker_data" : [ { "page" : "page7", "block" : "top/cpld_blk", "phys_page" : "page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I121", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page7_i121" } ], "is_cap" : 1, "part_type" : "CAPACITOR", "do_not_pop" : 0, "voltage" : "6.3", "node_list" : [ "C10_CPLD.2", "C10_CPLD.1" ], "is_polar_cap" : null, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "C385_XF" : { "voltage" : "6.3", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C385_XF.1", "C385_XF.2" ], "is_cap" : 1, "marker_data" : [ { "page_instance" : "I164", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i164", "sym_num" : 1, "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29" } ], "ohm_resistance" : null, "value" : "0.22UF", "part_number" : "402-000010-035", "refdes" : "C385_XF", "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling" }, "R52_SP_XF" : { "node_list" : [ "R52_SP_XF.2", "R52_SP_XF.1" ], "is_polar_cap" : null, "voltage" : "50", "do_not_pop" : 0, "part_type" : "RESISTOR", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i41", "sym_num" : 1, "page_instance" : "I41", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "is_cap" : null, "ohm_resistance" : "1000", "part_number" : "400-000010-010", "value" : "1K", "refdes" : "R52_SP_XF", "do_not_install" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film" }, "C412_XF" : { "voltage" : "6.3", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C412_XF.1", "C412_XF.2" ], "is_cap" : 1, "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "page_instance" : "I178", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i178", "sym_num" : 1 } ], "ohm_resistance" : null, "part_number" : "402-000010-001", "value" : ".22UF", "refdes" : "C412_XF", "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling" }, "D2_CPLD" : { "is_polar_cap" : null, "node_list" : [ "D2_CPLD.1", "D2_CPLD.3", "D2_CPLD.4", "D2_CPLD.2" ], "do_not_pop" : 0, "voltage" : "R2.1V,G2.95V,B2.85V", "part_type" : "LED", "part_number" : "404-000302-001", "value" : null, "refdes" : "D2_CPLD", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "remapped_page" : null, "block" : "top/cpld_blk", "page" : "page9", "phys_page" : "page9", "sym_num" : 1, "ppath" : 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"voltage" : "6.3", "do_not_pop" : 0 }, "C10_SD_XF" : { "voltage" : "25", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C10_SD_XF.2", "C10_SD_XF.1" ], "ohm_resistance" : null, "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i14", "sym_num" : 1, "page_instance" : "I14", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3" } ], "is_cap" : 1, "refdes" : "C10_SD_XF", "part_number" : "402-000010-041", "value" : "22UF", "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X5R,1206,25V,22UF,Bulk Ceramic" }, "C150_XF" : { "part_type" : "CAPACITOR", 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"part_number" : "999-999999-999", "value" : null, "ohm_resistance" : null, "marker_data" : [ {} ], "is_cap" : null, "do_not_install" : 0, "description" : "BLOCK DIAGRAM PLACEHOLDER" }, "R91_SP_XF" : { "is_polar_cap" : null, "node_list" : [ "R91_SP_XF.2", "R91_SP_XF.1" ], "voltage" : "50", "do_not_pop" : 0, "part_type" : "RESISTOR", "marker_data" : [ { "page_instance" : "I134", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i134", "sym_num" : 1, "phys_page" : "page5", "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5" } ], "is_cap" : null, "ohm_resistance" : "0", "part_number" : "400-000014-011", "value" : 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"is_polar_cap" : null, "node_list" : [ "C125_SP_XF.2", "C125_SP_XF.1" ], "value" : ".22UF", "part_number" : "402-000010-001", "refdes" : "C125_SP_XF", "is_cap" : 1, "marker_data" : [ { "phys_page" : "page8", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8_i101", "sym_num" : 1 } ], "ohm_resistance" : null, "part_type" : "CAPACITOR" }, "C44_SD_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "voltage" : "6.3", "do_not_pop" : 0, "node_list" : [ "C44_SD_XF.2", "C44_SD_XF.1" ], "is_polar_cap" : null, "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4", "page_instance" : "I12", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4_i12", "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "remapped_page" : null } ], "refdes" : "C44_SD_XF", "value" : ".22UF", "part_number" : "402-000010-001", "part_type" : "CAPACITOR" }, "C19_SP_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,1206,6.3V,100UF,Bulk Ceramic 1.6mm Thk", "voltage" : "6.3", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C19_SP_XF.2", "C19_SP_XF.1" ], "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : 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null, "ohm_resistance" : null, "value" : null, "part_number" : "EXTRA_PROPS", "refdes" : "GP_PLACEHOLDER", "part_type" : "", "voltage" : "", "do_not_pop" : 0, "node_list" : [], "is_polar_cap" : null, "description" : "EXTRA NET/PIN/PROP PROPERTIES", "do_not_install" : 0 }, "R119_SP_XF" : { "is_polar_cap" : null, "node_list" : [ "R119_SP_XF.1", "R119_SP_XF.2" ], "voltage" : "50", "do_not_pop" : 0, "part_type" : "RESISTOR", "is_cap" : null, "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i101", 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], "is_polar_cap" : null, "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk", "page" : "page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i157", "sym_num" : 1, "page_instance" : "I157", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6" } ], "is_cap" : 1, "ohm_resistance" : null, "part_number" : "402-000010-028", "value" : "4.7UF", "refdes" : "C421_XF", "part_type" : "CAPACITOR" }, "R88" : { "do_not_install" : 0, "description" : "RES,MF,0402,10K,50V,1/16W,1%,100ppm,Metal Film", "do_not_pop" : 0, "voltage" : "50", "node_list" : [ "R88.1", "R88.2" ], "is_polar_cap" : null, "value" : "10K", "part_number" : "400-000010-074", "refdes" : "R88", "is_cap" : null, "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page15", "phys_path" : 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null, "refdes" : "D4_CPLD", "value" : null, "part_number" : "404-000302-001", "part_type" : "LED", "voltage" : "R2.1V,G2.95V,B2.85V", "do_not_pop" : 0, "node_list" : [ "D4_CPLD.1", "D4_CPLD.3", "D4_CPLD.4", "D4_CPLD.2" ], "is_polar_cap" : null, "description" : "LED,SMT,0404,RGB_LED,R30ma_G25ma_B10ma,R2.15V_G2.95V_B1.85V,4 pin 1mmx1mm", "do_not_install" : 0 }, "R216_XF" : { "part_type" : "RESISTOR", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page14", "phys_page" : "page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I240", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i240" } ], "is_cap" : null, "ohm_resistance" : "1000", "value" : "1K", "part_number" : "400-000010-010", "refdes" : "R216_XF", "node_list" : [ "R216_XF.2", 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null, "description" : "RES,MF,0402,3.24K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "Q2" : { "do_not_install" : 0, "description" : "XSTR,N-CHAN MOSFET,3PIN VMT3,300MA,20V,1OHM", "do_not_pop" : 0, "voltage" : "20", "node_list" : [ "Q2.3", "Q2.2", "Q2.1" ], "is_polar_cap" : null, "value" : null, "part_number" : "405-000010-001", "refdes" : "Q2", "is_cap" : null, "marker_data" : [ { "ppath_without_last_instance" : "top/page13", "page_instance" : "I99", "sym_num" : 1, "ppath" : "top/page13_i99", "block" : "top", "page" : "page13", "phys_page" : "page13", "phys_path" : "@top_lib.top(sch_1):page13", "path" : "@top_lib.top(sch_1):page13", "remapped_page" : null } ], "ohm_resistance" : null, "part_type" : "TRANSISTOR" }, "C212_XF" : { "description" : "CAP,X5R,0402,4V,4.7UF,Bulk Ceramic", "do_not_install" : 0, "part_type" : "CAPACITOR", "is_cap" : 1, "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", 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"C8_SP_XF" : { "part_type" : "CAPACITOR", "ohm_resistance" : null, "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I28", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i28", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5", "phys_page" : "page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null } ], "is_cap" : 1, "refdes" : "C8_SP_XF", "part_number" : "402-000010-033", "value" : "100UF", "node_list" : [ "C8_SP_XF.2", "C8_SP_XF.1" ], "is_polar_cap" : null, "voltage" : "6.3", "do_not_pop" : 0, "description" : "CAP,X5R,1206,6.3V,100UF,Bulk Ceramic 1.6mm Thk", "do_not_install" : 0 }, "R241_XF" : { "part_type" : "RESISTOR", "value" : "4.64K", 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: "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i75", "sym_num" : 1, "page_instance" : "I75", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7" } ], "is_cap" : null, "do_not_install" : 0, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF" }, "C256_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_pop" : 0, "voltage" : "6.3", "node_list" : [ "C256_XF.1", "C256_XF.2" ], "is_polar_cap" : null, "value" : "0.22UF", "part_number" : "402-000010-035", "refdes" : "C256_XF", "marker_data" : [ { "page_instance" : "I148", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i148", "sym_num" : 1, "phys_page" : "page14", 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"do_not_install" : 0 }, "C174_XF" : { "part_type" : "CAPACITOR", "part_number" : "402-000010-035", "value" : "0.22UF", "refdes" : "C174_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page13", "phys_page" : "page13", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i82", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I82" } ], "is_cap" : 1, "ohm_resistance" : null, "node_list" : [ "C174_XF.1", "C174_XF.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "6.3", "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "R44_XF" : { "is_cap" : null, "marker_data" : [ { "page_instance" : "I26", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "ppath" : 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"part_number" : "402-000010-005", "refdes" : "C38_FL_XF", "part_type" : "CAPACITOR", "voltage" : "25", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C38_FL_XF.2", "C38_FL_XF.1" ], "description" : "CAP,X5R,0402,25V,0.01uF,Bulk Ceramic", "do_not_install" : 0 }, "C1_XF" : { "voltage" : "6.3", "do_not_pop" : 0, "node_list" : [ "C1_XF.1", "C1_XF.2" ], "is_polar_cap" : null, "is_cap" : 1, "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i117", "sym_num" : 1, "page_instance" : "I117", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23" } ], "ohm_resistance" : null, "value" : "10UF", "part_number" : "402-000015-008", "refdes" : "C1_XF", "part_type" : "CAPACITOR", "do_not_install" : 0, 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null, "ohm_resistance" : "200", "value" : "200", "part_number" : "400-000010-116", "refdes" : "R90_FL_XF", "is_polar_cap" : null, "node_list" : [ "R90_FL_XF.1", "R90_FL_XF.2" ], "voltage" : "50", "do_not_pop" : 0, "description" : "RES,MF,0402,200,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "R28_SP_XF" : { "node_list" : [ "R28_SP_XF.1", "R28_SP_XF.2" ], "is_polar_cap" : null, "voltage" : "50", "do_not_pop" : 0, "part_type" : "RESISTOR", "ohm_resistance" : "0", "is_cap" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i139", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I139", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null, "page" : 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"C233_XF.1", "C233_XF.2" ], "is_polar_cap" : null }, "C278_XF" : { "do_not_pop" : 0, "voltage" : "6.3", "is_polar_cap" : null, "node_list" : [ "C278_XF.1", "C278_XF.2" ], "refdes" : "C278_XF", "part_number" : "402-000010-035", "value" : "0.22UF", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_page" : "page14", "page" : "page14", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14" } ], "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling" }, "R76" : { "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "refdes" : "R76", "value" : "1K", "part_number" : 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6" } ], "is_cap" : null, "is_polar_cap" : null, "node_list" : [ "R41_SP_XF.1", "R41_SP_XF.2" ], "do_not_pop" : 0, "voltage" : "25" }, "R22_FL_XF" : { "refdes" : "R22_FL_XF", "value" : "0OHM", "part_number" : "400-000014-011", "ohm_resistance" : "0", "is_cap" : null, "marker_data" : [ { "page_instance" : "I21", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i21", "sym_num" : 1, "phys_page" : "page4", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4" } ], "part_type" : "RESISTOR", "do_not_pop" : 0, "voltage" : "50", "node_list" : [ "R22_FL_XF.1", "R22_FL_XF.2" ], "is_polar_cap" : null, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF", "do_not_install" : 0 }, "C471_XF" : { "ohm_resistance" : null, "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_page" : "page20", "block" : "top/xc2_fpga_blk", "page" : "page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i15", "sym_num" : 1, "page_instance" : "I15", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20" } ], "is_cap" : 1, "refdes" : "C471_XF", "value" : ".22UF", "part_number" : "402-000010-001", "part_type" : "CAPACITOR", "voltage" : "6.3", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C471_XF.2", "C471_XF.1" ], "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "C70" : { "refdes" : "C70", "part_number" : "402-000010-032", "value" : "47UF", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page19_i56", "ppath_without_last_instance" : "top/page19", "page_instance" : "I56", "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19", "remapped_page" : null, "page" : "page19", "block" : "top", "phys_page" : "page19" } ], "part_type" : "CAPACITOR", "do_not_pop" : 0, "voltage" : "10", "is_polar_cap" : null, "node_list" : [ "C70.1", "C70.2" ], "description" : "CAP,X5R,1206,10V,47UF,Bulk Ceramic 1.6mm Thk", "do_not_install" : 0 }, "R59_FL_XF" : { "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "ohm_resistance" : "1000", "is_cap" : null, "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "page_instance" : "I25", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i25", "page" : "page4", "block" : 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[ "R13_E1_XF.1", "R13_E1_XF.2" ], "is_polar_cap" : null }, "C69_FL_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "voltage" : "6.3", "do_not_pop" : 0, "node_list" : [ "C69_FL_XF.2", "C69_FL_XF.1" ], "is_polar_cap" : null, "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page9", "phys_page" : "page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I35", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i35" } ], "refdes" : "C69_FL_XF", "part_number" : "402-000010-001", "value" : ".22UF", "part_type" : "CAPACITOR" }, "F5_SP_XF" : { "voltage" : "24V", "do_not_pop" : 0, "node_list" : [ "F5_SP_XF.2", "F5_SP_XF.1" ], "is_polar_cap" : null, "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5", "phys_page" : "page5", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i136", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I136" } ], "is_cap" : null, "ohm_resistance" : null, "part_number" : "403-000006-003", "value" : null, "refdes" : "F5_SP_XF", "part_type" : "FUSE", "do_not_install" : 0, "description" : "FUSE,10A,1206,150A@24V_Int,VERYFASTACTING" }, "R18_E2_XF" : { "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal 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"page_instance" : "I53" } ], "is_cap" : 1, "ohm_resistance" : null, "value" : "10UF", "part_number" : "402-000015-008", "refdes" : "C303_XF", "do_not_install" : 0, "description" : "CAP,X6S,0402,6.3V,10uF,Bulk Ceramic" }, "C395_XF" : { "description" : "CAP,X5R,1206,4V,220UF,Bulk Ceramic", "do_not_install" : 0, "part_type" : "CAPACITOR", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i154", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I154", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4" } ], "refdes" : "C395_XF", "part_number" : "402-000010-039", "value" : "220UF", "is_polar_cap" : null, "node_list" : [ "C395_XF.1", "C395_XF.2" ], "voltage" : "4", "do_not_pop" : 0 }, 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0, "voltage" : "50", "is_polar_cap" : null, "node_list" : [ "R14_CPLD.1", "R14_CPLD.2" ] }, "C299_XF" : { "do_not_pop" : 0, "voltage" : "6.3", "node_list" : [ "C299_XF.1", "C299_XF.2" ], "is_polar_cap" : null, "refdes" : "C299_XF", "value" : "10UF", "part_number" : "402-000015-008", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "page_instance" : "I28", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i28", "sym_num" : 1, "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23" } ], "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X6S,0402,6.3V,10uF,Bulk Ceramic" }, "L2_MP" : { "ohm_resistance" : null, "is_cap" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : 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"block" : "top", "phys_page" : "page20" } ], "ohm_resistance" : null, "do_not_install" : 0, "description" : "XSTR,N-CHAN MOSFET,3PIN VMT3,300MA,20V,1OHM" }, "R164_XF" : { "ohm_resistance" : "1000", "is_cap" : null, "marker_data" : [ { "page_instance" : "I232", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i232", "sym_num" : 1, "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12" } ], "refdes" : "R164_XF", "value" : "1K", "part_number" : "400-000010-010", "part_type" : "RESISTOR", "voltage" : "50", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "R164_XF.2", "R164_XF.1" ], "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "C104_SP_XF" : { "do_not_install" : 0, "description" : "CAP,X7R,0402,10V,0.018UF,Precision Ceramic", "voltage" : "10", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C104_SP_XF.1", "C104_SP_XF.2" ], "is_cap" : 1, "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i50", "sym_num" : 1, "page_instance" : "I50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7" } ], "ohm_resistance" : null, "value" : "0.018UF", "part_number" : "402-000050-021", "refdes" : "C104_SP_XF", "part_type" : "CAPACITOR" }, "R180_XF" : { "part_type" : "RESISTOR", "value" : "100", "part_number" : "400-000010-004", "refdes" : "R180_XF", "is_cap" : null, "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i258", "sym_num" : 1, "page_instance" : "I258", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk" } ], "ohm_resistance" : "100", "node_list" : [ "R180_XF.2", "R180_XF.1" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50", "description" : "RES,MF,0402,100,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "C4_CPLD" : { "part_type" : "CAPACITOR", "value" : ".22UF", "part_number" : "402-000010-001", "refdes" : "C4_CPLD", "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page7_i132", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I132", 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"J1_E0_XF.A39", "J1_E0_XF.A18", "J1_E0_XF.A21", "J1_E0_XF.A24", "J1_E0_XF.A27", "J1_E0_XF.A31", "J1_E0_XF.A34", "J1_E0_XF.A37", "J1_E0_XF.A40", "J1_E0_XF.B17", "J1_E0_XF.B20", "J1_E0_XF.B23", "J1_E0_XF.B26", "J1_E0_XF.B30", "J1_E0_XF.B33", "J1_E0_XF.B36", "J1_E0_XF.B39", "J1_E0_XF.B18", "J1_E0_XF.B21", "J1_E0_XF.B24", "J1_E0_XF.B27", "J1_E0_XF.B31", "J1_E0_XF.B34", "J1_E0_XF.B37", "J1_E0_XF.B40", "J1_E0_XF.A1", "J1_E0_XF.A2", "J1_E0_XF.A3", "J1_E0_XF.A4", "J1_E0_XF.A5", "J1_E0_XF.A6", "J1_E0_XF.A13", "J1_E0_XF.A16", "J1_E0_XF.A19", "J1_E0_XF.A22", "J1_E0_XF.A25", "J1_E0_XF.A28", "J1_E0_XF.A29", "J1_E0_XF.A32", "J1_E0_XF.A35", "J1_E0_XF.A38", "J1_E0_XF.A41", "J1_E0_XF.B13", "J1_E0_XF.B16", "J1_E0_XF.B19", "J1_E0_XF.B22", "J1_E0_XF.B25", "J1_E0_XF.B28", "J1_E0_XF.B29", "J1_E0_XF.B32", "J1_E0_XF.B35", "J1_E0_XF.B38", "J1_E0_XF.B41", "J1_E0_XF.B7", "J1_E0_XF.B11", "J1_E0_XF.B1", "J1_E0_XF.B2", "J1_E0_XF.B3", "J1_E0_XF.B4", "J1_E0_XF.B5", "J1_E0_XF.B6", "J1_E0_XF.A42", "J1_E0_XF.B8", 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"refdes" : "R127_SP_XF", "value" : "10.0K", "part_number" : "400-000015-015", "part_type" : "RESISTOR", "voltage" : "25", "do_not_pop" : 0, "node_list" : [ "R127_SP_XF.1", "R127_SP_XF.2" ], "is_polar_cap" : null, "description" : "RES,MF,0402,10.0K,25V,1/16W,0.5%,100ppm,Metal Film", "do_not_install" : 0 }, "R192_XF" : { "part_type" : "RESISTOR", "part_number" : "400-000010-010", "value" : "1K", "refdes" : "R192_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i232", "sym_num" : 1, "page_instance" : "I232", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_page" : "page13", "block" : "top/xc2_fpga_blk", "page" : "page13" } ], "is_cap" : null, "ohm_resistance" : "1000", "is_polar_cap" : null, "node_list" : [ "R192_XF.2", "R192_XF.1" ], "do_not_pop" : 0, "voltage" : "50", "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "R178_XF" : { "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "part_type" : "RESISTOR", "refdes" : "R178_XF", "part_number" : "400-000010-010", "value" : "1K", "ohm_resistance" : "1000", "is_cap" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i252", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I252", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page12", "phys_page" : "page12" } ], "node_list" : [ "R178_XF.1", "R178_XF.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50" }, "TP8_CPLD" : { "do_not_install" : 0, "description" : "SM_050_TP-SM_050_TP", "is_polar_cap" : null, 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"CAP,X5R,0402,4V,4.7UF,Bulk Ceramic", "do_not_install" : 0 }, "R113_XF" : { "part_type" : "RESISTOR", "ohm_resistance" : "1500", "is_cap" : null, "marker_data" : [ { "page_instance" : "I91", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i91", "sym_num" : 1, "phys_page" : "page17", "page" : "page17", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17" } ], "refdes" : "R113_XF", "part_number" : "400-000010-097", "value" : "1.50K", "node_list" : [ "R113_XF.1", "R113_XF.2" ], "is_polar_cap" : null, "voltage" : "50", "do_not_pop" : 0, "description" : "RES,MF,0402,1.50K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "C19_E2_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_pop" : 0, "voltage" : "6.3", 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"ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i115", "sym_num" : 1, "page_instance" : "I115", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11" } ], "is_cap" : 1, "ohm_resistance" : null, "value" : "560UF", "part_number" : "402-000500-008", "refdes" : "C189_SP_XF", "do_not_install" : 0, "description" : "CAP,3-TERM,ALUM_CP,7343,2V,560uf,AlumOrgPoly,0.003 OHM ESR, LOW ESL" }, "C81" : { "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "do_not_install" : 0, "part_type" : "CAPACITOR", "value" : ".22UF", "part_number" : "402-000010-001", "refdes" : "C81", "is_cap" : 1, "marker_data" : [ { "ppath" : "top/page19_i59", "sym_num" : 1, "page_instance" : "I59", "ppath_without_last_instance" : "top/page19", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page19", "path" : "@top_lib.top(sch_1):page19", "phys_page" : "page19", "block" : "top", "page" : "page19" } ], "ohm_resistance" : null, "is_polar_cap" : null, "node_list" : [ "C81.1", "C81.2" ], "do_not_pop" : 0, "voltage" : "6.3" }, "R221_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_pop" : 0, "voltage" : "50", "node_list" : [ "R221_XF.2", "R221_XF.1" ], "is_polar_cap" : null, "refdes" : "R221_XF", "part_number" : "400-000010-010", "value" : "1K", "ohm_resistance" : "1000", "is_cap" : null, "marker_data" : [ { "phys_page" : "page14", "block" : "top/xc2_fpga_blk", "page" : "page14", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "page_instance" : "I214", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i214", "sym_num" : 1 } ], "part_type" : "RESISTOR" }, "M9" : { "description" : "RING PATTERN 2.9MM", "do_not_install" : 0, "part_type" : "", "refdes" : "M9", "part_number" : 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} ], "refdes" : "C47_FL_XF", "part_number" : "402-000010-001", "value" : ".22UF", "part_type" : "CAPACITOR", "voltage" : "6.3", "do_not_pop" : 0, "node_list" : [ "C47_FL_XF.2", "C47_FL_XF.1" ], "is_polar_cap" : null }, "C4_E1_XF" : { "part_type" : "CAPACITOR", "value" : "470UF", "part_number" : "402-000500-004", "refdes" : "C4_E1_XF", "is_cap" : 1, "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "page_instance" : "I86" } ], "ohm_resistance" : null, "is_polar_cap" : null, "node_list" : [ "C4_E1_XF.2", "C4_E1_XF.1" ], "do_not_pop" : 0, "voltage" : "2.5", "description" : "CAP,ALUM_CP,7343,2.5V,470uF,AlumOrgPoly,0.0045 OHM ESR", "do_not_install" : 0 }, "C84_SP_XF" : { "node_list" : [ "C84_SP_XF.1", "C84_SP_XF.2" ], "is_polar_cap" : null, "voltage" : "10", "do_not_pop" : 0, "part_type" : "CAPACITOR", "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i427", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I427", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6" } ], "ohm_resistance" : null, "part_number" : "402-000050-021", "value" : "0.018UF", "refdes" : "C84_SP_XF", "do_not_install" : 0, "description" : "CAP,X7R,0402,10V,0.018UF,Precision Ceramic" }, "R85_XF" : { "is_polar_cap" : null, "node_list" : [ "R85_XF.2", "R85_XF.1" ], "do_not_pop" : 0, "voltage" : "50", "part_type" : "RESISTOR", "part_number" : "400-000014-011", "value" : "0OHM", "refdes" : "R85_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I37", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i37", "block" : "top/xc2_fpga_blk", "page" : "page17", "phys_page" : "page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null } ], "is_cap" : null, "ohm_resistance" : "0", "do_not_install" : 0, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF" }, "C8_E2_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0402,4V,4.7UF,Bulk Ceramic", "do_not_pop" : 0, "voltage" : "4", "node_list" : [ "C8_E2_XF.1", "C8_E2_XF.2" ], "is_polar_cap" : null, "refdes" : "C8_E2_XF", "part_number" : "402-000010-028", "value" : "4.7UF", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i89", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3", "page_instance" : "I89", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3" } ], "part_type" : "CAPACITOR" }, "C189_XF" : { "part_type" : "CAPACITOR", "marker_data" : [ { "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : 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"402-000010-041", "value" : "22UF", "refdes" : "C39", "part_type" : "CAPACITOR", "voltage" : "25", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C39.2", "C39.1" ], "description" : "CAP,X5R,1206,25V,22UF,Bulk Ceramic", "do_not_install" : 0 }, "C68_XF" : { "part_type" : "CAPACITOR", "refdes" : "C68_XF", "value" : "10UF", "part_number" : "402-000015-008", "ohm_resistance" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i25", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "page_instance" : "I25", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "remapped_page" : null, "page" : "page22", "block" : "top/xc2_fpga_blk", "phys_page" : "page22" } ], "is_cap" : 1, "node_list" : [ "C68_XF.2", "C68_XF.1" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "6.3", "description" : "CAP,X6S,0402,6.3V,10uF,Bulk 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null, "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4", "page_instance" : "I47", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i47", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null } ], "is_cap" : 1, "refdes" : "C25_E2_XF", "part_number" : "402-000010-035", "value" : "0.22UF", "node_list" : [ "C25_E2_XF.1", "C25_E2_XF.2" ], "is_polar_cap" : null, "voltage" : "6.3", "do_not_pop" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0 }, "C50_SP_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "voltage" : "6.3", "do_not_pop" : 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"phys_page" : "page4" } ], "is_cap" : null, "ohm_resistance" : "10000", "value" : "10K", "part_number" : "400-000010-074", "refdes" : "R68_ND_XF" }, "C468_XF" : { "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "do_not_install" : 0, "part_type" : "CAPACITOR", "value" : ".22UF", "part_number" : "402-000010-001", "refdes" : "C468_XF", "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "page" : "page20", "block" : "top/xc2_fpga_blk", "phys_page" : "page20" } ], "ohm_resistance" : null, "node_list" : [ "C468_XF.2", "C468_XF.1" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "6.3" }, "R201_XF" : { "do_not_install" : 0, "description" : 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"part_number" : "HOLE_RING", "refdes" : "M2", "part_type" : "", "voltage" : "", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "M2.MTG2", "M2.MTG3", "M2.MTG4", "M2.MTG5" ] }, "R150_XF" : { "refdes" : "R150_XF", "value" : "1K", "part_number" : "400-000010-010", "ohm_resistance" : "1000", "is_cap" : null, "marker_data" : [ { "page_instance" : "I2418", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2418", "sym_num" : 1, "phys_page" : "page5", "block" : "top/xc2_fpga_blk", "page" : "page5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5" } ], "part_type" : "RESISTOR", "do_not_pop" : 0, "voltage" : "50", "node_list" : [ "R150_XF.2", "R150_XF.1" ], "is_polar_cap" : null, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "R147_XF" : { "do_not_pop" : 0, "voltage" : "50", "node_list" : [ "R147_XF.2", "R147_XF.1" ], "is_polar_cap" : null, "value" : "49.9", "part_number" : "400-000010-003", "refdes" : "R147_XF", "marker_data" : [ { "page_instance" : "I85", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i85", "sym_num" : 1, "phys_page" : "page20", "page" : "page20", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20" } ], "is_cap" : null, "ohm_resistance" : "49.9", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,49.9,50V,1/16W,1%,100ppm,Metal Film" }, "C14_FL_XF" : { "is_polar_cap" : null, "node_list" : [ "C14_FL_XF.2", "C14_FL_XF.1" ], "do_not_pop" : 0, "voltage" : "4", "part_type" : "CAPACITOR", "value" : "4.7UF", "part_number" : "402-000010-028", "refdes" : "C14_FL_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i10", "sym_num" : 1, "page_instance" : "I10", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page4" } ], "is_cap" : 1, "ohm_resistance" : null, "do_not_install" : 0, "description" : "CAP,X5R,0402,4V,4.7UF,Bulk Ceramic" }, "R2_CPLD" : { "do_not_install" : 0, "description" : "RES,MF,0402,10K,50V,1/16W,1%,100ppm,Metal Film", "voltage" : "50", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "R2_CPLD.2", "R2_CPLD.1" ], "marker_data" : [ { "remapped_page" : null, "phys_path" : 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"top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i65" } ], "is_cap" : null, "ohm_resistance" : "0", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF" }, "R29_FL_XF" : { "do_not_pop" : 0, "voltage" : "50", "node_list" : [ "R29_FL_XF.1", "R29_FL_XF.2" ], "is_polar_cap" : null, "part_number" : "400-000010-006", "value" : "511", "refdes" : "R29_FL_XF", "marker_data" : [ { "page_instance" : "I26", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i26", "sym_num" : 1, "phys_page" : "page5", "page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_path" : 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"marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i171", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I171", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10" } ], "is_cap" : 1, "ohm_resistance" : null, "value" : ".22UF", "part_number" : "402-000010-001", "refdes" : "C222_XF", "part_type" : "CAPACITOR", "voltage" : "6.3", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C222_XF.1", "C222_XF.2" ] }, "R52_FL_XF" : { "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R52_FL_XF.2", "R52_FL_XF.1" ], "is_polar_cap" : null, "is_cap" : null, "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page6", "path" : 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"phys_page" : "page14", "page" : "page14", "block" : "top/xc2_fpga_blk" } ], "is_cap" : null, "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film" }, "R58_SP_XF" : { "description" : "RES,MF,0402,4.99K,25V,1/16W,0.5%,100ppm,Metal Film", "do_not_install" : 0, "ohm_resistance" : "4990", "is_cap" : null, "marker_data" : [ { "page_instance" : "I43", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i43", "sym_num" : 1, "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7" } ], "refdes" : "R58_SP_XF", "part_number" : "400-000015-019", "value" : "4.99K", "part_type" : "RESISTOR", "voltage" : "25", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "R58_SP_XF.1", "R58_SP_XF.2" ] }, "C325_XF" : { "do_not_install" : 0, "description" : "CAP,X6S,0603,2.5V,47uF,Bulk Ceramic", "is_polar_cap" : null, "node_list" : [ "C325_XF.2", "C325_XF.1" ], "voltage" : "2.5", "do_not_pop" : 0, "part_type" : "CAPACITOR", "marker_data" : [ { "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "page_instance" : "I147", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i147", "sym_num" : 1 } ], "is_cap" : 1, "ohm_resistance" : null, "value" : "47UF", "part_number" : "402-000015-007", "refdes" : "C325_XF" }, "C62_FL_XF" : { "do_not_install" : 0, "description" : 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"is_polar_cap" : null, "node_list" : [ "Q5.2", "Q5.3", "Q5.1" ] }, "R179_XF" : { "is_polar_cap" : null, "node_list" : [ "R179_XF.1", "R179_XF.2" ], "voltage" : "50", "do_not_pop" : 0, "part_type" : "RESISTOR", "is_cap" : null, "marker_data" : [ { "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "page_instance" : "I255", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i255", "sym_num" : 1 } ], "ohm_resistance" : "1000", "value" : "1K", "part_number" : "400-000010-010", "refdes" : "R179_XF", "do_not_install" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film" }, "R42_SP_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF", "is_polar_cap" : null, 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], "is_cap" : null, "ohm_resistance" : null, "part_number" : "450-000057-001", "value" : null, "refdes" : "U6_FL_XF", "is_polar_cap" : null, "node_list" : [ "U6_FL_XF.4", "U6_FL_XF.9", "U6_FL_XF.10", "U6_FL_XF.11", "U6_FL_XF.12", "U6_FL_XF.13", "U6_FL_XF.14", "U6_FL_XF.20", "U6_FL_XF.26", "U6_FL_XF.29", "U6_FL_XF.27", "U6_FL_XF.15", "U6_FL_XF.16", "U6_FL_XF.17", "U6_FL_XF.18", "U6_FL_XF.5", "U6_FL_XF.6", "U6_FL_XF.7", "U6_FL_XF.8", "U6_FL_XF.3", "U6_FL_XF.28", "U6_FL_XF.21", "U6_FL_XF.22", "U6_FL_XF.2", "U6_FL_XF.23", "U6_FL_XF.24", "U6_FL_XF.25", "U6_FL_XF.1", "U6_FL_XF.19" ], "voltage" : "1.8", "do_not_pop" : 0, "description" : "IC,LinReg,CMOS,0.8-1.8V,29Pin QFN-28,5A,VID LDO,Active High Enable ", "do_not_install" : 0 }, "R84_FL_XF" : { "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF", "do_not_install" : 0, "part_type" : "RESISTOR", "ohm_resistance" : "0", "is_cap" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : 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"part_number" : "400-000010-010", "value" : "1K", "refdes" : "R47_SP_XF", "is_polar_cap" : null, "node_list" : [ "R47_SP_XF.2", "R47_SP_XF.1" ], "voltage" : "50", "do_not_pop" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "R66_ND_XF" : { "description" : "RES,MF,0402,10K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "part_type" : "RESISTOR", "refdes" : "R66_ND_XF", "value" : "10K", "part_number" : "400-000010-074", "ohm_resistance" : "10000", "is_cap" : null, "marker_data" : [ { "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4", "page_instance" : "I17", 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"ppath" : "top/page12_i11", "sym_num" : 1, "phys_page" : "page12", "block" : "top", "page" : "page12", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page12", "path" : "@top_lib.top(sch_1):page12" } ], "is_cap" : null, "refdes" : "R19", "value" : "8.66K", "part_number" : "400-000010-046", "node_list" : [ "R19.2", "R19.1" ], "is_polar_cap" : null, "voltage" : "50", "do_not_pop" : 0 }, "C158_XF" : { "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "do_not_install" : 0, "part_type" : "CAPACITOR", "ohm_resistance" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i178", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I178", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page6", "phys_page" : "page6" } ], "is_cap" : 1, "refdes" : "C158_XF", "part_number" : "402-000010-001", "value" : ".22UF", "node_list" : [ "C158_XF.1", "C158_XF.2" ], "is_polar_cap" : null, "voltage" : "6.3", "do_not_pop" : 0 }, "R8_CPLD" : { "do_not_install" : 0, "description" : "RES,MF,0402,10K,50V,1/16W,1%,100ppm,Metal Film", "do_not_pop" : 0, "voltage" : "50", "node_list" : [ "R8_CPLD.1", "R8_CPLD.2" ], "is_polar_cap" : null, "refdes" : "R8_CPLD", "part_number" : "400-000010-074", "value" : "10K", "ohm_resistance" : "10000", "marker_data" : [ { "page_instance" : "I105", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "ppath" : "top/page14_i1/cpld_blk/page4_i105", "sym_num" : 1, "phys_page" : "page4", "block" : "top/cpld_blk", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4" } ], "is_cap" : null, "part_type" : "RESISTOR" }, "J1_E2_XF" : { "node_list" : [ "J1_E2_XF.B14", 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"400-000010-010", "value" : "1K", "refdes" : "R18_E3_XF", "part_type" : "RESISTOR", "voltage" : "50", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "R18_E3_XF.1", "R18_E3_XF.2" ] }, "C243_XF" : { "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I25", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i25" } ], "refdes" : "C243_XF", "part_number" : "402-000015-005", "value" : "330UF", "part_type" : "CAPACITOR", "voltage" : "2.5", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C243_XF.2", "C243_XF.1" ], "description" : "CAP,X6S,1210,2.5V,330uF,Bulk Ceramic", "do_not_install" : 0 }, "R43_XF" : { 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"page" : "page17", "block" : "top/xc2_fpga_blk", "phys_page" : "page17", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i188", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I188" } ], "ohm_resistance" : "75", "is_polar_cap" : null, "node_list" : [ "R118_XF.1", "R118_XF.2" ], "do_not_pop" : 0, "voltage" : "50" }, "M8" : { "description" : "RING PATTERN 3.81MM", "do_not_install" : 0, "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page1", "path" : "@top_lib.top(sch_1):page1", "remapped_page" : null, "block" : "top", "page" : "page1", "phys_page" : "page1", "sym_num" : 1, "ppath" : "top/page1_i62", "ppath_without_last_instance" : "top/page1", "page_instance" : "I62" } ], "is_cap" : null, "ohm_resistance" : null, "part_number" : "HOLE_RING", "value" : null, "refdes" : "M8", "part_type" : "", "voltage" : "", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "M8.MTG2", "M8.MTG3", "M8.MTG4", "M8.MTG5" ] }, "C4" : { "description" : "CAP,X5R,0402,16V,1UF,Bulk Ceramic", "do_not_install" : 0, "part_number" : "402-000010-026", "value" : "1UF", "refdes" : "C4", "is_cap" : 1, "marker_data" : [ { "page_instance" : "I119", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i119", "sym_num" : 1, "phys_page" : "page10", "page" : "page10", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10" } ], "ohm_resistance" : null, "part_type" : "CAPACITOR", "do_not_pop" : 0, "voltage" : "16", "is_polar_cap" : null, "node_list" : [ "C4.1", "C4.2" ] }, "C254_XF" : { "voltage" : "6.3", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C254_XF.1", "C254_XF.2" ], "marker_data" : [ { "page" : "page14", "block" : "top/xc2_fpga_blk", "phys_page" : "page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : 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"phys_path" : "@top_lib.top(sch_1):page4", "path" : "@top_lib.top(sch_1):page4", "page_instance" : "I152", "ppath_without_last_instance" : "top/page4", "ppath" : "top/page4_i152", "sym_num" : 1 } ] }, "R9" : { "description" : "RES,MF,0402,8.66K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "marker_data" : [ { "block" : "top", "page" : "page12", "phys_page" : "page12", "phys_path" : "@top_lib.top(sch_1):page12", "path" : "@top_lib.top(sch_1):page12", "remapped_page" : null, "ppath_without_last_instance" : "top/page12", "page_instance" : "I3", "sym_num" : 1, "ppath" : "top/page12_i3" } ], "is_cap" : null, "ohm_resistance" : "8660", "part_number" : "400-000010-046", "value" : "8.66K", "refdes" : "R9", "part_type" : "RESISTOR", "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R9.2", "R9.1" ], "is_polar_cap" : null }, "C3_E0_XF" : { "is_polar_cap" : null, "node_list" : [ "C3_E0_XF.1", "C3_E0_XF.2" ], "do_not_pop" : 0, "voltage" : "6.3", "part_type" : "CAPACITOR", "refdes" : "C3_E0_XF", "part_number" : "402-000010-011", "value" : "4.7UF", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "page_instance" : "I22", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i22", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4" } ], "do_not_install" : 0, "description" : "CAP,X5R,0603,6.3V,4.7UF,Bulk Ceramic" }, "R41" : { "do_not_pop" : 0, "voltage" : "50", "is_polar_cap" : null, "node_list" : [ "R41.1", "R41.2" ], "refdes" : "R41", "value" : "27.4", "part_number" : "400-000010-002", "ohm_resistance" : "27.4", "marker_data" : [ { "page" : "page15", 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"@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null } ], "ohm_resistance" : null, "do_not_install" : 0, "description" : "CAP,X5R,0402,4V,4.7UF,Bulk Ceramic" }, "R76_SP_XF" : { "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R76_SP_XF.1", "R76_SP_XF.2" ], "is_polar_cap" : null, "is_cap" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i434", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I434", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "phys_page" : "page6" } ], "ohm_resistance" : "0", "value" : "0OHM", "part_number" : "400-000014-011", "refdes" : "R76_SP_XF", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,0Ohm,50V,1.5A,5%,100ppm,Metal Film LF" }, "C70_SP_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,1206,6.3V,100UF,Bulk Ceramic 1.6mm Thk", "is_polar_cap" : null, "node_list" : [ "C70_SP_XF.2", "C70_SP_XF.1" ], "voltage" : "6.3", "do_not_pop" : 0, "part_type" : "CAPACITOR", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "page_instance" : "I121", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i121", "sym_num" : 1 } ], "is_cap" : 1, "ohm_resistance" : null, "value" : "100UF", "part_number" : "402-000010-033", "refdes" : "C70_SP_XF" }, "R234_XF" : { "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R234_XF.2", "R234_XF.1" ], "is_polar_cap" : null, "ohm_resistance" : "4640", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2156", "sym_num" : 1, "page_instance" : "I2156", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk" } ], "is_cap" : null, "refdes" : "R234_XF", "value" : "4.64K", "part_number" : "400-000010-007", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,4.64K,50V,1/16W,1%,100ppm,Metal Film" }, "C32_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_pop" : 0, "voltage" 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: null }, "R44_SP_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,27.4,50V,1/16W,1%,100ppm,Metal Film", "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R44_SP_XF.1", "R44_SP_XF.2" ], "is_polar_cap" : null, "is_cap" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i126", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I126", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3" } ], "ohm_resistance" : "27.4", "part_number" : "400-000010-002", "value" : "27.4", "refdes" : "R44_SP_XF", "part_type" : "RESISTOR" }, "C36_ND_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0603,4V,10UF,Bulk Ceramic", "node_list" : [ "C36_ND_XF.2", "C36_ND_XF.1" ], "is_polar_cap" : null, "voltage" : "4", "do_not_pop" : 0, "part_type" : "CAPACITOR", "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4_i10", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4", "page_instance" : "I10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page4" } ], "ohm_resistance" : null, "value" : "10UF", "part_number" : "402-000010-027", "refdes" : "C36_ND_XF" }, "C7_FL_XF" : { "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3", "page_instance" : "I35", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3_i35", "page" : "page3", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "remapped_page" : null } ], "refdes" : "C7_FL_XF", "value" : "4.7UF", "part_number" : "402-000010-011", "part_type" : "CAPACITOR", "voltage" : "6.3", "do_not_pop" : 0, "node_list" : [ "C7_FL_XF.2", "C7_FL_XF.1" ], "is_polar_cap" : null, "description" : "CAP,X5R,0603,6.3V,4.7UF,Bulk Ceramic", "do_not_install" : 0 }, "R8_E1_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,4.64K,50V,1/16W,1%,100ppm,Metal Film", "node_list" : [ "R8_E1_XF.2", "R8_E1_XF.1" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50", "part_type" : "RESISTOR", "refdes" : "R8_E1_XF", "part_number" : "400-000010-007", "value" : "4.64K", "ohm_resistance" : "4640", "marker_data" : [ { "page_instance" : "I85", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i85", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3" } ], "is_cap" : null }, "NS2_SP_XF" : { "is_polar_cap" : null, "node_list" : [ "NS2_SP_XF.2", "NS2_SP_XF.1" ], "voltage" : "", "do_not_pop" : 0, "part_type" : "", "is_cap" : null, "marker_data" : [ { "path" : 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"page_instance" : "I64", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i64", "sym_num" : 1, "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23" } ], "is_cap" : 1, "ohm_resistance" : null, "part_number" : "402-000015-007", "value" : "47UF", "refdes" : "C380_XF" }, "R12_E0_XF" : { "description" : "RES,MF,0402,511,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "ohm_resistance" : "511", "is_cap" : null, "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "page" : 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7", "page_instance" : "I26", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7_i26" } ], "ohm_resistance" : "511", "part_number" : "400-000010-006", "value" : "511", "refdes" : "R37_FL_XF", "is_polar_cap" : null, "node_list" : [ "R37_FL_XF.1", "R37_FL_XF.2" ], "voltage" : "50", "do_not_pop" : 0, "description" : "RES,MF,0402,511,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "R246_XF" : { "do_not_install" : 0, "description" : "RES,MF,0402,49.9,50V,1/16W,1%,100ppm,Metal Film", "is_polar_cap" : null, "node_list" : [ "R246_XF.1", "R246_XF.2" ], "do_not_pop" : 0, "voltage" : "50", "part_type" : "RESISTOR", "refdes" : "R246_XF", "value" : "49.9", "part_number" : "400-000010-003", "ohm_resistance" : "49.9", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk", "phys_page" : "page6", "path" : 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1 } ], "is_cap" : null, "ohm_resistance" : "240", "value" : "240", "part_number" : "400-000010-090", "refdes" : "R160_XF", "part_type" : "RESISTOR" }, "C328_XF" : { "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0, "is_cap" : 1, "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i87", "sym_num" : 1, "page_instance" : "I87", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_page" : "page13", "page" : "page13", "block" : "top/xc2_fpga_blk" } ], "ohm_resistance" : null, "part_number" : "402-000010-035", "value" : "0.22UF", "refdes" : "C328_XF", "part_type" : "CAPACITOR", "voltage" : "6.3", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C328_XF.1", "C328_XF.2" ] }, "R1_FL_XF" : { "is_polar_cap" : null, "node_list" : [ "R1_FL_XF.1", "R1_FL_XF.2" ], "voltage" : "50", "do_not_pop" : 0, "part_type" : "RESISTOR", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null, "page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page5", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i4", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I4" } ], "is_cap" : null, "ohm_resistance" : "1000", "part_number" : "400-000010-010", "value" : "1K", "refdes" : "R1_FL_XF", "do_not_install" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film" }, "R10_SP_XF" : { "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "R10_SP_XF.2", "R10_SP_XF.1" ], "is_polar_cap" : null, "is_cap" : null, "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "phys_page" : "page10", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i8", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I8" } ], "ohm_resistance" : "3240", "value" : "3.24K", "part_number" : "400-000010-136", "refdes" : "R10_SP_XF", "part_type" : "RESISTOR", "do_not_install" : 0, "description" : "RES,MF,0402,3.24K,50V,1/16W,1%,100ppm,Metal Film" }, "C52_CPLD" : { "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "is_polar_cap" : null, "node_list" : [ "C52_CPLD.2", "C52_CPLD.1" ], "voltage" : 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"node_list" : [ "C54_XF.2", "C54_XF.1" ], "do_not_pop" : 0, "voltage" : "6.3", "description" : "CAP,X6S,0402,6.3V,10uF,Bulk Ceramic", "do_not_install" : 0 }, "C37_XF" : { "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "do_not_install" : 0, "part_type" : "CAPACITOR", "value" : "0.22UF", "part_number" : "402-000010-035", "refdes" : "C37_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page11", "phys_page" : "page11", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i627", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I627" } ], "is_cap" : 1, "ohm_resistance" : null, "is_polar_cap" : null, "node_list" : [ "C37_XF.1", "C37_XF.2" ], "do_not_pop" : 0, "voltage" : "6.3" }, "C16_SP_XF" : { "voltage" : "50", "do_not_pop" : 0, "node_list" : [ "C16_SP_XF.2", "C16_SP_XF.1" ], "is_polar_cap" : null, "is_cap" : 1, "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i153", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I153" } ], "ohm_resistance" : null, "value" : "2200PF", "part_number" : "402-000010-006", "refdes" : "C16_SP_XF", "part_type" : "CAPACITOR", "do_not_install" : 0, "description" : "CAP,X5R,0402,50V,2200pF,Bulk Ceramic" }, "C215_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0402,6.3V,.22uF,Hi-freq Decoupling", "is_polar_cap" : null, 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"C426_XF" : { "refdes" : "C426_XF", "value" : "4.7UF", "part_number" : "402-000010-028", "ohm_resistance" : null, "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I162", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i162" } ], "is_cap" : 1, "part_type" : "CAPACITOR", "do_not_pop" : 0, "voltage" : "4", "is_polar_cap" : null, "node_list" : [ "C426_XF.1", "C426_XF.2" ], "description" : "CAP,X5R,0402,4V,4.7UF,Bulk Ceramic", "do_not_install" : 0 }, "R123_XF" : { "refdes" : "R123_XF", "part_number" : "400-000010-137", "value" : "4.22K", "ohm_resistance" : "4220", "is_cap" : null, "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27", 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}, "TP11_CPLD" : { "do_not_pop" : 0, "voltage" : "", "is_polar_cap" : null, "node_list" : [ "TP11_CPLD.1" ], "refdes" : "TP11_CPLD", "part_number" : "SM_050_TP", "value" : null, "ohm_resistance" : null, "is_cap" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page7_i153", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I153", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7" } ], "part_type" : "CONNECTOR", "do_not_install" : 0, "description" : "SM_050_TP-SM_050_TP" }, "C28_FL_XF" : { "description" : "CAP,X5R,1206,10V,47UF,Bulk Ceramic 1.6mm Thk", "do_not_install" : 0, "is_cap" : 1, "marker_data" : [ { "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page7", "phys_page" : "page7", "phys_path" : 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"450-000020-002", "value" : null, "refdes" : "U9_XF", "is_cap" : null, "marker_data" : [ { "page" : "page17", "block" : "top/xc2_fpga_blk", "phys_page" : "page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I16", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i16" } ], "ohm_resistance" : null, "part_type" : "IC", "do_not_pop" : 0, "voltage" : "1.25", "node_list" : [ "U9_XF.5", "U9_XF.1", "U9_XF.2", "U9_XF.3", "U9_XF.4" ], "is_polar_cap" : null, "description" : "IC,VREF,1.25V Ref, SOT23-5,15mA,0.5%", "do_not_install" : 0 }, "C134_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0201,6.3V,0.22uF,Hi-freq Decoupling", "node_list" : [ "C134_XF.1", "C134_XF.2" ], "is_polar_cap" : null, "voltage" : "6.3", "do_not_pop" : 0, "part_type" : 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0 }, "C18" : { "node_list" : [ "C18.2", "C18.1" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "16", "part_type" : "CAPACITOR", "refdes" : "C18", "value" : "1UF", "part_number" : "402-000010-026", "ohm_resistance" : null, "is_cap" : 1, "marker_data" : [ { "phys_page" : "page10", "page" : "page10", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "page_instance" : "I130", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i130", "sym_num" : 1 } ], "do_not_install" : 0, "description" : "CAP,X5R,0402,16V,1UF,Bulk Ceramic" }, "C399_XF" : { "do_not_install" : 0, "description" : "CAP,X5R,0402,4V,4.7UF,Bulk Ceramic", "voltage" : "4", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "C399_XF.1", "C399_XF.2" ], "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i158", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : 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"node_list" : [ "C52_SD_XF.2", "C52_SD_XF.1" ], "is_polar_cap" : null, "description" : "CAP,X5R,1206,6.3V,100UF,Bulk Ceramic 1.6mm Thk", "do_not_install" : 0 }, "C308_XF" : { "description" : "CAP,X6S,0402,6.3V,10uF,Bulk Ceramic", "do_not_install" : 0, "part_type" : "CAPACITOR", "part_number" : "402-000015-008", "value" : "10UF", "refdes" : "C308_XF", "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i57", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I57", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23" } ], "ohm_resistance" : null, "is_polar_cap" : null, "node_list" : [ "C308_XF.1", "C308_XF.2" ], "do_not_pop" : 0, "voltage" : "6.3" }, "C191_SP_XF" : { "description" : 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"do_not_install" : 0, "description" : "CAP,ALUM_CP,7343,16V,68uf,AlumOrgPoly,0.040 OHM ESR" }, "R151_XF" : { "part_type" : "RESISTOR", "is_cap" : null, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2424", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "page_instance" : "I2424", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "remapped_page" : null, "page" : "page5", "block" : "top/xc2_fpga_blk", "phys_page" : "page5" } ], "ohm_resistance" : "1000", "value" : "1K", "part_number" : "400-000010-010", "refdes" : "R151_XF", "node_list" : [ "R151_XF.2", "R151_XF.1" ], "is_polar_cap" : null, "voltage" : "50", "do_not_pop" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "R98_XF" : { "node_list" : [ "R98_XF.2", "R98_XF.1" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50", "part_type" : "RESISTOR", "refdes" : "R98_XF", "part_number" : "400-000010-010", "value" : "1K", "ohm_resistance" : "1000", "is_cap" : null, "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i62", "sym_num" : 1, "page_instance" : "I62", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_page" : "page17", "block" : "top/xc2_fpga_blk", "page" : "page17" } ], "do_not_install" : 0, "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film" }, "R10_E0_XF" : { "do_not_pop" : 0, "voltage" : "50", "node_list" : [ "R10_E0_XF.1", "R10_E0_XF.2" ], "is_polar_cap" : null, "value" : "511", "part_number" : "400-000010-006", "refdes" : "R10_E0_XF", "is_cap" : null, "marker_data" : [ { "page_instance" : "I34", "ppath_without_last_instance" : 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"refdes" : "R200_XF", "value" : "1K", "part_number" : "400-000010-010" }, "R78" : { "do_not_install" : 0, "description" : "RES,MF,0402,511,50V,1/16W,1%,100ppm,Metal Film", "voltage" : "50", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "R78.2", "R78.1" ], "is_cap" : null, "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page3", "path" : "@top_lib.top(sch_1):page3", "remapped_page" : null, "block" : "top", "page" : "page3", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page3_i71", "ppath_without_last_instance" : "top/page3", "page_instance" : "I71" } ], "ohm_resistance" : "511", "part_number" : "400-000010-006", "value" : "511", "refdes" : "R78", "part_type" : "RESISTOR" }, "C249_XF" : { "node_list" : [ "C249_XF.2", "C249_XF.1" ], "is_polar_cap" : null, "voltage" : "6.3", "do_not_pop" : 0, "part_type" : "CAPACITOR", "is_cap" : 1, "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i41", "ppath_without_last_instance" : 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"phys_page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4" } ], "part_type" : "CAPACITOR" }, "R101_FL_XF" : { "part_type" : "RESISTOR", "refdes" : "R101_FL_XF", "value" : "1K", "part_number" : "400-000010-010", "ohm_resistance" : "1000", "marker_data" : [ { "page_instance" : "I15", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i15", "sym_num" : 1, "phys_page" : "page11", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page12", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12" } ], "is_cap" : null, "node_list" : [ "R101_FL_XF.1", "R101_FL_XF.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50", "description" : "RES,MF,0402,1K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0 }, "R19_CPLD" : { "description" : "RES,MF,0402,27.4,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "ohm_resistance" : "27.4", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page8_i29", "sym_num" : 1, "page_instance" : "I29", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page8", "phys_page" : "page8", "block" : "top/cpld_blk", "page" : "page8" } ], "is_cap" : null, "refdes" : "R19_CPLD", "part_number" : "400-000010-002", "value" : "27.4", "part_type" : "RESISTOR", "voltage" : "50", "do_not_pop" : 0, "is_polar_cap" : null, "node_list" : [ "R19_CPLD.2", "R19_CPLD.1" ] }, "R26_SP_XF" : { "node_list" : [ "R26_SP_XF.2", "R26_SP_XF.1" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "50", "part_type" : "RESISTOR", "value" : "90.9K", "part_number" : "400-000011-010", "refdes" : "R26_SP_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I36", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i36", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null } ], "is_cap" : null, "ohm_resistance" : "90900", "do_not_install" : 0, "description" : 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"value" : "511", "refdes" : "R12_E1_XF" }, "C307_XF" : { "do_not_install" : 0, "description" : "CAP,X6S,0402,6.3V,10uF,Bulk Ceramic", "node_list" : [ "C307_XF.1", "C307_XF.2" ], "is_polar_cap" : null, "do_not_pop" : 0, "voltage" : "6.3", "part_type" : "CAPACITOR", "refdes" : "C307_XF", "part_number" : "402-000015-008", "value" : "10UF", "ohm_resistance" : null, "marker_data" : [ { "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "page_instance" : "I58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i58", "sym_num" : 1 } ], "is_cap" : 1 }, "R30_FL_XF" : { "description" : "RES,MF,0402,10K,50V,1/16W,1%,100ppm,Metal Film", "do_not_install" : 0, "part_number" : "400-000010-074", "value" : "10K", "refdes" : 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"pin_type" : "INOUT", "pin_number" : "AJ61", "pin_name_unsanitized" : "IO_L17P_T2U_N8_AD10P_28", "pin_group" : "ALL_SIGNAL_PINS_18;", "refdes" : "U1_XF", "pin_name" : "IO_L17P_T2U_N8_AD10P_28", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 18, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I51", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30" } ] }, "U1_XF.AR14" : { "pin_group" : "ALL_SIGNAL_PINS_13;", "pin_name_unsanitized" : "MGTREFCLK1N_228", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i57", "sym_num" : 13, "page_instance" : "I57", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "remapped_page" : null, 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"1;", "pin_name" : "B", "refdes" : "C49_FL_XF", "net_name" : "GND", "part_number" : "402-000010-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8_i35", "sym_num" : 1, "page_instance" : "I35", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "phys_page" : "page8", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page8" } ] }, "R83.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R83.2", "marker_data" : [ { "page_instance" : "I70", "ppath_without_last_instance" : "top/page20", "ppath" : "top/page20_i70", "sym_num" : 1, "phys_page" : "page20", "page" : "page20", "block" : "top", "remapped_page" : null, "path" : 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"pin_name" : "VSS_36", "refdes" : "J1_XF", "part_number" : "410-000300-001", "marker_data" : [ { "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180" } ], "pin_name_unsanitized" : "VSS_36", "pinuse" : "UNSPEC;", "pin_number" : "50", "pin_type" : "GROUND", "node_name" : "J1_XF.50" }, "J2_P0_XF.B19" : { "pin_number" : "B19", "pin_type" : "INPUT", "node_name" : "J2_P0_XF.B19", "net_name" : "PCIE0_TXN<7>_XF", "pin_name" : "PETN3", "refdes" : "J2_P0_XF", "part_number" : "410-000324-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i85", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3", "page_instance" : "I85", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "phys_page" : "page3" } ], "pin_name_unsanitized" : "PETN3", "pinuse" : "IN;" }, "U1_XF.AG46" : { "refdes" : "U1_XF", "pin_name" : "IO_L24N_T3U_N11_30", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53", "sym_num" : 23, "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" 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: "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i71", "sym_num" : 1, "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23" } ], "refdes" : "C382_XF", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000015-007", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C382_XF.2" }, "U1_CPLD.M11" : { "pin_type" : "INOUT", "pin_number" : "M11", "node_name" : "U1_CPLD.M11", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page4_i211", "sym_num" : 3, "page_instance" : "I211", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "path" : 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"refdes" : "PM2_SP_XF", "pin_name" : "VOUT3_11", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I456", "sym_num" : 4, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i456" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT3_11", "pin_number" : "T3", "node_name" : "PM2_SP_XF.T3" }, "C271_XF.1" : { "net_name" : "AC_OCL1_PET_N<2>_XF", "pin_name" : "A", "refdes" : "C271_XF", "part_number" : "402-000010-035", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I136", "sym_num" : 1, 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"pinuse" : "UNSPEC;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "remapped_page" : null, "page" : "page22", "block" : "top/xc2_fpga_blk", "phys_page" : "page22", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "page_instance" : "I46" } ], "pin_name" : "B", "net_name" : "UNNAMED_22_RESISTOR_I46_B_XF", "refdes" : "R59_XF", "part_number" : "400-000010-090", "node_name" : "R59_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "R136_XF.1" : { "node_name" : "R136_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i105", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I105", 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"U1_XF.AG50" : { "node_name" : "U1_XF.AG50", "pin_type" : "INOUT", "pin_number" : "AG50", "pin_group" : "ALL_SIGNAL_PINS_23;", "pin_name_unsanitized" : "IO_L14P_T2L_N2_GC_30", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I53", "sym_num" : 23, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53" } ], "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L14P_T2L_N2_GC_30", "refdes" : "U1_XF" }, "U1_SP_XF.55" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I168", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i168", "page" : "page3", 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"node_name" : "U1_XF.AK26" }, "C473_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-028", "refdes" : "C473_XF", "pin_name" : "B", "net_name" : "GND", "marker_data" : [ { "page" : "page20", "block" : "top/xc2_fpga_blk", "phys_page" : "page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I25", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i25" } ], "node_name" : "C473_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_XF.BP35" : { "node_name" : "U1_XF.BP35", "pin_number" : "BP35", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_20;", "pin_name_unsanitized" : "IO_L8P_T1L_N2_AD5P_67", "marker_data" : [ { "sym_num" : 20, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", 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"part_number" : "450-000340-001", "pin_name" : "C0_DDR4_DQS_C13", "net_name" : "C0_RDIMM_DQS_C<15>_XF", "refdes" : "U1_XF" }, "J2_XF.49" : { "pin_name_unsanitized" : "CB0", "pinuse" : "TRI;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/xc2_fpga_blk", "phys_page" : "page6", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180" } ], "pin_name" : "CB0", "refdes" : "J2_XF", "net_name" : "C1_DDR4_DQ<64>_XF", "part_number" : "410-000300-001", "node_name" : "J2_XF.49", "pin_type" : "INOUT", "pin_number" : "49" }, "U1_XF.K52" : { "pin_group" : "C2_UNIB_1_6_57;", "pin_name_unsanitized" : "C2_DDR4_DQ28", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", 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null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "phys_page" : "page3" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C14_SP_XF.1" }, "U1_XF.T62" : { "pin_type" : "INOUT", "pin_number" : "T62", "node_name" : "U1_XF.T62", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "sym_num" : 22, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I46" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L6N_T0U_N11_AD6N_33", "net_name" : "NC", "pin_group" : "ALL_SIGNAL_PINS_22;", "pin_name_unsanitized" : "IO_L6N_T0U_N11_AD6N_33" }, "J1_PX1_XF.A15" : { "node_name" : "J1_PX1_XF.A15", "pin_number" : "A15", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_6", "marker_data" : [ { "block" : "top/xc2_fpga_blk/pcie_x1_conn_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i73@top_lib.pcie_x1_conn_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i73@top_lib.pcie_x1_conn_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i73/pcie_x1_conn_blk/page3", "page_instance" : "I14", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i73/pcie_x1_conn_blk/page3_i14" } ], "part_number" : "410-000328-001", "net_name" : "GND", "refdes" : "J1_PX1_XF", "pin_name" : "GND_6" }, "U1_E1_XF.5" : { "node_name" : "U1_E1_XF.5", "pin_type" : "INPUT", "pin_number" : "5", "pinuse" : "IN;", "pin_name_unsanitized" : "CLKIN_P", "part_number" : "450-000345-001", "pin_name" : "CLKIN_P", "net_name" : "CLKIN_P_E1", "refdes" : "U1_E1_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "page_instance" : "I37" } ] }, "U1_XF.BC50" : { "node_name" : "U1_XF.BC50", "pin_type" : "INOUT", "pin_number" : "BC50", "pin_name_unsanitized" : "GND_777", "pin_group" : "ALL_POWER_PINS_36;", "refdes" : "U1_XF", "pin_name" : "GND_777", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I71", "sym_num" : 36, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ] }, "C81_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C81_XF.1", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I152", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i152" } ], "part_number" : "402-000015-007", "net_name" : "PWR_VCCINT_XF", "pin_name" : "A", "refdes" : "C81_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "PM1_SP_XF.L4" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT2_7", "marker_data" : [ { "page_instance" : "I39", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i39", "sym_num" : 3, "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7" } ], "part_number" : "462-000309-001", "refdes" : "PM1_SP_XF", "net_name" : "PWR_SDIMM_VPP_XF", "pin_name" : "VOUT2_7", "node_name" : "PM1_SP_XF.L4", "pin_number" : "L4" }, "U1_XF.AV8" : { "pin_group" : "ALL_SIGNAL_PINS_3;", "pin_name_unsanitized" : "PCIE0_TXN1", "marker_data" : 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"path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I283", "sym_num" : 9, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283" } ], "node_name" : "U1_XF.G5", "pin_number" : "G5", "pin_type" : "INOUT" }, "R119_SP_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R119_SP_XF.1", "part_number" : "400-000010-074", "pin_name" : "A", "refdes" : "R119_SP_XF", "net_name" : "P3R3V", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i101", "sym_num" : 1, "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : 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"part_number" : "410-000317-001", "pin_name" : "PERP4", "net_name" : "E1S0_PER_P<4>_XF", "refdes" : "J1_E0_XF" }, "C8_CPLD.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "CPLD_P1R8V_1", "refdes" : "C8_CPLD", "part_number" : "402-000010-001", "marker_data" : [ { "page_instance" : "I111", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "ppath" : "top/page14_i1/cpld_blk/page7_i111", "sym_num" : 1, "phys_page" : "page7", "page" : "page7", "block" : "top/cpld_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7" } ], "node_name" : "C8_CPLD.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_XF.BN6" : { "pin_name_unsanitized" : "MGTYRXP2_221", "pin_group" : "ALL_SIGNAL_PINS_14;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "MGTYRXP2_221", "net_name" : "NC", "marker_data" : [ { "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "page_instance" : "I56", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i56", "sym_num" : 14 } ], "node_name" : "U1_XF.BN6", "pin_number" : "BN6", "pin_type" : "INOUT" }, "J2_XF.217" : { "pin_type" : "POWER", "pin_number" : "217", "node_name" : "J2_XF.217", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180" } ], "refdes" : "J2_XF", "pin_name" : "VDD_2", "net_name" : "PWR_SDIMM_VDD_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VDD_2", "pinuse" : "POWER;" }, "U1_XF.AE30" : { "node_name" : "U1_XF.AE30", "pin_number" : "AE30", "pin_type" : "INOUT", "pin_name_unsanitized" : "VCCINT_91", "pin_group" : "ALL_POWER_PINS_31;", "net_name" : "PWR_VCCINT_XF", "pin_name" : "VCCINT_91", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 31, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I186", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23" } ] }, "U1_XF.C58" : { "node_name" : "U1_XF.C58", "pin_type" : "INOUT", "pin_number" : "C58", "pin_name_unsanitized" : "C2_DDR4_DQ66", "pin_group" : "C2_LNIB_1_6_57;", "part_number" : "450-000340-001", "pin_name" : "C2_DDR4_DQ66", "refdes" : "U1_XF", "net_name" : "C2_DDR4_DQ<66>_XF", "marker_data" : [ { "phys_page" : "PAGE7", "block" : "top/xc2_fpga_blk", "page" : "PAGE7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425", "sym_num" : 65 } ] }, "U1_XF.F51" : { "node_name" : "U1_XF.F51", "pin_type" : "INOUT", "pin_number" : "F51", "pin_group" : "ALL_SIGNAL_PINS_26;", "pin_name_unsanitized" : "IO_L6N_T0U_N11_AD6N_37", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "phys_path" : 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} ], "part_number" : "450-000340-001", "pin_name" : "IO_L7P_T1L_N0_QBC_AD13P_67", "net_name" : "NC", "refdes" : "U1_XF", "node_name" : "U1_XF.BP39", "pin_type" : "INOUT", "pin_number" : "BP39" }, "R5_MP.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page3", "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page3", "remapped_page" : null, "block" : "top/mgmt_pwr_block", "page" : "page3", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page18_i1/mgmt_pwr_block/page3_i15", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page3", "page_instance" : "I15" } ], "pin_name" : "A", "refdes" : "R5_MP", "net_name" : "UNNAMED_3_RESISTOR_I15_A_MP", "part_number" : "400-000010-075", "node_name" : "R5_MP.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_E1_XF.9" : { "part_number" : "450-000345-001", "pin_name" : "SCLK", "net_name" : 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"page10" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R112.1" }, "U1_XF.N14" : { "marker_data" : [ { "page_instance" : "I57", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i57", "sym_num" : 13, "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31" } ], "pin_name" : "MGTREFCLK1N_235", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_13;", "pin_name_unsanitized" : "MGTREFCLK1N_235", "pin_number" : "N14", "pin_type" : "INOUT", "node_name" : "U1_XF.N14" }, "C37_FL_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C37_FL_XF.1", "part_number" : "402-000050-015", "net_name" : "UNNAMED_8_LT3071_I30_VIOC_FL", "pin_name" : "A", "refdes" : "C37_FL_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8_i32", "sym_num" : 1, "page_instance" : "I32", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "phys_page" : "page8", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page8" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "C18_ND_XF.1" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I37", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i37" } ], "part_number" : "402-000010-033", "refdes" : "C18_ND_XF", "pin_name" : "A", "net_name" : "PWR_NDIMM_VDD_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C18_ND_XF.1" }, "C54_FL_XF.1" : { "node_name" : "C54_FL_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i18", "sym_num" : 1, "page_instance" : "I18", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page5" } ], "net_name" : "PWR_AVTT_RLC_XF", "pin_name" : "A", "refdes" : "C54_FL_XF", "part_number" : "402-000010-028" }, "R26_CPLD.2" : { "node_name" : "R26_CPLD.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "phys_page" : "page9", "page" : "page9", "block" : "top/cpld_blk", "ppath" : "top/page14_i1/cpld_blk/page9_i71", "sym_num" : 1, "page_instance" : "I71", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page9" } ], "part_number" : "400-000010-006", "refdes" : "R26_CPLD", "pin_name" : "B", "net_name" : "RGB_LED_BLUE<0>_CPLD" }, "C126_SP_XF.2" : { "marker_data" : [ { "phys_page" : "page8", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "page_instance" : "I93", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8_i93", "sym_num" : 1 } ], "pin_name" : "B", "net_name" : "GND", "refdes" : "C126_SP_XF", "part_number" : "402-000010-001", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C126_SP_XF.2" }, "J4_XF.135" : { "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10" } ], "part_number" : "410-000300-001", "pin_name" : "DQ62", "refdes" : "J4_XF", "net_name" : "C3_DDR4_DQ<62>_XF", "pinuse" : "TRI;", "pin_name_unsanitized" : "DQ62", "pin_number" : "135", "pin_type" : "INOUT", "node_name" : "J4_XF.135" }, "PM4_SP_XF.D4" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_8", "marker_data" : [ { "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "page_instance" : "I79", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page4" } ], "part_number" : "462-000308-002", "pin_name" : "GND_8", "net_name" : "GND", "refdes" : "PM4_SP_XF", "node_name" : "PM4_SP_XF.D4", "pin_number" : "D4", "pin_type" : "POWER" }, "U1_XF.BB36" : { "pin_name_unsanitized" : "GND_750", "pin_group" : "ALL_POWER_PINS_36;", "part_number" : "450-000340-001", "pin_name" : "GND_750", "refdes" : "U1_XF", "net_name" : "GND", "marker_data" : [ { "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "sym_num" : 36, "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "node_name" : "U1_XF.BB36", "pin_type" : "INOUT", "pin_number" : "BB36" }, "U1_XF.CA29" : { "node_name" : "U1_XF.CA29", "pin_type" : "INOUT", "pin_number" : "CA29", "pin_group" : "ALL_POWER_PINS_38;", "pin_name_unsanitized" : "GND_1055", "marker_data" : [ { "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I73", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73", "sym_num" : 38 } ], "refdes" : "U1_XF", "pin_name" : "GND_1055", "net_name" : "GND", "part_number" : "450-000340-001" }, "PM4_SP_XF.J11" : { "node_name" : "PM4_SP_XF.J11", "pin_number" : "J11", "pin_type" : "POWER", "pin_name_unsanitized" : "VIN_6", "pinuse" : "POWER;", "marker_data" : [ { "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i80", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4" } ], "pin_name" : "VIN_6", "net_name" : "P12V_4650_TL_SP", "refdes" : "PM4_SP_XF", "part_number" : "462-000308-002" }, "R16_SP_XF.1" : { "node_name" : "R16_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R16_SP_XF", "pin_name" : "A", "net_name" : "ENB3V_SEQ_A", "part_number" : "400-000014-011", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i143", "sym_num" : 1, "page_instance" : "I143", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ] }, "U1_XF.AC2" : { "pin_group" : "ALL_SIGNAL_PINS_10;", "pin_name_unsanitized" : "E1S2_PER_P6", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "page" : "page13", "block" : "top/xc2_fpga_blk", "phys_page" : "page13", "sym_num" : 10, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i251", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I251" } ], "part_number" : "450-000340-001", "net_name" : "E1S2_PER_P<6>_XF", "pin_name" : "E1S2_PER_P6", "refdes" : "U1_XF", "node_name" : "U1_XF.AC2", "pin_number" : "AC2", "pin_type" : "INOUT" }, "PM2_SP_XF.B11" : { "node_name" : "PM2_SP_XF.B11", "pin_number" : "B11", "pin_name_unsanitized" : "GND_27", "pinuse" : "GROUND;", "net_name" : "GND", "pin_name" : "GND_27", "refdes" : "PM2_SP_XF", "part_number" : "462-000309-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "sym_num" : 5, "page_instance" : "I459", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ] }, "C23.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19", "remapped_page" : null, "page" : "page19", "block" : "top", "phys_page" : "page19", "sym_num" : 1, "ppath" : "top/page19_i81", "ppath_without_last_instance" : "top/page19", "page_instance" : "I81" } ], "net_name" : "P12V_MAIN", "pin_name" : "A", "refdes" : "C23", "part_number" : "402-000500-005", "node_name" : "C23.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "C316_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", 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"U1_XF.BH51" : { "pin_type" : "INOUT", "pin_number" : "BH51", "node_name" : "U1_XF.BH51", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20, "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30" } ], "refdes" : "U1_XF", "pin_name" : "IO_L9P_T1L_N4_AD12P_24", "net_name" : "NC", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_20;", "pin_name_unsanitized" : "IO_L9P_T1L_N4_AD12P_24" }, "R61_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "refdes" : "R61_XF", "net_name" : "GND", "part_number" : "400-000010-006", "marker_data" : [ { "page_instance" : "I42", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i42", "sym_num" : 1, "phys_page" : "page22", "block" : "top/xc2_fpga_blk", "page" : "page22", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22" } ], "node_name" : "R61_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_CPLD.A12" : { "pinuse" : "BI;", "pin_name_unsanitized" : "JT_FPGA_TDO", "pin_group" : "JT_GP_2;", "part_number" : "450-000313-001", "net_name" : "JT_FPGA_TDO", "pin_name" : "JT_FPGA_TDO", "refdes" : "U1_CPLD", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page5_i61", "sym_num" : 2, "page_instance" : "I61", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "phys_page" : "page5", "block" : "top/cpld_blk", "page" : "page5" } ], "node_name" : "U1_CPLD.A12", "pin_number" : "A12", "pin_type" : "INOUT" }, "C17_SP_XF.1" : { "part_number" : "402-000010-006", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I152_A_SP", "pin_name" : "A", "refdes" : "C17_SP_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i152", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I152", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "phys_page" : "page3" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C17_SP_XF.1" }, "C346_XF.1" : { "node_name" : "C346_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i59", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I59" } ], "part_number" : "402-000015-008", "pin_name" : "A", "refdes" : "C346_XF", "net_name" : "GND" }, "U1_XF.BJ10" : { "pin_number" : "BJ10", "pin_type" : "INOUT", "node_name" : "U1_XF.BJ10", "pin_name" : "OCL3_PET_N0", "net_name" : "AC_OCL3_PET_N<0>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_path" : 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"@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "page_instance" : "I13", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4_i13", "sym_num" : 1 } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "R78_FL_XF.1" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i2", "sym_num" : 1, "page_instance" : "I2", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page9" } ], "net_name" : "GND", "pin_name" : "A", "refdes" : "R78_FL_XF", "part_number" : "400-000010-010", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R78_FL_XF.1" }, "R6_CPLD.2" : { "part_number" : "400-000010-074", "pin_name" : "B", "refdes" : "R6_CPLD", "net_name" : "GND", "marker_data" : [ { "page" : "page4", "block" : "top/cpld_blk", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "page_instance" : "I103", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page4_i103" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R6_CPLD.2" }, "J4_XF.216" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10" } ], "part_number" : "410-000300-001", "pin_name" : "A2", "net_name" : "C3_DDR4_ADR<2>_XF", "refdes" : "J4_XF", "pinuse" : "IN;", "pin_name_unsanitized" : "A2", "pin_type" : "INPUT", "pin_number" : "216", "node_name" : "J4_XF.216" }, "PM2_SP_XF.T4" : { "pin_name" : "GND_75", "refdes" : "PM2_SP_XF", "net_name" : "GND", "part_number" : "462-000309-001", "marker_data" : [ { "page_instance" : "I459", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "sym_num" : 5, "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6" } ], "pin_name_unsanitized" : "GND_75", "pinuse" : "GROUND;", "pin_number" : "T4", "node_name" : "PM2_SP_XF.T4" }, "U1_XF.AK55" : { "node_name" : "U1_XF.AK55", "pin_type" : "INOUT", "pin_number" : "AK55", "pin_group" : "ALL_SIGNAL_PINS_24;", "pin_name_unsanitized" : "IO_L6N_T0U_N11_AD6N_29", "marker_data" : [ { "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I54", "sym_num" : 24, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54" } ], "pin_name" : "IO_L6N_T0U_N11_AD6N_29", "net_name" : "NC", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "R72_SP_XF.1" : { "node_name" : "R72_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "page_instance" : "I61", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i61", "sym_num" : 1 } ], "pin_name" : "A", "refdes" : "R72_SP_XF", "net_name" : "UNNAMED_7_RESISTOR_I61_A_SP", "part_number" : "400-000015-034" }, "J1_XF.248" : { "node_name" : "J1_XF.248", "pin_number" : "248", "pin_type" : "GROUND", "pin_name_unsanitized" : "VSS_86", "pinuse" : "UNSPEC;", "pin_name" : "VSS_86", "refdes" : "J1_XF", "net_name" : "GND", "part_number" : "410-000300-001", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4" } ] }, "C142_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-005", "pin_name" : "B", "refdes" : "C142_XF", "net_name" : "GNDADC_XF", "marker_data" : [ { "phys_page" : "page17", "page" : "page17", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "page_instance" : "I39", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i39", "sym_num" : 1 } ], "node_name" : "C142_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.BU51" : { "node_name" : "U1_XF.BU51", "pin_number" : "BU51", "pin_type" : "INOUT", "pin_name_unsanitized" : "C1_DDR4_DQS_C3", "pin_group" : "ALL_SIGNAL_PINS_39;", "part_number" : "450-000340-001", "net_name" : "C1_RDIMM_DQS_C<10>_XF", "pin_name" : "C1_DDR4_DQS_C3", "refdes" : "U1_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "page_instance" : "I2425", "sym_num" : 40, "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "page" : "PAGE5", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE5", "path" : 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"node_name" : "U1_XF.P48", "marker_data" : [ { "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34 } ], "part_number" : "450-000340-001", "pin_name" : "GND_203", "refdes" : "U1_XF", "net_name" : "GND", "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_203" }, "J1_E3_XF.B1" : { "node_name" : "J1_E3_XF.B1", "pin_number" : "B1", "pin_name_unsanitized" : "\\12v_1\\", "pinuse" : "POWER;", "marker_data" : [ { "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3_i101", "sym_num" : 1, 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: "A", "refdes" : "R6_CPLD", "net_name" : "ENB3V_LTC2975", "node_name" : "R6_CPLD.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "J6_XF.C" : { "pin_number" : "C", "pin_type" : "INPUT", "node_name" : "J6_XF.C", "pin_name" : "S", "net_name" : "NDIMM_VTT_BNC_XF", "refdes" : "J6_XF", "part_number" : "410-000168-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page28", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page28", "phys_page" : "page28", "page" : "page28", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page28_i9", "sym_num" : 1, "page_instance" : "I9", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page28" } ], "pin_name_unsanitized" : "S", "pinuse" : "IN;" }, "J2_P1_XF.A6" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "page_instance" : "I85", "sym_num" : 1, "ppath" : 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: { "node_name" : "U1_XF.BT35", "pin_type" : "INOUT", "pin_number" : "BT35", "pin_group" : "ALL_SIGNAL_PINS_20;", "pin_name_unsanitized" : "IO_L6P_T0U_N10_AD6P_67", "marker_data" : [ { "sym_num" : 20, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I49", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L6P_T0U_N10_AD6P_67", "net_name" : "NC" }, "C66_XF.1" : { "node_name" : "C66_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I136", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i136", "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null } ], "part_number" : "402-000015-007", "refdes" : "C66_XF", "pin_name" : "A", "net_name" : "PWR_VCCINT_XF" }, "C116_SP_XF.2" : { "marker_data" : [ { "page_instance" : "I29", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i29", "sym_num" : 1, "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7" } ], "net_name" : "GND", "pin_name" : "B", "refdes" : "C116_SP_XF", "part_number" : "402-000010-031", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C116_SP_XF.2" }, "C8_CPLD.1" : { "marker_data" : [ { "page_instance" : "I111", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "ppath" : "top/page14_i1/cpld_blk/page7_i111", "sym_num" : 1, "phys_page" : "page7", "block" : "top/cpld_blk", "page" : "page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7" } ], "pin_name" : "A", "net_name" : "GND", "refdes" : "C8_CPLD", "part_number" : "402-000010-001", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C8_CPLD.1" }, "U1_E2_XF.21" : { "node_name" : "U1_E2_XF.21", "pin_number" : "21", "pin_name_unsanitized" : "VDDA", "pinuse" : "POWER;", "pin_name" : "VDDA", "net_name" : "PWR_FPGA_3R3V", "refdes" : "U1_E2_XF", "part_number" : "450-000345-001", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i37", "sym_num" : 1 } ] }, "U1_XF.F52" : { "pin_group" : "ALL_POWER_PINS_27;", "pin_name_unsanitized" : "VREF_35", "marker_data" : [ { "sym_num" : 27, "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i67", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "page_instance" : "I67", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "remapped_page" : null, "page" : "page21", "block" : "top/xc2_fpga_blk", "phys_page" : "page21" } ], "pin_name" : "VREF_35", "net_name" : "UNNAMED_21_RESISTOR_I27_B_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.F52", "pin_number" : "F52", "pin_type" : "INOUT" }, "C285_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C285_XF.1", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page21", "phys_page" : "page21", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i48", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "page_instance" : "I48" } ], "part_number" : "402-000010-011", "net_name" : "PWR_FPGA_3R3V", "pin_name" : "A", "refdes" : "C285_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "J1_O1_XF.B11" : { "part_number" : "410-000324-001", "net_name" : "GND", "refdes" : "J1_O1_XF", "pin_name" : "GND_11", "marker_data" : [ { "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i29@top_lib.ocl_x4_conn_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i29@top_lib.ocl_x4_conn_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i29/ocl_x4_conn_blk/page3", "page_instance" : "I84", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i29/ocl_x4_conn_blk/page3_i84" } ], "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_11", "pin_number" : "B11", "node_name" : "J1_O1_XF.B11" }, "C14_E3_XF.2" : { "node_name" : "C14_E3_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "net_name" : "GND", "pin_name" : "B", "refdes" : "C14_E3_XF", "part_number" : "402-000010-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4", "page_instance" : "I35", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4_i35" } ] }, "U1_XF.D60" : { "pin_type" : "INOUT", "pin_number" : "D60", "node_name" : "U1_XF.D60", "marker_data" : [ { "page_instance" : "I67", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i67", "sym_num" : 27, "phys_page" : "page21", "page" : "page21", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21" } ], "net_name" : "UNNAMED_21_RESISTOR_I26_B_XF", "pin_name" : "IO_T0U_N12_VRP_35", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_27;", "pin_name_unsanitized" : "IO_T0U_N12_VRP_35" }, "PM4_SD_XF.C3" : { "pin_name_unsanitized" : "TSNS0_1", "pinuse" : "IN;", "pin_name" : "TSNS0_1", "net_name" : "UNNAMED_3_LTM4675_I40_TSNS01_SD", "refdes" : "PM4_SD_XF", "part_number" : "462-000304-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I40" } ], "node_name" : "PM4_SD_XF.C3", "pin_type" : "INPUT", "pin_number" : "C3" }, "U1_XF.M43" : { "marker_data" : [ { "page_instance" : "I58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "sym_num" : 26, "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31" } ], "part_number" : "450-000340-001", "pin_name" : "IO_L12P_T1U_N10_GC_38", "net_name" : "NC", "refdes" : "U1_XF", "pin_group" : "ALL_SIGNAL_PINS_26;", "pin_name_unsanitized" : "IO_L12P_T1U_N10_GC_38", "pin_number" : "M43", "pin_type" : "INOUT", "node_name" : "U1_XF.M43" }, "J3_XF.141" : { "node_name" : "J3_XF.141", "pin_type" : "INOUT", "pin_number" : "141", "pin_name_unsanitized" : "SCL", "pinuse" : "TRI;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8" } ], "refdes" : "J3_XF", "pin_name" : "SCL", "net_name" : "BASE_3R3V_SCL_2", "part_number" : "410-000300-001" }, "J1_XF.278" : { "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4" } ], "refdes" : "J1_XF", "pin_name" : "DQS7_T", "net_name" : "C0_RDIMM_DQS_T<7>_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "DQS7_T", "pinuse" : "TRI;", "pin_type" : "INOUT", "pin_number" : "278", "node_name" : "J1_XF.278" }, "C415_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C415_XF.1", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i176", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I176", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4" } ], "pin_name" : "A", "refdes" : "C415_XF", "net_name" : "PWR_SDIMM_VPP_XF", "part_number" : "402-000010-001", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "U1_XF.BM7" : { "node_name" : "U1_XF.BM7", "pin_type" : "INOUT", "pin_number" : "BM7", "pin_group" : "ALL_POWER_PINS_37;", "pin_name_unsanitized" : "GND_924", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I72", "sym_num" : 37, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : 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{ "node_name" : "PM7_SP_XF.E9", "pin_number" : "E9", "pin_type" : "INPUT", "pinuse" : "IN;", "pin_name_unsanitized" : "DIFFN", "marker_data" : [ { "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I150", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i150" } ], "part_number" : "462-000308-002", "net_name" : "SGND_PM7_SP", "pin_name" : "DIFFN", "refdes" : "PM7_SP_XF" }, "U1_XF.BW12" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73", "sym_num" : 38, "page_instance" : "I73", "ppath_without_last_instance" : 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"part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_119", "refdes" : "U1_XF", "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33 } ], "node_name" : "U1_XF.H60", "pin_number" : "H60", "pin_type" : "INOUT" }, "U1_XF.N12" : { "node_name" : "U1_XF.N12", "pin_number" : "N12", "pin_type" : "INOUT", "pin_name_unsanitized" : "GND_179", "pin_group" : "ALL_POWER_PINS_33;", "net_name" : "GND", "pin_name" : "GND_179", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : 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"pin_number" : "6", "pin_type" : "POWER", "node_name" : "J1.6" }, "U1_XF.CA14" : { "node_name" : "U1_XF.CA14", "pin_number" : "CA14", "pin_type" : "INOUT", "pin_name_unsanitized" : "GND_1053", "pin_group" : "ALL_POWER_PINS_38;", "part_number" : "450-000340-001", "pin_name" : "GND_1053", "refdes" : "U1_XF", "net_name" : "GND", "marker_data" : [ { "sym_num" : 38, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I73", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24" } ] }, "R128_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I106", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i106", "page" : "page17", "block" : "top/xc2_fpga_blk", "phys_page" : "page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null } ], "pin_name" : "B", "net_name" : "UNNAMED_17_RESISTOR_I104_A_XF", "refdes" : "R128_XF", "part_number" : "400-000010-010", "node_name" : "R128_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "J3_XF.257" : { "node_name" : "J3_XF.257", "pin_number" : "257", "pin_type" : "GROUND", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_12", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180" } ], "part_number" : "410-000300-001", "refdes" : "J3_XF", "pin_name" : "VSS_12", "net_name" : "GND" }, "C57.2" : { "node_name" : "C57.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "page" : "page20", "block" : "top", "phys_page" : "page20", "path" : "@top_lib.top(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page20", "page_instance" : "I32", "sym_num" : 1, "ppath" : "top/page20_i32" } ], "part_number" : "402-000010-043", "net_name" : "GND", "pin_name" : "B", "refdes" : "C57" }, "C34.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "net_name" : "GND", "pin_name" : "B", "refdes" : "C34", "part_number" : "402-000010-018", "marker_data" : [ { "page_instance" : "I15", "ppath_without_last_instance" : "top/page7", "ppath" : "top/page7_i15", "sym_num" : 1, "phys_page" : "page7", "page" : "page7", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page7" } ], "node_name" : "C34.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_XF.AC47" : { "pin_name" : "IO_L20N_T3L_N3_AD1N_32", "net_name" : "NC", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "sym_num" : 22, "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30" } ], "pin_name_unsanitized" : "IO_L20N_T3L_N3_AD1N_32", "pin_group" : "ALL_SIGNAL_PINS_22;", "pin_number" : "AC47", "pin_type" : "INOUT", "node_name" : "U1_XF.AC47" }, "R177_XF.2" : { "node_name" : "R177_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-004", "net_name" : "E1S1_FPGA_REFCLK_N<1>_XF", "pin_name" : "B", "refdes" : "R177_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i251", "sym_num" : 1, "page_instance" : "I251", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12" } ] }, "R230_XF.2" : { "node_name" : "R230_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-007", "pin_name" : "B", "net_name" : "OCL0_3R3V_SCL_XF", "refdes" : "R230_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page14", "phys_page" : "page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I260", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i260" } ] }, "U1_XF.CB51" : { "part_number" : "450-000340-001", "pin_name" : "C1_DDR4_ADR11", "refdes" : "U1_XF", "net_name" : "C1_DDR4_ADR<11>_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "page_instance" : "I2425", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "page" : "page5", "block" : "top/xc2_fpga_blk", "phys_page" : "page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "remapped_page" : null } ], "pin_name_unsanitized" : "C1_DDR4_ADR11", "pin_group" : "C1_ACTL_5_5;", "pin_number" : "CB51", "pin_type" : "INOUT", "node_name" : "U1_XF.CB51" }, "PM4_ND_XF.F3" : { "pin_number" : "F3", "pin_type" : "INPUT", "node_name" : "PM4_ND_XF.F3", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I40", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i40", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null } ], "part_number" : "462-000304-001", "net_name" : "UNNAMED_3_LTM4675_I40_RUN0_ND", "pin_name" : "RUN0", "refdes" : "PM4_ND_XF", "pinuse" : "IN;", "pin_name_unsanitized" : "RUN0" }, "J3_XF.18" : { "node_name" : "J3_XF.18", "pin_type" : "INOUT", "pin_number" : "18", "pin_name_unsanitized" : "DQS10_T_TDQS10_T", "pinuse" : "TRI;", "net_name" : "C2_RDIMM_DQS_T<10>_XF", "pin_name" : "DQS10_T_TDQS10_T", "refdes" : "J3_XF", "part_number" : "410-000300-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page8", "phys_page" : "page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180" } ] }, "J1_E3_XF.MH1" : { "pinuse" : "BI;", "pin_name_unsanitized" : "MH1", "marker_data" : [ { "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3", "page_instance" : "I101", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3_i101" } ], "part_number" : "410-000317-001", "refdes" : "J1_E3_XF", "pin_name" : "MH1", "net_name" : "UNNAMED_3_RESISTOR_I70_B_E3", "node_name" : "J1_E3_XF.MH1", "pin_number" : "MH1", "pin_type" : "INOUT" }, "U1_XF.BD8" : { "pin_group" : "ALL_SIGNAL_PINS_3;", "pin_name_unsanitized" : "MGTYTXN3_224", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page11", "phys_page" : "page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I775", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "MGTYTXN3_224", "net_name" : "NC", "node_name" : "U1_XF.BD8", "pin_type" : "INOUT", "pin_number" : "BD8" }, "R9.2" : { "marker_data" : [ { "ppath" : "top/page12_i3", "sym_num" : 1, "page_instance" : "I3", "ppath_without_last_instance" : "top/page12", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page12", "phys_page" : "page12", "page" : "page12", "block" : "top" } ], "part_number" : "400-000010-046", "refdes" : "R9", "pin_name" : "B", "net_name" : "FPGA_VCCAUX_P1R8V", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R9.2" }, "J1_XF.243" : { "node_name" : "J1_XF.243", "pin_number" : "243", "pin_type" : "GROUND", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_73", "part_number" : "410-000300-001", "net_name" : "GND", "pin_name" : "VSS_73", "refdes" : "J1_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk" } ] }, "C7_ND_XF.1" : { "part_number" : "402-000010-041", "refdes" : "C7_ND_XF", "pin_name" : "A", "net_name" : "P12V_FUSED_4675_ND", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I15", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i15", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C7_ND_XF.1" }, "J3_XF.136" : { "pin_name_unsanitized" : "VSS_76", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1 } ], "refdes" : "J3_XF", "pin_name" : "VSS_76", "net_name" : "GND", "part_number" : "410-000300-001", "node_name" : "J3_XF.136", "pin_number" : "136", "pin_type" : "GROUND" }, "J4_XF.261" : { "node_name" : "J4_XF.261", "pin_number" : "261", "pin_type" : "GROUND", "pin_name_unsanitized" : "VSS_23", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10" } ], "net_name" : "GND", "pin_name" : "VSS_23", "refdes" : "J4_XF", "part_number" : "410-000300-001" }, "J1_E0_XF.B21" : { "pin_number" : "B21", "pin_type" : "INPUT", "node_name" : "J1_E0_XF.B21", "refdes" : "J1_E0_XF", "pin_name" : "PETP1", "net_name" : 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"pin_name" : "GND_838", "refdes" : "U1_XF" }, "C5.1" : { "node_name" : "C5.1", "pin_type" : "ANALOG", "pin_number" : "1", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-026", "refdes" : "C5", "pin_name" : "A", "net_name" : "GND", "marker_data" : [ { "phys_page" : "page10", "page" : "page10", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "page_instance" : "I120", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i120", "sym_num" : 1 } ] }, "U1_XF.K6" : { "node_name" : "U1_XF.K6", "pin_number" : "K6", "pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_135", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : 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"pin_name_unsanitized" : "IO10_PB7A_2", "pinuse" : "BI;", "pin_name" : "IO10_PB7A_2", "net_name" : "NC", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152", "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152", "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null } ] }, "U1_XF.BY28" : { "node_name" : "U1_XF.BY28", "pin_number" : "BY28", "pin_type" : "INOUT", "pin_name_unsanitized" : "IO_T3U_N12_62", "pin_group" : "ALL_SIGNAL_PINS_15;", "pin_name" : "IO_T3U_N12_62", "net_name" : "NC", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "phys_path" : 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"pin_name_unsanitized" : "IO_L10N_T1U_N7_QBC_AD4N_20", "pin_group" : "ALL_SIGNAL_PINS_17;" }, "R102_FL_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "page_instance" : "I40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i40", "sym_num" : 1, "phys_page" : "page11", "page" : "page12", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page11" } ], "part_number" : "400-000014-011", "refdes" : "R102_FL_XF", "pin_name" : "B", "net_name" : "VMON_AVCC_RUC_LIN_XF", "node_name" : "R102_FL_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C23_XF.2" : { "node_name" : "C23_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I100", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i100" } ], "part_number" : "402-000015-006", "refdes" : "C23_XF", "pin_name" : "B", "net_name" : "GND" }, "U4_FL_XF.14" : { "pin_name_unsanitized" : "GND_14", "pinuse" : "POWER;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7", "page_instance" : "I30", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7_i30", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "remapped_page" : null } ], "pin_name" : "GND_14", "net_name" : "GND", "refdes" : "U4_FL_XF", "part_number" : "450-000057-001", "node_name" : "U4_FL_XF.14", "pin_number" : "14", "pin_type" : "POWER" }, "R10_FL_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R10_FL_XF.2", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page5", "phys_page" : "page5", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i29", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I29" } ], "pin_name" : "B", "refdes" : "R10_FL_XF", "net_name" : "POK_OD_AVTT_RLC_LIN", "part_number" : "400-000014-011", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "C29_SP_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C29_SP_XF.1", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i40", "sym_num" : 1, "page_instance" : "I40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_page" : "page5", "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "part_number" : "402-000010-003", "refdes" : "C29_SP_XF", "pin_name" : "A", "net_name" : "P12V_4650_TR_SP", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "U1_XF.C29" : { "node_name" : "U1_XF.C29", "pin_number" : "C29", "pin_type" : "INOUT", "pin_name_unsanitized" : "IO_L22P_T3U_N6_DBC_AD0P_71", "pin_group" : "ALL_SIGNAL_PINS_25;", "net_name" : "NC", "pin_name" : "IO_L22P_T3U_N6_DBC_AD0P_71", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i59", "sym_num" : 25, "page_instance" : "I59", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31" } ] }, "U1_CPLD.P10" : { "pin_group" : "PCTL_POK_3;", "pinuse" : "BI;", "pin_name_unsanitized" : "POK_OD_AVCC_RN_LIN", "marker_data" : [ { "page_instance" : "I211", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "ppath" : "top/page14_i1/cpld_blk/page4_i211", "sym_num" : 3, "phys_page" : "page4", "page" : "page4", "block" : "top/cpld_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4" } ], "part_number" : "450-000313-001", "net_name" : "POK_OD_AVCC_RN_LIN", "pin_name" : "POK_OD_AVCC_RN_LIN", "refdes" : "U1_CPLD", "node_name" : "U1_CPLD.P10", "pin_number" : "P10", "pin_type" : "INOUT" }, "C18.2" : { "part_number" : "402-000010-026", "net_name" : "GND", "pin_name" : "B", "refdes" : "C18", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "remapped_page" : null, "block" : "top", "page" : "page10", "phys_page" : "page10", "sym_num" : 1, "ppath" : "top/page10_i130", "ppath_without_last_instance" : "top/page10", "page_instance" : "I130" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C18.2" }, "J3_XF.144" : { "node_name" : "J3_XF.144", "pin_type" : "UNSPECIFIED", "pin_number" : "144", "pin_name_unsanitized" : "NC_6", "pinuse" : "BI;", "pin_name" : "NC_6", "net_name" : "NC", "refdes" : "J3_XF", "part_number" : "410-000300-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page8", "phys_page" : "page8", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180" } ] }, "U1_MP.TPAD" : { "pin_type" : "GROUND", "pin_number" : "TPAD", "node_name" : "U1_MP.TPAD", "pin_name" : "TPAD", "refdes" : "U1_MP", "net_name" : "GND", "part_number" : "450-000329-001", "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/mgmt_pwr_block", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page3", "page_instance" : "I2", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page3", "ppath" : "top/page18_i1/mgmt_pwr_block/page3_i2", "sym_num" : 1 } ], "pin_name_unsanitized" : "TPAD", "pinuse" : "UNSPEC;" }, "U1_XF.P3" : { "pin_name" : "E1S1_PER_N0", "net_name" : "E1S1_PER_N<0>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 9, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I283", "phys_path" : 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I7" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R68_FL_XF.1" }, "R7_CPLD.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "GND", "refdes" : "R7_CPLD", "part_number" : "400-000010-074", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_page" : "page4", "block" : "top/cpld_blk", "page" : "page4", "ppath" : "top/page14_i1/cpld_blk/page4_i104", "sym_num" : 1, "page_instance" : "I104", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4" } ], "node_name" : "R7_CPLD.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_XF.AG26" : { "node_name" : "U1_XF.AG26", "pin_number" : "AG26", "pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_31;", "pin_name_unsanitized" : "VCCINT_110", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "sym_num" : 31, "page_instance" : "I186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23" } ], "net_name" : "PWR_VCCINT_XF", "pin_name" : "VCCINT_110", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "U1_XF.T5" : { "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_219", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34, "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "path" : 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i101", "sym_num" : 1 } ], "pin_name_unsanitized" : "PERN1", "pinuse" : "OUT;" }, "R62_SP_XF.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i140", "sym_num" : 1, "page_instance" : "I140", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4" } ], "part_number" : "400-000014-011", "net_name" : "INTVCC_4650_TL_SP", "pin_name" : "A", "refdes" : "R62_SP_XF", "node_name" : "R62_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "C107_SP_XF.2" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i64", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I64", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7" } ], "part_number" : "402-000016-001", "refdes" : "C107_SP_XF", "pin_name" : "B", "net_name" : "UNNAMED_7_BYPASSCAPNPOL_I64_B_SP", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C107_SP_XF.2" }, "R129_XF.1" : { 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"pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R68_ND_XF.1" }, "U2_ND_XF.2" : { "node_name" : "U2_ND_XF.2", "pin_type" : "POWER", "pin_number" : "2", "pinuse" : "POWER;", "pin_name_unsanitized" : "VLDOIN", "marker_data" : [ { "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4", "page_instance" : "I19", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4_i19" } ], "part_number" : "450-000059-001", "net_name" : "PWR_NDIMM_VDD_XF", "pin_name" : "VLDOIN", "refdes" : "U2_ND_XF" }, "J3_XF.94" : { "node_name" : "J3_XF.94", "pin_type" : "GROUND", "pin_number" : "94", "pin_name_unsanitized" : "VSS_58", "pinuse" : "UNSPEC;", "net_name" : "GND", "pin_name" : "VSS_58", "refdes" : "J3_XF", "part_number" : "410-000300-001", "marker_data" : [ { "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1 } ] }, "U1_XF.J56" : { "node_name" : "U1_XF.J56", "pin_type" : "INOUT", "pin_number" : "J56", "pin_name_unsanitized" : "C2_DDR4_CS_N3", "pin_group" : "C2_ACTL_6_6;", "pin_name" : "C2_DDR4_CS_N3", "net_name" : "C2_DDR4_CS_N<3>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/xc2_fpga_blk", "phys_page" : "page7", "sym_num" : 6, "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "page_instance" : "I2425" } ] }, "U1_XF.G42" : { "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_101", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I68", "sym_num" : 33, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_101", "refdes" : "U1_XF", "node_name" : "U1_XF.G42", "pin_number" : "G42", "pin_type" : "INOUT" }, "C21_E0_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C21_E0_XF.1", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "page_instance" : "I54", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4" } ], "part_number" : "402-000010-035", "pin_name" : "A", "net_name" : "AC_CONN_CLK_REFP<0>_1", "refdes" : "C21_E0_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "J1_XF.117" : { "node_name" : "J1_XF.117", "pin_type" : "INOUT", "pin_number" : "117", "pinuse" : "TRI;", "pin_name_unsanitized" : "DQ52", "part_number" : "410-000300-001", "refdes" : "J1_XF", "pin_name" : "DQ52", "net_name" : "C0_DDR4_DQ<52>_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4" } ] }, "C350_XF.1" : { "marker_data" : [ { "page_instance" : "I151", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i151", "sym_num" : 1, "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29" } ], "part_number" : "402-000010-001", "pin_name" : "A", "refdes" : "C350_XF", "net_name" : "GND", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C350_XF.1" }, "U1_XF.AV3" : { "pin_name_unsanitized" : "PCIE0_RXN0", "pin_group" : "ALL_SIGNAL_PINS_3;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "PCIE0_RXN0", "net_name" : "PCIE0_RXN<0>_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page11", "phys_page" : "page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I775", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775" } ], "node_name" : "U1_XF.AV3", "pin_number" : "AV3", "pin_type" : "INOUT" }, "J1_E3_XF.A42" : { "pin_name_unsanitized" : "RFU_1", "pinuse" : "IN;", "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3_i101", "sym_num" : 1 } ], "refdes" : "J1_E3_XF", "pin_name" : "RFU_1", "net_name" : "RFU_<1>_E3", "part_number" : "410-000317-001", "node_name" : "J1_E3_XF.A42", "pin_type" : "INPUT", "pin_number" : "A42" }, "U6_SP_XF.3_4" : { "node_name" : "U6_SP_XF.3_4", "pin_type" : "OUTPUT", "pin_number" : "3_4", "pin_name_unsanitized" : "IP_N", "pinuse" : "OUT;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8_i94", "sym_num" : 1, "page_instance" : "I94", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "phys_page" : "page8", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page8" } ], "pin_name" : "IP_N", "refdes" : "U6_SP_XF", "net_name" : "P12V_4650_LLEFT_SP", "part_number" : "450-000162-001" }, "C420_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C420_XF.1", "marker_data" : [ { "page_instance" : "I156", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i156", "sym_num" : 1, "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6" } ], "part_number" : "402-000010-028", "net_name" : "GND", "pin_name" : "A", "refdes" : "C420_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "U1_XF.D8" : { "node_name" : "U1_XF.D8", "pin_number" : "D8", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_9;", "pin_name_unsanitized" : "E1S0_PET_N6", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page12", "phys_page" : "page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I283", "sym_num" : 9, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283" } ], "pin_name" : "E1S0_PET_N6", "refdes" : "U1_XF", "net_name" : "AC_E1S0_PET_N<6>_XF", "part_number" : "450-000340-001" }, "U1_XF.CA20" : { "pin_type" : "INOUT", "pin_number" : "CA20", "node_name" : "U1_XF.CA20", "pin_name" : "C0_DDR4_ADR4", "net_name" : "C0_DDR4_ADR<4>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "page_instance" : "I2425", "sym_num" : 4, "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425" } ], "pin_name_unsanitized" : "C0_DDR4_ADR4", "pin_group" : "C0_ACTL_4_4;" }, "U1_XF.C53" : { "pin_number" : "C53", "pin_type" : "INOUT", "node_name" : "U1_XF.C53", "marker_data" : [ { "page" : "PAGE7", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "page_instance" : "I2425", "sym_num" : 62, "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425" } ], "net_name" : "C2_DDR4_DQ<47>_XF", "pin_name" : "C2_DDR4_DQ47", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "C2_UNIB_1_6_57;", "pin_name_unsanitized" : "C2_DDR4_DQ47" }, "PM2_SP_XF.D7" : { "pin_number" : "D7", "node_name" : "PM2_SP_XF.D7", "part_number" : "462-000309-001", "net_name" : "P12V_MAIN", "refdes" : "PM2_SP_XF", "pin_name" : "VIN_1", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "sym_num" : 5, "page_instance" : "I459", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_1" }, "U1_XF.BH52" : { "pin_type" : "INOUT", "pin_number" : "BH52", "node_name" : "U1_XF.BH52", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L17P_T2U_N8_AD10P_24", "net_name" : "NC", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20, "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30" } ], "pin_name_unsanitized" : "IO_L17P_T2U_N8_AD10P_24", "pin_group" : "ALL_SIGNAL_PINS_20;" }, "C7_XF.2" : { "node_name" : "C7_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I113", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i113" } ], "part_number" : "402-000015-007", "refdes" : "C7_XF", "pin_name" : "B", "net_name" : "GND" }, "U2_SD_XF.3" : { "pin_number" : "3", "pin_type" : "POWER", "node_name" : "U2_SD_XF.3", "part_number" : "450-000059-001", "pin_name" : "VO", "refdes" : "U2_SD_XF", "net_name" : "PWR_SDIMM_VTT_XF", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "page_instance" : "I19", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4_i19", "sym_num" : 1 } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VO" }, "U10_FL_XF.13" : { "pin_number" : "13", "pin_type" : "POWER", "node_name" : "U10_FL_XF.13", "part_number" : "450-000057-001", "net_name" : "GND", "pin_name" : "GND_13", "refdes" : "U10_FL_XF", "marker_data" : [ { "phys_page" : "page11", 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"pin_number" : "BC12", "pin_type" : "INOUT", "node_name" : "U1_XF.BC12" }, "R28_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R28_XF.2", "marker_data" : [ { "phys_page" : "page18", "block" : "top/xc2_fpga_blk", "page" : "page18", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "page_instance" : "I21", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page18", "ppath" : "top/page6_i428/xc2_fpga_blk/page18_i21", "sym_num" : 1 } ], "part_number" : "400-000010-007", "pin_name" : "B", "net_name" : "FPGA_INIT_F_1", "refdes" : "R28_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "PM4_ND_XF.F4" : { "pin_number" : "F4", "pin_type" : "INPUT", "node_name" : "PM4_ND_XF.F4", "pin_name" : "RUN1", "net_name" : "UNNAMED_3_LTM4675_I40_RUN0_ND", "refdes" : "PM4_ND_XF", "part_number" : "462-000304-001", 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"pin_number" : "223", "pin_type" : "POWER", "pin_name_unsanitized" : "VDD_5", "pinuse" : "POWER;", "refdes" : "J2_XF", "pin_name" : "VDD_5", "net_name" : "PWR_SDIMM_VDD_XF", "part_number" : "410-000300-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk" } ] }, "U1_XF.BD33" : { "node_name" : "U1_XF.BD33", "pin_type" : "INOUT", "pin_number" : "BD33", "pin_name_unsanitized" : "VCCINT_227", "pin_group" : "ALL_POWER_PINS_32;", "part_number" : "450-000340-001", "pin_name" : "VCCINT_227", "net_name" : "PWR_VCCINT_XF", "refdes" : "U1_XF", "marker_data" : [ { "sym_num" : 32, "ppath" : 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1 } ], "node_name" : "J1_P1_XF.A20", "pin_number" : "A20" }, "C70_ND_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C70_ND_XF.2", "net_name" : "GND", "pin_name" : "B", "refdes" : "C70_ND_XF", "part_number" : "402-000010-039", "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "page_instance" : "I9", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i9", "sym_num" : 1 } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "U1_XF.E16" : { "node_name" : "U1_XF.E16", "pin_number" : "E16", "pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_69", "marker_data" : [ { "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "pin_name" : "GND_69", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001" }, "U1_XF.R45" : { "node_name" : "U1_XF.R45", "pin_type" : "INOUT", "pin_number" : "R45", "pin_group" : "ALL_SIGNAL_PINS_26;", "pin_name_unsanitized" : "IO_L1P_T0L_N0_DBC_38", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "sym_num" : 26, "page_instance" : "I58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk" } ], "pin_name" : "IO_L1P_T0L_N0_DBC_38", "net_name" : "NC", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "PM4_SD_XF.A2" : { "pin_number" : "A2", "pin_type" : "POWER", "node_name" : "PM4_SD_XF.A2", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i20", "sym_num" : 2, "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3" } ], "part_number" : "462-000304-001", "pin_name" : "GND_1", "net_name" : "GND", "refdes" : "PM4_SD_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_1" }, "R39.1" : { "marker_data" : [ { "page" : "page20", "block" : "top", "phys_page" : "page20", "path" : "@top_lib.top(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page20", "page_instance" : "I51", "sym_num" : 1, "ppath" : "top/page20_i51" } ], "part_number" : "400-000010-010", "refdes" : "R39", "pin_name" : "A", "net_name" : "FAN_PWM_OD", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R39.1" }, "R1_XF.2" : { "pin_name" : "B", "net_name" : "UNNAMED_17_RESISTOR_I51_A_XF", "refdes" : "R1_XF", "part_number" : "400-000014-011", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_page" : "page17", "page" : "page17", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i65", "sym_num" : 1, "page_instance" : "I65", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R1_XF.2" }, "C470_XF.1" : { "node_name" : "C470_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page20", "phys_page" : "page20", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i16", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I16" } ], "part_number" : "402-000010-028", "pin_name" : "A", "refdes" : "C470_XF", "net_name" : "PWR_AVTT_RLC_XF" }, "C3_E1_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-011", "pin_name" : "B", "refdes" : "C3_E1_XF", "net_name" : "PWR_FPGA_3R3V", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "page_instance" : "I22", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i22", "sym_num" : 1 } ], "node_name" : "C3_E1_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.U47" : { "node_name" : "U1_XF.U47", "pin_type" : "INOUT", "pin_number" : "U47", "pin_name_unsanitized" : "GND_242", "pin_group" : "ALL_POWER_PINS_34;", "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_242", "refdes" : "U1_XF", "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34 } ] }, "U1_XF.W7" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I251", "sym_num" : 10, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i251", "page" : "page13", "block" : "top/xc2_fpga_blk", "phys_page" : "page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null } ], "pin_name" : "E1S2_PET_P1", "net_name" : "AC_E1S2_PET_P<1>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_10;", "pin_name_unsanitized" : "E1S2_PET_P1", "pin_number" : "W7", "pin_type" : "INOUT", "node_name" : "U1_XF.W7" }, "C189_SP_XF.3" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i115", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I115", "path" : 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"top/page14_i1/cpld_blk/page9", "page_instance" : "I16", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page9_i16" } ], "refdes" : "D1_CPLD", "pin_name" : "L2C", "net_name" : "STAT_LED_ON_F<0>_CPLD", "part_number" : "404-000001-008" }, "R124_SP_XF.2" : { "node_name" : "R124_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i83", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I83" } ], "pin_name" : "B", "net_name" : "VMON_SDIMM_VPP_SW", "refdes" : "R124_SP_XF", "part_number" : "400-000014-011" }, "PM7_SP_XF.D7" : { "pin_name_unsanitized" : "VFB2", "pinuse" : "IN;", "pin_name" : "VFB2", "net_name" : "VFB_4650_SP", "refdes" : "PM7_SP_XF", "part_number" : "462-000308-002", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I150", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i150", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null } ], "node_name" : "PM7_SP_XF.D7", "pin_number" : "D7", "pin_type" : "INPUT" }, "U1_XF.AW43" : { "node_name" : "U1_XF.AW43", "pin_type" : "INOUT", "pin_number" : "AW43", "pin_name_unsanitized" : "GND_683", "pin_group" : "ALL_POWER_PINS_36;", "net_name" : "GND", "pin_name" : "GND_683", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "sym_num" : 36, "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24" } ] }, "J12_XF.G1" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page28_i17", "sym_num" : 1, "page_instance" : "I17", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page28", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page28", "path" : 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"refdes" : "R4_MP", "pin_name" : "B", "net_name" : "UNNAMED_3_RESISTOR_I15_A_MP" }, "J1_O0_XF.MH4" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "MH4", "part_number" : "410-000324-001", "refdes" : "J1_O0_XF", "net_name" : "GND", "pin_name" : "MH4", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i6/ocl_x4_conn_blk/page3_i84", "sym_num" : 1, "page_instance" : "I84", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i6/ocl_x4_conn_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i6@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i6@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk" } ], "node_name" : "J1_O0_XF.MH4", "pin_number" : "MH4" }, "U1_XF.J43" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "sym_num" : 26, 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"SCL", "pinuse" : "BI;" }, "C81_SP_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000016-001", "pin_name" : "A", "net_name" : "PM2_SP_AGND_SP", "refdes" : "C81_SP_XF", "marker_data" : [ { "page_instance" : "I401", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i401", "sym_num" : 1, "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6" } ], "node_name" : "C81_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "C112_SP_XF.1" : { "node_name" : "C112_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-031", "net_name" : "PWR_NDIMM_VPP_XF", "pin_name" : "A", "refdes" : "C112_SP_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i30", "sym_num" : 1, "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7" } ] }, "J3_XF.86" : { "pin_name_unsanitized" : "CAS_N_A15", "pinuse" : "IN;", "pin_name" : "CAS_N_A15", "refdes" : "J3_XF", "net_name" : "C2_DDR4_ADR<15>_XF", "part_number" : "410-000300-001", "marker_data" : [ { "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180" } ], "node_name" : "J3_XF.86", "pin_number" : "86", "pin_type" : "INPUT" }, "R148_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "net_name" : "GND", "refdes" : "R148_XF", "part_number" : "400-000010-006", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i71", "sym_num" : 1, "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk" } ], "node_name" : "R148_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.AR19" : { "part_number" : "450-000340-001", "pin_name" : "D02_0", "refdes" : "U1_XF", "net_name" : "CFG_FLASH_D02_0_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "phys_page" : "page18", "page" : "page18", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page18_i53", "sym_num" : 1, "page_instance" : "I53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page18" } ], "pin_name_unsanitized" : "D02_0", "pin_group" : "ALL_SIGNAL_PINS_1;", "pin_type" : "INOUT", "pin_number" : "AR19", "node_name" : "U1_XF.AR19" }, "R13_FL_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R13_FL_XF.2", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3", "page_instance" : "I19", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3_i19", "page" : "page3", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "remapped_page" : null } ], "pin_name" : "B", "refdes" : "R13_FL_XF", "net_name" : "P3R3V", "part_number" : "400-000010-010", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "C92_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "page" : "page20", "block" : "top/xc2_fpga_blk", "phys_page" : "page20", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I53" } ], "net_name" : "GND", "pin_name" : "B", "refdes" : "C92_XF", "part_number" : "402-000010-001", "node_name" : "C92_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "J4_XF.92" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10" } ], "part_number" : "410-000300-001", "net_name" : "PWR_NDIMM_VDD_XF", "pin_name" : "VDD_15", "refdes" : "J4_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_15", "pin_type" : "POWER", "pin_number" : "92", "node_name" : "J4_XF.92" }, "C14_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C14_XF.1", "marker_data" : [ { "page_instance" : "I121", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i121", "sym_num" : 1, "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23" } ], "part_number" : "402-000015-007", "refdes" : "C14_XF", "pin_name" : "A", "net_name" : "PWR_VCCINT_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "U1_XF.BN44" : { "node_name" : "U1_XF.BN44", "pin_type" : "INOUT", "pin_number" : "BN44", "pin_group" : "ALL_SIGNAL_PINS_17;", "pin_name_unsanitized" : "IO_L4N_T0U_N7_DBC_AD7N_19", "marker_data" : [ { "page_instance" : "I50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "sym_num" : 17, "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30" } ], "part_number" : "450-000340-001", "pin_name" : "IO_L4N_T0U_N7_DBC_AD7N_19", "net_name" : "NC", "refdes" : "U1_XF" }, "U1_XF.BU40" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20, "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L1N_T0L_N1_DBC_67", "net_name" : "NC", "pin_group" : "ALL_SIGNAL_PINS_20;", "pin_name_unsanitized" : "IO_L1N_T0L_N1_DBC_67", "pin_type" : "INOUT", "pin_number" : "BU40", "node_name" : "U1_XF.BU40" }, "PM7_SP_XF.B6" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_3", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i151", "sym_num" : 2, "page_instance" : "I151", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11" } ], "part_number" : "462-000308-002", "refdes" : "PM7_SP_XF", "pin_name" : "GND_3", "net_name" : "GND", "node_name" : "PM7_SP_XF.B6", "pin_number" : "B6", "pin_type" : "POWER" }, "C137_SP_XF.2" : { "pin_name" : "B", "refdes" : "C137_SP_XF", "net_name" : "UNNAMED_7_LTM4671_I37_FB1_SP", "part_number" : "402-000200-003", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I90", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i90" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C137_SP_XF.2" }, "C70.2" : { "node_name" : "C70.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "page" : "page19", "block" : "top", "phys_page" : "page19", "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19", "remapped_page" : null, "ppath_without_last_instance" : "top/page19", "page_instance" : "I56", "sym_num" : 1, "ppath" : "top/page19_i56" } ], "net_name" : "P3R3V", "pin_name" : "B", "refdes" : "C70", "part_number" : "402-000010-032" }, "R78_FL_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R78_FL_XF.2", "marker_data" : [ { "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I2", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i2" } ], "pin_name" : "B", "refdes" : "R78_FL_XF", "net_name" : "UNNAMED_9_LT3071_I30_V02_FL", "part_number" : "400-000010-010", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "J3_XF.192" : { "node_name" : "J3_XF.192", "pin_type" : "INOUT", "pin_number" : "192", "pin_name_unsanitized" : "CB5", "pinuse" : "TRI;", "pin_name" : "CB5", "refdes" : "J3_XF", "net_name" : "C2_DDR4_DQ<69>_XF", "part_number" : "410-000300-001", "marker_data" : [ { "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180" } ] }, "U1_SP_XF.27" : { "pin_number" : "27", "pin_type" : "INOUT", "node_name" : "U1_SP_XF.27", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i168", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I168", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3" } ], "pin_name" : "TSENSE2", "refdes" : "U1_SP_XF", "net_name" : "TS_LT4650_BR_SP", "part_number" : "450-000302-001", "pin_name_unsanitized" : "TSENSE2", "pinuse" : "UNSPEC;" }, "J8_XF.G2" : { "marker_data" : [ { "page_instance" : "I11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page28", "ppath" : "top/page6_i428/xc2_fpga_blk/page28_i11", "sym_num" : 1, "phys_page" : "page28", "page" : "page28", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page28", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page28" } ], "part_number" : "410-000168-001", "net_name" : "GND", "pin_name" : "G2", "refdes" : "J8_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "G2", "pin_type" : "POWER", "pin_number" : "G2", "node_name" : "J8_XF.G2" }, "R72_SP_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "UNNAMED_7_LTM4671_I37_FB1_SP", "refdes" : "R72_SP_XF", "part_number" : "400-000015-034", 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"node_name" : "R119_CPLD.1", "pin_name" : "A", "refdes" : "R119_CPLD", "net_name" : "UNNAMED_9_598BICOLORLED_I16_L2A_CPLD", "part_number" : "400-000010-006", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "phys_page" : "page9", "block" : "top/cpld_blk", "page" : "page9", "ppath" : "top/page14_i1/cpld_blk/page9_i8", "sym_num" : 1, "page_instance" : "I8", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page9" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "C24_E0_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C24_E0_XF.1", "marker_data" : [ { "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "path" : 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"part_number" : "462-000308-002" }, "U1_XF.AW2" : { "node_name" : "U1_XF.AW2", "pin_number" : "AW2", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_3;", "pin_name_unsanitized" : "PCIE0_RXP1", "marker_data" : [ { "page_instance" : "I775", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775", "sym_num" : 3, "phys_page" : "page11", "block" : "top/xc2_fpga_blk", "page" : "page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "PCIE0_RXP1", "net_name" : "PCIE0_RXP<1>_XF" }, "C17_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000015-008", "refdes" : "C17_XF", "pin_name" : "A", "net_name" : "PWR_VCCINT_XF", "marker_data" : [ { "page" : "page23", "block" : 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"net_name" : "GND", "pin_name" : "GND_70", "refdes" : "PM2_SP_XF", "part_number" : "462-000309-001", "node_name" : "PM2_SP_XF.L7", "pin_number" : "L7" }, "PM3_SP_XF.C10" : { "net_name" : "PWR_VCCINT_XF", "pin_name" : "VOUT2_12", "refdes" : "PM3_SP_XF", "part_number" : "462-000308-002", "marker_data" : [ { "phys_page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "page_instance" : "I152", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i152", "sym_num" : 1 } ], "pin_name_unsanitized" : "VOUT2_12", "pinuse" : "POWER;", "pin_number" : "C10", "pin_type" : "POWER", "node_name" : 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"UNSPEC;", "pin_group" : "1;", "net_name" : "PWR_NDIMM_VDD_XF", "pin_name" : "A", "refdes" : "C337_XF", "part_number" : "402-000010-001", "marker_data" : [ { "phys_page" : "page21", "block" : "top/xc2_fpga_blk", "page" : "page21", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "page_instance" : "I12", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i12", "sym_num" : 1 } ] }, "J4_XF.200" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_52", "part_number" : "410-000300-001", "pin_name" : "VSS_52", "refdes" : "J4_XF", "net_name" : "GND", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180" } ], "node_name" : "J4_XF.200", "pin_type" : "GROUND", "pin_number" : "200" }, "U1_E0_XF.19" : { "node_name" : "U1_E0_XF.19", "pin_type" : "INPUT", "pin_number" : "19", "pin_name_unsanitized" : "OE1_F", "pinuse" : "IN;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i37", "sym_num" : 1, "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4" } ], "refdes" : "U1_E0_XF", "pin_name" : "OE1_F", "net_name" : "E1S0_3R3V_CKEN_F<1>_XF", "part_number" : "450-000345-001" }, "J2_XF.193" : { "node_name" : "J2_XF.193", "pin_type" : "GROUND", "pin_number" : "193", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_34", "part_number" : "410-000300-001", "pin_name" : "VSS_34", "net_name" : "GND", "refdes" : "J2_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page6", "phys_page" : "page6", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180" } ] }, "C52_FL_XF.2" : { "node_name" : "C52_FL_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I19", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i19" } ], "part_number" : "402-000010-028", "refdes" : "C52_FL_XF", "pin_name" : "B", "net_name" : "GND" }, "U1_XF.W6" : { "node_name" : "U1_XF.W6", "pin_type" : "INOUT", "pin_number" : "W6", "pin_name_unsanitized" : "E1S2_PET_N1", "pin_group" : "ALL_SIGNAL_PINS_10;", "part_number" : "450-000340-001", "pin_name" : "E1S2_PET_N1", "net_name" : "AC_E1S2_PET_N<1>_XF", "refdes" : "U1_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_page" : "page13", "block" : "top/xc2_fpga_blk", "page" : "page13", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i251", "sym_num" : 10, "page_instance" : "I251", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13" } ] }, "PM4_SD_XF.C7" : { "pin_name_unsanitized" : "GND_18", "pinuse" : "POWER;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I20", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i20", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null } ], "refdes" : "PM4_SD_XF", "pin_name" : "GND_18", "net_name" : "GND", "part_number" : "462-000304-001", "node_name" : "PM4_SD_XF.C7", "pin_number" : "C7", "pin_type" : "POWER" }, "NS7_SP_XF.1" : { "node_name" : "NS7_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "refdes" : "NS7_SP_XF", "net_name" : "GND", "part_number" : "NET_SHORT", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "page_instance" : "I116", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i116", "sym_num" : 1 } ] }, "C58_SP_XF.2" : { "node_name" : "C58_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "net_name" : "GND", "pin_name" : "B", "refdes" : "C58_SP_XF", "part_number" : "402-000500-005", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null, "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page10", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i99", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I99" } ] }, "R61_SP_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R61_SP_XF.1", "part_number" : "400-000010-112", "pin_name" : "A", "net_name" : "UNNAMED_4_CAPACITOR_I64_B_SP", "refdes" : "R61_SP_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i133", "sym_num" : 1, "page_instance" : "I133", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "U1_CPLD.D2" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page3", "page_instance" : "I447", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page3_i447", "block" : "top/cpld_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "remapped_page" : null } ], "refdes" : "U1_CPLD", "pin_name" : "SI5341_LOL_N", "net_name" : "SI5341_LOL_N", "part_number" : "450-000313-001", "pin_group" : "SI5341_1;", "pin_name_unsanitized" : "SI5341_LOL_N", "pinuse" : "BI;", "pin_number" : "D2", "pin_type" : "INOUT", "node_name" : "U1_CPLD.D2" }, "U1_XF.B55" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "PAGE7", "phys_page" : "PAGE7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "page_instance" : "I2425", "sym_num" : 61, "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425" } ], "net_name" : "C2_DDR4_DQ<39>_XF", "pin_name" : "C2_DDR4_DQ39", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "C2_UNIB_1_6_57;", "pin_name_unsanitized" : "C2_DDR4_DQ39", "pin_number" : "B55", "pin_type" : "INOUT", "node_name" : "U1_XF.B55" }, "U1_CPLD.L2" : { "node_name" : "U1_CPLD.L2", "pin_type" : "INOUT", "pin_number" : "L2", "pin_name_unsanitized" : "IO8_PL17A_PCLKT3_0_3", "pinuse" : "BI;", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152", "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152", "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null } ], "net_name" : "NC", "pin_name" : "IO8_PL17A_PCLKT3_0_3", "refdes" : "U1_CPLD", "part_number" : "450-000313-001" }, "U1_CPLD.G7" : { "pin_name_unsanitized" : "VCC_3", "pinuse" : "POWER;", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_page" : "page7", "block" : "top/cpld_blk", "page" : "page7", "ppath" : "top/page14_i1/cpld_blk/page7_i151", "sym_num" : 7, "page_instance" : "I151", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7" } ], "pin_name" : "VCC_3", "net_name" : "CPLD_P3R3V", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "node_name" : "U1_CPLD.G7", "pin_number" : "G7" }, "J1_E2_XF.B32" : { "pin_name" : "GND_25", "refdes" : "J1_E2_XF", "net_name" : "GND", "part_number" : "410-000317-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3", "page_instance" : "I101", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3" } ], "pin_name_unsanitized" : "GND_25", "pinuse" : "GROUND;", "pin_number" : "B32", "node_name" : "J1_E2_XF.B32" }, "C49_FL_XF.1" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8", "page_instance" : "I35", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8_i35", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page8", "phys_page" : "page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "remapped_page" : null } ], "pin_name" : "A", "refdes" : "C49_FL_XF", "net_name" : "PWR_AVTT_SW_XF", "part_number" : "402-000010-001", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C49_FL_XF.1" }, "U1_CPLD.M12" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_18", "marker_data" : [ { "phys_page" : "page7", "block" : "top/cpld_blk", "page" : "page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "page_instance" : "I151", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "ppath" : "top/page14_i1/cpld_blk/page7_i151", "sym_num" : 7 } ], "part_number" : "450-000313-001", "refdes" : "U1_CPLD", "pin_name" : "GND_18", "net_name" : "GND", "node_name" : "U1_CPLD.M12", "pin_number" : "M12" }, "R177_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R177_XF.1", "part_number" : "400-000010-004", "refdes" : "R177_XF", "pin_name" : "A", "net_name" : "E1S1_FPGA_REFCLK_P<1>_XF", "marker_data" : [ { "page_instance" : "I251", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i251", "sym_num" : 1, "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "C94_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C94_XF.2", "part_number" : "402-000015-008", "pin_name" : "B", "net_name" : "GND", "refdes" : "C94_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : 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"remapped_page" : null, "page" : "page14", "block" : "top/xc2_fpga_blk", "phys_page" : "page14", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i260", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I260" } ] }, "J3.2" : { "refdes" : "J3", "net_name" : "P3R3V", "pin_name" : "2", "part_number" : "410-000105-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page19_i41", "ppath_without_last_instance" : "top/page19", "page_instance" : "I41", "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19", "remapped_page" : null, "page" : "page19", "block" : "top", "phys_page" : "page19" } ], "pin_name_unsanitized" : "\\2\\", "pinuse" : "POWER;", "pin_number" : "2", "node_name" : "J3.2" }, "C12_XF.1" : { "node_name" : "C12_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "C12_XF", "pin_name" : "A", "net_name" : "PWR_VCCINT_XF", "part_number" : "402-000015-007", "marker_data" : [ { "page_instance" : "I119", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i119", "sym_num" : 1, "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23" } ] }, "J1_XF.256" : { "node_name" : "J1_XF.256", "pin_type" : "INOUT", "pin_number" : "256", "pin_name_unsanitized" : "DQS5_T", "pinuse" : "TRI;", "pin_name" : "DQS5_T", "refdes" : "J1_XF", "net_name" : "C0_RDIMM_DQS_T<5>_XF", "part_number" : "410-000300-001", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : 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"page_instance" : "I80" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT2_6", "pin_number" : "B8", "pin_type" : "POWER", "node_name" : "PM7_SP_XF.B8" }, "R259_XF.1" : { "node_name" : "R259_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2416", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2416", "page" : "page9", "block" : "top/xc2_fpga_blk", "phys_page" : "page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "remapped_page" : null } ], "part_number" : "400-000010-004", "refdes" : "R259_XF", "pin_name" : "A", "net_name" : "C3_SYS_CLK_P_XF" }, "J1_E1_XF.MH3" : { "node_name" : "J1_E1_XF.MH3", "pin_number" : "MH3", "pin_type" : "INOUT", "pinuse" : "BI;", "pin_name_unsanitized" : "MH3", "part_number" : "410-000317-001", "pin_name" : "MH3", "refdes" : "J1_E1_XF", "net_name" : "UNNAMED_3_RESISTOR_I70_B_E1", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "page_instance" : "I101", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i101", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null } ] }, "U1_XF.G60" : { "pin_name" : "C2_DDR4_DQ22", "refdes" : "U1_XF", "net_name" : "C2_DDR4_DQ<22>_XF", "part_number" : "450-000340-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" : 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"pin_name_unsanitized" : "VOUT_16", "pinuse" : "POWER;", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i30", "sym_num" : 1 } ], "refdes" : "U6_FL_XF", "pin_name" : "VOUT_16", "net_name" : "PWR_AVCC_RN_XF", "part_number" : "450-000057-001", "node_name" : "U6_FL_XF.16", "pin_type" : "POWER", "pin_number" : "16" }, "PM7_SP_XF.L7" : { "node_name" : "PM7_SP_XF.L7", "pin_number" : "L7", "pin_type" : "POWER", "pin_name_unsanitized" : "VIN_18", "pinuse" : "POWER;", "pin_name" : "VIN_18", "refdes" : "PM7_SP_XF", "net_name" : "P12V_4650_BR_SP", "part_number" : "462-000308-002", "marker_data" : [ { "phys_page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80", "sym_num" : 1 } ] }, "C364_XF.2" : { "net_name" : "C2_SYS_CLK_P_XF", "pin_name" : "B", "refdes" : "C364_XF", "part_number" : "402-000010-035", "marker_data" : [ { "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" 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"node_name" : "U6_FL_XF.25" }, "R56_FL_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000014-011", "net_name" : "VMON_AVTT_RLC_LIN_XF", "pin_name" : "B", "refdes" : "R56_FL_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I45", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i45", "page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null } ], "node_name" : "R56_FL_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.C34" : { "node_name" : "U1_XF.C34", "pin_type" : "INOUT", "pin_number" : "C34", "pin_name_unsanitized" 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"phys_page" : "page30" } ], "node_name" : "U1_XF.BU29", "pin_type" : "INOUT", "pin_number" : "BU29" }, "U1_XF.K33" : { "pin_name_unsanitized" : "IO_L17N_T2U_N9_AD10N_72", "pin_group" : "ALL_SIGNAL_PINS_24;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L17N_T2U_N9_AD10N_72", "net_name" : "NC", "marker_data" : [ { "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "page_instance" : "I54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54", "sym_num" : 24 } ], "node_name" : "U1_XF.K33", "pin_type" : "INOUT", "pin_number" : "K33" }, "R136_SP_XF.1" : { "node_name" : "R136_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : 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"ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null } ], "pin_name" : "DQ33", "net_name" : "C3_DDR4_DQ<33>_XF", "refdes" : "J4_XF", "part_number" : "410-000300-001" }, "U5_XF.12" : { "pin_name_unsanitized" : "OE0_F", "pinuse" : "IN;", "pin_name" : "OE0_F", "net_name" : "OCL2_3R3V_CKEN_F<1>_XF", "refdes" : "U5_XF", "part_number" : "450-000345-001", "marker_data" : [ { "phys_page" : "page29", "block" : "top/xc2_fpga_blk", "page" : "page29", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "page_instance" : "I63", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "ppath" : 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"pin_name_unsanitized" : "VSS_21", "part_number" : "410-000300-001", "net_name" : "GND", "pin_name" : "VSS_21", "refdes" : "J2_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk" } ], "node_name" : "J2_XF.9", "pin_type" : "GROUND", "pin_number" : "9" }, "U1_XF.L52" : { "marker_data" : [ { "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425", "sym_num" : 60, "phys_page" : "PAGE7", "block" : "top/xc2_fpga_blk", "page" : "PAGE7", "remapped_page" : null, "phys_path" : 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"@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8" } ], "net_name" : "PWR_NDIMM_VTT_XF", "pin_name" : "VTT_2", "refdes" : "J3_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VTT_2", "pinuse" : "POWER;", "pin_type" : "POWER", "pin_number" : "221", "node_name" : "J3_XF.221" }, "C11_E3_XF.1" : { "node_name" : "C11_E3_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3_i94", "sym_num" : 1, "page_instance" : "I94", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8" } ], "part_number" : "402-000010-028", "net_name" : "GND", "pin_name" : "A", "refdes" : "C11_E3_XF" }, "J3_XF.104" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8" } ], "pin_name" : "DQ34", "refdes" : "J3_XF", "net_name" : "C2_DDR4_DQ<34>_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "DQ34", "pinuse" : "TRI;", "pin_number" : "104", "pin_type" : "INOUT", "node_name" : "J3_XF.104" }, "R200_XF.2" : { "pin_name" : "B", "net_name" : "GND", "refdes" : "R200_XF", "part_number" : "400-000010-010", "marker_data" : [ { "sym_num" : 1, "ppath" : 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"remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i38", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "page_instance" : "I38" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "C38_XF.1" : { "node_name" : "C38_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "page_instance" : "I625", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i625", "sym_num" : 1, "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11" } ], "part_number" : "402-000010-035", "net_name" : "AC_PCIE0_TXP<3>_XF", "pin_name" : "A", "refdes" : "C38_XF" }, "C41_SD_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C41_SD_XF.2", "pin_name" : "B", "refdes" : "C41_SD_XF", "net_name" : "GND", "part_number" : "402-000010-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4_i25", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4", "page_instance" : "I25" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "J11_XF.G2" : { "pin_name_unsanitized" : "G2", "pinuse" : "POWER;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page28_i15", "sym_num" : 1, "page_instance" : "I15", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page28", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page28", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page28", "phys_page" : "page28", "block" : "top/xc2_fpga_blk", "page" : "page28" } ], "pin_name" : "G2", "net_name" : "GND", "refdes" : "J11_XF", "part_number" : "410-000168-001", "node_name" : "J11_XF.G2", "pin_type" : "POWER", "pin_number" : "G2" }, "PM5_SP_XF.H1" : { "pin_type" : "POWER", "pin_number" : "H1", "node_name" : "PM5_SP_XF.H1", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I79", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i79", "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null } ], "part_number" : "462-000308-002", "net_name" : "GND", "pin_name" : "GND_30", "refdes" : "PM5_SP_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_30" }, "C168_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C168_XF.1", "part_number" : "402-000010-035", "net_name" : "AC_E1S2_PET_N<5>_XF", "pin_name" : "A", "refdes" : "C168_XF", "marker_data" : [ { "page_instance" : "I65", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i65", "sym_num" : 1, "phys_page" : "page13", "block" : "top/xc2_fpga_blk", "page" : "page13", "remapped_page" : null, "phys_path" : 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"sym_num" : 29, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I86", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "page" : "page20", "block" : "top/xc2_fpga_blk", "phys_page" : "page20" } ], "part_number" : "450-000340-001", "net_name" : "PWR_AVTT_RLC_XF", "pin_name" : "MGTAVTT_RLC_6", "refdes" : "U1_XF", "node_name" : "U1_XF.AU9", "pin_type" : "INOUT", "pin_number" : "AU9" }, "U5_XF.3" : { "net_name" : "NC", "refdes" : "U5_XF", "pin_name" : "NC_2", "part_number" : "450-000345-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i63", "sym_num" : 1, "page_instance" : "I63", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "remapped_page" : null, "phys_path" : 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: "U4_XF.6" }, "PM1_SP_XF.F9" : { "pin_type" : "INPUT", "pin_number" : "F9", "node_name" : "PM1_SP_XF.F9", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I87", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i87", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null } ], "net_name" : "UNNAMED_7_LTM4671_I87_TRACKSS0_SP", "pin_name" : "TRACK_SS0", "refdes" : "PM1_SP_XF", "part_number" : "462-000309-001", "pin_name_unsanitized" : "TRACK_SS0", "pinuse" : "IN;" }, "U1_XF.W54" : { "pin_type" : "INOUT", "pin_number" : "W54", "node_name" : "U1_XF.W54", "pin_name" : "IO_L8N_T1L_N3_AD5N_32", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "sym_num" : 22, "page_instance" : "I46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30" } ], "pin_name_unsanitized" : "IO_L8N_T1L_N3_AD5N_32", "pin_group" : "ALL_SIGNAL_PINS_22;" }, "R16_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "phys_page" : "page18", "page" : "page18", "block" : "top/xc2_fpga_blk", "ppath" : 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"C48_CPLD", "net_name" : "GND", "part_number" : "402-000010-001" }, "C410_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-001", "pin_name" : "A", "net_name" : "GND", "refdes" : "C410_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I171", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i171" } ], "node_name" : "C410_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "C14_SP_XF.2" : { "node_name" : "C14_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I155", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i155", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3" } ], "refdes" : "C14_SP_XF", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000010-006" }, "C22_E0_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-035", "pin_name" : "A", "refdes" : "C22_E0_XF", "net_name" : "AC_FPGA_CLK_REF_N<1>_1", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "page_instance" : "I49" } ], "node_name" : "C22_E0_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "C280_XF.1" : { "part_number" : "402-000010-035", "pin_name" : "A", "net_name" : "AC_OCL3_PET_N<1>_XF", "refdes" : "C280_XF", "marker_data" : [ { "phys_page" : "page14", "block" : "top/xc2_fpga_blk", "page" : "page14", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "page_instance" : "I183", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i183", "sym_num" : 1 } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C280_XF.1" }, "J3.17" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "\\17\\", "part_number" : "410-000105-001", "net_name" : "GND", "pin_name" : "17", "refdes" : "J3", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page19_i41", "ppath_without_last_instance" : "top/page19", "page_instance" : "I41", "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19", "remapped_page" : null, "page" : "page19", "block" : "top", "phys_page" : "page19" } ], "node_name" : "J3.17", "pin_number" : "17" }, "R68_SP_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page5", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i138", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I138" } ], "net_name" : "CKO_LTM4650_PM7_SP", "pin_name" : "A", "refdes" : "R68_SP_XF", "part_number" : "400-000014-011", "node_name" : "R68_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.AM9" : { "pin_number" : "AM9", "pin_type" : "INOUT", "node_name" : "U1_XF.AM9", "part_number" : "450-000340-001", "net_name" : "AC_PCIE1_TXP<0>_XF", "pin_name" : "PCIE1_TXP0", "refdes" : "U1_XF", "marker_data" : [ { "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I775", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page11", "phys_page" : "page11" } ], "pin_name_unsanitized" : "PCIE1_TXP0", "pin_group" : "ALL_SIGNAL_PINS_3;" }, "R77.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R77.2", "pin_name" : "B", "refdes" : "R77", "net_name" : "P3R3V", "part_number" : "400-000010-006", "marker_data" : [ { "ppath_without_last_instance" : "top/page3", "page_instance" : "I61", "sym_num" : 1, "ppath" : "top/page3_i61", "block" : "top", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page3", "path" : "@top_lib.top(sch_1):page3", "remapped_page" : null } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "R62_FL_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000010-010", "pin_name" : "A", "net_name" : "GND", "refdes" : "R62_FL_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7_i3", "sym_num" : 1, "page_instance" : "I3", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7" } ], "node_name" : "R62_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "C12.2" : { "marker_data" : [ { "page" : "page19", "block" : "top", "phys_page" : "page19", "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19", "remapped_page" : null, "ppath_without_last_instance" : "top/page19", "page_instance" : "I99", "sym_num" : 1, "ppath" : "top/page19_i99" } ], "pin_name" : "B", "refdes" : "C12", "net_name" : "GND", "part_number" : "402-000500-005", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C12.2" }, "PM7_SP_XF.F3" : { "node_name" : "PM7_SP_XF.F3", "pin_type" : "POWER", "pin_number" : "F3", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_22", "marker_data" : [ { "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i151", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I151", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page11" } ], "part_number" : "462-000308-002", "refdes" : "PM7_SP_XF", "pin_name" : "GND_22", "net_name" : "GND" }, "J3_XF.128" : { "part_number" : "410-000300-001", "net_name" : "C2_DDR4_DQ<60>_XF", "pin_name" : "DQ60", "refdes" : "J3_XF", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8" } ], "pinuse" : "TRI;", "pin_name_unsanitized" : "DQ60", "pin_number" : "128", "pin_type" : "INOUT", "node_name" : "J3_XF.128" }, "R10_SP_XF.2" : { "net_name" : "CMP_4650_SP", "pin_name" : "B", "refdes" : "R10_SP_XF", "part_number" : "400-000010-136", "marker_data" : [ { "phys_page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "page_instance" : "I8", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i8", "sym_num" : 1 } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R10_SP_XF.2" }, "C29_FL_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C29_FL_XF.1", "marker_data" : [ { "page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I32", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i32" } ], "part_number" : "402-000050-015", "pin_name" : "A", "net_name" : "UNNAMED_5_LT3071_I30_VIOC_FL", "refdes" : "C29_FL_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "D3_CPLD.2" : { "node_name" : "D3_CPLD.2", "pin_type" : "INOUT", "pin_number" : "2", "pinuse" : "TRI;", "pin_name_unsanitized" : "RED_K", "part_number" : "404-000302-001", "refdes" : "D3_CPLD", "pin_name" : "RED_K", "net_name" : "UNNAMED_9_LUMEXRGBLED_I91_REDK_CPLD", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page9", "page_instance" : "I91", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page9_i91", "page" : "page9", "block" : "top/cpld_blk", "phys_page" : "page9", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "remapped_page" : null } ] }, "PM3_SP_XF.J7" : { "node_name" : "PM3_SP_XF.J7", "pin_type" : "POWER", "pin_number" : "J7", "pin_name_unsanitized" : "EXTVCC", "pinuse" : "POWER;", "pin_name" : "EXTVCC", "net_name" : "NC", "refdes" : "PM3_SP_XF", "part_number" : "462-000308-002", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I152", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i152", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null } ] }, "U1_XF.CC5" : { "pin_number" : "CC5", "pin_type" : "INOUT", "node_name" : "U1_XF.CC5", "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I73", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73", "sym_num" : 38 } ], "pin_name" : "GND_1078", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_38;", "pin_name_unsanitized" : "GND_1078" }, "C26_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C26_XF.2", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I649", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i649", "page" : "page11", "block" : "top/xc2_fpga_blk", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null } ], "part_number" : "402-000010-035", "pin_name" : "B", "refdes" : "C26_XF", "net_name" : "PCIE1_TXP<7>_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "C1_E1_XF.2" : { "part_number" : "402-000010-001", "pin_name" : "B", "net_name" : "PWR_FPGA_3R3V", "refdes" : "C1_E1_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i19", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "page_instance" : "I19", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C1_E1_XF.2" }, "U1_XF.V27" : { "node_name" : "U1_XF.V27", "pin_type" : "INOUT", "pin_number" : "V27", "pin_name_unsanitized" : "VCCINT_4", "pin_group" : "ALL_POWER_PINS_31;", "part_number" : "450-000340-001", "pin_name" : "VCCINT_4", "net_name" : "PWR_VCCINT_XF", "refdes" : "U1_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I186", "sym_num" : 31, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null } ] }, "U1_XF.BA4" : { "pin_group" : "ALL_POWER_PINS_36;", "pin_name_unsanitized" : "GND_714", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "sym_num" : 36, "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24" } ], "part_number" : "450-000340-001", "pin_name" : "GND_714", "refdes" : "U1_XF", "net_name" : "GND", "node_name" : "U1_XF.BA4", "pin_number" : "BA4", "pin_type" : "INOUT" }, "C116_SP_XF.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "page_instance" : "I29", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i29", "sym_num" : 1, "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7" } ], "part_number" : "402-000010-031", "refdes" : "C116_SP_XF", "pin_name" : "A", "net_name" : "PWR_NDIMM_VPP_XF", "node_name" : "C116_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "R19.1" : { "pin_name" : "A", "net_name" : "PSU_1R8V_SDA", "refdes" : "R19", "part_number" : "400-000010-046", "marker_data" : [ { "ppath" : "top/page12_i11", "sym_num" : 1, "page_instance" : "I11", "ppath_without_last_instance" : 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"R3_XF", "part_number" : "400-000014-011" }, "C51_SP_XF.2" : { "node_name" : "C51_SP_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I147", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i147" } ], "part_number" : "402-000202-005", "pin_name" : "B", "net_name" : "CMP_4650_SP", "refdes" : "C51_SP_XF" }, "J1_P0_XF.B2" : { "pin_number" : "B2", "node_name" : "J1_P0_XF.B2", "marker_data" : [ { "phys_page" : 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: "VSS_34", "net_name" : "GND", "node_name" : "J4_XF.193", "pin_number" : "193", "pin_type" : "GROUND" }, "R33.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R33.2", "refdes" : "R33", "pin_name" : "B", "net_name" : "FPGA_VCCAUX_P1R8V", "part_number" : "400-000010-046", "marker_data" : [ { "ppath" : "top/page13_i97", "sym_num" : 1, "page_instance" : "I97", "ppath_without_last_instance" : "top/page13", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page13", "phys_page" : "page13", "page" : "page13", "block" : "top" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "PM4_SP_XF.M12" : { "node_name" : "PM4_SP_XF.M12", "pin_number" : "M12", "pin_type" : "POWER", "pin_name_unsanitized" : "GND_54", "pinuse" : "POWER;", "pin_name" : "GND_54", "net_name" : "GND", "refdes" : "PM4_SP_XF", "part_number" : "462-000308-002", "marker_data" : [ { "remapped_page" : null, "phys_path" : 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"B", "net_name" : "GND", "refdes" : "C240_XF", "marker_data" : [ { "page_instance" : "I21", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i21", "sym_num" : 1, "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23" } ] }, "C191_SP_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C191_SP_XF.2", "part_number" : "402-000010-033", "pin_name" : "B", "refdes" : "C191_SP_XF", "net_name" : "GND", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I114", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i114", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "U1_XF.U53" : { "pin_number" : "U53", "pin_type" : "INOUT", "node_name" : "U1_XF.U53", "part_number" : "450-000340-001", "pin_name" : "IO_L21P_T3L_N4_AD8P_33", "refdes" : "U1_XF", "net_name" : "NC", "marker_data" : [ { "sym_num" : 22, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I46", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30" } ], 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"block" : "top/xc2_fpga_blk/cxltc_2c_x8", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i20", "sym_num" : 1, "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C2_E0_XF.2" }, "U1_XF.R6" : { "node_name" : "U1_XF.R6", "pin_type" : "INOUT", "pin_number" : "R6", "pin_group" : "ALL_SIGNAL_PINS_9;", "pin_name_unsanitized" : "E1S1_PET_N7", "marker_data" : [ { "page" : "page12", "block" : "top/xc2_fpga_blk", "phys_page" : "page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I283", "sym_num" : 9, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "E1S1_PET_N7", "net_name" : "AC_E1S1_PET_N<7>_XF" }, "R6_E1_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R6_E1_XF.1", "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "page_instance" : "I83", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i83", "sym_num" : 1 } ], "part_number" : "400-000010-007", "refdes" : "R6_E1_XF", "pin_name" : "A", "net_name" : "P3R3V", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "J1_E0_XF.B12" : { "part_number" : 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"R2_E2_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "J1_XF.15" : { "pin_name_unsanitized" : "VSS_38", "pinuse" : "UNSPEC;", "pin_name" : "VSS_38", "net_name" : "GND", "refdes" : "J1_XF", "part_number" : "410-000300-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4" } ], "node_name" : "J1_XF.15", "pin_number" : "15", "pin_type" : "GROUND" }, "J1_XF.287" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "path" : 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"pin_type" : "INOUT" }, "C193_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C193_XF.1", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i178", "sym_num" : 1, "page_instance" : "I178", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8" } ], "pin_name" : "A", "refdes" : "C193_XF", "net_name" : "GND", "part_number" : "402-000010-001", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "J1_E0_XF.B26" : { "pin_number" : "B26", "pin_type" : "INPUT", "node_name" : "J1_E0_XF.B26", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "remapped_page" : null, "phys_path" : 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"405-000010-001", "pin_name" : "G", "net_name" : "UNNAMED_20_NMOSFETVMT3_I61_G", "refdes" : "Q14", "node_name" : "Q14.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_XF.AT25" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "sym_num" : 31, "page_instance" : "I186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk" } ], "part_number" : "450-000340-001", "pin_name" : "VCCINT_146", "net_name" : "PWR_VCCINT_XF", "refdes" : "U1_XF", "pin_group" : "ALL_POWER_PINS_31;", "pin_name_unsanitized" : "VCCINT_146", "pin_number" : "AT25", "pin_type" : "INOUT", "node_name" : "U1_XF.AT25" }, "R22_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R22_XF.2", "part_number" : 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"pin_name" : "BIAS", "refdes" : "U2_FL_XF", "net_name" : "P3R3V" }, "J1_P1_XF.A21" : { "node_name" : "J1_P1_XF.A21", "pin_number" : "A21", "pinuse" : "POWER;", "pin_name_unsanitized" : "PWR_5R0V_V2", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "page" : "page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1, "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3" } ], "part_number" : "410-000324-001", "net_name" : "NC", "refdes" : "J1_P1_XF", "pin_name" : "PWR_5R0V_V2" }, "U1_E0_XF.13" : { "marker_data" : [ { "sym_num" : 1, "ppath" : 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"phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I2", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i2" } ] }, "J1_O2_XF.B2" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_8", "part_number" : "410-000324-001", "pin_name" : "GND_8", "net_name" : "GND", "refdes" : "J1_O2_XF", "marker_data" : [ { "page_instance" : "I84", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i30/ocl_x4_conn_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i30/ocl_x4_conn_blk/page3_i84", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i30@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i30@top_lib.ocl_x4_conn_blk(sch_1):page3" } ], "node_name" : "J1_O2_XF.B2", "pin_number" : "B2" }, "U1_XF.BN58" : { "marker_data" : [ { "phys_page" : "PAGE5", "block" : "top/xc2_fpga_blk", "page" : "PAGE5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "sym_num" : 45 } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "C1_DDR4_DQ50", "net_name" : "C1_DDR4_DQ<50>_XF", "pin_group" : "C1_LNIB_1_5_39;", "pin_name_unsanitized" : "C1_DDR4_DQ50", "pin_type" : "INOUT", "pin_number" : "BN58", "node_name" : "U1_XF.BN58" }, "C210_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C210_XF.1", "part_number" : "402-000010-028", "refdes" : "C210_XF", "pin_name" : "A", "net_name" : "GND", "marker_data" : [ { "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I159", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i159" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "C369_XF.1" : { "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page29", "phys_page" : "page29", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i156", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "page_instance" : "I156" } ], "net_name" : "AC_OCL1_FPGA_REFCLK_N_XF", "pin_name" : "A", "refdes" : "C369_XF", "part_number" : "402-000010-035", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C369_XF.1" }, "U1_XF.U14" : { "marker_data" : [ { "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "page_instance" : "I283", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283", "sym_num" : 9 } ], "refdes" : "U1_XF", "pin_name" : "E1S1_REFCLK_N1", "net_name" : "E1S1_FPGA_REFCLK_N<1>_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_9;", "pin_name_unsanitized" : "E1S1_REFCLK_N1", "pin_number" : "U14", "pin_type" : "INOUT", "node_name" : "U1_XF.U14" }, "U6_XF.4" : { "pin_name" : "VCC", "net_name" : "PWR_FPGA_3R3V", "refdes" : "U6_XF", "part_number" : "450-000037-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i1", "sym_num" : 1, "page_instance" : "I1", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk" } ], "pin_name_unsanitized" : "VCC", "pinuse" : "POWER;", "pin_type" : "POWER", "pin_number" : "4", "node_name" : "U6_XF.4" }, "U2_CPLD.6" : { "pin_number" : "6", "pin_type" : "INPUT", "node_name" : "U2_CPLD.6", "part_number" : "450-000331-001", "refdes" : "U2_CPLD", "pin_name" : "S0", "net_name" : "JT_CPLD_INST_F", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page8", "phys_page" : "page8", "block" : "top/cpld_blk", "page" : "page8", "ppath" : "top/page14_i1/cpld_blk/page8_i17", "sym_num" : 1, "page_instance" : "I17", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page8" } ], "pinuse" : "IN;", "pin_name_unsanitized" : "S0" }, "U1_XF.BY59" : { "node_name" : "U1_XF.BY59", "pin_type" : "INOUT", "pin_number" : "BY59", "pin_name_unsanitized" : "C1_DDR4_DQ25", "pin_group" : "C1_LNIB_1_5_39;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "C1_DDR4_DQ25", "net_name" : "C1_DDR4_DQ<25>_XF", "marker_data" : [ { "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "sym_num" : 42, "phys_page" : "PAGE5", "block" : "top/xc2_fpga_blk", "page" : "PAGE5", "remapped_page" : null, "phys_path" : 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"pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-035", "net_name" : "E1S0_PET_P<0>_XF", "pin_name" : "B", "refdes" : "C109_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "page" : "page12", "block" : "top/xc2_fpga_blk", "phys_page" : "page12", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I79" } ], "node_name" : "C109_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C3_CPLD.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-001", "pin_name" : "B", "net_name" : "CPLD_P1R8V_1", "refdes" : "C3_CPLD", "marker_data" : [ { "page_instance" : "I127", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", 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"pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_58", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "sym_num" : 33, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I68" } ], "part_number" : "450-000340-001", "pin_name" : "GND_58", "refdes" : "U1_XF", "net_name" : "GND" }, "U5_XF.32" : { "marker_data" : [ { "page" : "page29", "block" : "top/xc2_fpga_blk", "phys_page" : "page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", 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"refdes" : "J4_XF", "pin_name" : "DQ40", "net_name" : "C3_DDR4_DQ<40>_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "DQ40", "pinuse" : "TRI;", "pin_type" : "INOUT", "pin_number" : "108", "node_name" : "J4_XF.108" }, "U1_XF.AT40" : { "pin_number" : "AT40", "pin_type" : "INOUT", "node_name" : "U1_XF.AT40", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "sym_num" : 36, "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "GND_621", "net_name" : "GND", "pin_group" : "ALL_POWER_PINS_36;", "pin_name_unsanitized" : "GND_621" }, "R74.2" : { "part_number" : "400-000010-010", "net_name" : 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"pin_number" : "AV22", "pin_type" : "INOUT" }, "U1_XF.A15" : { "pin_number" : "A15", "pin_type" : "INOUT", "node_name" : "U1_XF.A15", "part_number" : "450-000340-001", "net_name" : "C3_DDR4_DQ<62>_XF", "pin_name" : "C3_DDR4_DQ62", "refdes" : "U1_XF", "marker_data" : [ { "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "sym_num" : 55, "phys_page" : "PAGE9", "page" : "PAGE9", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9" } ], "pin_name_unsanitized" : "C3_DDR4_DQ62", "pin_group" : "C3_UNIB_1_7_48;" }, "U1_XF.BL63" : { "node_name" : "U1_XF.BL63", "pin_type" : "INOUT", "pin_number" : "BL63", "pin_group" : "C1_UNIB_1_5_39;", "pin_name_unsanitized" : "C1_DDR4_DQ46", "marker_data" : [ { "page" : "PAGE5", "block" : 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"PM2_SP_XF", "net_name" : "P12V_MAIN", "part_number" : "462-000309-001", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I459", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459" } ] }, "PM3_SP_XF.E1" : { "node_name" : "PM3_SP_XF.E1", "pin_type" : "POWER", "pin_number" : "E1", "pin_name_unsanitized" : "GND_13", "pinuse" : "POWER;", "marker_data" : [ { "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I153", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i153" } ], "pin_name" : "GND_13", "refdes" : "PM3_SP_XF", "net_name" : "GND", "part_number" : "462-000308-002" }, "J1_O3_XF.A12" : { "pin_name_unsanitized" : "PERST_F", "pinuse" : "BI;", "marker_data" : [ { "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i52@top_lib.ocl_x4_conn_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i52@top_lib.ocl_x4_conn_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i52/ocl_x4_conn_blk/page3", "page_instance" : "I84", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i52/ocl_x4_conn_blk/page3_i84" } ], "pin_name" : "PERST_F", "refdes" : "J1_O3_XF", "net_name" : "OCL3_3R3V_PERST_F_XF", "part_number" : "410-000324-001", "node_name" : "J1_O3_XF.A12", "pin_type" : "INOUT", "pin_number" : "A12" }, "U1_XF.BE24" : { "node_name" : "U1_XF.BE24", "pin_number" : "BE24", "pin_type" : "INOUT", "pin_name_unsanitized" : "VCCINT_236", "pin_group" : "ALL_POWER_PINS_32;", "net_name" : "PWR_VCCINT_XF", "pin_name" : "VCCINT_236", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i187", "sym_num" : 32, "page_instance" : "I187", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23" } ] }, "U1_XF.N2" : { "node_name" : "U1_XF.N2", "pin_number" : "N2", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_9;", "pin_name_unsanitized" : "E1S1_PER_P2", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page12", "phys_page" : "page12", "sym_num" : 9, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I283" } ], "part_number" : "450-000340-001", "pin_name" : "E1S1_PER_P2", "refdes" : "U1_XF", "net_name" : "E1S1_PER_P<2>_XF" }, "J1_O1_XF.A7" : { "node_name" : "J1_O1_XF.A7", "pin_number" : "A7", "pin_type" : "OUTPUT", "pin_name_unsanitized" : "PERN1", "pinuse" : "OUT;", "refdes" : "J1_O1_XF", "pin_name" : "PERN1", "net_name" : "OCL1_PER_N<1>_XF", "part_number" : "410-000324-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i29@top_lib.ocl_x4_conn_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i29@top_lib.ocl_x4_conn_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i29/ocl_x4_conn_blk/page3", "page_instance" : "I84", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i29/ocl_x4_conn_blk/page3_i84" } ] }, "M12.MTG5" : { "refdes" : "M12", "net_name" : "GND", "pin_name" : "MTG5", "part_number" : "HOLE_RING", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page1_i70", "ppath_without_last_instance" : "top/page1", "page_instance" : "I70", "path" : "@top_lib.top(sch_1):page1", "phys_path" : "@top_lib.top(sch_1):page1", "remapped_page" : null, "page" : "page1", "block" : "top", "phys_page" : "page1" } ], "pin_name_unsanitized" : "MTG5", "pinuse" : "NC;", "pin_number" : "MTG5", "node_name" : "M12.MTG5" }, "U3_XF.D5" : { "pin_number" : "D5", "pin_type" : "NC", "node_name" : "U3_XF.D5", "net_name" : "NC", "pin_name" : "DNU_10", "refdes" : "U3_XF", "part_number" : "450-000341-001", "marker_data" : [ { "phys_page" : "page15", "block" : "top/xc2_fpga_blk", "page" : "page15", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "page_instance" : "I39", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i39", "sym_num" : 2 } ], "pin_name_unsanitized" : "DNU_10", "pinuse" : "UNSPEC;" }, "J3_XF.21" : { "pin_name_unsanitized" : "DQ14", "pinuse" : "TRI;", "pin_name" : "DQ14", "net_name" : "C2_DDR4_DQ<14>_XF", "refdes" : "J3_XF", "part_number" : "410-000300-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null } ], "node_name" : "J3_XF.21", "pin_number" : "21", "pin_type" : "INOUT" }, "U1_CPLD.D11" : { "node_name" : "U1_CPLD.D11", "pin_type" : "INOUT", "pin_number" : "D11", "pinuse" : "BI;", "pin_name_unsanitized" : "FPGA_CPLD_DVAL", "pin_group" : "FP_CFG_4;", "part_number" : "450-000313-001", "pin_name" : "FPGA_CPLD_DVAL", "refdes" : "U1_CPLD", "net_name" : "FPGA_CPLD_DVAL_1", "marker_data" : [ { "block" : "top/cpld_blk", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page6", "page_instance" : "I129", "sym_num" : 4, "ppath" : "top/page14_i1/cpld_blk/page6_i129" } ] }, "U1_CPLD.L11" : { "pin_number" : "L11", "node_name" : "U1_CPLD.L11", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I151", "sym_num" : 7, "ppath" : "top/page14_i1/cpld_blk/page7_i151", "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null } ], "net_name" : "GND", "refdes" : "U1_CPLD", "pin_name" : "GND_16", "part_number" : "450-000313-001", "pin_name_unsanitized" : "GND_16", "pinuse" : "GROUND;" }, "J1_P0_XF.MH1" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "MH1", "part_number" : "410-000324-001", "refdes" : "J1_P0_XF", "pin_name" : "MH1", "net_name" : "GND", "marker_data" : [ { "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3" } ], "node_name" : "J1_P0_XF.MH1", "pin_number" : "MH1" }, "U1_CPLD.K5" : { "pin_name_unsanitized" : "IO6_PL17C_3", "pinuse" : "BI;", "pin_name" : "IO6_PL17C_3", "net_name" : "NC", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "marker_data" : [ { "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152", "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152" } ], "node_name" : "U1_CPLD.K5", "pin_type" : "INOUT", "pin_number" : "K5" }, "U11.11" : { "pinuse" : "IN;", "pin_name_unsanitized" : "AIN6", "part_number" : "450-000333-001", "pin_name" : "AIN6", "refdes" : "U11", "net_name" : "UNNAMED_4_BYPASSCAPNPOL_I51_B", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page4", "path" : "@top_lib.top(sch_1):page4", "phys_page" : "page4", "block" : "top", "page" : "page4", "ppath" : "top/page4_i97", "sym_num" : 1, "page_instance" : "I97", "ppath_without_last_instance" : "top/page4" } ], "node_name" : "U11.11", "pin_type" : "INPUT", "pin_number" : "11" }, "J1_XF.80" : { "node_name" : "J1_XF.80", "pin_type" : "POWER", "pin_number" : "80", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_6", "part_number" : "410-000300-001", "pin_name" : "VDD_6", "net_name" : "PWR_SDIMM_VDD_XF", "refdes" : "J1_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180" } ] }, "U1_XF.BL56" : { "node_name" : "U1_XF.BL56", "pin_number" : "BL56", "pin_type" : "INOUT", "pin_name_unsanitized" : "C1_DDR4_DQ55", "pin_group" : "C1_UNIB_1_5_39;", "pin_name" : "C1_DDR4_DQ55", "refdes" : "U1_XF", "net_name" : "C1_DDR4_DQ<55>_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "sym_num" : 45, "phys_page" : "PAGE5", "block" : "top/xc2_fpga_blk", "page" : "PAGE5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5" } ] }, "U8_FL_XF.1" : { "pin_type" : "POWER", "pin_number" : "1", "node_name" : "U8_FL_XF.1", "marker_data" : [ { "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page10", "page_instance" : "I138", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page10_i138" } ], "part_number" : "450-000011-002", "pin_name" : "out", "net_name" : "PWR_RN_RUC_MGTVCCAUX_XF", "refdes" : "U8_FL_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "\\out\\" }, "U1_XF.AT56" : { "pin_name_unsanitized" : "IO_L3P_T0L_N4_AD15P_27", "pin_group" : "ALL_SIGNAL_PINS_18;", "net_name" : "NC", "pin_name" : "IO_L3P_T0L_N4_AD15P_27", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I51", "sym_num" : 18, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51" } ], "node_name" : "U1_XF.AT56", "pin_number" : "AT56", "pin_type" : "INOUT" }, "C12_E1_XF.1" : { "node_name" : "C12_E1_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "page_instance" : "I95", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i95", "sym_num" : 1 } ], "part_number" : "402-000010-028", "refdes" : "C12_E1_XF", "pin_name" : "A", "net_name" : "GND" }, "J1_XF.4" : { "pin_number" : "4", "pin_type" : "GROUND", "node_name" : "J1_XF.4", "part_number" : "410-000300-001", "pin_name" : "VSS_8", "net_name" : "GND", "refdes" : "J1_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_8" }, "C367_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page9", "phys_page" : "page9", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2417", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2417" } ], "part_number" : "402-000010-035", "net_name" : "C3_SYS_CLK_N_XF", "pin_name" : "B", "refdes" : "C367_XF", "node_name" : "C367_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "PM1_SP_XF.J5" : { "pin_number" : "J5", "node_name" : "PM1_SP_XF.J5", "marker_data" : [ { "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7" } ], "net_name" : "P12V_MAIN", "pin_name" : "VIN_7", "refdes" : "PM1_SP_XF", "part_number" : "462-000309-001", "pin_name_unsanitized" : "VIN_7", "pinuse" : "POWER;" }, "U1_XF.A57" : { "pin_name" : "C2_DDR4_DQ32", "net_name" : "C2_DDR4_DQ<32>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425", "sym_num" : 61, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_page" : "PAGE7", "page" : "PAGE7", "block" : "top/xc2_fpga_blk" } ], "pin_name_unsanitized" : "C2_DDR4_DQ32", "pin_group" : "C2_LNIB_1_6_57;", "pin_number" : "A57", "pin_type" : "INOUT", "node_name" : "U1_XF.A57" }, "U1_XF.B16" : { "pin_number" : "B16", "pin_type" : "INOUT", "node_name" : "U1_XF.B16", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "PAGE9", "phys_page" : "PAGE9", "sym_num" : 55, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2425" } ], "pin_name" : "C3_DDR4_DQS_T15", "net_name" : "C3_RDIMM_DQS_T<16>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_48;", "pin_name_unsanitized" : "C3_DDR4_DQS_T15" }, "U1_XF.AL53" : { "node_name" : "U1_XF.AL53", "pin_number" : "AL53", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_24;", "pin_name_unsanitized" : "IO_L8P_T1L_N2_AD5P_29", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54", "sym_num" : 24, "page_instance" : "I54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk" } ], "refdes" : "U1_XF", "pin_name" : "IO_L8P_T1L_N2_AD5P_29", "net_name" : "NC", "part_number" : "450-000340-001" }, "J1_P1_XF.B17" : { "node_name" : "J1_P1_XF.B17", "pin_number" : "B17", "pin_name_unsanitized" : "GND_13", "pinuse" : "GROUND;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1, "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : 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"page_instance" : "I40" } ], "part_number" : "462-000304-001", "refdes" : "PM4_SD_XF", "pin_name" : "TSNS1B", "net_name" : "UNNAMED_3_LTM4675_I40_TSNS1A_SD" }, "R86_FL_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "refdes" : "R86_FL_XF", "net_name" : "UNNAMED_10_RESISTOR_I75_A_FL", "part_number" : "400-000010-029", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page10", "page_instance" : "I75", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page10_i75", "page" : "page10", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page10", "remapped_page" : null } ], "node_name" : "R86_FL_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "M2.MTG2" : { "pin_name_unsanitized" : "MTG2", "pinuse" : "NC;", "marker_data" : [ { "page" : "page1", "block" : "top", "phys_page" : "page1", "path" : "@top_lib.top(sch_1):page1", "phys_path" : "@top_lib.top(sch_1):page1", "remapped_page" : null, "ppath_without_last_instance" : "top/page1", "page_instance" : "I58", "sym_num" : 1, "ppath" : "top/page1_i58" } ], "net_name" : "GND", "refdes" : "M2", "pin_name" : "MTG2", "part_number" : "HOLE_RING", "node_name" : "M2.MTG2", "pin_number" : "MTG2" }, "U1_XF.BT53" : { "marker_data" : [ { "page" : "PAGE5", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "page_instance" : "I2425", "sym_num" : 40, "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425" } ], "refdes" : "U1_XF", "pin_name" : "C1_DDR4_DQ9", "net_name" : "C1_DDR4_DQ<9>_XF", "part_number" : "450-000340-001", "pin_group" : "C1_LNIB_1_5_39;", "pin_name_unsanitized" : "C1_DDR4_DQ9", "pin_number" : "BT53", "pin_type" : "INOUT", "node_name" : "U1_XF.BT53" }, "J4_XF.178" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180" } ], "refdes" : "J4_XF", "pin_name" : "VSS_89", "net_name" : "GND", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_89", "pinuse" : "UNSPEC;", "pin_number" : "178", "pin_type" : "GROUND", "node_name" : "J4_XF.178" }, "C296_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C296_XF.1", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i52", "sym_num" : 1, "page_instance" : "I52", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk" } ], "net_name" : "GND", "pin_name" : "A", "refdes" : "C296_XF", "part_number" : "402-000010-001", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "J3_XF.263" : { "marker_data" : [ { "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1 } ], "refdes" : "J3_XF", "pin_name" : "VSS_29", "net_name" : "GND", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_29", "pinuse" : "UNSPEC;", "pin_number" : "263", "pin_type" : "GROUND", "node_name" : "J3_XF.263" }, "R187_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R187_XF.2", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_page" : "page13", "block" : "top/xc2_fpga_blk", "page" : "page13", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i211", "sym_num" : 1, "page_instance" : "I211", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13" } ], "net_name" : "E1S2_FPGA_REFCLK_N<1>_XF", "pin_name" : "B", "refdes" : "R187_XF", "part_number" : "400-000010-010", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "R50_FL_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "UNNAMED_7_LT3071_I30_V02_FL", "refdes" : "R50_FL_XF", "part_number" : "400-000010-010", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7_i2", "sym_num" : 1, "page_instance" : "I2", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "phys_page" : "page7", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page7" } ], "node_name" : "R50_FL_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "C58.2" : { "node_name" : "C58.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "ppath_without_last_instance" : "top/page20", "page_instance" : "I35", "sym_num" : 1, "ppath" : "top/page20_i35", "page" : "page20", "block" : "top", "phys_page" : "page20", "path" : "@top_lib.top(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page20", "remapped_page" : null } ], "part_number" : "402-000010-043", "pin_name" : "B", "refdes" : "C58", "net_name" : "GND" }, "C8_E1_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C8_E1_XF.1", "part_number" : "402-000010-028", "refdes" : "C8_E1_XF", "pin_name" : "A", "net_name" : "GND", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i89", "sym_num" : 1, "page_instance" : "I89", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "U1_XF.AA12" : { "node_name" : "U1_XF.AA12", "pin_type" : "INOUT", "pin_number" : "AA12", "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_319", "marker_data" : [ { "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_319", "refdes" : "U1_XF" }, "U1_SP_XF.40" : { "pinuse" : "OUT;", "pin_name_unsanitized" : "REFM", "part_number" : "450-000302-001", "refdes" : "U1_SP_XF", "pin_name" : "REFM", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I51_B_SP", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i168", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I168" } ], "node_name" : "U1_SP_XF.40", "pin_number" : "40", "pin_type" : "OUTPUT" }, "U6_FL_XF.13" : { "pin_number" : "13", "pin_type" : "POWER", "node_name" : "U6_FL_XF.13", "part_number" : "450-000057-001", "net_name" : "GND", "pin_name" : "GND_13", "refdes" : "U6_FL_XF", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i30", "sym_num" : 1 } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_13" }, "R83_SP_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i450", "sym_num" : 1, "page_instance" : "I450", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6" } ], "refdes" : "R83_SP_XF", "pin_name" : "A", "net_name" : "PM2_SP_AGND_SP", "part_number" : "400-000014-011", "node_name" : "R83_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "R132_SP_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page8", "phys_page" : "page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8", "page_instance" : "I96", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8_i96" } ], "pin_name" : "A", "refdes" : "R132_SP_XF", "net_name" : "GND", "part_number" : "400-000015-032", "node_name" : "R132_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "R174_XF.1" : { "node_name" : "R174_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "net_name" : "E1S0_FPGA_REFCLK_P<0>_XF", "pin_name" : "A", "refdes" : "R174_XF", "part_number" : "400-000010-004", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page12", "phys_page" : "page12", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i230", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I230" } ] }, "C195_XF.2" : { "node_name" : "C195_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "page_instance" : "I35", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i35", "sym_num" : 1, "phys_page" : "page20", "block" : "top/xc2_fpga_blk", "page" : "page20", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20" } ], "part_number" : "402-000010-028", "net_name" : "GND", "pin_name" : "B", "refdes" : "C195_XF" }, "U1_XF.BC28" : { "pin_name_unsanitized" : "VCCINT_212", "pin_group" : "ALL_POWER_PINS_32;", "refdes" : "U1_XF", "pin_name" : "VCCINT_212", "net_name" : "PWR_VCCINT_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "sym_num" : 32, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i187", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I187" } ], "node_name" : "U1_XF.BC28", "pin_type" : "INOUT", "pin_number" : "BC28" }, "J2_XF.73" : { "node_name" : "J2_XF.73", "pin_number" : "73", "pin_type" : "POWER", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_1", "part_number" : "410-000300-001", "pin_name" : "VDD_1", "net_name" : "PWR_SDIMM_VDD_XF", "refdes" : "J2_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "block" : "top/xc2_fpga_blk", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null } ] }, "C11_FL_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I8", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i8", "page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null } ], "part_number" : "402-000010-011", "refdes" : "C11_FL_XF", "pin_name" : "B", "net_name" : "GND", "node_name" : "C11_FL_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_CPLD.K9" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VCCIO2_2", "part_number" : "450-000313-001", "refdes" : "U1_CPLD", "pin_name" : "VCCIO2_2", "net_name" : "CPLD_P3R3V", "marker_data" : [ { "page" : "page7", "block" : "top/cpld_blk", "phys_page" : "page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152", "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152" } ], "node_name" : "U1_CPLD.K9", "pin_number" : "K9" }, "PM7_SP_XF.A12" : { "node_name" : "PM7_SP_XF.A12", "pin_number" : "A12", "pin_type" : "POWER", "pin_name_unsanitized" : "VOUT2_5", "pinuse" : "POWER;", "refdes" : "PM7_SP_XF", "pin_name" : "VOUT2_5", "net_name" : "PWR_VCCINT_XF", "part_number" : "462-000308-002", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80", "sym_num" : 1, "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11" } ] }, "R89_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i72", "sym_num" : 1 } ], "part_number" : "400-000010-006", "pin_name" : "B", "refdes" : "R89_XF", "net_name" : "UNNAMED_29_PI6CB33401_I89_BWSELTRI_XF", "node_name" : "R89_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "C1.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page7", "page_instance" : "I8", "sym_num" : 1, "ppath" : "top/page7_i8", "block" : "top", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page7", "path" : "@top_lib.top(sch_1):page7", "remapped_page" : null } ], "refdes" : "C1", "pin_name" : "A", "net_name" : "P3R3V", "part_number" : "402-000010-011", "node_name" : "C1.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "C334_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C334_XF.2", "marker_data" : [ { "phys_page" : "page21", "block" : "top/xc2_fpga_blk", "page" : "page21", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "page_instance" : "I5", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i5", "sym_num" : 1 } ], "pin_name" : "B", "refdes" : "C334_XF", "net_name" : "GND", "part_number" : "402-000015-008", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "U1_XF.BY16" : { "pin_type" : "INOUT", "pin_number" : "BY16", "node_name" : "U1_XF.BY16", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "VCCO_60_2", "net_name" : "PWR_SDIMM_VDD_XF", "marker_data" : [ { "sym_num" : 28, "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i62", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "page_instance" : "I62", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page22", "phys_page" : "page22" } ], "pin_name_unsanitized" : "VCCO_60_2", "pin_group" : "ALL_POWER_PINS_28;" }, "R36_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R36_XF.1", "part_number" : "400-000010-006", "refdes" : "R36_XF", "pin_name" : "A", "net_name" : "GND", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page18", "phys_page" : "page18", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page18", "page_instance" : "I31", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page18_i31" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "U2_ND_XF.8" : { "pin_type" : "POWER", "pin_number" : "8", "node_name" : "U2_ND_XF.8", "part_number" : "450-000059-001", "pin_name" : "GND", "refdes" : "U2_ND_XF", "net_name" : "GND", "marker_data" : [ { "page_instance" : "I19", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4_i19", "sym_num" : 1, "phys_page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "GND" }, "PM1_SP_XF.F3" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_35", "marker_data" : [ { "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I11", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11" } ], "part_number" : "462-000309-001", "refdes" : "PM1_SP_XF", "net_name" : "GND", "pin_name" : "GND_35", "node_name" : "PM1_SP_XF.F3", "pin_number" : "F3" }, "R26_SD_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-006", "pin_name" : "B", "net_name" : "UNNAMED_3_LTM4675_I40_WP_SD", "refdes" : "R26_SD_XF", "marker_data" : [ { "page_instance" : "I42", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i42", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3" } ], "node_name" : "R26_SD_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.BV23" : { "node_name" : "U1_XF.BV23", "pin_type" : "INOUT", "pin_number" : "BV23", "pin_name_unsanitized" : "C0_DDR4_DQ29", "pin_group" : "C0_UNIB_1_4_66;", "refdes" : "U1_XF", "pin_name" : "C0_DDR4_DQ29", "net_name" : "C0_DDR4_DQ<29>_XF", "part_number" : "450-000340-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "PAGE3", "phys_page" : "PAGE3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "page_instance" : "I2425", "sym_num" : 69, "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425" } ] }, "R71.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "ppath" : "top/page4_i116", "sym_num" : 1, "page_instance" : "I116", "ppath_without_last_instance" : "top/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top" } ], "part_number" : "400-000010-010", "refdes" : "R71", "pin_name" : "B", "net_name" : "UNNAMED_4_BYPASSCAPNPOL_I101_B", "node_name" : "R71.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "J3.12" : { "pin_name_unsanitized" : "\\12\\", "pinuse" : "POWER;", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page19", "path" : "@top_lib.top(sch_1):page19", "remapped_page" : null, "block" : "top", "page" : "page19", "phys_page" : "page19", "sym_num" : 1, "ppath" : "top/page19_i41", "ppath_without_last_instance" : "top/page19", "page_instance" : "I41" } ], "net_name" : "P3R3V", "refdes" : "J3", "pin_name" : "12", "part_number" : "410-000105-001", "node_name" : "J3.12", "pin_number" : "12" }, "J2_XF.202" : { "pin_name_unsanitized" : "VSS_59", "pinuse" : "UNSPEC;", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180" } ], "pin_name" : "VSS_59", "net_name" : "GND", "refdes" : "J2_XF", "part_number" : "410-000300-001", "node_name" : "J2_XF.202", "pin_number" : "202", "pin_type" : "GROUND" }, "C107_FL_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "net_name" : "PWR_VCCAUX_B_FL", "pin_name" : "A", "refdes" : "C107_FL_XF", "part_number" : "402-000010-028", "marker_data" : [ { "page_instance" : "I55", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i55", "sym_num" : 1, "phys_page" : "page9", "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9" } ], "node_name" : "C107_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.BT62" : { "pin_number" : "BT62", "pin_type" : "INOUT", "node_name" : "U1_XF.BT62", "net_name" : "C1_RDIMM_DQS_T<4>_XF", "pin_name" : "C1_DDR4_DQS_T8", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_page" : "PAGE5", "block" : "top/xc2_fpga_blk", "page" : "PAGE5", "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "sym_num" : 43, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5" } ], "pin_name_unsanitized" : "C1_DDR4_DQS_T8", "pin_group" : "ALL_SIGNAL_PINS_39;" }, "U1_XF.AG18" : { "node_name" : "U1_XF.AG18", "pin_number" : "AG18", "pin_type" : "INOUT", "pin_name_unsanitized" : "E1S_3R3V_SDA1", "pin_group" : "E1S_SB_0_1_9_9;", "net_name" : "E1S1_3R3V_SDA_XF", "pin_name" : "E1S_3R3V_SDA1", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I283", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283", "sym_num" : 9, "phys_page" : "page12", "block" : "top/xc2_fpga_blk", "page" : "page12", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12" } ] }, "C368_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C368_XF.1", "refdes" : "C368_XF", "pin_name" : "A", "net_name" : "AC_OCL2_CONN_REFCLK_P_XF", "part_number" : "402-000010-035", "marker_data" : [ { "page" : "page29", "block" : "top/xc2_fpga_blk", "phys_page" : "page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "page_instance" : "I169", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i169" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "U1_XF.AL62" : { "node_name" : "U1_XF.AL62", "pin_number" : "AL62", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_18;", "pin_name_unsanitized" : "IO_L18P_T2U_N10_AD2P_28", "marker_data" : [ { "sym_num" : 18, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I51", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30" } ], "part_number" : "450-000340-001", "pin_name" : "IO_L18P_T2U_N10_AD2P_28", "net_name" : "NC", "refdes" : "U1_XF" }, "U1_XF.P15" : { "pin_name_unsanitized" : "MGTVCCAUX_RN_1", "pin_group" : "ALL_POWER_PINS_29;", "part_number" : "450-000340-001", "net_name" : "PWR_RN_RUC_MGTVCCAUX_XF", "pin_name" : "MGTVCCAUX_RN_1", "refdes" : "U1_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page20", "phys_page" : "page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I86", "sym_num" : 29, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i86" } ], "node_name" : "U1_XF.P15", "pin_type" : "INOUT", "pin_number" : "P15" }, "C34_SP_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C34_SP_XF.2", "pin_name" : "B", "refdes" : "C34_SP_XF", "net_name" : "GND", "part_number" : "402-000010-006", "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "page_instance" : "I147", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i147", "sym_num" : 1 } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "NS8_SP_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "NS8_SP_XF.1", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i155", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I155", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "phys_page" : "page11" } ], "net_name" : "GND", "pin_name" : "A", "refdes" : "NS8_SP_XF", "part_number" : "NET_SHORT", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "C57_SP_XF.2" : { "pin_name" : "B", "refdes" : "C57_SP_XF", "net_name" : "GND", "part_number" : "402-000010-003", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "phys_page" : "page10", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i41", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I41" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C57_SP_XF.2" }, "U1_XF.AF25" : { "node_name" : "U1_XF.AF25", "pin_number" : "AF25", "pin_type" : "INOUT", "pin_name_unsanitized" : "VCCINT_99", "pin_group" : "ALL_POWER_PINS_31;", "net_name" : "PWR_VCCINT_XF", "pin_name" : "VCCINT_99", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 31, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I186", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23" } ] }, "U1_CPLD.B3" : { "pin_type" : "INOUT", "pin_number" : "B3", "node_name" : "U1_CPLD.B3", "part_number" : "450-000313-001", "net_name" : "NC", "pin_name" : "IO1_PT9C_0", "refdes" : "U1_CPLD", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7", "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152" } ], "pinuse" : "BI;", "pin_name_unsanitized" : "IO1_PT9C_0" }, "U1_XF.BH58" : { "pin_number" : "BH58", "pin_type" : "INOUT", "node_name" : "U1_XF.BH58", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i47", "sym_num" : 19, "page_instance" : "I47", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "remapped_page" : null, "phys_path" : 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"pin_name" : "A", "refdes" : "C138_XF", "net_name" : "UNNAMED_17_BYPASSCAPNPOL_I48_A_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i48", "sym_num" : 1, "page_instance" : "I48", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_page" : "page17", "block" : "top/xc2_fpga_blk", "page" : "page17" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C138_XF.1" }, "PM2_SP_XF.E7" : { "node_name" : "PM2_SP_XF.E7", "pin_number" : "E7", "pin_name_unsanitized" : "INTVCC0", "pinuse" : "POWER;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I516", "sym_num" : 1, "ppath" : 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"P3R3V", "part_number" : "400-000015-015", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R127_SP_XF.2" }, "C96.3" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "C", "marker_data" : [ { "page_instance" : "I62", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i62", "sym_num" : 1, "phys_page" : "page10", "page" : "page10", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10" } ], "part_number" : "402-000041-001", "net_name" : "GND", "pin_name" : "C", "refdes" : "C96", "node_name" : "C96.3", "pin_type" : "POWER", "pin_number" : "3" }, "U1_XF.J22" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2425", "sym_num" : 7, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "block" : "top/xc2_fpga_blk", "page" : "page9", "phys_page" : "page9", "phys_path" : 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"pin_number" : "1", "pin_type" : "ANALOG" }, "R4_SD_XF.2" : { "node_name" : "R4_SD_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4", "page_instance" : "I28", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4_i28", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "remapped_page" : null } ], "refdes" : "R4_SD_XF", "pin_name" : "B", "net_name" : "VMON_SDIMM_VTT_LIN", "part_number" : "400-000014-011" }, "PM7_SP_XF.H10" : { "pin_name_unsanitized" : "GND_38", "pinuse" : "POWER;", "marker_data" : [ { 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{ "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i457", "sym_num" : 2, "page_instance" : "I457", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ] }, "J1_XF.235" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", 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"pin_number" : "AD60", "pin_type" : "INOUT", "node_name" : "U1_XF.AD60", "marker_data" : [ { "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "page_instance" : "I53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53", "sym_num" : 23 } ], "refdes" : "U1_XF", "pin_name" : "IO_L11N_T1U_N9_GC_31", "net_name" : "NC", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_23;", "pin_name_unsanitized" : "IO_L11N_T1U_N9_GC_31" }, "R95_XF.1" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I41", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i41", "block" : "top/xc2_fpga_blk", "page" : "page17", "phys_page" : "page17", "phys_path" : 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"U1_XF.AV55", "pin_type" : "INOUT", "pin_number" : "AV55" }, "R10_E3_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R10_E3_XF", "pin_name" : "A", "net_name" : "GND", "part_number" : "400-000010-006", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4_i34", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4", "page_instance" : "I34" } ], "node_name" : "R10_E3_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_XF.A20" : { "pin_group" : "C3_LNIB_1_7_48;", "pin_name_unsanitized" : "C3_DDR4_DQ57", "marker_data" : [ { "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "sym_num" : 55, "phys_page" : "PAGE9", "block" : "top/xc2_fpga_blk", "page" : "PAGE9", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9" } ], "net_name" : "C3_DDR4_DQ<57>_XF", "pin_name" : "C3_DDR4_DQ57", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.A20", "pin_number" : "A20", "pin_type" : "INOUT" }, "U1_XF.AD43" : { "pin_number" : "AD43", "pin_type" : "INOUT", "node_name" : "U1_XF.AD43", "part_number" : "450-000340-001", "pin_name" : "VCCAUX_IO_1", "refdes" : "U1_XF", "net_name" : "FPGA_VCCAUX_P1R8V", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i188", "sym_num" : 30, "page_instance" : "I188", "ppath_without_last_instance" : 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"pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "C369_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "page_instance" : "I156", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i156", "sym_num" : 1 } ], "part_number" : "402-000010-035", "pin_name" : "B", "net_name" : "OCL1_FPGA_REFCLK_N_XF", "refdes" : "C369_XF", "node_name" : "C369_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C76_FL_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C76_FL_XF.2", "pin_name" : "B", "net_name" : "GND", "refdes" : "C76_FL_XF", "part_number" : "402-000010-028", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_page" : "page9", "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i21", "sym_num" : 1, "page_instance" : "I21", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "J4_XF.47" : { "pinuse" : "TRI;", "pin_name_unsanitized" : "CB4", "part_number" : "410-000300-001", "pin_name" : "CB4", "net_name" : "C3_DDR4_DQ<68>_XF", "refdes" : "J4_XF", "marker_data" : [ { "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1 } ], "node_name" : "J4_XF.47", "pin_number" : "47", "pin_type" : "INOUT" }, "Q1_XF.3" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i42", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "page_instance" : "I42", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "remapped_page" : null, "page" : "page15", "block" : "top/xc2_fpga_blk", "phys_page" : "page15" } ], "part_number" : "405-000010-001", "pin_name" : "D", "refdes" : "Q1_XF", "net_name" : "UNNAMED_15_MAX4641_I1_IN2_XF", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "D", "pin_number" : "3", "pin_type" : "ANALOG", "node_name" : "Q1_XF.3" }, "C210_XF.2" : { "node_name" : "C210_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I159", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i159", "sym_num" : 1, "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10" } ], "net_name" : "PWR_NDIMM_VDD_XF", "pin_name" : "B", "refdes" : "C210_XF", "part_number" : "402-000010-028" }, "J4_XF.68" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null } ], "part_number" : "410-000300-001", "net_name" : "C3_DDR4_ADR<8>_XF", "pin_name" : "A8", "refdes" : "J4_XF", "pinuse" : "IN;", "pin_name_unsanitized" : "A8", "pin_type" : "INPUT", "pin_number" : "68", "node_name" : "J4_XF.68" }, "U1.8" : { "node_name" : "U1.8", "pin_type" : "INPUT", "pin_number" : "8", "pinuse" : "IN;", "pin_name_unsanitized" : "XA", "part_number" : "450-000308-002", "pin_name" : "XA", "net_name" : "SI5341_XTAL_A", "refdes" : "U1", "marker_data" : [ { "page_instance" : "I51", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i51", "sym_num" : 1, "phys_page" : "page10", "page" : "page10", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10" } ] }, "U1_FL_XF.6" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_6", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I30", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i30", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page5", "phys_page" : "page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null } ], "part_number" : "450-000057-001", "net_name" : "PWR_AVTT_SW_XF", "pin_name" : "VIN_6", "refdes" : "U1_FL_XF", "node_name" : "U1_FL_XF.6", "pin_type" : "POWER", "pin_number" : "6" }, "J2_XF.139" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk", "page" : "page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6" } ], "pin_name" : "SA0", "refdes" : "J2_XF", "net_name" : "C1_DDR4_SA<0>_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "SA0", "pinuse" : "IN;", "pin_type" : "INPUT", "pin_number" : "139", "node_name" : "J2_XF.139" }, "U1_XF.BD46" : { "pin_number" : "BD46", "pin_type" : "INOUT", "node_name" : "U1_XF.BD46", "refdes" : "U1_XF", "pin_name" : "IO_L2P_T0L_N2_24", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20, "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30" } ], "pin_name_unsanitized" : "IO_L2P_T0L_N2_24", "pin_group" : "ALL_SIGNAL_PINS_20;" }, "R254_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R254_XF.1", "part_number" : "400-000010-003", "refdes" : "R254_XF", "pin_name" : "A", "net_name" : "C2_DDR4_VREFCA_1_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page8", "phys_page" : "page8", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i148", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I148" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "C37_SP_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "page_instance" : "I113", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i113", "sym_num" : 1 } ], "part_number" : "402-000010-033", "pin_name" : "B", "refdes" : "C37_SP_XF", "net_name" : "GND", "node_name" : "C37_SP_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "C54_SP_XF.2" : { "node_name" : "C54_SP_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I111", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i111", "sym_num" : 1, "phys_page" : "page5", "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5" } ], "net_name" : "GND", "pin_name" : "B", "refdes" : "C54_SP_XF", "part_number" : "402-000010-033" }, "U1_XF.BM44" : { "node_name" : "U1_XF.BM44", "pin_number" : "BM44", "pin_type" : "INOUT", "pin_name_unsanitized" : "IO_L6N_T0U_N11_AD6N_19", "pin_group" : "ALL_SIGNAL_PINS_17;", "pin_name" : "IO_L6N_T0U_N11_AD6N_19", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "sym_num" : 17, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I50" } ] }, "R189_XF.2" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i213", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I213", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page13", "phys_page" : "page13" } ], "part_number" : "400-000010-010", "pin_name" : "B", "net_name" : "E1S2_FPGA_REFCLK_N<0>_XF", "refdes" : "R189_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R189_XF.2" }, "J1_XF.192" : { "pin_name" : "CB5", "refdes" : "J1_XF", "net_name" : "C0_DDR4_DQ<69>_XF", "part_number" : "410-000300-001", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1 } ], "pin_name_unsanitized" : "CB5", "pinuse" : "TRI;", "pin_type" : "INOUT", "pin_number" : "192", "node_name" : "J1_XF.192" }, "U1_XF.AV59" : { "node_name" : "U1_XF.AV59", "pin_type" : "INOUT", "pin_number" : "AV59", "pin_group" : "ALL_SIGNAL_PINS_18;", "pin_name_unsanitized" : "IO_L1N_T0L_N1_DBC_28", "marker_data" : [ { "sym_num" : 18, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I51", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30" } ], "refdes" : "U1_XF", "pin_name" : "IO_L1N_T0L_N1_DBC_28", "net_name" : "NC", "part_number" : "450-000340-001" }, "R56_XF.1" : { "node_name" : "R56_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i44", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "page_instance" : "I44", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page22", "phys_page" : "page22" } ], "part_number" : "400-000010-090", "refdes" : "R56_XF", "pin_name" : "A", "net_name" : "GND" }, "U3_XF.E5" : { "pin_name_unsanitized" : "DNU_15", "pinuse" : "UNSPEC;", "pin_name" : "DNU_15", "refdes" : "U3_XF", "net_name" : "NC", "part_number" : "450-000341-001", "marker_data" : [ { "page_instance" : "I39", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i39", "sym_num" : 2, "phys_page" : "page15", "block" : "top/xc2_fpga_blk", "page" : "page15", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "path" : 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"C0_DDR4_CS_N<0>_XF", "refdes" : "J1_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4" } ], "node_name" : "J1_XF.84", "pin_number" : "84", "pin_type" : "INPUT" }, "U1.61" : { "pin_number" : "61", "pin_type" : "INPUT", "node_name" : "U1.61", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top", "ppath" : "top/page10_i51", "sym_num" : 1, "page_instance" : "I51", "ppath_without_last_instance" : "top/page10" } ], "part_number" : "450-000308-002", "net_name" : "NC", "pin_name" : "FB_IN_P", "refdes" : "U1", "pinuse" : "IN;", "pin_name_unsanitized" : "FB_IN_P" }, "J5.12" : { "node_name" : "J5.12", "pin_type" : "OUTPUT", "pin_number" : "12", "pin_name_unsanitized" : "CJTAG_REF", "pinuse" : "OUT;", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page15", "path" : "@top_lib.top(sch_1):page15", "phys_page" : "page15", "block" : "top", "page" : "page15", "ppath" : "top/page15_i110", "sym_num" : 1, "page_instance" : "I110", "ppath_without_last_instance" : "top/page15" } ], "pin_name" : "CJTAG_REF", "refdes" : "J5", "net_name" : "CJTAG_REF", "part_number" : "410-000316-001" }, "U1_XF.J15" : { "node_name" : "U1_XF.J15", "pin_type" : "INOUT", "pin_number" : "J15", "pin_group" : "C3_UNIB_1_7_48;", "pin_name_unsanitized" : "C3_DDR4_DQ4", "marker_data" : [ { "phys_page" : "PAGE9", "page" : "PAGE9", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_path" : 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"ALL_SIGNAL_PINS_23;", "pin_type" : "INOUT", "pin_number" : "AF56", "node_name" : "U1_XF.AF56" }, "PM4_ND_XF.B8" : { "pin_type" : "OUTPUT", "pin_number" : "B8", "node_name" : "PM4_ND_XF.B8", "part_number" : "462-000304-001", "pin_name" : "SW0", "refdes" : "PM4_ND_XF", "net_name" : "SW0_NODE_ND", "marker_data" : [ { "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I13", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i13" } ], "pinuse" : "OUT;", "pin_name_unsanitized" : "SW0" }, "PM5_SP_XF.H6" : { "pin_number" : "H6", "pin_type" : "POWER", "node_name" : "PM5_SP_XF.H6", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i79", "sym_num" : 2, "page_instance" : "I79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_page" : "page5", "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "part_number" : "462-000308-002", "pin_name" : "GND_35", "net_name" : "GND", "refdes" : "PM5_SP_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_35" }, "M11.MTG5" : { "node_name" : "M11.MTG5", "pin_number" : "MTG5", "pin_name_unsanitized" : "MTG5", "pinuse" : "NC;", "marker_data" : [ { "page_instance" : "I69", "ppath_without_last_instance" : "top/page1", "ppath" : "top/page1_i69", "sym_num" : 1, "phys_page" : "page1", "block" : "top", "page" : "page1", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page1", "path" : "@top_lib.top(sch_1):page1" } ], "refdes" : "M11", "net_name" : "GND", "pin_name" : "MTG5", "part_number" : "HOLE_RING" }, "D3_CPLD.1" : { "pin_type" : "INOUT", "pin_number" : "1", "node_name" : "D3_CPLD.1", "part_number" : "404-000302-001", "pin_name" : "CMN_A", "refdes" : "D3_CPLD", "net_name" : "CPLD_P3R3V", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page9_i91", "sym_num" : 1, "page_instance" : "I91", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page9", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "phys_page" : "page9", "page" : "page9", "block" : "top/cpld_blk" } ], "pinuse" : "TRI;", "pin_name_unsanitized" : "CMN_A" }, "PM3_SP_XF.D8" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I151", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i151", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null } ], "pin_name" : "TRACK2", "refdes" : "PM3_SP_XF", "net_name" : "SS_LTM4650_SP", "part_number" : "462-000308-002", "pin_name_unsanitized" : "TRACK2", "pinuse" : "IN;", "pin_number" : "D8", "pin_type" : "INPUT", "node_name" : "PM3_SP_XF.D8" }, "U1_XF.U46" : { "pin_type" : "INOUT", "pin_number" : "U46", "node_name" : "U1_XF.U46", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" : 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: "I76" } ], "part_number" : "400-000010-033", "pin_name" : "B", "refdes" : "R36_SP_XF", "net_name" : "VS_AVTT_LIN_P_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "Q6.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "Q6.2", "marker_data" : [ { "phys_page" : "page20", "page" : "page20", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page20", "page_instance" : "I20", "ppath_without_last_instance" : "top/page20", "ppath" : "top/page20_i20", "sym_num" : 1 } ], "pin_name" : "S", "net_name" : "GND", "refdes" : "Q6", "part_number" : "405-000010-001", "pin_name_unsanitized" : "S", "pinuse" : "UNSPEC;" }, "U1_XF.BL44" : { "node_name" : "U1_XF.BL44", "pin_number" : "BL44", "pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_37;", "pin_name_unsanitized" : "GND_916", "marker_data" : [ { "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "sym_num" : 37 } ], "pin_name" : "GND_916", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "R119_SP_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R119_SP_XF.2", "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "page_instance" : "I101", "ppath_without_last_instance" : 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"phys_path" : "@top_lib.top(sch_1):page7", "path" : "@top_lib.top(sch_1):page7", "remapped_page" : null } ] }, "R13_SP_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "page_instance" : "I8", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i8", "sym_num" : 1 } ], "net_name" : "UNNAMED_4_CAPACITOR_I11_A_SP", "pin_name" : "A", "refdes" : "R13_SP_XF", "part_number" : "400-000010-136", "node_name" : "R13_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "C7_MP.1" : { "part_number" : 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"C18_SP_XF.1", "net_name" : "PWR_VCCINT_XF", "pin_name" : "A", "refdes" : "C18_SP_XF", "part_number" : "402-000010-033", "marker_data" : [ { "page_instance" : "I29", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i29", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "C29.2" : { "node_name" : "C29.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "refdes" : "C29", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000500-005", "marker_data" : [ { "ppath" : "top/page19_i73", "sym_num" : 1, "page_instance" : "I73", "ppath_without_last_instance" : "top/page19", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page19", "path" : "@top_lib.top(sch_1):page19", "phys_page" : "page19", "block" : "top", "page" : "page19" } ] }, "J4_XF.13" : { "pin_name_unsanitized" : "VSS_33", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10" } ], "net_name" : "GND", "pin_name" : "VSS_33", "refdes" : "J4_XF", "part_number" : "410-000300-001", "node_name" : "J4_XF.13", "pin_type" : "GROUND", "pin_number" : "13" }, "R99_SP_XF.2" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I512", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i512", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null } ], "refdes" : "R99_SP_XF", "pin_name" : "B", "net_name" : "VMON_AVTT_SW_XF", "part_number" : "400-000014-011", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R99_SP_XF.2" }, "PM4_ND_XF.J2" : { "node_name" : "PM4_ND_XF.J2", "pin_type" : "POWER", "pin_number" : "J2", "pin_name_unsanitized" : "GND_32", "pinuse" : "POWER;", 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: "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I78", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i78" } ], "pin_name" : "SW1", "refdes" : "PM5_SP_XF", "net_name" : "SW1_4650_TR_SP", "part_number" : "462-000308-002", "pin_name_unsanitized" : "SW1", "pinuse" : "OUT;" }, "C116_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-035", "pin_name" : "B", "refdes" : "C116_XF", "net_name" : "E1S1_PET_P<1>_XF", "marker_data" : [ { "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "page_instance" : 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"SGND_4", "net_name" : "SGND_PM7_SP", "part_number" : "462-000308-002", "marker_data" : [ { "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "page_instance" : "I150", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i150", "sym_num" : 3 } ], "pin_name_unsanitized" : "SGND_4", "pinuse" : "POWER;", "pin_number" : "F7", "pin_type" : "POWER", "node_name" : "PM7_SP_XF.F7" }, "J2_P1_XF.A3" : { "node_name" : "J2_P1_XF.A3", "pin_number" : "A3", "pin_type" : "OUTPUT", "pin_name_unsanitized" : "PERP0", "pinuse" : "OUT;", "refdes" : "J2_P1_XF", "pin_name" : "PERP0", "net_name" : "PCIE1_RXP<4>_XF", "part_number" : "410-000324-001", "marker_data" : [ { "page_instance" : "I85", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i85", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3" } ] }, "R36_SP_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000010-033", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I150_A_SP", "pin_name" : "A", "refdes" : "R36_SP_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : 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"410-000300-001", "pin_name" : "DQS3_T", "net_name" : "C3_RDIMM_DQS_T<3>_XF", "refdes" : "J4_XF", "pinuse" : "TRI;", "pin_name_unsanitized" : "DQS3_T", "pin_number" : "186", "pin_type" : "INOUT", "node_name" : "J4_XF.186" }, "U1_E3_XF.28" : { "pinuse" : "OUT;", "pin_name_unsanitized" : "Q3_N", "part_number" : "450-000345-001", "refdes" : "U1_E3_XF", "pin_name" : "Q3_N", "net_name" : "AC_FPGA_CLK_REF_N<1>_2", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4_i37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4", "page_instance" : "I37", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4" } ], "node_name" : "U1_E3_XF.28", "pin_number" : "28", "pin_type" : "OUTPUT" }, "C14_MP.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "GND", "refdes" : "C14_MP", "part_number" : "402-000010-029", "marker_data" : [ { "ppath" : "top/page18_i1/mgmt_pwr_block/page4_i6", "sym_num" : 1, "page_instance" : "I6", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "phys_page" : "page4", "block" : "top/mgmt_pwr_block", "page" : "page4" } ], "node_name" : "C14_MP.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.B61" : { "marker_data" : [ { "sym_num" : 33, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I68", "path" : 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"sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i2" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R33_FL_XF.1" }, "C215_XF.1" : { "marker_data" : [ { "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I164", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i164" } ], "part_number" : "402-000010-001", "pin_name" : "A", "refdes" : "C215_XF", "net_name" : "GND", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C215_XF.1" }, "U2_XF.C4" : { "pin_type" : "INOUT", "pin_number" : "C4", "node_name" : "U2_XF.C4", "net_name" : "CFG_FLASH_D02_0_XF", "pin_name" : "DQ2_W_N", "refdes" : "U2_XF", "part_number" : "450-000341-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "phys_page" : "page15", "page" : "page15", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i37", "sym_num" : 1, "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15" } ], "pin_name_unsanitized" : "DQ2_W_N", "pinuse" : "TRI;" }, "C312_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i91", "sym_num" : 1, "page_instance" : "I91", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_page" : "page13", "page" : "page13", "block" : "top/xc2_fpga_blk" } ], "net_name" : "AC_E1S3_PET_N<2>_XF", "pin_name" : "A", "refdes" : "C312_XF", "part_number" : "402-000010-035", "node_name" : "C312_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "J1_E0_XF.A36" : { "pin_number" : "A36", "pin_type" : "OUTPUT", "node_name" : "J1_E0_XF.A36", "marker_data" : [ { "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3_i101", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3" } ], "pin_name" : "PERN6", "refdes" : "J1_E0_XF", "net_name" : "E1S0_PER_N<6>_XF", "part_number" : "410-000317-001", "pin_name_unsanitized" : "PERN6", "pinuse" : "OUT;" }, "CLK_VIS_P_XF.1" : { "pin_number" : "1", "pin_type" : "POWER", "node_name" : "CLK_VIS_P_XF.1", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page16_i97", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page16", "page_instance" : "I97", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "remapped_page" : null, "page" : "page16", "block" : "top/xc2_fpga_blk", "phys_page" : "page16" } ], "pin_name" : "1", "net_name" : "CLK_O_VIS_P_XF", "refdes" : "CLK_VIS_P_XF", "part_number" : "TP_020_VIA", "pin_name_unsanitized" : "\\1\\", "pinuse" : "POWER;" }, "U1_SP_XF.43" : { "pinuse" : "IN;", "pin_name_unsanitized" : "ISENSEP1", "part_number" : "450-000302-001", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I147_A_SP", "pin_name" : "ISENSEP1", "refdes" : "U1_SP_XF", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I168", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i168" } ], "node_name" : "U1_SP_XF.43", "pin_number" : "43", "pin_type" : "INPUT" }, "U6_FL_XF.10" : { "pin_type" : "POWER", "pin_number" : "10", "node_name" : "U6_FL_XF.10", "part_number" : "450-000057-001", "refdes" : "U6_FL_XF", "pin_name" : "GND_10", "net_name" : "GND", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i30", "sym_num" : 1 } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_10" }, "J4_XF.173" : { "pin_name" : "VSS_78", "net_name" : "GND", "refdes" : "J4_XF", "part_number" : "410-000300-001", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10" } ], "pin_name_unsanitized" : "VSS_78", "pinuse" : "UNSPEC;", "pin_type" : "GROUND", "pin_number" : "173", "node_name" : "J4_XF.173" }, "J3_XF.268" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_42", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page8", "phys_page" : "page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180" } ], "part_number" : "410-000300-001", "pin_name" : "VSS_42", "net_name" : "GND", "refdes" : "J3_XF", "node_name" : "J3_XF.268", "pin_number" : "268", "pin_type" : "GROUND" }, "R1_P0_XF.2" : { "part_number" : "400-000014-011", "refdes" : "R1_P0_XF", "pin_name" : "B", "net_name" : "PCIE0_REFP_XF", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "page_instance" : "I156", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i156", "sym_num" : 1 } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R1_P0_XF.2" }, "U1_XF.Y46" : { "pin_number" : "Y46", "pin_type" : "INOUT", "node_name" : "U1_XF.Y46", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I69", "sym_num" : 34, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "part_number" : "450-000340-001", "pin_name" : "GND_312", "refdes" : "U1_XF", "net_name" : "GND", "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_312" }, "PM3_SP_XF.J3" : { "pin_name_unsanitized" : "VIN_2", "pinuse" : "POWER;", "marker_data" : [ { "phys_page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "page_instance" : "I152", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i152", "sym_num" : 1 } ], "pin_name" : "VIN_2", "refdes" : "PM3_SP_XF", "net_name" : "P12V_4650_BL_SP", "part_number" : "462-000308-002", "node_name" : "PM3_SP_XF.J3", "pin_type" : "POWER", "pin_number" : "J3" }, "PM7_SP_XF.D9" : { "node_name" : "PM7_SP_XF.D9", "pin_number" : "D9", "pin_type" : "POWER", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_9", "marker_data" : [ { "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i151", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I151", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page11" } ], "part_number" : "462-000308-002", "refdes" : "PM7_SP_XF", "pin_name" : "GND_9", "net_name" : "GND" }, "C11_E1_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C11_E1_XF.2", "part_number" : "402-000010-028", "refdes" : "C11_E1_XF", "pin_name" : "B", "net_name" : "P12V_MAIN", "marker_data" : [ { "page_instance" : "I94", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i94", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "remapped_page" : null, "phys_path" : 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"U1_XF.AB42" }, "SPARE_TP_P.1" : { "pin_type" : "POWER", "pin_number" : "1", "node_name" : "SPARE_TP_P.1", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top", "ppath" : "top/page10_i164", "sym_num" : 1, "page_instance" : "I164", "ppath_without_last_instance" : "top/page10" } ], "refdes" : "SPARE_TP_P", "pin_name" : "1", "net_name" : "SP_REF_CLK_P<0>", "part_number" : "TP_020_VIA", "pin_name_unsanitized" : "\\1\\", "pinuse" : "POWER;" }, "J2_XF.115" : { "pinuse" : "TRI;", "pin_name_unsanitized" : "DQ42", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : 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"POWER", "pin_number" : "A10", "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT2_3", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i80", "sym_num" : 1 } ], "part_number" : "462-000308-002", "refdes" : "PM4_SP_XF", "pin_name" : "VOUT2_3", "net_name" : "PWR_VCCINT_XF" }, "C84.2" : { "marker_data" : [ { "page_instance" : "I47", "ppath_without_last_instance" : "top/page19", "ppath" : "top/page19_i47", "sym_num" : 1, "phys_page" : "page19", "block" : "top", "page" : "page19", "remapped_page" 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"net_name" : "GND", "pin_name" : "GND_12", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_12", "pin_number" : "B14", "node_name" : "J2_P0_XF.B14" }, "PM2_SP_XF.F7" : { "pin_number" : "F7", "node_name" : "PM2_SP_XF.F7", "part_number" : "462-000309-001", "pin_name" : "GND_48", "refdes" : "PM2_SP_XF", "net_name" : "GND", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "phys_page" : "page6", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I459" } ], "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_48" }, "U1_CPLD.R9" : { "pin_group" : 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"net_name" : "AC_OCL1_CONN_REFCLK_N_XF", "refdes" : "U7_XF", "node_name" : "U7_XF.18", "pin_number" : "18", "pin_type" : "OUTPUT" }, "U2_FL_XF.17" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT_17", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6", "page_instance" : "I30", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6_i30", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "remapped_page" : null } ], "part_number" : "450-000057-001", "refdes" : "U2_FL_XF", "pin_name" : "VOUT_17", "net_name" : "PWR_AVTT_RS_XF", "node_name" : "U2_FL_XF.17", "pin_type" : "POWER", "pin_number" : "17" }, "PM5_SP_XF.G11" : { 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: "U1_E0_XF", "pinuse" : "OUT;", "pin_name_unsanitized" : "Q2_N", "pin_type" : "OUTPUT", "pin_number" : "23", "node_name" : "U1_E0_XF.23" }, "C81_ND_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C81_ND_XF.2", "marker_data" : [ { "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I28", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i28" } ], "part_number" : "402-000010-034", "refdes" : "C81_ND_XF", "pin_name" : "B", "net_name" : "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" 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"pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "NS2_FL_XF.2" }, "J2_XF.5" : { "pin_type" : "INOUT", "pin_number" : "5", "node_name" : "J2_XF.5", "part_number" : "410-000300-001", "pin_name" : "DQ0", "net_name" : "C1_DDR4_DQ<0>_XF", "refdes" : "J2_XF", "marker_data" : [ { "phys_page" : "page6", "block" : "top/xc2_fpga_blk", "page" : "page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1 } ], "pinuse" : "TRI;", "pin_name_unsanitized" : "DQ0" }, "PM2_SP_XF.V4" : { "pin_number" : "V4", "node_name" : "PM2_SP_XF.V4", "net_name" : "GND", "pin_name" : "GND_77", "refdes" : "PM2_SP_XF", "part_number" : "462-000309-001", "marker_data" : [ { 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} ], "node_name" : "J3.14", "pin_number" : "14" }, "PM2_SP_XF.T9" : { "pin_name_unsanitized" : "VIN_16", "pinuse" : "POWER;", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I459", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459" } ], "net_name" : "P12V_MAIN", "refdes" : "PM2_SP_XF", "pin_name" : "VIN_16", "part_number" : "462-000309-001", "node_name" : "PM2_SP_XF.T9", "pin_number" : "T9" }, "J3_XF.123" : { "node_name" : "J3_XF.123", "pin_number" : "123", "pin_type" : "GROUND", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : 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: [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I54", "sym_num" : 24, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54", "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null } ], "pin_name_unsanitized" : "IO_L4P_T0U_N6_DBC_AD7P_72", "pin_group" : "ALL_SIGNAL_PINS_24;", "pin_number" : "U30", "pin_type" : "INOUT", "node_name" : "U1_XF.U30" }, "R61_FL_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-010", "pin_name" : "B", "refdes" : "R61_FL_XF", "net_name" : "UNNAMED_6_LT3071_I30_V01_FL", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "phys_path" : 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"ALL_POWER_PINS_29;", "pin_name_unsanitized" : "MGTAVTT_RS_14", "marker_data" : [ { "sym_num" : 29, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I86", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "page" : "page20", "block" : "top/xc2_fpga_blk", "phys_page" : "page20" } ], "refdes" : "U1_XF", "pin_name" : "MGTAVTT_RS_14", "net_name" : "PWR_AVTT_RS_XF", "part_number" : "450-000340-001" }, "U1_XF.AM5" : { "node_name" : "U1_XF.AM5", "pin_type" : "INOUT", "pin_number" : "AM5", "pin_name_unsanitized" : "GND_542", "pin_group" : "ALL_POWER_PINS_35;", "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_542", "refdes" : "U1_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : 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"net_name" : "GND", "refdes" : "U1_XF" }, "C49_SP_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C49_SP_XF.2", "part_number" : "402-000010-001", "pin_name" : "B", "refdes" : "C49_SP_XF", "net_name" : "GND", "marker_data" : [ { "page_instance" : "I3", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i3", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "C23_E2_XF.2" : { "node_name" : "C23_E2_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i51", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4" } ], "net_name" : "E1S2_FPGA_REFCLK_N<0>_XF", "pin_name" : "B", "refdes" : "C23_E2_XF", "part_number" : "402-000010-035" }, "C322_XF.2" : { "node_name" : "C322_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000015-007", "pin_name" : "B", "net_name" : "GND", "refdes" : "C322_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i142", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I142", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23" } ] }, "C153_XF.2" : { "part_number" : "402-000010-035", "pin_name" : "B", "net_name" : "E1S2_PET_P<2>_XF", "refdes" : "C153_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i78", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I78", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "page" : "page13", "block" : "top/xc2_fpga_blk", "phys_page" : "page13" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C153_XF.2" }, "U7_XF.15" : { "node_name" : "U7_XF.15", "pin_number" : "15", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDDO_1", "part_number" : "450-000345-001", "pin_name" : "VDDO_1", "refdes" : "U7_XF", "net_name" : "PWR_FPGA_3R3V", "marker_data" : [ { "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "page_instance" : "I89", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i89", "sym_num" : 1 } ] }, "R3_ND_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "POK_OD_NDIMM_VDD_SW", "refdes" : "R3_ND_XF", "part_number" : "400-000014-011", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I61", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i61", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null } ], "node_name" : "R3_ND_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C225_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-028", "pin_name" : "B", "net_name" : "GND", "refdes" : "C225_XF", "marker_data" : [ { "page_instance" : "I173", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : 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: "E1S3_PER_N5", "pin_group" : "ALL_SIGNAL_PINS_10;", "pin_number" : "AL5", "pin_type" : "INOUT", "node_name" : "U1_XF.AL5" }, "C281_XF.1" : { "node_name" : "C281_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "phys_page" : "page14", "page" : "page14", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "page_instance" : "I184", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i184", "sym_num" : 1 } ], "part_number" : "402-000010-035", "net_name" : "AC_OCL3_PET_N<0>_XF", "pin_name" : "A", "refdes" : "C281_XF" }, "U1_XF.AC32" : { "marker_data" : [ { "page_instance" : "I186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : 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"pin_name_unsanitized" : "TSNS0_2", "pinuse" : "IN;", "pin_number" : "D3", "pin_type" : "INPUT", "node_name" : "PM4_ND_XF.D3" }, "U1_E0_XF.10" : { "pinuse" : "BI;", "pin_name_unsanitized" : "SDATA", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i37", "sym_num" : 1, "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4" } ], "part_number" : "450-000345-001", "pin_name" : "SDATA", "net_name" : "UNNAMED_4_PI6CB33401_I37_SDATA_E0", "refdes" : "U1_E0_XF", "node_name" : "U1_E0_XF.10", "pin_type" : "INOUT", "pin_number" : "10" }, "F7_ND_XF.1" : { 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"marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "sym_num" : 7, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_page" : "page9", "block" : "top/xc2_fpga_blk", "page" : "page9" } ], "node_name" : "U1_XF.U25", "pin_number" : "U25", "pin_type" : "INOUT" }, "PM3_SP_XF.B3" : { "node_name" : "PM3_SP_XF.B3", "pin_type" : "POWER", "pin_number" : "B3", "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT1_8", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I152", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i152", "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page10", "path" : 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"@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14" } ], "pin_name" : "B", "net_name" : "OCL1_PET_P<2>_XF", "refdes" : "C182_XF", "part_number" : "402-000010-035" }, "C483_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C483_XF.2", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i6", "sym_num" : 1, "page_instance" : "I6", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_page" : "page20", "page" : "page20", "block" : "top/xc2_fpga_blk" } ], "part_number" : "402-000010-001", "refdes" : "C483_XF", "pin_name" : "B", "net_name" : "GND", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "J2_P0_XF.B13" : { "node_name" : "J2_P0_XF.B13", "pin_type" : "INPUT", "pin_number" : "B13", "pinuse" : "IN;", "pin_name_unsanitized" : "REFCLK_N", "part_number" : "410-000324-001", "pin_name" : "REFCLK_N", "refdes" : "J2_P0_XF", "net_name" : "NC", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3", "page_instance" : "I85", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i85", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "remapped_page" : null } ] }, "J3_XF.50" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_36", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8" } ], "part_number" : "410-000300-001", "pin_name" : "VSS_36", "net_name" : "GND", "refdes" : "J3_XF", "node_name" : "J3_XF.50", "pin_number" : "50", "pin_type" : "GROUND" }, "R95_SP_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I134", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i134", "sym_num" : 1, "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11" } ], "net_name" : "UNNAMED_11_LTM4650FIXED_I150_PGOOD1_SP", "pin_name" : "A", "refdes" : "R95_SP_XF", "part_number" : "400-000014-011", "node_name" : "R95_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "J1_XF.142" : { "part_number" : "410-000300-001", "pin_name" : "VPP_1", "net_name" : "PWR_SDIMM_VPP_XF", "refdes" : "J1_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VPP_1", "pin_number" : "142", "pin_type" : "POWER", "node_name" : "J1_XF.142" }, "U1_E1_XF.30" : { "node_name" : "U1_E1_XF.30", "pin_number" : "30", "pinuse" : "NC;", "pin_name_unsanitized" : "NC_7", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i37", "sym_num" : 1 } ], "part_number" : "450-000345-001", "net_name" : "NC", "pin_name" : "NC_7", "refdes" : "U1_E1_XF" }, "C213_XF.2" : { "node_name" : "C213_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-028", "pin_name" : "B", "refdes" : "C213_XF", "net_name" : "PWR_NDIMM_VDD_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i162", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I162", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page10", "phys_page" : "page10" } ] }, "J1_XF.194" : { "pin_type" : "INOUT", "pin_number" : "194", "node_name" : "J1_XF.194", "pin_name" : "CB1", "net_name" : "C0_DDR4_DQ<65>_XF", "refdes" : "J1_XF", "part_number" : "410-000300-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4" } ], "pin_name_unsanitized" : "CB1", "pinuse" : "TRI;" }, "C11_ND_XF.1" : { "node_name" : "C11_ND_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "C11_ND_XF", "pin_name" : "A", "net_name" : "PWR_NDIMM_VDD_XF", "part_number" : "402-000010-039", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "page_instance" : "I38", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i38", "sym_num" : 1 } ] }, "PM4_SP_XF.E4" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_16", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i79", "sym_num" : 2, "page_instance" : "I79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4" } ], "part_number" : "462-000308-002", "net_name" : "GND", "pin_name" : "GND_16", "refdes" : "PM4_SP_XF", "node_name" : "PM4_SP_XF.E4", "pin_type" : "POWER", "pin_number" : "E4" }, "U1_XF.BD26" : { "pin_name" : "GND_790", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "sym_num" : 36, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "pin_name_unsanitized" : "GND_790", "pin_group" : "ALL_POWER_PINS_36;", "pin_type" : "INOUT", "pin_number" : "BD26", "node_name" : "U1_XF.BD26" }, "J2_XF.135" : { "pin_type" : "INOUT", "pin_number" : "135", "node_name" : "J2_XF.135", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page6", "phys_page" : "page6", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180" } ], "pin_name" : "DQ62", "refdes" : "J2_XF", "net_name" : "C1_DDR4_DQ<62>_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "DQ62", "pinuse" : "TRI;" }, "PM4_ND_XF.L4" : { "net_name" : "GND", "pin_name" : "GND_41", "refdes" : "PM4_ND_XF", "part_number" : "462-000304-001", "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i20", "sym_num" : 2 } ], "pin_name_unsanitized" : "GND_41", "pinuse" : "POWER;", "pin_number" : "L4", "pin_type" : "POWER", "node_name" : "PM4_ND_XF.L4" }, "U1_XF.BM24" : { "node_name" : "U1_XF.BM24", "pin_number" : "BM24", "pin_type" : "INOUT", "pin_name_unsanitized" : "C0_DDR4_DQS_T9", "pin_group" : "ALL_SIGNAL_PINS_66;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "C0_DDR4_DQS_T9", "net_name" : "C0_RDIMM_DQS_T<13>_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "sym_num" : 70, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_page" : "PAGE3", "page" : "PAGE3", "block" : "top/xc2_fpga_blk" } ] }, "U1_XF.AB11" : { "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_341", "marker_data" : [ { "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I69", "sym_num" : 34, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69" } ], "pin_name" : "GND_341", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.AB11", "pin_type" : "INOUT", "pin_number" : "AB11" }, "U1_XF.J19" : { "node_name" : "U1_XF.J19", "pin_number" : "J19", "pin_type" : "INOUT", "pin_name_unsanitized" : "IO_T0U_N12_VRP_77", "pin_group" : "ALL_SIGNAL_PINS_28;", "pin_name" : "IO_T0U_N12_VRP_77", "refdes" : "U1_XF", "net_name" : "UNNAMED_22_RESISTOR_I35_B_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page22", "block" : "top/xc2_fpga_blk", "page" : "page22", "remapped_page" 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"pin_type" : "ANALOG", "node_name" : "C63_XF.1" }, "U1_XF.AR7" : { "pin_type" : "INOUT", "pin_number" : "AR7", "node_name" : "U1_XF.AR7", "pin_name" : "GND_593", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "sym_num" : 35 } ], "pin_name_unsanitized" : "GND_593", "pin_group" : "ALL_POWER_PINS_35;" }, "U1_XF.BR35" : { "pin_type" : "INOUT", "pin_number" : "BR35", "node_name" : "U1_XF.BR35", "refdes" : "U1_XF", "pin_name" : "IO_L8N_T1L_N3_AD5N_67", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page30", 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"net_name" : "PWR_VCCINT_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_31;", "pin_name_unsanitized" : "VCCINT_77", "pin_number" : "AD23", "pin_type" : "INOUT", "node_name" : "U1_XF.AD23" }, "R201_XF.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "phys_page" : "page13", "page" : "page13", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "page_instance" : "I222", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i222", "sym_num" : 1 } ], "part_number" : "400-000010-004", "pin_name" : "A", "net_name" : "E1S3_FPGA_REFCLK_P<1>_XF", "refdes" : "R201_XF", "node_name" : "R201_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U11_FL_XF.10" : { "pin_number" : "10", "pin_type" : "POWER", "node_name" : "U11_FL_XF.10", "part_number" : "450-000057-001", "pin_name" : "GND_10", "net_name" : "GND", "refdes" : "U11_FL_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_page" : "page9", "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i66", "sym_num" : 1, "page_instance" : "I66", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_10" }, "PM4_SD_XF.M1" : { "part_number" : "462-000304-001", "refdes" : "PM4_SD_XF", "pin_name" : "VOUT1_4", "net_name" : "PWR_SDIMM_VDD_XF", "marker_data" : [ { "page_instance" : "I13", "ppath_without_last_instance" : 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"pin_group" : "ALL_SIGNAL_PINS_20;" }, "J1_O3_XF.B4" : { "pin_name_unsanitized" : "PETN0", "pinuse" : "IN;", "net_name" : "OCL3_PET_N<0>_XF", "pin_name" : "PETN0", "refdes" : "J1_O3_XF", "part_number" : "410-000324-001", "marker_data" : [ { "page_instance" : "I84", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i52/ocl_x4_conn_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i52/ocl_x4_conn_blk/page3_i84", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i52@top_lib.ocl_x4_conn_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i52@top_lib.ocl_x4_conn_blk(sch_1):page3" } ], "node_name" : "J1_O3_XF.B4", "pin_number" : "B4", "pin_type" : "INPUT" }, "C31_SP_XF.1" : { "node_name" : "C31_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", 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], "refdes" : "R102_XF", "pin_name" : "B", "net_name" : "UNNAMED_17_RESISTOR_I55_A_XF", "part_number" : "400-000010-101", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "U1_XF.BB27" : { "pin_group" : "ALL_POWER_PINS_31;", "pin_name_unsanitized" : "VCCINT_199", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I186", "sym_num" : 31, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186" } ], "pin_name" : "VCCINT_199", "refdes" : "U1_XF", "net_name" : "PWR_VCCINT_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.BB27", "pin_number" : "BB27", "pin_type" : "INOUT" }, "C25_FL_XF.1" : { "net_name" : "GND", "pin_name" : "A", "refdes" : "C25_FL_XF", "part_number" : "402-000020-011", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8", "page_instance" : "I25", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8_i25", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page8", "phys_page" : "page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "remapped_page" : null } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C25_FL_XF.1" }, "U1_XF.AA21" : { "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_322", "marker_data" : [ { "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : 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], "node_name" : "C29_FL_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "R10_SP_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000010-136", "net_name" : "UNNAMED_10_CAPACITOR_I11_A_SP", "pin_name" : "A", "refdes" : "R10_SP_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I8", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i8", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null } ], "node_name" : "R10_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_XF.AB50" : { "pin_type" : "INOUT", "pin_number" : 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"pin_name_unsanitized" : "GND_612", "pin_group" : "ALL_POWER_PINS_36;" }, "U1_XF.BL10" : { "node_name" : "U1_XF.BL10", "pin_type" : "INOUT", "pin_number" : "BL10", "pin_name_unsanitized" : "OCL2_PET_N2", "pin_group" : "ALL_SIGNAL_PINS_12;", "pin_name" : "OCL2_PET_N2", "refdes" : "U1_XF", "net_name" : "AC_OCL2_PET_N<2>_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I275", "sym_num" : 12, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i275", "page" : "page14", "block" : "top/xc2_fpga_blk", "phys_page" : "page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null } ] }, "J4_XF.228" : { "pin_type" : "INPUT", "pin_number" : "228", "node_name" : "J4_XF.228", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", 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"pin_name_unsanitized" : "IO_L5N_T0U_N9_AD14N_70", "pin_group" : "ALL_SIGNAL_PINS_25;", "pin_type" : "INOUT", "pin_number" : "R37", "node_name" : "U1_XF.R37" }, "PM5_SP_XF.F1" : { "node_name" : "PM5_SP_XF.F1", "pin_type" : "POWER", "pin_number" : "F1", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_20", "part_number" : "462-000308-002", "pin_name" : "GND_20", "refdes" : "PM5_SP_XF", "net_name" : "GND", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5", "phys_page" : "page5", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I79" } ] }, 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"GND", "refdes" : "C3_FL_XF", "part_number" : "402-000010-011", "marker_data" : [ { "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6", "page_instance" : "I8", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6_i8" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "R7_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000010-006", "pin_name" : "A", "net_name" : "GND", "refdes" : "R7_XF", "marker_data" : [ { "page" : "page18", "block" : "top/xc2_fpga_blk", "phys_page" : "page18", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page18", "page_instance" : "I33", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page18_i33" } ], "node_name" : "R7_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "R6_SD_XF.2" : { "node_name" : "R6_SD_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000014-011", "pin_name" : "B", "net_name" : "UNNAMED_3_LTM4675_I40_VTRIM0CFG_SD", "refdes" : "R6_SD_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i66", "sym_num" : 1, "page_instance" : "I66", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk" } ] }, "U1_XF.L42" : { "pin_number" : "L42", "pin_type" : "INOUT", "node_name" : "U1_XF.L42", "pin_name" : "IO_L13P_T2L_N0_GC_QBC_38", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 26, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I58", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31" } ], "pin_name_unsanitized" : "IO_L13P_T2L_N0_GC_QBC_38", "pin_group" : "ALL_SIGNAL_PINS_26;" }, "U1_XF.BP60" : { "pin_name" : "IO_T3U_N12_22", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "page_instance" : "I55", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i55", "sym_num" : 15 } ], "pin_name_unsanitized" : "IO_T3U_N12_22", "pin_group" : "ALL_SIGNAL_PINS_15;", "pin_type" : "INOUT", "pin_number" : "BP60", "node_name" : "U1_XF.BP60" }, "PM4_SD_XF.B9" : { "net_name" : "P12V_FUSED_4675_SD", "pin_name" : "VIN0_2", "refdes" : "PM4_SD_XF", "part_number" : "462-000304-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i13", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page3" } ], "pin_name_unsanitized" : "VIN0_2", "pinuse" : "POWER;", "pin_number" : "B9", "pin_type" : "POWER", "node_name" : "PM4_SD_XF.B9" }, "J1_P0_XF.B21" : { "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1 } ], "part_number" : "410-000324-001", "refdes" : "J1_P0_XF", "pin_name" : "PWR_3R3V_VACT_TX", "net_name" : "NC", "pinuse" : "POWER;", "pin_name_unsanitized" : "PWR_3R3V_VACT_TX", "pin_number" : "B21", "node_name" : "J1_P0_XF.B21" }, "R115_SP_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i25", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I25", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7" } ], "net_name" : "UNNAMED_7_BYPASSCAPNPOL_I44_B_SP", "pin_name" : "B", "refdes" : "R115_SP_XF", "part_number" : "400-000014-011", "node_name" : "R115_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "J2_XF.67" : { "node_name" : "J2_XF.67", "pin_type" : "POWER", "pin_number" : "67", "pin_name_unsanitized" : "VDD_23", "pinuse" : "POWER;", "pin_name" : "VDD_23", "refdes" : "J2_XF", "net_name" : "PWR_SDIMM_VDD_XF", "part_number" : "410-000300-001", "marker_data" : [ { "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1 } ] }, "R121_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I190", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i190", "sym_num" : 1, "phys_page" : "page17", "block" : "top/xc2_fpga_blk", "page" : "page17", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17" } ], "net_name" : "UNNAMED_17_RESISTOR_I105_B_XF", "pin_name" : "A", "refdes" : "R121_XF", "part_number" : "400-000010-001", "node_name" : "R121_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "J2_XF.48" : { "pin_type" : "GROUND", "pin_number" : "48", "node_name" : "J2_XF.48", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page6", "phys_page" : "page6" } ], "net_name" : "GND", "pin_name" : "VSS_30", "refdes" : "J2_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_30", "pinuse" : "UNSPEC;" }, "U1_XF.AD9" : { "pin_type" : "INOUT", "pin_number" : "AD9", "node_name" : "U1_XF.AD9", "marker_data" : [ { "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "page_instance" : "I56", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i56", "sym_num" : 14 } ], "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "MGTYTXP3_231", "refdes" : "U1_XF", "pin_group" : "ALL_SIGNAL_PINS_14;", "pin_name_unsanitized" : "MGTYTXP3_231" }, "U1_XF.AE47" : { "pin_type" : "INOUT", "pin_number" : "AE47", "node_name" : "U1_XF.AE47", "marker_data" : [ { "sym_num" : 23, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I53", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31" } ], "part_number" : "450-000340-001", "pin_name" : "IO_L19P_T3L_N0_DBC_AD9P_30", "refdes" : "U1_XF", "net_name" : "NC", "pin_group" : "ALL_SIGNAL_PINS_23;", "pin_name_unsanitized" : "IO_L19P_T3L_N0_DBC_AD9P_30" }, "P4.2" : { "pin_number" : "2", "pin_type" : "INOUT", "node_name" : "P4.2", "pin_name" : "P2", "net_name" : "UNNAMED_20_FERRITEBEAD_I56_B", "refdes" : "P4", "part_number" : "410-000322-001", "marker_data" : [ { "block" : "top", "page" : "page20", "phys_page" : "page20", "phys_path" : "@top_lib.top(sch_1):page20", "path" : "@top_lib.top(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page20", "page_instance" : "I26", "sym_num" : 1, "ppath" : "top/page20_i26" } ], "pin_name_unsanitized" : "P2", "pinuse" : "BI;" }, "R16_E2_XF.2" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4", "page_instance" : "I41", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i41", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null } ], "part_number" : "400-000010-010", "refdes" : "R16_E2_XF", "pin_name" : "B", "net_name" : "GND", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R16_E2_XF.2" }, "P1.3" : { "pin_number" : "3", "pin_type" : "INOUT", "node_name" : "P1.3", "marker_data" : [ { "ppath" : "top/page20_i29", "sym_num" : 1, "page_instance" : "I29", "ppath_without_last_instance" : "top/page20", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page20", "path" : "@top_lib.top(sch_1):page20", "phys_page" : "page20", "block" : "top", "page" : "page20" } ], "refdes" : "P1", "pin_name" : "P3", "net_name" : "NC", "part_number" : "410-000320-001", "pin_name_unsanitized" : "P3", "pinuse" : "BI;" }, "J2.4" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_4", "marker_data" : [ { "block" : "top", "page" : "page19", "phys_page" : "page19", "phys_path" : "@top_lib.top(sch_1):page19", "path" : "@top_lib.top(sch_1):page19", "remapped_page" : null, "ppath_without_last_instance" : "top/page19", "page_instance" : "I34", "sym_num" : 1, "ppath" : "top/page19_i34" } ], "part_number" : "410-000047-001", "pin_name" : "GND_4", "refdes" : "J2", "net_name" : "GND", "node_name" : "J2.4", "pin_type" : "POWER", "pin_number" : "4" }, "U1_XF.BY10" : { "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_1038", "refdes" : "U1_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "sym_num" : 38, "ppath" : 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"pin_number" : "1", "node_name" : "R3_E0_XF.1" }, "FB1_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "FB1_XF.2", "part_number" : "401-000001-003", "net_name" : "GND", "pin_name" : "B", "refdes" : "FB1_XF", "marker_data" : [ { "page" : "page17", "block" : "top/xc2_fpga_blk", "phys_page" : "page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I22", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i22" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "C194_SP_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "page_instance" : "I29", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "ppath" : 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"pin_group" : "ALL_POWER_PINS_34;" }, "C32.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C32.1", "pin_name" : "A", "net_name" : "GND", "refdes" : "C32", "part_number" : "402-000010-026", "marker_data" : [ { "block" : "top", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page10", "page_instance" : "I59", "sym_num" : 1, "ppath" : "top/page10_i59" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "J2_XF.226" : { "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1, "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : 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"net_name" : "GND" }, "U1_XF.BY24" : { "pin_name_unsanitized" : "C0_DDR4_DQ3", "pin_group" : "C0_LNIB_1_4_66;", "part_number" : "450-000340-001", "pin_name" : "C0_DDR4_DQ3", "refdes" : "U1_XF", "net_name" : "C0_DDR4_DQ<3>_XF", "marker_data" : [ { "sym_num" : 66, "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "page_instance" : "I2425", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "PAGE3", "phys_page" : "PAGE3" } ], "node_name" : "U1_XF.BY24", "pin_type" : "INOUT", "pin_number" : "BY24" }, "C45.1" : { "marker_data" : [ { "page_instance" : "I63", "ppath_without_last_instance" : "top/page4", "ppath" : "top/page4_i63", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top", "remapped_page" : null, "path" : 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"node_name" : "J2_XF.45" }, "C466_XF.2" : { "node_name" : "C466_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "GND", "refdes" : "C466_XF", "part_number" : "402-000010-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I80", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "page" : "page20", "block" : "top/xc2_fpga_blk", "phys_page" : "page20" } ] }, "J1_PX1_XF.A2" : { "pin_number" : "A2", "node_name" : "J1_PX1_XF.A2", "net_name" : "NC", "refdes" : "J1_PX1_XF", "pin_name" : "P12V_3", "part_number" : "410-000328-001", "marker_data" : [ { "sym_num" : 1, "ppath" : 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1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i22" } ], "node_name" : "C3_E2_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.BL21" : { "pin_group" : "ALL_SIGNAL_PINS_66;", "pin_name_unsanitized" : "C0_DDR4_DQS_T8", "marker_data" : [ { "sym_num" : 70, "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "page_instance" : "I2425", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "PAGE3", "phys_page" : "PAGE3" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "C0_DDR4_DQS_T8", "net_name" : "C0_RDIMM_DQS_T<4>_XF", "node_name" : "U1_XF.BL21", "pin_type" : "INOUT", "pin_number" : "BL21" }, "R111_FL_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R111_FL_XF.1", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null, "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page9", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i52", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I52" } ], "part_number" : "400-000010-010", "net_name" : "GND", "pin_name" : "A", "refdes" : "R111_FL_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "U1_XF.AT21" : { "pin_number" : "AT21", "pin_type" : "INOUT", "node_name" : "U1_XF.AT21", "marker_data" : [ { "page_instance" : "I188", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i188", 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"pin_group" : "ALL_POWER_PINS_30;" }, "U1_XF.U57" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34, "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24" } ], "net_name" : "GND", "pin_name" : "GND_244", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_244", "pin_type" : "INOUT", "pin_number" : "U57", "node_name" : "U1_XF.U57" }, "PM2_SP_XF.G9" : { "pinuse" : "IN;", "pin_name_unsanitized" : "FB0", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i516", "ppath_without_last_instance" : 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"VSS_56", "pin_number" : "165", "pin_type" : "GROUND", "node_name" : "J1_XF.165" }, "PM4_SP_XF.L12" : { "part_number" : "462-000308-002", "pin_name" : "GND_52", "net_name" : "GND", "refdes" : "PM4_SP_XF", "marker_data" : [ { "page_instance" : "I79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i79", "sym_num" : 2, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_52", "pin_number" : "L12", "pin_type" : "POWER", "node_name" : "PM4_SP_XF.L12" }, "C60_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C60_XF.2", "pin_name" : "B", "refdes" : "C60_XF", "net_name" : "GND", "part_number" : "402-000015-007", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "page_instance" : "I53", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page22", "phys_page" : "page22" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "C466_XF.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "phys_page" : "page20", "block" : "top/xc2_fpga_blk", "page" : "page20", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "page_instance" : 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"pin_number" : "Y39", "node_name" : "U1_XF.Y39" }, "U1_XF.BJ8" : { "pin_group" : "ALL_POWER_PINS_37;", "pin_name_unsanitized" : "GND_880", "marker_data" : [ { "sym_num" : 37, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I72", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24" } ], "net_name" : "GND", "pin_name" : "GND_880", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.BJ8", "pin_number" : "BJ8", "pin_type" : "INOUT" }, "R93_SP_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I443", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : 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"top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6" } ], "refdes" : "J2_XF", "pin_name" : "DQ55", "net_name" : "C1_DDR4_DQ<55>_XF", "part_number" : "410-000300-001", "node_name" : "J2_XF.269", "pin_type" : "INOUT", "pin_number" : "269" }, "J2_P0_XF.MH4" : { "part_number" : "410-000324-001", "pin_name" : "MH4", "refdes" : "J2_P0_XF", "net_name" : "GND", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i85", "sym_num" : 1, "page_instance" : "I85", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk" } ], "pinuse" : "GROUND;", "pin_name_unsanitized" : "MH4", "pin_number" : "MH4", "node_name" : "J2_P0_XF.MH4" }, "U1_XF.V23" : { "pin_name_unsanitized" : "VCCINT_2", "pin_group" : "ALL_POWER_PINS_31;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "VCCINT_2", "net_name" : "PWR_VCCINT_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I186", "sym_num" : 31, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186" } ], "node_name" : "U1_XF.V23", "pin_number" : "V23", "pin_type" : "INOUT" }, "U1_XF.AT11" : { "node_name" : "U1_XF.AT11", "pin_number" : "AT11", "pin_type" : "INOUT", "pin_name_unsanitized" : "GND_613", "pin_group" : "ALL_POWER_PINS_36;", "refdes" : "U1_XF", "pin_name" : "GND_613", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I71", "sym_num" : 36, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ] }, "U4_SP_XF.4" : { "pin_number" : "4", "pin_type" : "INOUT", "node_name" : "U4_SP_XF.4", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page12_i42", "sym_num" : 1, "page_instance" : "I42", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page12", "remapped_page" : null, "phys_path" : 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"pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C98_SP_XF.1" }, "J1_XF.276" : { "part_number" : "410-000300-001", "net_name" : "GND", "pin_name" : "VSS_66", "refdes" : "J1_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_66", "pin_type" : "GROUND", "pin_number" : "276", "node_name" : "J1_XF.276" }, "C20_FL_XF.1" : { "node_name" : "C20_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "C20_FL_XF", "pin_name" : "A", "net_name" : "GND", "part_number" : "402-000020-011", "marker_data" : [ { "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page5", "phys_page" : "page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I25", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i25" } ] }, "R19_SP_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R19_SP_XF.2", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I160", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i160", "page" : "page3", "block" : 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"node_name" : "C51.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.T4" : { "pin_type" : "INOUT", "pin_number" : "T4", "node_name" : "U1_XF.T4", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page12", "phys_page" : "page12", "sym_num" : 9, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I283" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "E1S1_PER_P6", "net_name" : "E1S1_PER_P<6>_XF", "pin_group" : "ALL_SIGNAL_PINS_9;", "pin_name_unsanitized" : "E1S1_PER_P6" }, "PM5_SP_XF.K10" : { "pin_number" : "K10", "pin_type" : "POWER", "node_name" : "PM5_SP_XF.K10", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i80", "sym_num" : 1, "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5" } ], "pin_name" : "VIN_11", "refdes" : "PM5_SP_XF", "net_name" : "P12V_4650_TR_SP", "part_number" : "462-000308-002", "pin_name_unsanitized" : "VIN_11", "pinuse" : "POWER;" }, "R152_XF.2" : { "node_name" : "R152_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "UNNAMED_29_PI6CB33401_I63_SADRTRI_XF", "refdes" : "R152_XF", "part_number" : "400-000010-006", "marker_data" : [ { "path" : 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"page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i37", "sym_num" : 1 } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "J1_E0_XF.A5" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_5", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3", "page_instance" : "I101", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3_i101", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null } ], "part_number" : "410-000317-001", "net_name" : "GND", "refdes" : "J1_E0_XF", "pin_name" : "GND_5", "node_name" : "J1_E0_XF.A5", "pin_number" : "A5" }, "J3_XF.154" : { "refdes" : "J3_XF", "pin_name" : "VSS_26", "net_name" : "GND", "part_number" : "410-000300-001", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8" } ], "pin_name_unsanitized" : "VSS_26", "pinuse" : "UNSPEC;", "pin_number" : "154", "pin_type" : "GROUND", "node_name" : "J3_XF.154" }, "U4_FL_XF.13" : { "node_name" : "U4_FL_XF.13", "pin_type" : "POWER", "pin_number" : "13", "pin_name_unsanitized" : "GND_13", "pinuse" : "POWER;", "marker_data" : [ { "phys_path" : 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"@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk", "page" : "page6" } ], "part_number" : "410-000300-001", "net_name" : "GND", "pin_name" : "VSS_61", "refdes" : "J2_XF", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_61" }, "U1_XF.H9" : { "pin_name_unsanitized" : "MGTYTXP2_236", "pin_group" : "ALL_SIGNAL_PINS_14;", "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "MGTYTXP2_236", "refdes" : "U1_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "sym_num" : 14, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i56", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I56" } ], "node_name" : "U1_XF.H9", "pin_type" : "INOUT", "pin_number" : "H9" }, "J1_P1_XF.MH4" : { "pin_number" : "MH4", "node_name" : "J1_P1_XF.MH4", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1, "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3" } ], "net_name" : "GND", "refdes" : "J1_P1_XF", "pin_name" : "MH4", "part_number" : "410-000324-001", "pin_name_unsanitized" : "MH4", "pinuse" : "GROUND;" }, "R141_XF.2" : { "part_number" : "400-000010-097", "refdes" : "R141_XF", "pin_name" : "B", "net_name" : "GND", "marker_data" : [ { "page" : "page17", "block" : "top/xc2_fpga_blk", "phys_page" : "page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I114", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i114" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R141_XF.2" }, "U1_XF.BN48" : { "pin_group" : "ALL_SIGNAL_PINS_17;", "pin_name_unsanitized" : "IO_L10N_T1U_N7_QBC_AD4N_19", "marker_data" : [ { "sym_num" : 17, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I50", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30" } ], "part_number" : "450-000340-001", "pin_name" : "IO_L10N_T1U_N7_QBC_AD4N_19", "refdes" : "U1_XF", "net_name" : "NC", "node_name" : "U1_XF.BN48", "pin_type" : "INOUT", "pin_number" : "BN48" }, "U1_XF.R17" : { "node_name" : "U1_XF.R17", "pin_number" : "R17", "pin_type" : "INOUT", "pin_name_unsanitized" : "E1S_3R3V_CKEN0_F3", "pin_group" : "E1S_SB_2_3_10_10;", "part_number" : "450-000340-001", "pin_name" : "E1S_3R3V_CKEN0_F3", "net_name" : "E1S3_3R3V_CKEN_F<0>_XF", "refdes" : "U1_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page13", "phys_page" : "page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I251", "sym_num" : 10, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i251" } ] }, "U1_CPLD.R6" : { "pin_name_unsanitized" : "IO9_PB7B_2", "pinuse" : "BI;", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page7_i152", "sym_num" : 8, "page_instance" : "I152", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top/cpld_blk" } ], "refdes" : "U1_CPLD", "pin_name" : "IO9_PB7B_2", "net_name" : "NC", "part_number" : "450-000313-001", "node_name" : "U1_CPLD.R6", "pin_number" : "R6", "pin_type" : "INOUT" }, "C12_MP.1" : { "part_number" : "402-000050-016", "pin_name" : "A", "net_name" : "UNNAMED_4_RESISTOR_I2_B_MP", "refdes" : "C12_MP", "marker_data" : [ { "ppath" : "top/page18_i1/mgmt_pwr_block/page4_i11", "sym_num" : 1, "page_instance" : "I11", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/mgmt_pwr_block" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C12_MP.1" }, "U1_XF.F16" : { "pin_number" : "F16", "pin_type" : "INOUT", "node_name" : "U1_XF.F16", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_page" : "PAGE9", "block" : "top/xc2_fpga_blk", "page" : "PAGE9", "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "sym_num" : 56, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9" } ], "pin_name" : "C3_DDR4_DQ64", "refdes" : "U1_XF", "net_name" : "C3_DDR4_DQ<64>_XF", "part_number" : "450-000340-001", "pin_group" : "C3_LNIB_1_7_48;", "pin_name_unsanitized" : "C3_DDR4_DQ64" }, "J3_XF.14" : { "pin_type" : "INOUT", "pin_number" : "14", "node_name" : "J3_XF.14", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8" } ], "pin_name" : "DQ12", "net_name" : "C2_DDR4_DQ<12>_XF", "refdes" : "J3_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "DQ12", "pinuse" : "TRI;" }, "U1_XF.P34" : { "marker_data" : [ { "sym_num" : 24, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I54", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L7P_T1L_N0_QBC_AD13P_72", "net_name" : "NC", "pin_group" : "ALL_SIGNAL_PINS_24;", "pin_name_unsanitized" : "IO_L7P_T1L_N0_QBC_AD13P_72", "pin_type" : "INOUT", "pin_number" : "P34", "node_name" : "U1_XF.P34" }, "U1_XF.T54" : { "pin_type" : "INOUT", "pin_number" : "T54", "node_name" : "U1_XF.T54", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : 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"top/page6_i428/xc2_fpga_blk/page12" } ], "net_name" : "E1S1_PET_N<4>_XF", "pin_name" : "B", "refdes" : "C133_XF", "part_number" : "402-000010-035", "node_name" : "C133_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "C101_SP_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C101_SP_XF.2", "pin_name" : "B", "refdes" : "C101_SP_XF", "net_name" : "GND", "part_number" : "402-000010-041", "marker_data" : [ { "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "page_instance" : "I491", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i491", "sym_num" : 1 } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "U1_XF.BY49" : { "node_name" : "U1_XF.BY49", "pin_type" : "INOUT", "pin_number" : "BY49", "pin_name_unsanitized" : "C1_DDR4_ADR5", "pin_group" : "C1_ACTL_5_5;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "C1_DDR4_ADR5", "net_name" : "C1_DDR4_ADR<5>_XF", "marker_data" : [ { "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "page_instance" : "I2425", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "remapped_page" : null, "page" : "page5", "block" : "top/xc2_fpga_blk", "phys_page" : "page5" } ] }, "M16.MTG3" : { "pin_number" : "MTG3", "node_name" : "M16.MTG3", "pin_name" : "MTG3", "refdes" : "M16", "net_name" : "GND", "part_number" : "HOLE_RING", "marker_data" : [ { "ppath" : "top/page1_i77", "sym_num" : 1, "page_instance" : "I77", "ppath_without_last_instance" : "top/page1", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page1", "path" : "@top_lib.top(sch_1):page1", "phys_page" : "page1", "block" : "top", "page" : "page1" } ], "pin_name_unsanitized" : "MTG3", "pinuse" : "NC;" }, "C432_XF.2" : { "node_name" : "C432_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-001", "refdes" : "C432_XF", "pin_name" : "B", "net_name" : "PWR_SDIMM_VDD_XF", "marker_data" : [ { "phys_page" : "page6", "block" : "top/xc2_fpga_blk", "page" : "page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "page_instance" : "I169", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i169", "sym_num" : 1 } ] }, "U1_XF.BP1" : { "pin_number" : "BP1", "pin_type" : "INOUT", "node_name" : "U1_XF.BP1", "pin_name" : "GND_945", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I72", "sym_num" : 37, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "pin_name_unsanitized" : "GND_945", "pin_group" : "ALL_POWER_PINS_37;" }, "U1_XF.U15" : { "node_name" : "U1_XF.U15", "pin_number" : "U15", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_9;", "pin_name_unsanitized" : "E1S1_REFCLK_P1", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : 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: "ANALOG", "pin_number" : "2" }, "U1.33" : { "pin_name_unsanitized" : "VDDO3", "pinuse" : "POWER;", "marker_data" : [ { "block" : "top", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page10", "page_instance" : "I51", "sym_num" : 1, "ppath" : "top/page10_i51" } ], "pin_name" : "VDDO3", "net_name" : "VDDO3", "refdes" : "U1", "part_number" : "450-000308-002", "node_name" : "U1.33", "pin_number" : "33", "pin_type" : "POWER" }, "U1_XF.E7" : { "pin_name_unsanitized" : "GND_65", "pin_group" : "ALL_POWER_PINS_33;", "refdes" : "U1_XF", "pin_name" : "GND_65", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : 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"pin_number" : "27", "pin_type" : "OUTPUT" }, "U1_XF.H50" : { "refdes" : "U1_XF", "pin_name" : "VCCO_36_1", "net_name" : "PWR_NDIMM_VDD_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page21", "page" : "page21", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "page_instance" : "I67", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i67", "sym_num" : 27 } ], "pin_name_unsanitized" : "VCCO_36_1", "pin_group" : "ALL_POWER_PINS_27;", "pin_number" : "H50", "pin_type" : "INOUT", "node_name" : "U1_XF.H50" }, "U1_XF.BY20" : { "pin_group" : "ALL_SIGNAL_PINS_4;", "pin_name_unsanitized" : "C0_SYS_CLK_P", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : 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"node_name" : "U1_XF.W16", "pin_type" : "INOUT", "pin_number" : "W16" }, "J1_E1_XF.B29" : { "pin_number" : "B29", "node_name" : "J1_E1_XF.B29", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "page_instance" : "I101" } ], "part_number" : "410-000317-001", "pin_name" : "GND_24", "net_name" : "GND", "refdes" : "J1_E1_XF", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_24" }, "U1_XF.BD44" : { "node_name" : "U1_XF.BD44", "pin_number" : "BD44", "pin_type" : "INOUT", "pin_name_unsanitized" : "GND_799", "pin_group" : "ALL_POWER_PINS_36;", "refdes" : "U1_XF", "pin_name" : "GND_799", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 36, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I71", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24" } ] }, "U1_XF.L61" : { "pin_group" : "C2_ACTL_6_6;", "pin_name_unsanitized" : "C2_DDR4_ADR3", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : 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"ANALOG", "node_name" : "C197_XF.1" }, "U1_XF.BM46" : { "node_name" : "U1_XF.BM46", "pin_type" : "INOUT", "pin_number" : "BM46", "pin_name_unsanitized" : "IO_L11N_T1U_N9_GC_19", "pin_group" : "ALL_SIGNAL_PINS_17;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L11N_T1U_N9_GC_19", "net_name" : "NC", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30", "sym_num" : 17, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I50" } ] }, "M18.MTG4" : { "pin_number" : "MTG4", "node_name" : "M18.MTG4", "marker_data" : [ { "phys_page" : "page1", "page" : "page1", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page1", "phys_path" : "@top_lib.top(sch_1):page1", "page_instance" : "I76", "ppath_without_last_instance" : "top/page1", "ppath" : "top/page1_i76", "sym_num" : 1 } ], "part_number" : "HOLE_RING", "refdes" : "M18", "net_name" : "GND", "pin_name" : "MTG4", "pinuse" : "NC;", "pin_name_unsanitized" : "MTG4" }, "C79_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C79_XF.1", "marker_data" : [ { "page_instance" : "I150", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i150", "sym_num" : 1, "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23" } ], "net_name" : "PWR_VCCINT_XF", "pin_name" : "A", "refdes" : "C79_XF", "part_number" : "402-000015-007", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "U1_FL_XF.4" : { "node_name" : "U1_FL_XF.4", "pin_type" : "POWER", "pin_number" : "4", "pin_name_unsanitized" : "GND_4", "pinuse" : "POWER;", "pin_name" : "GND_4", "net_name" : "GND", "refdes" : "U1_FL_XF", "part_number" : "450-000057-001", "marker_data" : [ { "phys_page" : "page5", "page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i30", "sym_num" : 1 } ] }, "R80_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_page" : "page17", "page" : "page17", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i59", "sym_num" : 1, "page_instance" : "I59", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17" } ], "refdes" : "R80_XF", "pin_name" : "B", "net_name" : "UNNAMED_17_BYPASSCAPNPOL_I57_A_XF", "part_number" : "400-000010-010", "node_name" : "R80_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "R42_FL_XF.1" : { "pin_name" : "A", "net_name" : "UNNAMED_6_BYPASSCAPNPOL_I25_B_FL", "refdes" : "R42_FL_XF", "part_number" : "400-000014-011", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6_i24", "sym_num" : 1, "page_instance" : "I24", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page6" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R42_FL_XF.1" }, "R21_SP_XF.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i161", "sym_num" : 1, "page_instance" : "I161", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "part_number" : "400-000010-006", "refdes" : "R21_SP_XF", "pin_name" : "A", "net_name" : "GND", "node_name" : "R21_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.AV10" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I71", "sym_num" : 36, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71" } ], "refdes" : "U1_XF", "pin_name" : "GND_646", "net_name" : "GND", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_36;", "pin_name_unsanitized" : "GND_646", "pin_type" : "INOUT", "pin_number" : "AV10", "node_name" : "U1_XF.AV10" }, "PM7_SP_XF.K8" : { "pin_name" : "GND_49", "refdes" : "PM7_SP_XF", "net_name" : "GND", "part_number" : "462-000308-002", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i151", "sym_num" : 2, "page_instance" : "I151", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "pin_name_unsanitized" : "GND_49", "pinuse" : "POWER;", "pin_type" : "POWER", "pin_number" : "K8", "node_name" : "PM7_SP_XF.K8" }, "C105_XF.2" : { "node_name" : "C105_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I70", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i70", "page" : "page12", "block" : "top/xc2_fpga_blk", "phys_page" : "page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null } ], "pin_name" : "B", "refdes" : "C105_XF", "net_name" : "E1S0_PET_P<4>_XF", "part_number" : "402-000010-035" }, "R35_FL_XF.1" : { "net_name" : "UNNAMED_5_LT3071_I30_V00_FL", "pin_name" : "A", "refdes" : "R35_FL_XF", "part_number" : "400-000010-010", "marker_data" : [ { "page_instance" : "I7", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i7", "sym_num" : 1, "phys_page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R35_FL_XF.1" }, "U1_XF.AM43" : { "pin_type" : "INOUT", "pin_number" : "AM43", "node_name" : "U1_XF.AM43", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "VCCAUX_5", "net_name" : "FPGA_VCCAUX_P1R8V", "marker_data" : [ { "sym_num" : 30, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i188", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I188", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23" } ], "pin_name_unsanitized" : "VCCAUX_5", "pin_group" : "ALL_POWER_PINS_30;" }, "R48_SP_XF.1" : { "node_name" : "R48_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000010-010", "refdes" : "R48_SP_XF", "pin_name" : "A", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I145_A_SP", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I33", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i33" } ] }, "U1_XF.E33" : { "pin_name_unsanitized" : "IO_L16N_T2U_N7_QBC_AD3N_71", "pin_group" : "ALL_SIGNAL_PINS_25;", "part_number" : "450-000340-001", "pin_name" : "IO_L16N_T2U_N7_QBC_AD3N_71", "refdes" : "U1_XF", "net_name" : "NC", "marker_data" : [ { "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I59", "sym_num" : 25, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i59" } ], "node_name" : "U1_XF.E33", "pin_number" : "E33", "pin_type" : "INOUT" }, "PM3_SP_XF.H2" : { "node_name" : "PM3_SP_XF.H2", "pin_number" : "H2", "pin_type" : "POWER", "pin_name_unsanitized" : "GND_31", "pinuse" : "POWER;", "pin_name" : "GND_31", "refdes" : "PM3_SP_XF", "net_name" : "GND", "part_number" : "462-000308-002", "marker_data" : [ { "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i153", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I153", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null, "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page10" } ] }, "PM5_SP_XF.J3" : { "pin_type" : "POWER", "pin_number" : "J3", "node_name" : "PM5_SP_XF.J3", "part_number" : "462-000308-002", "refdes" : "PM5_SP_XF", "pin_name" : "VIN_2", "net_name" : "P12V_4650_TR_SP", "marker_data" : [ { "phys_path" : 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"pin_type" : "INOUT", "node_name" : "J3_XF.247" }, "PM3_SP_XF.G11" : { "pin_number" : "G11", "pin_type" : "OUTPUT", "node_name" : "PM3_SP_XF.G11", "part_number" : "462-000308-002", "refdes" : "PM3_SP_XF", "pin_name" : "SW2", "net_name" : "SW2_4650_BL_SP", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i151", "sym_num" : 3, "page_instance" : "I151", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10" } ], "pinuse" : "OUT;", "pin_name_unsanitized" : "SW2" }, "C46_FL_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C46_FL_XF.1", "part_number" : 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: { "pin_name_unsanitized" : "IO10_PR5C_1", "pinuse" : "BI;", "pin_name" : "IO10_PR5C_1", "net_name" : "NC", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_page" : "page7", "block" : "top/cpld_blk", "page" : "page7", "ppath" : "top/page14_i1/cpld_blk/page7_i152", "sym_num" : 8, "page_instance" : "I152", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7" } ], "node_name" : "U1_CPLD.F13", "pin_type" : "INOUT", "pin_number" : "F13" }, "C135_XF.1" : { "refdes" : "C135_XF", "pin_name" : "A", "net_name" : "AC_E1S1_PET_N<2>_XF", "part_number" : "402-000010-035", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page12", "phys_page" : "page12", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i91", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I91" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C135_XF.1" }, "U10_FL_XF.9" : { "node_name" : "U10_FL_XF.9", "pin_number" : "9", "pin_type" : "POWER", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_9", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page11", "phys_page" : "page11", "page" : "page12", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i30", "sym_num" : 1, "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11" } ], "part_number" : "450-000057-001", "net_name" : "GND", "pin_name" : "GND_9", "refdes" : "U10_FL_XF" }, "PM2_SP_XF.W4" : { "marker_data" : [ { "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "page_instance" : "I459", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "sym_num" : 5 } ], "part_number" : "462-000309-001", "pin_name" : "GND_78", "net_name" : "GND", "refdes" : "PM2_SP_XF", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_78", "pin_number" : "W4", "node_name" : "PM2_SP_XF.W4" }, "U1_XF.BD15" : { "pin_number" : "BD15", "pin_type" : "INOUT", "node_name" : "U1_XF.BD15", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_page" : "page20", "page" : "page20", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i86", "sym_num" : 29, "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20" } ], "part_number" : "450-000340-001", "pin_name" : "MGTAVCC_RLC_6", "net_name" : "PWR_AVCC_RS_RLC_XF", "refdes" : "U1_XF", "pin_group" : "ALL_POWER_PINS_29;", "pin_name_unsanitized" : "MGTAVCC_RLC_6" }, "U1_XF.D54" : { "pin_name" : "C2_DDR4_DQ45", "refdes" : "U1_XF", "net_name" : "C2_DDR4_DQ<45>_XF", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 62, "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "page_instance" : "I2425", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "PAGE7", "phys_page" : "PAGE7" } ], "pin_name_unsanitized" : "C2_DDR4_DQ45", "pin_group" : "C2_UNIB_1_6_57;", "pin_type" : "INOUT", "pin_number" : "D54", "node_name" : "U1_XF.D54" }, "J1_XF.214" : { "node_name" : "J1_XF.214", "pin_type" : "INPUT", "pin_number" : "214", "pinuse" : "IN;", "pin_name_unsanitized" : "A4", "part_number" : "410-000300-001", "refdes" : "J1_XF", "pin_name" : "A4", "net_name" : "C0_DDR4_ADR<4>_XF", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1 } ] }, "U4_FL_XF.20" : { "node_name" : "U4_FL_XF.20", "pin_number" : "20", "pin_type" : "POWER", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_20", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7_i30", "sym_num" : 1, "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "phys_page" : "page7", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page7" } ], "part_number" : "450-000057-001", "pin_name" : "GND_20", "net_name" : "GND", "refdes" : "U4_FL_XF" }, "C23_E1_XF.2" : { "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "page_instance" : "I51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i51", "sym_num" : 1 } ], "part_number" : "402-000010-035", "pin_name" : "B", "refdes" : "C23_E1_XF", "net_name" : "E1S1_FPGA_REFCLK_N<0>_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C23_E1_XF.2" }, "U1_CPLD.M9" : { "node_name" : "U1_CPLD.M9", "pin_type" : "INOUT", "pin_number" : "M9", "pin_group" : "PCTL_POK_3;", "pin_name_unsanitized" : "POK_OD_AVTT_RUC_LIN", "pinuse" : "BI;", "marker_data" : [ { "sym_num" : 3, "ppath" : "top/page14_i1/cpld_blk/page4_i211", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "page_instance" : "I211", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/cpld_blk", "phys_page" : "page4" } ], "pin_name" : "POK_OD_AVTT_RUC_LIN", "net_name" : "POK_OD_AVTT_RUC_LIN", "refdes" : "U1_CPLD", "part_number" : "450-000313-001" }, "U1_XF.BE41" : { "part_number" : "450-000340-001", "pin_name" : "GND_819", "refdes" : "U1_XF", "net_name" : "GND", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "sym_num" : 37, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I72" } ], "pin_name_unsanitized" : "GND_819", "pin_group" : "ALL_POWER_PINS_37;", "pin_number" : "BE41", "pin_type" : "INOUT", "node_name" : "U1_XF.BE41" }, "C331_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "refdes" : "C331_XF", "net_name" : "GND", "part_number" : "402-000010-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I40", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "page" : "page20", "block" : "top/xc2_fpga_blk", "phys_page" : "page20" } ], "node_name" : "C331_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C10_SD_XF.1" : { "refdes" : "C10_SD_XF", "pin_name" : "A", "net_name" : "P12V_FUSED_4675_SD", "part_number" : "402-000010-041", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i14", "sym_num" : 1, "page_instance" : "I14", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C10_SD_XF.1" }, "U1_XF.AL60" : { "pin_group" : "ALL_SIGNAL_PINS_18;", "pin_name_unsanitized" : "IO_L24N_T3U_N11_28", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I51", "sym_num" : 18, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51" } ], "net_name" : "NC", "pin_name" : "IO_L24N_T3U_N11_28", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.AL60", "pin_type" : "INOUT", "pin_number" : "AL60" }, "J1_P1_XF.MH3" : { "marker_data" : [ { "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3" } ], "pin_name" : "MH3", "refdes" : "J1_P1_XF", "net_name" : "GND", "part_number" : "410-000324-001", "pin_name_unsanitized" : "MH3", "pinuse" : "GROUND;", "pin_number" : "MH3", "node_name" : "J1_P1_XF.MH3" }, "U1_XF.BT60" : { "pin_group" : "C1_LNIB_1_5_39;", "pin_name_unsanitized" : "C1_DDR4_DQ66", "marker_data" : [ { "sym_num" : 47, "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "page_instance" : "I2425", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "PAGE5", "phys_page" : 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"pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i29", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5", "phys_page" : "page5" } ], "part_number" : "402-000010-033", "net_name" : "GND", "pin_name" : "B", "refdes" : "C2_SP_XF" }, "U1_XF.BT43" : { "marker_data" : [ { "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : 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"pin_type" : "INOUT" }, "PM4_SD_XF.F6" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i13", "sym_num" : 1, "page_instance" : "I13", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3" } ], "pin_name" : "SGND_2", "refdes" : "PM4_SD_XF", "net_name" : "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF", "part_number" : "462-000304-001", "pin_name_unsanitized" : "SGND_2", "pinuse" : "POWER;", "pin_type" : "POWER", "pin_number" : "F6", "node_name" : "PM4_SD_XF.F6" }, "R121_XF.2" : { "marker_data" : [ { "page_instance" : "I190", "ppath_without_last_instance" : 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"pin_group" : "ALL_POWER_PINS_37;", "pin_name_unsanitized" : "GND_884" }, "J2_P1_XF.A14" : { "net_name" : "GND", "pin_name" : "GND_5", "refdes" : "J2_P1_XF", "part_number" : "410-000324-001", "marker_data" : [ { "page_instance" : "I85", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i85", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3" } ], "pin_name_unsanitized" : "GND_5", "pinuse" : "GROUND;", "pin_number" : "A14", "node_name" : "J2_P1_XF.A14" }, "J1_E3_XF.A30" : { "pin_number" : "A30", "pin_type" : "OUTPUT", "node_name" : "J1_E3_XF.A30", "pin_name" : "PERN4", "refdes" : "J1_E3_XF", "net_name" : "E1S3_PER_N<4>_XF", "part_number" : "410-000317-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3", "page_instance" : "I101", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3_i101", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null } ], "pin_name_unsanitized" : "PERN4", "pinuse" : "OUT;" }, "C130_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "page" : "page12", "block" : "top/xc2_fpga_blk", "phys_page" : "page12", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i82", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I82" } ], "pin_name" : "B", "net_name" : "E1S1_PET_N<7>_XF", "refdes" : "C130_XF", "part_number" : "402-000010-035", "node_name" : "C130_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.AP55" : { "pin_name_unsanitized" : "IO_L4P_T0U_N6_DBC_AD7P_27", "pin_group" : "ALL_SIGNAL_PINS_18;", "part_number" : "450-000340-001", "pin_name" : "IO_L4P_T0U_N6_DBC_AD7P_27", "refdes" : "U1_XF", "net_name" : "NC", "marker_data" : [ { "page_instance" : "I51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51", "sym_num" : 18, "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30" } ], "node_name" : "U1_XF.AP55", "pin_type" : "INOUT", "pin_number" : "AP55" }, "VMON_SPARE_SW_XF.1" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i271", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26", "page_instance" : "I271", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page26", "phys_page" : "page26" } ], "part_number" : "TP_020_VIA", "pin_name" : "1", "net_name" : "VMON_SPARE_SW_XF", "refdes" : "VMON_SPARE_SW_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "\\1\\", "pin_type" : "POWER", "pin_number" : "1", "node_name" : "VMON_SPARE_SW_XF.1" }, "C228_XF.2" : { "node_name" : "C228_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I149", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i149" } ], "pin_name" : "B", "refdes" : "C228_XF", "net_name" : "GND", "part_number" : "402-000010-028" }, "C277_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C277_XF.2", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I179", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i179", "block" : "top/xc2_fpga_blk", "page" : "page14", "phys_page" : "page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null } ], "pin_name" : "B", "net_name" : "OCL2_PET_N<0>_XF", "refdes" : "C277_XF", "part_number" : "402-000010-035", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "C53_CPLD.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "C53_CPLD", "pin_name" : "A", "net_name" : "GND", "part_number" : "402-000010-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top/cpld_blk", "ppath" : "top/page14_i1/cpld_blk/page7_i25", "sym_num" : 1, "page_instance" : "I25", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7" } ], "node_name" : "C53_CPLD.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "J3_XF.19" : { "node_name" : "J3_XF.19", "pin_type" : "INOUT", "pin_number" : "19", "pinuse" : "TRI;", "pin_name_unsanitized" : "DQS10_C_TDQS10_C", "marker_data" : [ { "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1 } ], "part_number" : "410-000300-001", "net_name" : "C2_RDIMM_DQS_C<10>_XF", "pin_name" : "DQS10_C_TDQS10_C", "refdes" : "J3_XF" }, "R204_XF.2" : { "marker_data" : [ { "page_instance" : "I228", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i228", "sym_num" : 1, "phys_page" : "page13", "page" : "page13", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13" } ], "net_name" : "E1S3_FPGA_REFCLK_N<0>_XF", "pin_name" : "B", "refdes" : "R204_XF", "part_number" : "400-000010-004", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R204_XF.2" }, "U1_XF.AR3" : { "node_name" : "U1_XF.AR3", "pin_type" : "INOUT", "pin_number" : "AR3", "pin_name_unsanitized" : "GND_591", "pin_group" : "ALL_POWER_PINS_35;", "net_name" : "GND", "pin_name" : "GND_591", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "sym_num" : 35, "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ] }, "PM7_SP_XF.M9" : { "node_name" : "PM7_SP_XF.M9", "pin_type" : "POWER", "pin_number" : "M9", "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_30", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80", "sym_num" : 1, "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11" } ], "part_number" : "462-000308-002", "pin_name" : "VIN_30", "refdes" : "PM7_SP_XF", "net_name" : "P12V_4650_BR_SP" }, "U1_CPLD.C8" : { "marker_data" : [ { "sym_num" : 4, "ppath" : "top/page14_i1/cpld_blk/page6_i129", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page6", "page_instance" : "I129", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/cpld_blk", "phys_page" : "page6" } ], "part_number" : "450-000313-001", "refdes" : "U1_CPLD", "pin_name" : "FPGA_CPLD_DCLK", "net_name" : "FPGA_CPLD_DCLK_1", "pinuse" : "IN;", "pin_name_unsanitized" : "FPGA_CPLD_DCLK", "pin_number" : "C8", "pin_type" : "INPUT", "node_name" : "U1_CPLD.C8" }, "U1_XF.H54" : { "node_name" : "U1_XF.H54", "pin_type" : "INOUT", "pin_number" : "H54", "pin_name_unsanitized" : "C2_DDR4_DQS_C6", "pin_group" : "ALL_SIGNAL_PINS_57;", "part_number" : "450-000340-001", "pin_name" : "C2_DDR4_DQS_C6", "refdes" : "U1_XF", "net_name" : "C2_RDIMM_DQS_C<3>_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "page_instance" : "I2425", "sym_num" : 60, "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425", "page" : "PAGE7", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "remapped_page" : null } ] }, "U5_XF.25" : { "node_name" : "U5_XF.25", "pin_number" : "25", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDDO_2", "marker_data" : [ { "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "page_instance" : "I63", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i63", "sym_num" : 1 } ], "part_number" : "450-000345-001", "refdes" : "U5_XF", "pin_name" : "VDDO_2", "net_name" : "PWR_FPGA_3R3V" }, "U1_XF.BE50" : { "pin_type" : "INOUT", "pin_number" : "BE50", "node_name" : "U1_XF.BE50", "refdes" : "U1_XF", "pin_name" : "IO_L7N_T1L_N1_QBC_AD13N_24", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20, "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30" } ], "pin_name_unsanitized" : "IO_L7N_T1L_N1_QBC_AD13N_24", "pin_group" : "ALL_SIGNAL_PINS_20;" }, "U1_XF.N3" : { "node_name" : "U1_XF.N3", "pin_type" : "INOUT", "pin_number" : "N3", "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_175", "marker_data" : [ { "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "refdes" : "U1_XF", "pin_name" : "GND_175", "net_name" : "GND", "part_number" : "450-000340-001" }, "C198_SP_XF.1" : { "pin_name" : "A", "refdes" : "C198_SP_XF", "net_name" : "PWR_VCCINT_XF", "part_number" : "402-000010-033", "marker_data" : [ { "phys_page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "page_instance" : "I111", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i111", "sym_num" : 1 } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C198_SP_XF.1" }, "U1_XF.AP59" : { "pin_number" : "AP59", "pin_type" : "INOUT", "node_name" : "U1_XF.AP59", "part_number" : "450-000340-001", "pin_name" : "IO_T0U_N12_VRP_28", "refdes" : "U1_XF", "net_name" : "NC", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51", "sym_num" : 18, "page_instance" : "I51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : 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"R180_XF.2" : { "node_name" : "R180_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "page_instance" : "I258", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i258", "sym_num" : 1, "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12" } ], "part_number" : "400-000010-004", "pin_name" : "B", "refdes" : "R180_XF", "net_name" : "E1S1_FPGA_REFCLK_N<0>_XF" }, "C34_XF.2" : { "node_name" : "C34_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I633", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "ppath" 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: "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I46" } ], "part_number" : "402-000020-011", "pin_name" : "A", "net_name" : "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF", "refdes" : "C68_SD_XF", "node_name" : "C68_SD_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_XF.AE43" : { "node_name" : "U1_XF.AE43", "pin_number" : "AE43", "pin_type" : "INOUT", "pin_name_unsanitized" : "GND_426", "pin_group" : "ALL_POWER_PINS_35;", "part_number" : "450-000340-001", "pin_name" : "GND_426", "refdes" : "U1_XF", "net_name" : "GND", "marker_data" : [ { "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "sym_num" : 35 } ] }, "U1_XF.M29" : { "pin_type" : "INOUT", "pin_number" : "M29", "node_name" : "U1_XF.M29", "pin_name" : "IO_L10N_T1U_N7_QBC_AD4N_72", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54", "sym_num" : 24, "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31" } ], "pin_name_unsanitized" : "IO_L10N_T1U_N7_QBC_AD4N_72", "pin_group" : "ALL_SIGNAL_PINS_24;" }, "U1_XF.AF12" : { "pin_group" : "ALL_SIGNAL_PINS_10;", "pin_name_unsanitized" : "E1S3_PET_N3", "marker_data" : [ { "phys_page" : "page13", "block" : "top/xc2_fpga_blk", "page" : "page13", "remapped_page" : null, "phys_path" : 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"U1_XF", "net_name" : "PWR_VCCINT_XF", "node_name" : "U1_XF.AB29", "pin_number" : "AB29", "pin_type" : "INOUT" }, "U1_XF.AE60" : { "pin_number" : "AE60", "pin_type" : "INOUT", "node_name" : "U1_XF.AE60", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I53", "sym_num" : 23, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53" } ], "net_name" : "NC", "pin_name" : "IO_L10N_T1U_N7_QBC_AD4N_31", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_23;", "pin_name_unsanitized" : "IO_L10N_T1U_N7_QBC_AD4N_31" }, "U1_XF.E27" : { "pin_name_unsanitized" : "C3_DDR4_DQS_C5", "pin_group" : "ALL_SIGNAL_PINS_48;", "refdes" : "U1_XF", "pin_name" : "C3_DDR4_DQS_C5", "net_name" : "C3_RDIMM_DQS_C<11>_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page" : "PAGE9", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2425", "sym_num" : 50, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425" } ], "node_name" : "U1_XF.E27", "pin_type" : "INOUT", "pin_number" : "E27" }, "U1_XF.BN3" : { "node_name" : "U1_XF.BN3", "pin_type" : "INOUT", "pin_number" : "BN3", "pin_name_unsanitized" : "GND_932", "pin_group" : "ALL_POWER_PINS_37;", "part_number" : "450-000340-001", "pin_name" : "GND_932", "refdes" : "U1_XF", "net_name" : "GND", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I14" } ], "node_name" : "C10_SD_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "R234_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000010-007", "pin_name" : "A", "net_name" : "PWR_SDIMM_VDD_XF", "refdes" : "R234_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2156", "sym_num" : 1, "page_instance" : "I2156", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk", "page" : "page3" } ], "node_name" : "R234_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.A32" : { "node_name" : "U1_XF.A32", "pin_number" : "A32", "pin_type" : "INOUT", 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: "B", "refdes" : "R78_XF", "part_number" : "400-000010-010", "node_name" : "R78_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_XF.BP23" : { "pin_type" : "INOUT", "pin_number" : "BP23", "node_name" : "U1_XF.BP23", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I72", "sym_num" : 37, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72" } ], "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_955", "refdes" : "U1_XF", "pin_group" : "ALL_POWER_PINS_37;", "pin_name_unsanitized" : "GND_955" }, "U1_XF.BF4" : { "pin_name_unsanitized" : "PCIE_X1_RXP", "pin_group" : "ALL_SIGNAL_PINS_3;", "refdes" : "U1_XF", "pin_name" : "PCIE_X1_RXP", "net_name" : "PCIE_X1_RXP_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page" : "page11", "block" : "top/xc2_fpga_blk", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I775", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775" } ], "node_name" : "U1_XF.BF4", "pin_type" : "INOUT", "pin_number" : "BF4" }, "U1_XF.AT16" : { "pin_number" : "AT16", "pin_type" : "INOUT", "node_name" : "U1_XF.AT16", "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "sym_num" : 36 } ], "pin_name" : "GND_615", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_36;", "pin_name_unsanitized" : "GND_615" }, "U1_XF.BL16" : { "pin_type" : "INOUT", "pin_number" : "BL16", "node_name" : "U1_XF.BL16", "marker_data" : [ { "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "sym_num" : 37, "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "refdes" : "U1_XF", "pin_name" : "GND_910", "net_name" : "GND", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_37;", "pin_name_unsanitized" : "GND_910" }, "C229_XF.1" : { "node_name" : "C229_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-001", "pin_name" : "A", "net_name" : "C3_DDR4_VREFCA_1_XF", "refdes" : "C229_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i152", "sym_num" : 1, "page_instance" : "I152", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10" } ] }, "PM4_SP_XF.M9" : { "part_number" : "462-000308-002", "net_name" : "P12V_4650_TL_SP", "pin_name" : "VIN_30", "refdes" : "PM4_SP_XF", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i80", "sym_num" : 1 } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_30", "pin_number" : "M9", "pin_type" : "POWER", "node_name" : "PM4_SP_XF.M9" }, "C158_XF.1" : { "part_number" : "402-000010-001", "refdes" : "C158_XF", "pin_name" : "A", "net_name" : "GND", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i178", "sym_num" : 1, "page_instance" : "I178", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C158_XF.1" }, "C2_E3_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-001", "pin_name" : "A", "refdes" : "C2_E3_XF", "net_name" : "GND", "marker_data" : [ { "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4_i20", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4" } ], "node_name" : "C2_E3_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "J1_XF.55" : { "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4" } ], "part_number" : "410-000300-001", "pin_name" : "VSS_49", "refdes" : "J1_XF", "net_name" : "GND", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_49", "pin_number" : "55", "pin_type" : "GROUND", "node_name" : "J1_XF.55" }, "U1_XF.AE27" : { "pin_group" : "ALL_POWER_PINS_35;", "pin_name_unsanitized" : "GND_418", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "sym_num" : 35, "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24" } ], "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_418", "refdes" : "U1_XF", "node_name" : "U1_XF.AE27", "pin_number" : "AE27", "pin_type" : "INOUT" }, "U1_XF.AD5" : { "node_name" : "U1_XF.AD5", "pin_type" : "INOUT", "pin_number" : "AD5", "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_384", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34, "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24" } ], "part_number" : "450-000340-001", "pin_name" : "GND_384", "net_name" : "GND", "refdes" : "U1_XF" }, "U1_XF.BK39" : { "pin_group" : "ALL_SIGNAL_PINS_20;", "pin_name_unsanitized" : "IO_L15P_T2L_N4_AD11P_67", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I49", "sym_num" : 20, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null } ], "part_number" : "450-000340-001", "pin_name" : "IO_L15P_T2L_N4_AD11P_67", "refdes" : "U1_XF", "net_name" : "NC", "node_name" : "U1_XF.BK39", "pin_number" : "BK39", "pin_type" : "INOUT" }, "R15_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "net_name" : "GND", "refdes" : "R15_XF", "part_number" : "400-000014-011", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page16", "phys_page" : "page16", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page16", "page_instance" : "I28", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page16_i28" } ], "node_name" : "R15_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_CPLD.A9" : { "pin_name" : "BASE_3R3V_SCL", "net_name" : "BASE_3R3V_SCL_2", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "marker_data" : [ { "sym_num" : 2, "ppath" : "top/page14_i1/cpld_blk/page5_i61", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page5", "page_instance" : "I61", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "remapped_page" : null, "page" : "page5", "block" : "top/cpld_blk", "phys_page" : "page5" } ], "pin_name_unsanitized" : "BASE_3R3V_SCL", "pinuse" : "BI;", "pin_number" : "A9", "pin_type" : "INOUT", "node_name" : "U1_CPLD.A9" }, "J1_E3_XF.A19" : { "node_name" : "J1_E3_XF.A19", "pin_number" : "A19", "pin_name_unsanitized" : "GND_9", "pinuse" : "GROUND;", "refdes" : "J1_E3_XF", "net_name" : "GND", "pin_name" : "GND_9", "part_number" : "410-000317-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3_i101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3", "page_instance" : "I101" } ] }, "R111_SP_XF.1" : { "node_name" : "R111_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000014-011", "refdes" : "R111_SP_XF", "pin_name" : "A", "net_name" : "UNNAMED_7_LTM4671_I37_FREQ12_SP", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i63", "sym_num" : 1, "page_instance" : "I63", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7" } ] }, "J1_O2_XF.A8" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_3", "part_number" : "410-000324-001", "pin_name" : "GND_3", "refdes" : "J1_O2_XF", "net_name" : "GND", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i30@top_lib.ocl_x4_conn_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i30@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "page" : "page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i30/ocl_x4_conn_blk/page3_i84", "sym_num" : 1, "page_instance" : "I84", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i30/ocl_x4_conn_blk/page3" } ], "node_name" : "J1_O2_XF.A8", "pin_number" : "A8" }, "U1_XF.L5" : { "pin_group" : "ALL_SIGNAL_PINS_14;", "pin_name_unsanitized" : "MGTYRXN0_236", "marker_data" : [ { "page_instance" : "I56", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i56", "sym_num" : 14, "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "MGTYRXN0_236", "net_name" : "NC", "node_name" : "U1_XF.L5", "pin_number" : "L5", "pin_type" : "INOUT" }, "R196_SP_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000015-032", "refdes" : "R196_SP_XF", "pin_name" : "B", "net_name" : "IS_VCCINTLR_SW_P_SP", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", 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"page" : "page24" } ], "net_name" : "GND", "pin_name" : "GND_583", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.AP26", "pin_number" : "AP26", "pin_type" : "INOUT" }, "U1_E0_XF.28" : { "node_name" : "U1_E0_XF.28", "pin_type" : "OUTPUT", "pin_number" : "28", "pin_name_unsanitized" : "Q3_N", "pinuse" : "OUT;", "marker_data" : [ { "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "page_instance" : "I37", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i37" } ], "refdes" : "U1_E0_XF", "pin_name" : "Q3_N", "net_name" : "AC_FPGA_CLK_REF_N<1>_1", "part_number" : "450-000345-001" }, "C5_FL_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000020-011", "net_name" : "GND", "pin_name" : "A", "refdes" : "C5_FL_XF", "marker_data" : [ { "page" : "page4", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "page_instance" : "I23", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i23" } ], "node_name" : "C5_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.BM22" : { "pin_name" : "VCCO_61_2", "net_name" : "PWR_SDIMM_VDD_XF", "refdes" : "U1_XF", "part_number" : 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"UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000016-001", "pin_name" : "A", "refdes" : "C103_SP_XF", "net_name" : "PM1_SP_AGND_SP", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i44", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I44" } ], "node_name" : "C103_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "R93_SP_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I443", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i443" } ], "part_number" : "400-000014-011", "pin_name" : "B", "refdes" : "R93_SP_XF", "net_name" : "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP", "node_name" : "R93_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C23.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C23.2", "net_name" : "GND", "pin_name" : "B", "refdes" : "C23", "part_number" : "402-000500-005", "marker_data" : [ { "ppath" : "top/page19_i81", "sym_num" : 1, "page_instance" : "I81", "ppath_without_last_instance" : "top/page19", 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"C11_E2_XF.1", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i94", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3", "page_instance" : "I94", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "phys_page" : "page3" } ], "part_number" : "402-000010-028", "pin_name" : "A", "net_name" : "GND", "refdes" : "C11_E2_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "U1_XF.BE11" : { "node_name" : "U1_XF.BE11", "pin_type" : "INOUT", "pin_number" : "BE11", "pin_group" : "ALL_SIGNAL_PINS_3;", "pin_name_unsanitized" : "MGTYTXP1_224", "marker_data" : [ { "sym_num" : 3, "ppath" : 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"pin_name_unsanitized" : "VSS_3", "pinuse" : "UNSPEC;", "marker_data" : [ { "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180" } ], "refdes" : "J1_XF", "pin_name" : "VSS_3", "net_name" : "GND", "part_number" : "410-000300-001" }, "U1_XF.Y15" : { "pin_type" : "INOUT", "pin_number" : "Y15", "node_name" : "U1_XF.Y15", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page20", "phys_page" : "page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I86", "sym_num" : 29, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i86" } ], "part_number" : "450-000340-001", "net_name" : "PWR_AVCC_RUC_XF", "pin_name" : "MGTAVCC_RUC_3", "refdes" : "U1_XF", "pin_group" : "ALL_POWER_PINS_29;", "pin_name_unsanitized" : "MGTAVCC_RUC_3" }, "U1_CPLD.M4" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VCCIO3", "part_number" : "450-000313-001", "pin_name" : "VCCIO3", "refdes" : "U1_CPLD", "net_name" : "CPLD_P1R8V_1", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152", "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152", "page" : "page7", "block" : "top/cpld_blk", "phys_page" : "page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null } ], "node_name" : "U1_CPLD.M4", "pin_number" : "M4" }, "U1_XF.W62" : { "node_name" : "U1_XF.W62", "pin_number" : "W62", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_23;", "pin_name_unsanitized" : "IO_L23N_T3U_N9_31", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "sym_num" : 23, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I53" } ], "pin_name" : "IO_L23N_T3U_N9_31", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001" }, "U1_XF.N56" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I46", "sym_num" : 22, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46" } ], "refdes" : "U1_XF", "pin_name" : "IO_L16P_T2U_N6_QBC_AD3P_33", "net_name" : "NC", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_22;", "pin_name_unsanitized" : "IO_L16P_T2U_N6_QBC_AD3P_33", "pin_type" : "INOUT", "pin_number" : "N56", "node_name" : "U1_XF.N56" }, "J1_P0_XF.A8" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_3", "part_number" : "410-000324-001", "net_name" : "GND", "pin_name" : "GND_3", "refdes" : "J1_P0_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "page" : "page3", "phys_page" : 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"R3_E0_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R3_E0_XF.2", "marker_data" : [ { "page_instance" : "I79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3_i79", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3" } ], "pin_name" : "B", "net_name" : "E1S0_3R3V_SCL_XF", "refdes" : "R3_E0_XF", "part_number" : "400-000010-007", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "C45_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C45_XF.2", "part_number" : "402-000010-035", "pin_name" : "B", "refdes" : "C45_XF", "net_name" : "PCIE1_TXN<4>_XF", "marker_data" : [ { "page" : "page11", "block" : "top/xc2_fpga_blk", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I642", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i642" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "U1_XF.AT22" : { "node_name" : "U1_XF.AT22", "pin_number" : "AT22", "pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_36;", "pin_name_unsanitized" : "GND_617", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : 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"page_instance" : "I22", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4" } ] }, "C474_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C474_XF.2", "part_number" : "402-000010-001", "pin_name" : "B", "net_name" : "GND", "refdes" : "C474_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page20", "phys_page" : "page20", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i26", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I26" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "U1_XF.BL22" : { "pin_name" : "C0_DDR4_DQ33", "refdes" : "U1_XF", "net_name" : "C0_DDR4_DQ<33>_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_path" : 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"B", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page4", "page_instance" : "I152", "ppath_without_last_instance" : "top/page4", "ppath" : "top/page4_i152", "sym_num" : 1 } ], "net_name" : "GND", "pin_name" : "B", "refdes" : "R28", "part_number" : "400-000010-010", "node_name" : "R28.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "C98_SP_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-031", "pin_name" : "B", "net_name" : "GND", "refdes" : "C98_SP_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i502", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I502", "path" : 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"sym_num" : 1, "page_instance" : "I115", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4" } ], "part_number" : "402-000500-008", "pin_name" : "B2", "net_name" : "GND", "refdes" : "C35_SP_XF" }, "J4_XF.7" : { "node_name" : "J4_XF.7", "pin_type" : "INOUT", "pin_number" : "7", "pin_name_unsanitized" : "DQS9_T_TDQS9_T", "pinuse" : "TRI;", "pin_name" : "DQS9_T_TDQS9_T", "refdes" : "J4_XF", "net_name" : "C3_RDIMM_DQS_T<9>_XF", "part_number" : "410-000300-001", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10" } ] }, "C92_FL_XF.2" : { "pin_name" : "B", "refdes" : "C92_FL_XF", "net_name" : "GND", "part_number" : "402-000010-001", "marker_data" : [ { "phys_page" : "page11", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page12", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12", "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i37", "sym_num" : 1 } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C92_FL_XF.2" }, "PM4_ND_XF.A3" : { "node_name" : "PM4_ND_XF.A3", "pin_number" : "A3", "pin_type" : "POWER", "pin_name_unsanitized" : "GND_2", "pinuse" : "POWER;", "marker_data" : [ { "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i20", "sym_num" : 2, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3" } ], "pin_name" : "GND_2", "refdes" : "PM4_ND_XF", "net_name" : "GND", "part_number" : "462-000304-001" }, "R13_XF.2" : { "pin_name" : "B", "refdes" : "R13_XF", "net_name" : "UNNAMED_17_RESISTOR_I202_A_XF", "part_number" : "400-000010-066", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I203", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i203", "page" : "page17", "block" : "top/xc2_fpga_blk", "phys_page" : "page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R13_XF.2" }, "R41.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "refdes" : "R41", "net_name" : "FP_JT_VREF", "part_number" : "400-000010-002", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page15", "phys_page" : "page15", "page" : "page15", "block" : "top", "ppath" : "top/page15_i14", "sym_num" : 1, "page_instance" : "I14", "ppath_without_last_instance" : "top/page15" } ], "node_name" : "R41.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "M2.MTG4" : { "pin_number" : "MTG4", "node_name" : "M2.MTG4", "part_number" : "HOLE_RING", "net_name" : "GND", "pin_name" : "MTG4", "refdes" : "M2", "marker_data" : [ { "block" : "top", "page" : "page1", "phys_page" : "page1", "phys_path" : "@top_lib.top(sch_1):page1", "path" : "@top_lib.top(sch_1):page1", "remapped_page" : null, "ppath_without_last_instance" : "top/page1", "page_instance" : "I58", "sym_num" : 1, "ppath" : "top/page1_i58" } ], "pinuse" : "NC;", "pin_name_unsanitized" : "MTG4" }, "PM2_SP_XF.W7" : { "node_name" : "PM2_SP_XF.W7", "pin_type" : "INOUT", "pin_number" : "W7", "pinuse" : "BI;", "pin_name_unsanitized" : "TSENSE3_N", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "sym_num" : 4, "ppath" : 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"J1_XF.230" : { "node_name" : "J1_XF.230", "pin_number" : "230", "pin_type" : "UNSPECIFIED", "pinuse" : "BI;", "pin_name_unsanitized" : "NC_4", "part_number" : "410-000300-001", "pin_name" : "NC_4", "refdes" : "J1_XF", "net_name" : "NC", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4" } ] }, "R27_SP_XF.2" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I140", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i140", "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", 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: "VOUT0_3", "part_number" : "462-000309-001", "pin_name_unsanitized" : "VOUT0_3", "pinuse" : "POWER;", "pin_number" : "C1", "node_name" : "PM1_SP_XF.C1" }, "U1_XF.BH3" : { "marker_data" : [ { "page_instance" : "I275", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i275", "sym_num" : 12, "phys_page" : "page14", "block" : "top/xc2_fpga_blk", "page" : "page14", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "OCL3_PER_N2", "net_name" : "OCL3_PER_N<2>_XF", "pin_group" : "ALL_SIGNAL_PINS_12;", "pin_name_unsanitized" : "OCL3_PER_N2", "pin_type" : "INOUT", "pin_number" : "BH3", "node_name" : "U1_XF.BH3" }, "J1_E3_XF.B39" : { "node_name" : "J1_E3_XF.B39", "pin_type" : "INPUT", "pin_number" : "B39", "pin_name_unsanitized" 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"pin_type" : "INOUT", "pin_number" : "AV52", "node_name" : "U1_XF.AV52", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51", "sym_num" : 18, "page_instance" : "I51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30" } ], "net_name" : "NC", "pin_name" : "IO_L7N_T1L_N1_QBC_AD13N_27", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_18;", "pin_name_unsanitized" : "IO_L7N_T1L_N1_QBC_AD13N_27" }, "R269_XF.2" : { "node_name" : "R269_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "PWR_AVTT_RN_XF", "refdes" : "R269_XF", "part_number" : "400-000010-004", "marker_data" : [ { "page_instance" : "I31", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i31", "sym_num" : 1, "phys_page" : "page20", "block" : "top/xc2_fpga_blk", "page" : "page20", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20" } ] }, "C133_SP_XF.1" : { "node_name" : "C133_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I520", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i520" } ], "part_number" : "402-000200-003", "net_name" : "PM2_SP_AGND_SP", "pin_name" : "A", "refdes" : "C133_SP_XF" }, "R90_SP_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R90_SP_XF", "pin_name" : "B", "net_name" : "UNNAMED_5_LTM4650FIXED_I78_MODEPLLIN_SP", "part_number" : "400-000014-011", "marker_data" : [ { "page_instance" : "I139", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i139", "sym_num" : 1, "phys_page" : "page5", "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5" } ], "node_name" : "R90_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U3_XF.A2" : { "pin_number" : "A2", "pin_type" : "NC", "node_name" : "U3_XF.A2", "part_number" : "450-000341-001", "pin_name" : "DNU_1", "refdes" : "U3_XF", "net_name" : "NC", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "page_instance" : "I39", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i39", "page" : "page15", "block" : "top/xc2_fpga_blk", "phys_page" : "page15", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "remapped_page" : null } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "DNU_1" }, "C474_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I26", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i26", "sym_num" : 1, "phys_page" : "page20", "page" : "page20", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20" } ], "refdes" : "C474_XF", "pin_name" : "A", "net_name" : "PWR_RN_RUC_MGTVCCAUX_XF", "part_number" : "402-000010-001", "node_name" : "C474_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.BL12" : { "node_name" : "U1_XF.BL12", "pin_number" : "BL12", "pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_37;", "pin_name_unsanitized" : "GND_909", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "sym_num" : 37, "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24" } ], "net_name" : "GND", "pin_name" : "GND_909", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "C20.2" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page7_i13", "ppath_without_last_instance" : "top/page7", "page_instance" : "I13", "path" : "@top_lib.top(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top", "phys_page" : "page7" } ], "pin_name" : "B", "refdes" : "C20", "net_name" : "GND", "part_number" : "402-000010-001", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C20.2" }, "R113_FL_XF.2" : { "node_name" : "R113_FL_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page9", "phys_page" : "page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I74", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i74" } ], "part_number" : "400-000010-116", "net_name" : "UNNAMED_9_LT3071_I66_IMON_FL", "pin_name" : "B", "refdes" : "R113_FL_XF" }, "U1_XF.AT12" : { "pin_name_unsanitized" : "PCIE1_TXN7", "pin_group" : "ALL_SIGNAL_PINS_3;", "pin_name" : "PCIE1_TXN7", "net_name" : "AC_PCIE1_TXN<7>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775", "sym_num" : 3, "page_instance" : "I775", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_page" : "page11", "block" : "top/xc2_fpga_blk", "page" : "page11" } ], "node_name" : "U1_XF.AT12", "pin_number" : "AT12", "pin_type" : "INOUT" }, "R28_FL_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R28_FL_XF.2", "pin_name" : "B", "refdes" : "R28_FL_XF", "net_name" : "P3R3V", "part_number" : "400-000010-074", "marker_data" : [ { "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page5", "phys_page" : "page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I27", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i27" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "R4.1" : { "node_name" : "R4.1", "pin_number" : "1", "pin_type" : "ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000014-011", "pin_name" : "A", "refdes" : "R4", "net_name" : "DIS_1R8V_I2C_XLAT_F", "marker_data" : [ { "ppath" : "top/page12_i14", "sym_num" : 1, "page_instance" : "I14", "ppath_without_last_instance" : "top/page12", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page12", "phys_page" : "page12", "page" : "page12", "block" : "top" } ] }, "R14_E0_XF.1" : { "node_name" : "R14_E0_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i42", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "page_instance" : "I42", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4" } ], "refdes" : "R14_E0_XF", "pin_name" : "A", "net_name" : "PWR_FPGA_3R3V", "part_number" : "400-000010-010" }, "R41_FL_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8_i5", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8", "page_instance" : "I5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page8", "phys_page" : "page8" } ], "part_number" : "400-000010-010", "net_name" : "P3R3V", "pin_name" : "B", "refdes" : "R41_FL_XF", "node_name" : "R41_FL_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "R22_SP_XF.2" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I83", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i83", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null } ], "part_number" : "400-000010-033", "pin_name" : "B", "net_name" : "VS_VCCINT_P_SP", "refdes" : "R22_SP_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R22_SP_XF.2" }, "R120_SP_XF.2" : { "net_name" : "UNNAMED_3_LTC2975_I168_SHARECLK_SP", "pin_name" : "B", "refdes" : "R120_SP_XF", "part_number" : "400-000010-108", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i102", "sym_num" : 1, "page_instance" : "I102", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R120_SP_XF.2" }, "U1.24" : { "node_name" : "U1.24", "pin_number" : "24", "pin_type" : "OUTPUT", "pin_name_unsanitized" : "OUT0_P", "pinuse" : "OUT;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page10_i51", "ppath_without_last_instance" : "top/page10", "page_instance" : "I51", "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "remapped_page" : null, "page" : "page10", "block" : "top", "phys_page" : "page10" } ], "pin_name" : "OUT0_P", "net_name" : "DDR4_REF_CLK_P", "refdes" : "U1", "part_number" : "450-000308-002" }, "NS3_SD_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "NS3_SD_XF.1", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4_i5", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4", "page_instance" : "I5" } ], "part_number" : "NET_SHORT", "pin_name" : "A", "refdes" : "NS3_SD_XF", "net_name" : "PWR_SDIMM_VTT_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "C69_SP_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "refdes" : "C69_SP_XF", "net_name" : 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"pin_name_unsanitized" : "GND_9", "pinuse" : "GROUND;" }, "C247_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C247_XF.1", "pin_name" : "A", "net_name" : "PWR_VCCINT_XF", "refdes" : "C247_XF", "part_number" : "402-000015-006", "marker_data" : [ { "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "page_instance" : "I39", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i39", "sym_num" : 1 } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "R109_SD_XF.1" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i26", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", 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"refdes" : "J1_XF", "pin_name" : "A10_AP", "net_name" : "C0_DDR4_ADR<10>_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180" } ], "pinuse" : "IN;", "pin_name_unsanitized" : "A10_AP", "pin_type" : "INPUT", "pin_number" : "225", "node_name" : "J1_XF.225" }, "U1_XF.BU37" : { "pin_name_unsanitized" : "GND_999", "pin_group" : "ALL_POWER_PINS_37;", "part_number" : "450-000340-001", "pin_name" : "GND_999", "net_name" : "GND", "refdes" : "U1_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I72", "sym_num" : 37, "ppath" : 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"pin_name" : "B", "refdes" : "C23_FL_XF", "net_name" : "GND", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C23_FL_XF.2" }, "C248_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000015-006", "net_name" : "PWR_VCCINT_XF", "pin_name" : "A", "refdes" : "C248_XF", "marker_data" : [ { "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "page_instance" : "I40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i40", "sym_num" : 1 } ], "node_name" : "C248_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "R10_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R10_XF.2", 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"pin_name" : "C2_DDR4_DQ70", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "C2_UNIB_1_6_57;", "pin_name_unsanitized" : "C2_DDR4_DQ70", "pin_type" : "INOUT", "pin_number" : "A58", "node_name" : "U1_XF.A58" }, "U1_XF.AA25" : { "pin_number" : "AA25", "pin_type" : "INOUT", "node_name" : "U1_XF.AA25", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I69", "sym_num" : 34, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69" } ], "net_name" : "GND", "pin_name" : "GND_324", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_324" }, "U11.12" : { "pin_name_unsanitized" : "AIN7", "pinuse" : "IN;", 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"pin_name_unsanitized" : "A", "pin_group" : "1;" }, "U1_E1_XF.21" : { "node_name" : "U1_E1_XF.21", "pin_number" : "21", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDDA", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i37", "sym_num" : 1, "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4" } ], "part_number" : "450-000345-001", "pin_name" : "VDDA", "net_name" : "PWR_FPGA_3R3V", "refdes" : "U1_E1_XF" }, "U1_XF.AB19" : { "pin_number" : "AB19", "pin_type" : "INOUT", "node_name" : "U1_XF.AB19", "marker_data" : [ { "ppath" : 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"net_name" : "GND", "refdes" : "PM2_SP_XF", "pin_name" : "GND_59", "part_number" : "462-000309-001", "pin_name_unsanitized" : "GND_59", "pinuse" : "GROUND;" }, "J1_E3_XF.B10" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3_i101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3", "page_instance" : "I101", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "phys_page" : "page3" } ], "part_number" : "410-000317-001", "pin_name" : "PERST0_F", "net_name" : "E1S3_3R3V_PERST_F<0>_XF", "refdes" : "J1_E3_XF", "pinuse" : "IN;", "pin_name_unsanitized" : "PERST0_F", "pin_number" : "B10", "pin_type" : "INPUT", "node_name" : "J1_E3_XF.B10" }, "PM7_SP_XF.L10" : { "node_name" : "PM7_SP_XF.L10", "pin_number" : "L10", "pin_type" : "POWER", "pin_name_unsanitized" : "VIN_21", "pinuse" : "POWER;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80", "sym_num" : 1, "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "refdes" : "PM7_SP_XF", "pin_name" : "VIN_21", "net_name" : "P12V_4650_BR_SP", "part_number" : "462-000308-002" }, "J1_XF.77" : { "pin_name_unsanitized" : "VTT_1", "pinuse" : "POWER;", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : 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} ], "node_name" : "R15_E3_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "C69_XF.1" : { "net_name" : "PWR_VCCINT_XF", "pin_name" : "A", "refdes" : "C69_XF", "part_number" : "402-000015-007", "marker_data" : [ { "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "page_instance" : "I138", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i138", "sym_num" : 1 } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C69_XF.1" }, "C228_XF.1" : { "node_name" : "C228_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "sym_num" : 1, "ppath" : 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"pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C159_XF.1" }, "FB7.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "net_name" : "P12V_MAIN", "pin_name" : "A", "refdes" : "FB7", "part_number" : "401-000001-002", "marker_data" : [ { "block" : "top", "page" : "page20", "phys_page" : "page20", "phys_path" : "@top_lib.top(sch_1):page20", "path" : "@top_lib.top(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page20", "page_instance" : "I56", "sym_num" : 1, "ppath" : "top/page20_i56" } ], "node_name" : "FB7.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "J1_O0_XF.B4" : { "pin_number" : "B4", "pin_type" : "INPUT", "node_name" : "J1_O0_XF.B4", "part_number" : "410-000324-001", "refdes" : "J1_O0_XF", "pin_name" : "PETN0", "net_name" : "OCL0_PET_N<0>_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i6/ocl_x4_conn_blk/page3_i84", "ppath_without_last_instance" : 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: "2", "node_name" : "C284_XF.2", "pin_name" : "B", "refdes" : "C284_XF", "net_name" : "GND", "part_number" : "402-000010-011", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "page_instance" : "I47", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i47", "page" : "page21", "block" : "top/xc2_fpga_blk", "phys_page" : "page21", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "remapped_page" : null } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "U1_XF.AT59" : { "pin_number" : "AT59", "pin_type" : "INOUT", "node_name" : "U1_XF.AT59", "marker_data" : [ { "sym_num" : 18, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I51", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30" } ], "pin_name" : "VCCO_28_3", "net_name" : "NC", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_18;", "pin_name_unsanitized" : "VCCO_28_3" }, "U1_XF.W60" : { "pin_type" : "INOUT", "pin_number" : "W60", "node_name" : "U1_XF.W60", "refdes" : "U1_XF", "pin_name" : "IO_L20N_T3L_N3_AD1N_31", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I53", "sym_num" : 23, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53" } ], "pin_name_unsanitized" : "IO_L20N_T3L_N3_AD1N_31", "pin_group" : "ALL_SIGNAL_PINS_23;" }, "J4_XF.20" : { "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10" } ], "pin_name" : "VSS_51", "refdes" : "J4_XF", "net_name" : "GND", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_51", "pinuse" : "UNSPEC;", "pin_number" : "20", "pin_type" : "GROUND", "node_name" : "J4_XF.20" }, "C414_XF.2" : { "node_name" : "C414_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "C414_XF", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000010-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i175", "sym_num" : 1, "page_instance" : "I175", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4" } ] }, "J2_XF.245" : { "node_name" : "J2_XF.245", "pin_number" : "245", "pin_type" : "INOUT", "pin_name_unsanitized" : "DQS4_T", "pinuse" : "TRI;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "block" : "top/xc2_fpga_blk", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : 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{ "part_number" : "450-000313-001", "pin_name" : "RGB_LED_BLUE0", "refdes" : "U1_CPLD", "net_name" : "RGB_LED_BLUE<0>_CPLD", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page3_i447", "sym_num" : 1, "page_instance" : "I447", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/cpld_blk", "page" : "page3" } ], "pinuse" : "BI;", "pin_name_unsanitized" : "RGB_LED_BLUE0", "pin_group" : "BK0_LED_1;", "pin_type" : "INOUT", "pin_number" : "E6", "node_name" : "U1_CPLD.E6" }, "J4_XF.106" : { "node_name" : "J4_XF.106", "pin_number" : "106", "pin_type" : "INOUT", "pin_name_unsanitized" : "DQ44", "pinuse" : "TRI;", "refdes" : "J4_XF", "pin_name" : "DQ44", "net_name" : "C3_DDR4_DQ<44>_XF", "part_number" : "410-000300-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk", 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"pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk" } ], "net_name" : "GND", "pin_name" : "VSS_3", "refdes" : "J3_XF", "part_number" : "410-000300-001", "node_name" : "J3_XF.2", "pin_number" : "2", "pin_type" : "GROUND" }, "C94_XF.1" : { "node_name" : "C94_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "refdes" : "C94_XF", "net_name" : "PWR_VCCINT_XF", "part_number" : "402-000015-008", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i106", "sym_num" : 1, "page_instance" : "I106", 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"pinuse" : "UNSPEC;" }, "R77_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page17", "phys_page" : "page17", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i52", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I52" } ], "net_name" : "UNNAMED_17_BYPASSCAPNPOL_I48_B_XF", "pin_name" : "B", "refdes" : "R77_XF", "part_number" : "400-000010-010", "node_name" : "R77_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "PM4_SP_XF.C8" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : 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"pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "ppath" : "top/page7_i5", "sym_num" : 1, "page_instance" : "I5", "ppath_without_last_instance" : "top/page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page7", "path" : "@top_lib.top(sch_1):page7", "phys_page" : "page7", "block" : "top", "page" : "page7" } ], "part_number" : "400-000010-084", "pin_name" : "B", "net_name" : "UNNAMED_7_NMOSFETVMT3_I2_D", "refdes" : "R22" }, "U1_XF.L55" : { "marker_data" : [ { "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425", "sym_num" : 6 } ], "pin_name" : "C2_DDR4_CKE0", "net_name" : "C2_DDR4_CKE<0>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "C2_ACTL_6_6;", "pin_name_unsanitized" : "C2_DDR4_CKE0", "pin_type" : "INOUT", "pin_number" : "L55", "node_name" : "U1_XF.L55" }, "U1_CPLD.C6" : { "part_number" : "450-000313-001", "net_name" : "JT_CPLD_TDO", "pin_name" : "TDO", "refdes" : "U1_CPLD", "marker_data" : [ { "page_instance" : "I61", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page5", "ppath" : "top/page14_i1/cpld_blk/page5_i61", "sym_num" : 2, "phys_page" : "page5", "block" : "top/cpld_blk", "page" : "page5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5" } ], "pinuse" : "BI;", "pin_name_unsanitized" : "TDO", "pin_number" : "C6", "pin_type" : "INOUT", "node_name" : "U1_CPLD.C6" }, "PM3_SP_XF.H5" : { "pin_number" : "H5", "pin_type" : "POWER", "node_name" : "PM3_SP_XF.H5", "pin_name" : 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"pinuse" : "POWER;", "pin_name_unsanitized" : "GND_9" }, "U1_XF.AJ23" : { "node_name" : "U1_XF.AJ23", "pin_type" : "INOUT", "pin_number" : "AJ23", "pin_group" : "ALL_POWER_PINS_35;", "pin_name_unsanitized" : "GND_498", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I70", "sym_num" : 35, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "net_name" : "GND", "pin_name" : "GND_498", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "C69.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C69.2", "marker_data" : [ { "phys_page" : "page19", "block" : "top", "page" : "page19", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page19", "path" : "@top_lib.top(sch_1):page19", "page_instance" : "I61", "ppath_without_last_instance" : "top/page19", "ppath" : "top/page19_i61", "sym_num" : 1 } ], "pin_name" : "B", "net_name" : "P3R3V", "refdes" : "C69", "part_number" : "402-000010-032", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "C100_SP_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "phys_page" : "page6", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i494", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I494" } ], "net_name" : "GND", "pin_name" : "B", "refdes" : "C100_SP_XF", "part_number" : "402-000010-031", "node_name" : "C100_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "PM7_SP_XF.M4" : { "pin_name" : "VIN_25", "net_name" : "P12V_4650_BR_SP", "refdes" : "PM7_SP_XF", "part_number" : "462-000308-002", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I80", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "phys_page" : "page11" } ], "pin_name_unsanitized" : "VIN_25", "pinuse" : "POWER;", "pin_number" : "M4", "pin_type" : "POWER", "node_name" : "PM7_SP_XF.M4" }, "C29.1" : { "refdes" : "C29", "pin_name" : "A", "net_name" : "P12V_MAIN", "part_number" : "402-000500-005", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19", "remapped_page" : null, "page" : "page19", "block" : "top", "phys_page" : "page19", "sym_num" : 1, "ppath" : "top/page19_i73", "ppath_without_last_instance" : "top/page19", "page_instance" : "I73" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C29.1" }, "C6_E0_XF.1" : { "pin_name" : "A", "refdes" : "C6_E0_XF", "net_name" : "GND", "part_number" : "402-000010-012", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3", "page_instance" : "I98", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3_i98", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C6_E0_XF.1" }, "R2_E1_XF.2" : { "node_name" : "R2_E1_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "UNNAMED_4_PI6CB33401_I37_OE2F_E1", "refdes" : "R2_E1_XF", "part_number" : "400-000010-006", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i14", "sym_num" : 1, "page_instance" : "I14", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4" } ] }, "J3_XF.109" : { "pin_name" : "VSS_2", "refdes" : "J3_XF", "net_name" : "GND", "part_number" : "410-000300-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180" } ], "pin_name_unsanitized" : "VSS_2", "pinuse" : "UNSPEC;", "pin_type" : "GROUND", "pin_number" : "109", "node_name" : "J3_XF.109" }, "U1.55" : { "marker_data" : [ { "phys_page" : "page10", "block" : "top", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "page_instance" : "I51", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i51", "sym_num" : 1 } ], "refdes" : "U1", "pin_name" : "RSVD_3", "net_name" : "NC", "part_number" : "450-000308-002", "pin_name_unsanitized" : "RSVD_3", "pinuse" : "IN;", "pin_type" : "INPUT", "pin_number" : "55", "node_name" : "U1.55" }, "PM3_SP_XF.G5" : { "node_name" : "PM3_SP_XF.G5", "pin_number" : "G5", "pin_type" : "OUTPUT", "pin_name_unsanitized" : "CLKOUT", "pinuse" : "OUT;", "marker_data" : [ { "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i151", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I151", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "phys_page" : "page10" } ], "net_name" : "UNNAMED_10_LTM4650FIXED_I151_CLKOUT_SP", "pin_name" : "CLKOUT", "refdes" : "PM3_SP_XF", "part_number" : "462-000308-002" }, "R16_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R16_XF.2", "pin_name" : "B", "refdes" : "R16_XF", "net_name" : "POR_OVERRIDE_XF", "part_number" : "400-000010-006", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "remapped_page" : null, "page" : "page18", "block" : "top/xc2_fpga_blk", "phys_page" : "page18", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page18_i32", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page18", "page_instance" : "I32" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "J1_E1_XF.B35" : { "pin_number" : "B35", "node_name" : "J1_E1_XF.B35", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i101", "sym_num" : 1, "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3" } ], "refdes" : "J1_E1_XF", "pin_name" : "GND_26", "net_name" : "GND", "part_number" : "410-000317-001", "pin_name_unsanitized" : "GND_26", "pinuse" : "GROUND;" }, "U1.16" : { "pin_number" : "16", "pin_type" : "INPUT", "node_name" : "U1.16", "part_number" : "450-000308-002", "refdes" : "U1", "pin_name" : "SCLK", "net_name" : "BASE_1R8V_SCL", "marker_data" : [ { "ppath_without_last_instance" : "top/page10", "page_instance" : "I51", "sym_num" : 1, "ppath" : "top/page10_i51", "page" : "page10", "block" : "top", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "remapped_page" : null } ], "pinuse" : "IN;", "pin_name_unsanitized" : "SCLK" }, "R62.1" : { "part_number" : "400-000010-074", "pin_name" : "A", "refdes" : "R62", "net_name" : "JT_FPGA_INST_F", "marker_data" : [ { "phys_page" : "page15", "page" : "page15", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page15", "page_instance" : "I105", "ppath_without_last_instance" : "top/page15", "ppath" : "top/page15_i105", "sym_num" : 1 } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R62.1" }, "U7_FL_XF.7" : { "pin_type" : "POWER", "pin_number" : "7", "node_name" : "U7_FL_XF.7", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i30", "sym_num" : 1, "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page9" } ], "pin_name" : "VIN_7", "net_name" : "PWR_VCCAUX_SW_XF", "refdes" : "U7_FL_XF", "part_number" : "450-000057-001", "pin_name_unsanitized" : "VIN_7", "pinuse" : "POWER;" }, "C449_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C449_XF.2", "marker_data" : [ { "page_instance" : "I161", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i161", "sym_num" : 1, "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8" } ], "pin_name" : "B", "net_name" : "PWR_NDIMM_VDD_XF", "refdes" : "C449_XF", "part_number" : "402-000010-028", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "U1_XF.BC15" : { "pin_number" : "BC15", "pin_type" : "INOUT", "node_name" : "U1_XF.BC15", "net_name" : "NC", "pin_name" : "MGTREFCLK1P_225", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 13, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i57", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I57", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31" } ], "pin_name_unsanitized" : "MGTREFCLK1P_225", "pin_group" : "ALL_SIGNAL_PINS_13;" }, "J3_XF.211" : { "pin_name_unsanitized" : "A7", "pinuse" : "IN;", "pin_name" : "A7", "net_name" : "C2_DDR4_ADR<7>_XF", "refdes" : "J3_XF", "part_number" : "410-000300-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk" } ], "node_name" : "J3_XF.211", "pin_type" : "INPUT", "pin_number" : "211" }, "J2_P1_XF.A19" : { "pin_name_unsanitized" : "PERN3", "pinuse" : "OUT;", "marker_data" : [ { "page_instance" : "I85", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i85", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3" } ], "pin_name" : "PERN3", "net_name" : "PCIE1_RXN<7>_XF", "refdes" : "J2_P1_XF", "part_number" : "410-000324-001", "node_name" : "J2_P1_XF.A19", "pin_number" : "A19", "pin_type" : "OUTPUT" }, "U3_FL_XF.5" : { "pin_name_unsanitized" : "VIN_5", "pinuse" : "POWER;", "pin_name" : "VIN_5", "net_name" : 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"pin_name" : "VDD_DIG", "part_number" : "450-000345-001", "marker_data" : [ { "page_instance" : "I63", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i63", "sym_num" : 1, "phys_page" : "page29", "block" : "top/xc2_fpga_blk", "page" : "page29", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29" } ] }, "U1_XF.AK51" : { "pin_group" : "ALL_POWER_PINS_35;", "pin_name_unsanitized" : "GND_524", "marker_data" : [ { "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : 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"pin_type" : "INOUT", "pin_name_unsanitized" : "GND_28", "pin_group" : "ALL_POWER_PINS_33;", "part_number" : "450-000340-001", "pin_name" : "GND_28", "net_name" : "GND", "refdes" : "U1_XF", "marker_data" : [ { "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ] }, "C9_CPLD.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page7_i120", "sym_num" : 1, "page_instance" : "I120", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", 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"ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null } ], "pin_name" : "GND_95", "net_name" : "GND", "refdes" : "PM2_SP_XF", "part_number" : "462-000309-001" }, "C84.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-001", "pin_name" : "A", "net_name" : "GND", "refdes" : "C84", "marker_data" : [ { "page" : "page19", "block" : "top", "phys_page" : "page19", "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19", "remapped_page" : null, "ppath_without_last_instance" : "top/page19", "page_instance" : "I47", "sym_num" : 1, "ppath" : "top/page19_i47" } ], "node_name" : "C84.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "C484_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C484_XF.2", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i8", "sym_num" : 1, "page_instance" : "I8", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_page" : "page20", "page" : "page20", "block" : "top/xc2_fpga_blk" } ], "part_number" : "402-000010-001", "pin_name" : "B", "net_name" : "GND", "refdes" : "C484_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "PM3_SP_XF.K4" : { "refdes" : "PM3_SP_XF", "pin_name" : "VIN_9", "net_name" : "P12V_4650_BL_SP", "part_number" : "462-000308-002", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i152", 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"phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I283", "sym_num" : 9, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283" } ], "node_name" : "U1_XF.AG19", "pin_number" : "AG19", "pin_type" : "INOUT" }, "U1_XF.BH59" : { "pin_type" : "INOUT", "pin_number" : "BH59", "node_name" : "U1_XF.BH59", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i47", "sym_num" : 19, "page_instance" : "I47", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk" } ], "part_number" : "450-000340-001", "pin_name" : "IO_L1N_T0L_N1_DBC_25", "net_name" : "NC", "refdes" : "U1_XF", "pin_group" : "ALL_SIGNAL_PINS_19;", "pin_name_unsanitized" : "IO_L1N_T0L_N1_DBC_25" }, "R42_XF.1" : { "pin_name" : "A", "net_name" : "FPGA_VCCAUX_P1R8V", "refdes" : "R42_XF", "part_number" : "400-000010-007", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "page_instance" : "I7", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i7", "block" : "top/xc2_fpga_blk", "page" : "page15", "phys_page" : "page15", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "remapped_page" : null } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R42_XF.1" }, "U7_XF.17" : { "node_name" : "U7_XF.17", "pin_number" : "17", "pin_type" : "OUTPUT", "pin_name_unsanitized" : "Q1_P", "pinuse" : "OUT;", "marker_data" : [ { "sym_num" : 1, "ppath" : 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"pin_number" : "A13" }, "C428_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C428_XF.1", "net_name" : "GND", "pin_name" : "A", "refdes" : "C428_XF", "part_number" : "402-000010-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i164", "sym_num" : 1, "page_instance" : "I164", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk", "page" : "page6" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "C13_CPLD.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C13_CPLD.1", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I117", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page7_i117", "block" : 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"pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C477_XF.1" }, "U6_FL_XF.17" : { "pin_name" : "VOUT_17", "net_name" : "PWR_AVCC_RN_XF", "refdes" : "U6_FL_XF", "part_number" : "450-000057-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "page_instance" : "I30" } ], "pin_name_unsanitized" : "VOUT_17", "pinuse" : "POWER;", "pin_number" : "17", "pin_type" : "POWER", "node_name" : "U6_FL_XF.17" }, "J4_XF.83" : { "refdes" : "J4_XF", "pin_name" : "VDD_8", "net_name" : "PWR_NDIMM_VDD_XF", "part_number" : "410-000300-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page10", "phys_page" : "page10" } ], "pin_name_unsanitized" : "VDD_8", "pinuse" : "POWER;", "pin_type" : "POWER", "pin_number" : "83", "node_name" : "J4_XF.83" }, "U1_XF.BN16" : { "pin_name_unsanitized" : "GND_937", "pin_group" : "ALL_POWER_PINS_37;", "part_number" : "450-000340-001", "pin_name" : "GND_937", "refdes" : "U1_XF", "net_name" : "GND", "marker_data" : [ { "sym_num" : 37, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "ppath_without_last_instance" : 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"pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C358_XF.1" }, "U1_XF.BU55" : { "node_name" : "U1_XF.BU55", "pin_number" : "BU55", "pin_type" : "INOUT", "pin_group" : "C1_LNIB_1_5_39;", "pin_name_unsanitized" : "C1_DDR4_DQ18", "marker_data" : [ { "sym_num" : 41, "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "page_instance" : "I2425", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "PAGE5", "phys_page" : "PAGE5" } ], "net_name" : "C1_DDR4_DQ<18>_XF", "pin_name" : "C1_DDR4_DQ18", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "J3_XF.55" : { "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : 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"@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "page_instance" : "I80", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i80" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_24" }, "PM2_SP_XF.C8" : { "pin_name_unsanitized" : "GND_19", "pinuse" : "GROUND;", "refdes" : "PM2_SP_XF", "pin_name" : "GND_19", "net_name" : "GND", "part_number" : "462-000309-001", "marker_data" : [ { "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "page_instance" : "I459", "ppath_without_last_instance" : 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"net_name" : "GND", "refdes" : "C30_SD_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4_i22", "sym_num" : 1, "page_instance" : "I22", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C30_SD_XF.2" }, "U1_XF.BM18" : { "node_name" : "U1_XF.BM18", "pin_number" : "BM18", "pin_type" : "INOUT", "pin_group" : "OCL_SB_0_1_11_11;", "pin_name_unsanitized" : "OCL_3R3V_CWAKE_F0", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I274", "sym_num" : 11, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i274", "page" : "page14", "block" : "top/xc2_fpga_blk", "phys_page" : "page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null } ], "part_number" : "450-000340-001", "net_name" : "OCL0_3R3V_CWAKE_F_XF", "pin_name" : "OCL_3R3V_CWAKE_F0", "refdes" : "U1_XF" }, "C20_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C20_XF.1", "part_number" : "402-000015-007", "refdes" : "C20_XF", "pin_name" : "A", "net_name" : "PWR_VCCINT_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i97", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I97", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : 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"pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I249", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i249", "page" : "page13", "block" : "top/xc2_fpga_blk", "phys_page" : "page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null } ], "part_number" : "400-000010-007", "pin_name" : "A", "net_name" : "PWR_FPGA_3R3V", "refdes" : "R208_XF", "node_name" : "R208_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.BM37" : { "pin_name_unsanitized" : "VCCO_67_2", "pin_group" : "ALL_POWER_PINS_20;", "net_name" : "NC", "pin_name" : "VCCO_67_2", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "path" : 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"IO_L3P_T0L_N4_AD15P_19", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I50", "sym_num" : 17, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50" } ], "net_name" : "NC", "pin_name" : "IO_L3P_T0L_N4_AD15P_19", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "C417_XF.2" : { "node_name" : "C417_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "refdes" : "C417_XF", "net_name" : "GND", "part_number" : "402-000010-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i152", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I152", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4" } ] }, "R53_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R53_XF.2", "net_name" : "UNNAMED_22_RESISTOR_I37_B_XF", "pin_name" : "B", "refdes" : "R53_XF", "part_number" : "400-000010-006", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page22", "phys_page" : "page22", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "page_instance" : "I37" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "R196_XF.1" : { "node_name" : "R196_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "page" : "page13", "block" : "top/xc2_fpga_blk", "phys_page" : "page13", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i205", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I205" } ], "part_number" : "400-000010-010", "net_name" : "E1S2_FPGA_REFCLK_N<1>_XF", "pin_name" : "A", "refdes" : "R196_XF" }, "PM5_SP_XF.D1" : { "pin_type" : "POWER", "pin_number" : "D1", "node_name" : "PM5_SP_XF.D1", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5", "phys_page" : "page5", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I79" } ], "part_number" : "462-000308-002", "net_name" : "GND", "pin_name" : "GND_5", "refdes" : "PM5_SP_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_5" }, "U1_XF.BH12" : { "part_number" : "450-000340-001", "pin_name" : "MGTREFCLK1N_223", "net_name" : "NC", "refdes" : "U1_XF", "marker_data" : [ { "sym_num" : 13, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i57", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I57", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31" } ], "pin_name_unsanitized" : "MGTREFCLK1N_223", "pin_group" : "ALL_SIGNAL_PINS_13;", "pin_type" : "INOUT", "pin_number" : "BH12", "node_name" : "U1_XF.BH12" }, "R42_SP_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R42_SP_XF.2", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i192", "sym_num" : 1, "page_instance" : "I192", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "part_number" : "400-000014-011", "pin_name" : "B", "refdes" : "R42_SP_XF", "net_name" : "UNNAMED_3_LTC2975_I168_VINISN2975_SP", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "R21_FL_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R21_FL_XF", "pin_name" : "B", "net_name" : "UNNAMED_4_BYPASSCAPNPOL_I23_B_FL", "part_number" : "400-000010-006", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i22", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "page_instance" : "I22" } ], "node_name" : "R21_FL_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "R2.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R2.1", "part_number" : "400-000010-020", "pin_name" : "A", "net_name" : "P3R3V", "refdes" : "R2", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page13", "phys_page" : "page13", "page" : "page13", "block" : "top", "ppath" : "top/page13_i91", "sym_num" : 1, "page_instance" : "I91", "ppath_without_last_instance" : "top/page13" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "R35_SP_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R35_SP_XF", "pin_name" : "B", "net_name" : "VS_AVTT_LIN_N_XF", "part_number" : "400-000010-033", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I78", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i78" } ], "node_name" : "R35_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "R48_FL_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R48_FL_XF.2", "part_number" : "400-000010-010", "net_name" : "UNNAMED_4_LT3071_I30_V01_FL", "pin_name" : "B", "refdes" : "R48_FL_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i16", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "page_instance" : "I16", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page4" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "U1_XF.AG52" : { "pin_name_unsanitized" : "VCCO_30_3", "pin_group" : "ALL_POWER_PINS_23;", "refdes" : "U1_XF", "pin_name" : "VCCO_30_3", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53", "sym_num" : 23, "page_instance" : "I53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31" } ], "node_name" : "U1_XF.AG52", "pin_type" : "INOUT", "pin_number" : "AG52" }, "D1_MP.2" : { "refdes" : "D1_MP", "pin_name" : "A", "net_name" : "UNNAMED_4_LED_I22_A_MP", "part_number" : "404-000001-001", "marker_data" : [ { "page_instance" : "I22", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page4", "ppath" : "top/page18_i1/mgmt_pwr_block/page4_i22", "sym_num" : 1, "phys_page" : "page4", "block" : "top/mgmt_pwr_block", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4" } ], "pin_name_unsanitized" : "A", "pinuse" : "BI;", "pin_type" : "INOUT", "pin_number" : "2", "node_name" : "D1_MP.2" }, "C40.2" : { "node_name" : "C40.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "ppath" : "top/page20_i37", "sym_num" : 1, "page_instance" : "I37", "ppath_without_last_instance" : "top/page20", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page20", "phys_page" : "page20", "page" : "page20", "block" : "top" } ], "part_number" : "402-000010-041", "net_name" : "GND", "pin_name" : "B", "refdes" : "C40" }, "C274_XF.1" : { "node_name" : "C274_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_page" : "page14", "page" : "page14", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "page_instance" : "I173", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i173", "sym_num" : 1 } ], "pin_name" : "A", "net_name" : "AC_OCL2_PET_N<3>_XF", "refdes" : "C274_XF", "part_number" : "402-000010-035" }, "J3_XF.58" : { "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180" } ], "net_name" : "C2_DDR4_RESET_N_XF", "pin_name" : "RESET_N", "refdes" : "J3_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "RESET_N", "pinuse" : "IN;", "pin_type" : "INPUT", "pin_number" : "58", "node_name" : "J3_XF.58" }, "U1_XF.T26" : { "node_name" : "U1_XF.T26", "pin_number" : "T26", "pin_type" : "INOUT", "pin_name_unsanitized" : "C3_DDR4_ADR12", "pin_group" : "C3_ACTL_7_7;", "pin_name" : "C3_DDR4_ADR12", "net_name" : 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page9", "page_instance" : "I28", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page9", "remapped_page" : null, "page" : "page9", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page9" } ], "part_number" : "450-000162-001", "pin_name" : "NC_10", "net_name" : "NC", "refdes" : "U3_SP_XF", "pinuse" : "IN;", "pin_name_unsanitized" : "NC_10" }, "J1_P0_XF.B16" : { "node_name" : "J1_P0_XF.B16", "pin_number" : "B16", "pin_type" : "INPUT", "pin_name_unsanitized" : "PETN2", "pinuse" : "IN;", "pin_name" : "PETN2", "net_name" : "PCIE0_TXN<2>_XF", "refdes" : "J1_P0_XF", "part_number" : "410-000324-001", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1 } ] }, "J3_XF.225" : { "part_number" : "410-000300-001", "net_name" : "C2_DDR4_ADR<10>_XF", "pin_name" : "A10_AP", "refdes" : "J3_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : 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"node_name" : "J2_P1_XF.A4" }, "U1_XF.BG9" : { "node_name" : "U1_XF.BG9", "pin_type" : "INOUT", "pin_number" : "BG9", "pin_name_unsanitized" : "MGTAVTT_RS_1", "pin_group" : "ALL_POWER_PINS_29;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "MGTAVTT_RS_1", "net_name" : "PWR_AVTT_RS_XF", "marker_data" : [ { "phys_page" : "page20", "page" : "page20", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i86", "sym_num" : 29 } ] }, "U2_SP_XF.5" : { "pin_name_unsanitized" : "GND", "pinuse" : "POWER;", "pin_name" : "GND", "refdes" : "U2_SP_XF", "net_name" : "GND", "part_number" : "450-000162-001", "marker_data" : [ { "sym_num" : 1, "ppath" : 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5, "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6" } ], "pin_name_unsanitized" : "GND_49", "pinuse" : "GROUND;" }, "C449_XF.1" : { "part_number" : "402-000010-028", "pin_name" : "A", "refdes" : "C449_XF", "net_name" : "GND", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i161", "sym_num" : 1, "page_instance" : "I161", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C449_XF.1" }, "R339.2" : { "node_name" : "R339.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "phys_page" : "page10", "block" : "top", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "page_instance" : "I70", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i70", "sym_num" : 1 } ], "part_number" : "400-000010-007", "pin_name" : "B", "refdes" : "R339", "net_name" : "UNNAMED_10_RESISTOR_I70_B" }, "R30_XF.2" : { "pin_name" : "B", "net_name" : "UNNAMED_21_RESISTOR_I32_B_XF", "refdes" : "R30_XF", "part_number" : "400-000010-006", "marker_data" : [ { "phys_page" : "page21", "block" : "top/xc2_fpga_blk", "page" : "page21", "remapped_page" : null, "phys_path" : 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: "Y56", "pin_type" : "INOUT" }, "R115_SP_XF.1" : { "part_number" : "400-000014-011", "net_name" : "UNNAMED_7_LTM4671_I87_MODECLKIN0_SP", "pin_name" : "A", "refdes" : "R115_SP_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i25", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I25", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R115_SP_XF.1" }, "J4_XF.134" : { "pin_type" : "GROUND", "pin_number" : "134", "node_name" : "J4_XF.134", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10" } ], "refdes" : "J4_XF", "pin_name" : "VSS_71", "net_name" : "GND", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_71", "pinuse" : "UNSPEC;" }, "PM5_SP_XF.F11" : { "pin_name_unsanitized" : "GND_24", "pinuse" : "POWER;", "pin_name" : "GND_24", "net_name" : "GND", "refdes" : "PM5_SP_XF", "part_number" : "462-000308-002", "marker_data" : [ { "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : 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"net_name" : "PWR_SDIMM_VDD_XF", "part_number" : "402-000010-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I164", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i164" } ] }, "J1_O2_XF.A4" : { "pin_name_unsanitized" : "PERN0", "pinuse" : "OUT;", "net_name" : "OCL2_PER_N<0>_XF", "pin_name" : "PERN0", "refdes" : "J1_O2_XF", "part_number" : "410-000324-001", "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i30@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_path" : 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"J1_E3_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3_i101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3", "page_instance" : "I101" } ], "pinuse" : "OUT;", "pin_name_unsanitized" : "PERP3", "pin_type" : "OUTPUT", "pin_number" : "A27", "node_name" : "J1_E3_XF.A27" }, "U11_FL_XF.1" : { "marker_data" : [ { "page_instance" : "I66", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i66", "sym_num" : 1, "phys_page" : "page9", "page" : "page9", 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"phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "phys_page" : "page21", "page" : "page21", "block" : "top/xc2_fpga_blk" } ], "pin_name_unsanitized" : "IO_T0U_N12_VRP_21", "pin_group" : "ALL_SIGNAL_PINS_27;" }, "J4_XF.72" : { "pin_name" : "A1", "refdes" : "J4_XF", "net_name" : "C3_DDR4_ADR<1>_XF", "part_number" : "410-000300-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180" } ], "pin_name_unsanitized" : "A1", "pinuse" : "IN;", "pin_number" : "72", "pin_type" : "INPUT", "node_name" : "J4_XF.72" }, "C214_XF.1" : { "node_name" : "C214_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "refdes" : "C214_XF", "net_name" : "GND", "part_number" : "402-000010-028", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page10", "phys_page" : "page10", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i163", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I163" } ] }, "C9_CPLD.2" : { "pin_name" : "B", "net_name" : "CPLD_P1R8V_1", "refdes" : "C9_CPLD", "part_number" : "402-000010-001", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page7_i120", "sym_num" : 1, "page_instance" : "I120", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "remapped_page" : null, "phys_path" : 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"path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4" } ], "node_name" : "R27_FL_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C484_XF.1" : { "part_number" : "402-000010-001", "net_name" : "PWR_AVTT_RS_XF", "pin_name" : "A", "refdes" : "C484_XF", "marker_data" : [ { "page" : "page20", "block" : "top/xc2_fpga_blk", "phys_page" : "page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I8", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i8" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C484_XF.1" }, "U1_XF.AK45" : { "pin_name_unsanitized" : "IO_L21N_T3L_N5_AD8N_29", "pin_group" : "ALL_SIGNAL_PINS_24;", "pin_name" : "IO_L21N_T3L_N5_AD8N_29", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 24, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I54", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31" } ], "node_name" : "U1_XF.AK45", "pin_type" : "INOUT", "pin_number" : "AK45" }, "C23_SP_XF.2" : { "pin_name" : "B", "net_name" : "GND", "refdes" : "C23_SP_XF", "part_number" : "402-000010-006", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I151", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i151" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C23_SP_XF.2" }, "R123_SP_XF.1" : { "refdes" : "R123_SP_XF", "pin_name" : "A", "net_name" : "PWR_NDIMM_VPP_XF", "part_number" : "400-000014-011", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i81", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I81", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : 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"pinuse" : "IN;", "pin_name" : "REFCLKP1", "refdes" : "J1_E1_XF", "net_name" : "CONN_CLK_REFP<1>_E1", "part_number" : "410-000317-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "page_instance" : "I101", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3" } ], "node_name" : "J1_E1_XF.A15", "pin_number" : "A15", "pin_type" : "INPUT" }, "J2_P1_XF.B16" : { "pin_type" : "INPUT", "pin_number" : "B16", "node_name" : "J2_P1_XF.B16", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i85", "sym_num" : 1, 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"pin_name_unsanitized" : "SGND_3" }, "U1_XF.CA22" : { "pin_group" : "ALL_SIGNAL_PINS_66;", "pin_name_unsanitized" : "C0_DDR4_DQS_C0", "marker_data" : [ { "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "sym_num" : 66, "phys_page" : "PAGE3", "block" : "top/xc2_fpga_blk", "page" : "PAGE3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3" } ], "pin_name" : "C0_DDR4_DQS_C0", "net_name" : "C0_RDIMM_DQS_C<0>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.CA22", "pin_type" : "INOUT", "pin_number" : "CA22" }, "J4_XF.158" : { "node_name" : "J4_XF.158", "pin_number" : "158", "pin_type" : "GROUND", "pin_name_unsanitized" : "VSS_37", "pinuse" : "UNSPEC;", "marker_data" : [ { "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" 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"J2_P1_XF.B12" : { "pinuse" : "IN;", "pin_name_unsanitized" : "REFCLK_P", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "page" : "page3", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i85", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "page_instance" : "I85" } ], "part_number" : "410-000324-001", "refdes" : "J2_P1_XF", "pin_name" : "REFCLK_P", "net_name" : "NC", "node_name" : "J2_P1_XF.B12", "pin_number" : "B12", "pin_type" : "INPUT" }, "U2_FL_XF.20" : { "node_name" : "U2_FL_XF.20", "pin_type" : "POWER", "pin_number" : "20", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_20", 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"pin_type" : "ANALOG" }, "U1_XF.AN1" : { "net_name" : "PCIE1_RXN<0>_XF", "pin_name" : "PCIE1_RXN0", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775", "sym_num" : 3, "page_instance" : "I775", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11" } ], "pin_name_unsanitized" : "PCIE1_RXN0", "pin_group" : "ALL_SIGNAL_PINS_3;", "pin_type" : "INOUT", "pin_number" : "AN1", "node_name" : "U1_XF.AN1" }, "R62_XF.2" : { "part_number" : "400-000010-010", "pin_name" : "B", "refdes" : "R62_XF", "net_name" : "GND", "marker_data" : [ { "page_instance" : "I219", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "ppath" : 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"@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page14", "phys_page" : "page14" } ], "node_name" : "U1_XF.BM8", "pin_type" : "INOUT", "pin_number" : "BM8" }, "J1_XF.277" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4" } ], "refdes" : "J1_XF", "pin_name" : "DQS7_C", "net_name" : "C0_RDIMM_DQS_C<7>_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "DQS7_C", "pinuse" : "TRI;", "pin_number" : "277", "pin_type" : "INOUT", "node_name" : "J1_XF.277" }, "R16.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000014-011", "pin_name" : "A", "net_name" : "CPLD_P1R8V_1", "refdes" : "R16", "marker_data" : [ { "page_instance" : "I139", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i139", "sym_num" : 1, "phys_page" : "page10", "page" : "page10", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10" } ], "node_name" : "R16.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "C23_SP_XF.1" : { "node_name" : "C23_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i151", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I151", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "phys_page" : "page3" } ], "part_number" : "402-000010-006", "pin_name" : "A", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I151_A_SP", "refdes" : "C23_SP_XF" }, "J3_XF.199" : { "node_name" : "J3_XF.199", "pin_type" : "INOUT", "pin_number" : "199", "pinuse" : "TRI;", "pin_name_unsanitized" : "CB7", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8" } ], "part_number" : "410-000300-001", "refdes" : "J3_XF", "pin_name" : "CB7", "net_name" : "C2_DDR4_DQ<71>_XF" }, "PM1_SP_XF.P4" : { "node_name" : "PM1_SP_XF.P4", "pin_number" : "P4", "pin_name_unsanitized" : "GND_63", "pinuse" : "GROUND;", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I11" } ], "pin_name" : "GND_63", "refdes" : "PM1_SP_XF", "net_name" : "GND", "part_number" : "462-000309-001" }, "U1_XF.BF32" : { "part_number" : "450-000340-001", "pin_name" : "GND_839", "net_name" : "GND", "refdes" : "U1_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "sym_num" : 37, "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24" } ], "pin_name_unsanitized" : "GND_839", "pin_group" : "ALL_POWER_PINS_37;", "pin_number" : "BF32", "pin_type" : "INOUT", "node_name" : "U1_XF.BF32" }, "R255_XF.1" : { "node_name" : "R255_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2156", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2156", "page" : "page9", "block" : "top/xc2_fpga_blk", "phys_page" : "page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "remapped_page" : null } ], "pin_name" : "A", "refdes" : "R255_XF", "net_name" : "PWR_NDIMM_VDD_XF", "part_number" : "400-000010-007" }, "U1_XF.CA16" : { "pin_name_unsanitized" : "C0_DDR4_ADR1", "pin_group" : "C0_ACTL_4_4;", "part_number" : "450-000340-001", "pin_name" : "C0_DDR4_ADR1", "net_name" : "C0_DDR4_ADR<1>_XF", "refdes" : "U1_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page3", "phys_page" : "page3", "sym_num" : 4, "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "page_instance" : "I2425" } ], "node_name" : "U1_XF.CA16", "pin_type" : "INOUT", "pin_number" : "CA16" }, "U4_FL_XF.25" : { "part_number" : "450-000057-001", "pin_name" : "V02", "refdes" : "U4_FL_XF", "net_name" : "UNNAMED_7_LT3071_I30_V02_FL", "marker_data" : [ { "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7_i30", "sym_num" : 1, "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7" } ], "pinuse" : "IN;", "pin_name_unsanitized" : "V02", "pin_number" : "25", "pin_type" : "INPUT", "node_name" : "U4_FL_XF.25" }, "C29_XF.2" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i643", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I643", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "page" : "page11", "block" : "top/xc2_fpga_blk", "phys_page" : "page11" } ], "part_number" : "402-000010-035", "net_name" : "PCIE1_TXP<4>_XF", "pin_name" : "B", "refdes" : "C29_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C29_XF.2" }, "PM4_SD_XF.J3" : { "node_name" : "PM4_SD_XF.J3", "pin_type" : "INPUT", "pin_number" : "J3", "pinuse" : "IN;", "pin_name_unsanitized" : "TSNS1A", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i40", "sym_num" : 3, "page_instance" : "I40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3" } ], "part_number" : "462-000304-001", "refdes" : "PM4_SD_XF", "pin_name" : "TSNS1A", "net_name" : "UNNAMED_3_LTM4675_I40_TSNS1A_SD" }, "R123_XF.1" : { "marker_data" : [ { "phys_page" : "page27", "block" : "top/xc2_fpga_blk", "page" : "page27", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27", "page_instance" : "I51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i51", "sym_num" : 1 } ], "part_number" : "400-000010-137", "refdes" : "R123_XF", "pin_name" : "A", "net_name" : "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R123_XF.1" }, "J4_XF.112" : { "node_name" : "J4_XF.112", "pin_number" : "112", "pin_type" : "GROUND", "pin_name_unsanitized" : "VSS_9", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1 } ], "net_name" : "GND", "pin_name" : "VSS_9", "refdes" : "J4_XF", "part_number" : "410-000300-001" }, "U1_XF.BW63" : { "pin_name" : "GND_1032", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 38, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I73", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24" } ], "pin_name_unsanitized" : "GND_1032", "pin_group" : "ALL_POWER_PINS_38;", "pin_type" : "INOUT", "pin_number" : "BW63", "node_name" : "U1_XF.BW63" }, "U1_XF.V41" : { "net_name" : "PWR_VCCINT_XF", "pin_name" : "VCCINT_11", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "sym_num" : 31, "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23" } ], "pin_name_unsanitized" : "VCCINT_11", "pin_group" : "ALL_POWER_PINS_31;", "pin_number" : "V41", "pin_type" : "INOUT", "node_name" : "U1_XF.V41" }, "C26_FL_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C26_FL_XF.1", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6_i33", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6", "page_instance" : "I33", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page6", "phys_page" : "page6" } ], "part_number" : "402-000010-032", "net_name" : "PWR_AVTT_SW_XF", "pin_name" : "A", "refdes" : "C26_FL_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "U1_XF.BW40" : { "pin_name_unsanitized" : "VAUX_N8", "pin_group" : "ALL_SIGNAL_PINS_2;", "pin_name" : "VAUX_N8", "net_name" : "UNNAMED_17_BYPASSCAPNPOL_I198_B_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I221", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i221", "sym_num" : 2, "phys_page" : "page17", "page" : "page17", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17" } ], "node_name" : "U1_XF.BW40", "pin_type" : "INOUT", "pin_number" : "BW40" }, "Q14.2" : { "pin_name" : "S", "net_name" : "UNNAMED_20_NMOSFETVMT3_I61_S", "refdes" : "Q14", "part_number" : "405-000010-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page20", "path" : "@top_lib.top(sch_1):page20", "remapped_page" : null, "block" : "top", "page" : "page20", "phys_page" : "page20", "sym_num" : 1, "ppath" : "top/page20_i61", "ppath_without_last_instance" : "top/page20", "page_instance" : "I61" } ], "pin_name_unsanitized" : "S", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "Q14.2" }, "U1_XF.N39" : { "pin_type" : "INOUT", "pin_number" : "N39", "node_name" : "U1_XF.N39", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i59", "sym_num" : 25, "page_instance" : "I59", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : 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"node_name" : "PM7_SP_XF.F10", "pin_number" : "F10", "pin_type" : "POWER" }, "U6_XF.10" : { "node_name" : "U6_XF.10", "pin_number" : "10", "pin_type" : "OUTPUT", "pinuse" : "OUT;", "pin_name_unsanitized" : "CK4O_P", "part_number" : "450-000037-001", "pin_name" : "CK4O_P", "refdes" : "U6_XF", "net_name" : "DDR4_SYS_CLK_P<3>_XF", "marker_data" : [ { "page_instance" : "I1", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i1", "sym_num" : 1, "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29" } ] }, "C6_E0_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "net_name" : "P12V_MAIN", "pin_name" : "B", "refdes" : "C6_E0_XF", "part_number" : "402-000010-012", "marker_data" : [ { "remapped_page" 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"phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page18_i1/mgmt_pwr_block/page3_i5", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page3", "page_instance" : "I5" } ], "part_number" : "402-000050-011", "net_name" : "UNNAMED_3_TIMINGCAPNPOL_I5_A_MP", "pin_name" : "A", "refdes" : "C2_MP" }, "U1_XF.G26" : { "pin_number" : "G26", "pin_type" : "INOUT", "node_name" : "U1_XF.G26", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "sym_num" : 50, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_page" : "PAGE9", "block" : "top/xc2_fpga_blk", "page" : "PAGE9" } ], "pin_name" : "C3_DDR4_DQ21", "net_name" : "C3_DDR4_DQ<21>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "C3_UNIB_1_7_48;", "pin_name_unsanitized" : "C3_DDR4_DQ21" }, "R67_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page17", "phys_page" : "page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I79", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i79" } ], "pin_name" : "B", "net_name" : "UNNAMED_17_RESISTOR_I56_A_XF", "refdes" : "R67_XF", "part_number" : "400-000010-097", "node_name" : "R67_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "J3_XF.36" : { "part_number" : "410-000300-001", "refdes" : "J3_XF", "pin_name" : "DQ28", "net_name" : "C2_DDR4_DQ<28>_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page8", "phys_page" : "page8" } ], "pinuse" : "TRI;", "pin_name_unsanitized" : "DQ28", "pin_number" : "36", "pin_type" : "INOUT", "node_name" : "J3_XF.36" }, "R173_XF.1" : { "part_number" : "400-000010-010", "refdes" : "R173_XF", "pin_name" : "A", "net_name" : "E1S0_FPGA_REFCLK_P<0>_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i228", "sym_num" : 1, "page_instance" : "I228", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R173_XF.1" }, "U1_XF.AJ2" : { "node_name" : "U1_XF.AJ2", "pin_number" : "AJ2", "pin_type" : "INOUT", "pin_name_unsanitized" : "E1S3_PER_P1", "pin_group" : "ALL_SIGNAL_PINS_10;", "net_name" : "E1S3_PER_P<1>_XF", "pin_name" : "E1S3_PER_P1", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I251", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i251", "sym_num" : 10, "phys_page" : "page13", "page" : "page13", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13" } ] }, "U1_XF.AH60" : { "pin_name_unsanitized" : "GND_489", "pin_group" : "ALL_POWER_PINS_35;", "part_number" : "450-000340-001", "pin_name" : "GND_489", "refdes" : "U1_XF", "net_name" : "GND", "marker_data" : [ { "sym_num" : 35, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I70", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24" } ], "node_name" : "U1_XF.AH60", "pin_number" : "AH60", "pin_type" : "INOUT" }, "PM1_SP_XF.H4" : { "net_name" : "PWR_NDIMM_VPP_XF", "refdes" : "PM1_SP_XF", "pin_name" : "VOUT1_7", "part_number" : "462-000309-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I37", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i37", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null } ], "pin_name_unsanitized" : "VOUT1_7", "pinuse" : "POWER;", "pin_number" : "H4", "node_name" : "PM1_SP_XF.H4" }, "C105_SP_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C105_SP_XF.2", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i55", "sym_num" : 1, "page_instance" : "I55", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7" } ], "part_number" : "402-000016-001", "net_name" : "UNNAMED_7_BYPASSCAPNPOL_I55_B_SP", "pin_name" : "B", "refdes" : "C105_SP_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "M3.MTG5" : { "part_number" : "HOLE_RING", "net_name" : "GND", "refdes" : "M3", "pin_name" : "MTG5", "marker_data" : [ { "page_instance" : "I59", "ppath_without_last_instance" : "top/page1", "ppath" : "top/page1_i59", "sym_num" : 1, "phys_page" : "page1", "block" : "top", "page" : "page1", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page1", "path" : "@top_lib.top(sch_1):page1" } ], "pinuse" : "NC;", "pin_name_unsanitized" : "MTG5", "pin_number" : "MTG5", "node_name" : "M3.MTG5" }, "U1_XF.CB26" : { "node_name" : "U1_XF.CB26", "pin_number" : "CB26", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_66;", "pin_name_unsanitized" : "C0_DDR4_DQS_T3", "marker_data" : [ { "sym_num" : 67, "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "page_instance" : "I2425", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "remapped_page" : null, "page" : "PAGE3", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE3" } ], "part_number" : "450-000340-001", "pin_name" : "C0_DDR4_DQS_T3", "net_name" : "C0_RDIMM_DQS_T<10>_XF", "refdes" : "U1_XF" }, "U1_XF.BA39" : { "node_name" : "U1_XF.BA39", "pin_number" : "BA39", "pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_36;", "pin_name_unsanitized" : "GND_729", "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "sym_num" : 36 } ], "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_729", "refdes" : "U1_XF" }, "U1_XF.BU46" : { "pin_name_unsanitized" : "IO_L3P_T0L_N4_AD15P_20", "pin_group" : "ALL_SIGNAL_PINS_17;", "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L3P_T0L_N4_AD15P_20", "refdes" : "U1_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "sym_num" : 17, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I50" } ], "node_name" : "U1_XF.BU46", "pin_type" : "INOUT", "pin_number" : "BU46" }, "PM4_SP_XF.A7" : { "refdes" : "PM4_SP_XF", "pin_name" : "GND_2", "net_name" : "GND", "part_number" : "462-000308-002", "marker_data" : [ { "page_instance" : "I79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i79", "sym_num" : 2, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4" } ], "pin_name_unsanitized" : "GND_2", "pinuse" : "POWER;", "pin_type" : "POWER", "pin_number" : "A7", "node_name" : "PM4_SP_XF.A7" }, "PM2_SP_XF.F10" : { "part_number" : "462-000309-001", "net_name" : "UNNAMED_6_RESISTOR_I435_B_SP", "pin_name" : "FREQ0", "refdes" : "PM2_SP_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i516", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I516", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6" } ], "pinuse" : "IN;", "pin_name_unsanitized" : "FREQ0", "pin_type" : "INPUT", "pin_number" : "F10", "node_name" : "PM2_SP_XF.F10" }, "C20_E3_XF.2" : { "node_name" : "C20_E3_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4_i52", "sym_num" : 1, "page_instance" : "I52", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4" } ], "net_name" : "CONN_CLK_REFP<1>_E3", "pin_name" : "B", "refdes" : "C20_E3_XF", "part_number" : "402-000010-035" }, "C4_SP_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C4_SP_XF.2", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : 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"net_name" : "UNNAMED_4_RESISTOR_I16_A_MP", "part_number" : "400-000015-024", "node_name" : "R6_MP.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "R24_FL_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R24_FL_XF.1", "part_number" : "400-000014-011", "pin_name" : "A", "refdes" : "R24_FL_XF", "net_name" : "UNNAMED_5_LT3071_I30_IMON_FL", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I43", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i43", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page5", "phys_page" : "page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "U1_XF.AW9" : { "net_name" : "PWR_AVTT_RLC_XF", "pin_name" : "MGTAVTT_RLC_8", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i86", "sym_num" : 29, "phys_page" : "page20", "page" : "page20", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20" } ], "pin_name_unsanitized" : "MGTAVTT_RLC_8", "pin_group" : "ALL_POWER_PINS_29;", "pin_type" : "INOUT", "pin_number" : "AW9", "node_name" : "U1_XF.AW9" }, "U1_CPLD.F16" : { "node_name" : "U1_CPLD.F16", "pin_type" : "INOUT", "pin_number" : "F16", "pin_name_unsanitized" : "PCIE1_RESET_3V_F", "pinuse" : "BI;", "pin_group" : "PCIE_RST_1;", "net_name" : "PCIE1_RESET_3V_F", "pin_name" : "PCIE1_RESET_3V_F", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "marker_data" : [ { "page" : "page3", "block" : "top/cpld_blk", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page3", "page_instance" : "I447", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page3_i447" } ] }, "U2_MP.8" : { "node_name" : "U2_MP.8", "pin_number" : "8", "pin_type" : "INOUT", "pinuse" : "TRI;", "pin_name_unsanitized" : "RT_CLK", "part_number" : "450-000329-001", "net_name" : "UNNAMED_4_RESISTOR_I16_B_MP", "pin_name" : "RT_CLK", "refdes" : "U2_MP", "marker_data" : [ { "page_instance" : "I1", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page4", "ppath" : "top/page18_i1/mgmt_pwr_block/page4_i1", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/mgmt_pwr_block", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4" } ] }, "R18_E0_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "page_instance" : "I38", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i38", "sym_num" : 1 } ], "part_number" : "400-000010-010", "net_name" : "GND", "pin_name" : "B", "refdes" : "R18_E0_XF", "node_name" : "R18_E0_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "PM7_SP_XF.M7" : { "node_name" : "PM7_SP_XF.M7", "pin_type" : "POWER", "pin_number" : "M7", "pin_name_unsanitized" : "VIN_28", "pinuse" : "POWER;", "pin_name" : "VIN_28", "net_name" : "P12V_4650_BR_SP", "refdes" : "PM7_SP_XF", "part_number" : "462-000308-002", "marker_data" : [ { "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I80", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80" } ] }, "R120_SP_XF.1" : { "node_name" : "R120_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "page_instance" : "I102", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i102", "sym_num" : 1 } ], "part_number" : "400-000010-108", "pin_name" : "A", "refdes" : "R120_SP_XF", "net_name" : "P3R3V" }, "C398_XF.2" : { "node_name" : "C398_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "PWR_SDIMM_VDD_XF", "refdes" : "C398_XF", "part_number" : "402-000010-028", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i157", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I157" } ] }, "M21.MTG2" : { "marker_data" : [ { "path" : "@top_lib.top(sch_1):page1", "phys_path" : "@top_lib.top(sch_1):page1", "remapped_page" : null, "page" : "page1", "block" : "top", "phys_page" : "page1", "sym_num" : 1, "ppath" : "top/page1_i74", "ppath_without_last_instance" : "top/page1", "page_instance" : "I74" } ], "net_name" : "GND", "refdes" : "M21", "pin_name" : "MTG2", "part_number" : "HOLE_RING", "pin_name_unsanitized" : "MTG2", "pinuse" : "NC;", "pin_number" : "MTG2", "node_name" : "M21.MTG2" }, "J1_XF.17" : { "pin_number" : "17", "pin_type" : "GROUND", "node_name" : "J1_XF.17", "pin_name" : "VSS_43", "refdes" : "J1_XF", "net_name" : "GND", "part_number" : "410-000300-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4" } ], "pin_name_unsanitized" : "VSS_43", "pinuse" : "UNSPEC;" }, "U1_CPLD.J1" : { "pin_type" : "INPUT", "pin_number" : "J1", "node_name" : "U1_CPLD.J1", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "remapped_page" : null, "block" : "top/cpld_blk", "page" : "page5", "phys_page" : "page5", "sym_num" : 2, "ppath" : "top/page14_i1/cpld_blk/page5_i61", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page5", "page_instance" : "I61" } ], "pin_name" : "FPGA_CPLD_SSTAT_CLK", "net_name" : "FPGA_CPLD_SSTAT_CLK", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "pin_name_unsanitized" : "FPGA_CPLD_SSTAT_CLK", "pinuse" : "IN;" }, "C101_XF.2" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i761", "sym_num" : 1, "page_instance" : "I761", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_page" : "page11", "block" : "top/xc2_fpga_blk", "page" : "page11" } ], "part_number" : "402-000010-035", "pin_name" : "B", "refdes" : "C101_XF", "net_name" : "AC_PCIE_X1_REFP_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C101_XF.2" }, "C133_SP_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C133_SP_XF.2", "marker_data" : [ { "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "page_instance" : "I520", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i520", "sym_num" : 1 } ], "refdes" : "C133_SP_XF", "pin_name" : "B", "net_name" : "UNNAMED_6_LTM4671_I457_FB1_SP", "part_number" : "402-000200-003", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "R113_FL_XF.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i74", "sym_num" : 1, "page_instance" : "I74", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page9" } ], "part_number" : "400-000010-116", "net_name" : "IMON_VCCAUX_LIN_XF", "pin_name" : "A", "refdes" : "R113_FL_XF", "node_name" : "R113_FL_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "J1_PX1_XF.B10" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "P3R3V_AUX", "part_number" : "410-000328-001", "pin_name" : "P3R3V_AUX", "refdes" : "J1_PX1_XF", "net_name" : "NC", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i73/pcie_x1_conn_blk/page3_i14", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i73/pcie_x1_conn_blk/page3", "page_instance" : "I14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i73@top_lib.pcie_x1_conn_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i73@top_lib.pcie_x1_conn_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/pcie_x1_conn_blk", "page" : "page3", "phys_page" : "page3" } ], "node_name" : "J1_PX1_XF.B10", "pin_number" : "B10" }, "U1_XF.W28" : { "pin_type" : "INOUT", "pin_number" : "W28", "node_name" : "U1_XF.W28", "part_number" : "450-000340-001", "net_name" : "PWR_VCCINT_XF", "pin_name" : "VCCINT_18", "refdes" : "U1_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I186", "sym_num" : 31, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null } ], "pin_name_unsanitized" : "VCCINT_18", "pin_group" : "ALL_POWER_PINS_31;" }, "C14.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C14.1", "marker_data" : [ { "page_instance" : "I20", "ppath_without_last_instance" : "top/page15", "ppath" : "top/page15_i20", "sym_num" : 1, "phys_page" : "page15", "page" : "page15", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page15" } ], "part_number" : "402-000010-001", "pin_name" : "A", "net_name" : "GND", "refdes" : "C14", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "PM5_SP_XF.E2" : { "pin_number" : "E2", "pin_type" : "POWER", "node_name" : "PM5_SP_XF.E2", "marker_data" : [ { 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i139", "sym_num" : 1, "phys_page" : "page14", "page" : "page14", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14" } ], "part_number" : "402-000010-035", "refdes" : "C232_XF", "pin_name" : "A", "net_name" : "AC_OCL1_PET_P<0>_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C232_XF.1" }, "R48_FL_XF.1" : { "part_number" : "400-000010-010", "net_name" : "GND", "pin_name" : "A", "refdes" : "R48_FL_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i16", "sym_num" : 1, "page_instance" : "I16", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", 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"GND", "pin_name" : "MTG4", "refdes" : "M12", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page1", "path" : "@top_lib.top(sch_1):page1", "remapped_page" : null, "block" : "top", "page" : "page1", "phys_page" : "page1", "sym_num" : 1, "ppath" : "top/page1_i70", "ppath_without_last_instance" : "top/page1", "page_instance" : "I70" } ], "node_name" : "M12.MTG4", "pin_number" : "MTG4" }, "J1_XF.98" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4" } ], "pin_name" : "VSS_70", "net_name" : "GND", "refdes" : "J1_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_70", "pinuse" : "UNSPEC;", "pin_number" : "98", "pin_type" : "GROUND", "node_name" : "J1_XF.98" }, "U1_XF.BG5" : { "pin_name" : "GND_850", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "sym_num" : 37, "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk" } ], "pin_name_unsanitized" : "GND_850", "pin_group" : "ALL_POWER_PINS_37;", "pin_number" : "BG5", "pin_type" : "INOUT", "node_name" : "U1_XF.BG5" }, "J1_E2_XF.B5" : { "pin_number" : "B5", "node_name" : "J1_E2_XF.B5", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i101", "ppath_without_last_instance" : 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"phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8" } ], "pin_name_unsanitized" : "VDD_10", "pinuse" : "POWER;" }, "U1_XF.R8" : { "pin_name" : "GND_209", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I69", "sym_num" : 34, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "pin_name_unsanitized" : "GND_209", "pin_group" : "ALL_POWER_PINS_34;", "pin_type" : "INOUT", "pin_number" : "R8", "node_name" : "U1_XF.R8" }, "PM4_SP_XF.C11" : { "node_name" : "PM4_SP_XF.C11", "pin_number" : "C11", "pin_type" : "POWER", "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT2_13", "part_number" : "462-000308-002", "net_name" : "PWR_VCCINT_XF", "pin_name" : "VOUT2_13", "refdes" : "PM4_SP_XF", "marker_data" : [ { "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i80", "sym_num" : 1, "phys_page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4" } ] }, "R125_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R125_XF.1", "marker_data" : [ { "page" : "page29", "block" : "top/xc2_fpga_blk", "phys_page" : "page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "page_instance" : "I67", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i67" } ], "pin_name" : "A", "refdes" : "R125_XF", "net_name" : "PWR_FPGA_3R3V", "part_number" : "400-000010-020", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "U1_XF.A47" : { "pin_type" : "INOUT", "pin_number" : "A47", "node_name" : "U1_XF.A47", "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L10N_T1U_N7_QBC_AD4N_37", "refdes" : "U1_XF", "marker_data" : [ { "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "page_instance" : "I58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "sym_num" : 26 } ], "pin_name_unsanitized" : "IO_L10N_T1U_N7_QBC_AD4N_37", "pin_group" : "ALL_SIGNAL_PINS_26;" }, "R111_SP_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R111_SP_XF.2", "marker_data" : [ { "phys_page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "page_instance" : "I63", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i63", "sym_num" : 1 } ], "pin_name" : "B", "refdes" : "R111_SP_XF", "net_name" : "UNNAMED_7_BYPASSCAPNPOL_I64_B_SP", "part_number" : "400-000014-011", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "U1_XF.BC49" : { "node_name" : "U1_XF.BC49", "pin_type" : "INOUT", "pin_number" : "BC49", "pin_name_unsanitized" : "IO_T0U_N12_VRP_26", "pin_group" : "ALL_SIGNAL_PINS_19;", "pin_name" : "IO_T0U_N12_VRP_26", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I47", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i47", "sym_num" : 19, "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30" } ] }, "R253_XF.1" : { "part_number" : "400-000010-003", "pin_name" : "A", "net_name" : "C2_DDR4_VREFCA_1_XF", "refdes" : "R253_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page8", "phys_page" : "page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I147", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i147" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R253_XF.1" }, "J1_XF.267" : { "pin_type" : "INOUT", "pin_number" : "267", "node_name" : "J1_XF.267", "part_number" : "410-000300-001", "refdes" : "J1_XF", "pin_name" : "DQS6_T", "net_name" : "C0_RDIMM_DQS_T<6>_XF", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : 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"marker_data" : [ { "sym_num" : 1, "ppath" : "top/page20_i39", "ppath_without_last_instance" : "top/page20", "page_instance" : "I39", "path" : "@top_lib.top(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page20", "remapped_page" : null, "page" : "page20", "block" : "top", "phys_page" : "page20" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "U1_XF.BW19" : { "node_name" : "U1_XF.BW19", "pin_number" : "BW19", "pin_type" : "INOUT", "pin_name_unsanitized" : "C0_DDR4_ADR6", "pin_group" : "C0_ACTL_4_4;", "net_name" : "C0_DDR4_ADR<6>_XF", "pin_name" : "C0_DDR4_ADR6", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk", "page" : "page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "sym_num" : 4, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3" } ] }, "J4_XF.45" : { "node_name" : "J4_XF.45", "pin_number" : "45", "pin_type" : "INOUT", "pin_name_unsanitized" : "DQ26", "pinuse" : "TRI;", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10" } ], "refdes" : "J4_XF", "pin_name" : "DQ26", "net_name" : "C3_DDR4_DQ<26>_XF", "part_number" : "410-000300-001" }, "PM5_SP_XF.J9" : { "marker_data" : [ { "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i80", "sym_num" : 1, "phys_page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5" } ], "pin_name" : "VIN_4", "net_name" : "P12V_4650_TR_SP", "refdes" : "PM5_SP_XF", "part_number" : "462-000308-002", "pin_name_unsanitized" : "VIN_4", "pinuse" : "POWER;", "pin_number" : "J9", "pin_type" : "POWER", "node_name" : "PM5_SP_XF.J9" }, "R15_FL_XF.1" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i43", "sym_num" : 1, "page_instance" : "I43", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1" } ], "part_number" : "400-000014-011", "net_name" : "UNNAMED_4_LT3071_I30_IMON_FL", "pin_name" : "A", "refdes" : "R15_FL_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R15_FL_XF.1" }, "U1_XF.BE37" : { "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "GND_817", "net_name" : "GND", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "sym_num" : 37, "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk" } ], "pin_name_unsanitized" : "GND_817", "pin_group" : "ALL_POWER_PINS_37;", "pin_number" : "BE37", "pin_type" : "INOUT", "node_name" : "U1_XF.BE37" }, "C305_XF.2" : { "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i55", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I55" } ], "refdes" : "C305_XF", "pin_name" : "B", "net_name" : "PWR_VCCINT_XF", "part_number" : "402-000015-008", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C305_XF.2" }, "R9_ND_XF.2" : { "node_name" : "R9_ND_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i69", "sym_num" : 1, "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk" } ], "pin_name" : "B", "net_name" : "UNNAMED_3_LTM4675_I40_FSWPHCFG_ND", "refdes" : "R9_ND_XF", "part_number" : "400-000010-039" }, "C202_XF.2" : { "marker_data" : [ { "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I155", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i155" } ], "refdes" : "C202_XF", "pin_name" : "B", "net_name" : "PWR_NDIMM_VDD_XF", "part_number" : "402-000010-039", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C202_XF.2" }, "U1_XF.BH21" : { "pin_name" : "C0_DDR4_DQ48", "net_name" : "C0_DDR4_DQ<48>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "remapped_page" : null, "page" : "PAGE3", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE3", "sym_num" : 72, "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "page_instance" : "I2425" } ], "pin_name_unsanitized" : "C0_DDR4_DQ48", "pin_group" : "C0_LNIB_1_4_66;", "pin_number" : "BH21", "pin_type" : "INOUT", "node_name" : "U1_XF.BH21" }, "C165_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i168", "sym_num" : 1, "page_instance" : "I168", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk" } ], "refdes" : "C165_XF", "pin_name" : "A", "net_name" : "GND", "part_number" : "402-000015-008", "node_name" : "C165_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "PM4_ND_XF.H9" : { "node_name" : "PM4_ND_XF.H9", "pin_type" : "POWER", "pin_number" : "H9", "pin_name_unsanitized" : "GND_31", "pinuse" : "POWER;", "marker_data" : [ { "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page3" } ], "pin_name" : "GND_31", "refdes" : "PM4_ND_XF", "net_name" : "GND", "part_number" : "462-000304-001" }, "C25.1" : { "part_number" : "402-000500-005", "net_name" : "P12V_MAIN", "pin_name" : "A", "refdes" : "C25", "marker_data" : [ { "ppath" : "top/page19_i80", "sym_num" : 1, "page_instance" : "I80", "ppath_without_last_instance" : "top/page19", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page19", "path" : "@top_lib.top(sch_1):page19", "phys_page" : "page19", "block" : "top", "page" : "page19" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C25.1" }, "J4_XF.226" : { "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10" } ], "part_number" : "410-000300-001", "refdes" : "J4_XF", "pin_name" : "VDD_7", "net_name" : "PWR_NDIMM_VDD_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_7", "pin_number" : "226", "pin_type" : "POWER", "node_name" : "J4_XF.226" }, "PM4_ND_XF.K6" : { "pin_number" : "K6", "pin_type" : "POWER", "node_name" : "PM4_ND_XF.K6", "pin_name" : "GND_36", "net_name" : "GND", "refdes" : "PM4_ND_XF", "part_number" : "462-000304-001", "marker_data" : [ { "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i20", "sym_num" : 2, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3" } ], "pin_name_unsanitized" : "GND_36", "pinuse" : "POWER;" }, "PM2_SP_XF.K5" : { "part_number" : "462-000309-001", "refdes" : "PM2_SP_XF", "net_name" : "GND", "pin_name" : "GND_44", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "sym_num" : 5, "page_instance" : "I459", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6" } ], "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_44", "pin_number" : "K5", "node_name" : "PM2_SP_XF.K5" }, "R113_XF.1" : { "node_name" : "R113_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R113_XF", "pin_name" : "A", "net_name" : "GND", "part_number" : "400-000010-097", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_page" : "page17", "block" : "top/xc2_fpga_blk", "page" : "page17", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i91", "sym_num" : 1, "page_instance" : "I91", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17" } ] }, "R10_E2_XF.2" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i34", "sym_num" : 1, "page_instance" : "I34", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : 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"PETN2", "refdes" : "J1_E1_XF", "part_number" : "410-000317-001", "marker_data" : [ { "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i101", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3" } ] }, "U1_XF.AC57" : { "pin_name_unsanitized" : "IO_L1N_T0L_N1_DBC_32", "pin_group" : "ALL_SIGNAL_PINS_22;", "part_number" : "450-000340-001", "pin_name" : "IO_L1N_T0L_N1_DBC_32", "refdes" : "U1_XF", "net_name" : "NC", "marker_data" : [ { "page_instance" : "I46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "sym_num" : 22, "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30" } ], "node_name" : "U1_XF.AC57", "pin_type" : "INOUT", "pin_number" : "AC57" }, "PM7_SP_XF.H4" : { "node_name" : "PM7_SP_XF.H4", "pin_number" : "H4", "pin_type" : "POWER", "pin_name_unsanitized" : "GND_33", "pinuse" : "POWER;", "marker_data" : [ { "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "page_instance" : "I151", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i151", "sym_num" : 2 } ], "refdes" : "PM7_SP_XF", "pin_name" : "GND_33", "net_name" : "GND", "part_number" : "462-000308-002" }, "U1_XF.AG6" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_page" : "page13", "block" : "top/xc2_fpga_blk", "page" : "page13", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i251", "sym_num" : 10, "page_instance" : "I251", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13" } ], "pin_name" : "E1S3_PER_P3", "refdes" : "U1_XF", "net_name" : "E1S3_PER_P<3>_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_10;", "pin_name_unsanitized" : "E1S3_PER_P3", "pin_number" : "AG6", "pin_type" : "INOUT", "node_name" : "U1_XF.AG6" }, "J1_P1_XF.B5" : { "refdes" : "J1_P1_XF", "pin_name" : "GND_9", "net_name" : "GND", "part_number" : "410-000324-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1, "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk" } ], "pin_name_unsanitized" : "GND_9", "pinuse" : "GROUND;", "pin_number" : "B5", "node_name" : "J1_P1_XF.B5" }, "C436_XF.1" : { "node_name" : "C436_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-028", "refdes" : "C436_XF", "pin_name" : "A", "net_name" : "GND", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I177", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i177" } ] }, "TP11_CPLD.1" : { "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page7_i153", "sym_num" : 1, "page_instance" : "I153", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top/cpld_blk" } ], "part_number" : "SM_050_TP", "refdes" : "TP11_CPLD", "pin_name" : "1", "net_name" : "UNNAMED_7_SM050TP_I153_1_CPLD", "pinuse" : "POWER;", "pin_name_unsanitized" : "\\1\\", "pin_number" : "1", "pin_type" : "POWER", "node_name" : "TP11_CPLD.1" }, "J2_XF.252" : { "pin_number" : "252", "pin_type" : "GROUND", "node_name" : "J2_XF.252", "part_number" : "410-000300-001", "pin_name" : "VSS_94", "refdes" : "J2_XF", "net_name" : "GND", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/xc2_fpga_blk", "phys_page" : "page6", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_94" }, "U1_XF.B7" : { "pin_type" : "INOUT", "pin_number" : "B7", "node_name" : "U1_XF.B7", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I68", "sym_num" : 33, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "GND_22", "net_name" : "GND", "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_22" }, "R96_SP_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R96_SP_XF.1", "marker_data" : [ { "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "page_instance" : "I135", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i135", "sym_num" : 1 } ], "part_number" : "400-000014-011", "pin_name" : "A", "net_name" : "UNNAMED_11_LTM4650FIXED_I150_PGOOD2_SP", "refdes" : "R96_SP_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "R108_SD_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000014-011", "pin_name" : "B", "net_name" : "UNNAMED_3_LTM4675_I40_COMP0A_SD", "refdes" : "R108_SD_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i23", "sym_num" : 1, "page_instance" : "I23", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk" } ], "node_name" : "R108_SD_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "R93_FL_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R93_FL_XF.1", "pin_name" : "A", "net_name" : "DAC_AVCC_LIN_XF", "refdes" : "R93_FL_XF", "part_number" : "400-000010-006", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i22", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11", "page_instance" : "I22", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page11", "remapped_page" : null, "page" : "page12", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page11" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "U1_XF.AB7" : { "marker_data" : [ { "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I69", "sym_num" : 34, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69" } ], "refdes" : "U1_XF", "pin_name" : "GND_339", "net_name" : "GND", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_339", "pin_type" : "INOUT", "pin_number" : "AB7", "node_name" : "U1_XF.AB7" }, "U1_XF.AR11" : { "pin_number" : "AR11", "pin_type" : "INOUT", "node_name" : "U1_XF.AR11", "net_name" : "AC_PCIE1_TXP<5>_XF", "pin_name" : "PCIE1_TXP5", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "page" : "page11", "block" : "top/xc2_fpga_blk", "phys_page" : "page11", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I775" } ], "pin_name_unsanitized" : "PCIE1_TXP5", "pin_group" : "ALL_SIGNAL_PINS_3;" }, "PM2_SP_XF.C2" : { "pin_name_unsanitized" : "VOUT0_8", "pinuse" : "POWER;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i516", "sym_num" : 1, "page_instance" : "I516", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "net_name" : "PWR_AVTT_SW_XF", "refdes" : "PM2_SP_XF", "pin_name" : "VOUT0_8", "part_number" : "462-000309-001", "node_name" : "PM2_SP_XF.C2", "pin_number" : "C2" }, "J4_XF.209" : { "node_name" : "J4_XF.209", "pin_type" : "POWER", "pin_number" : "209", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_22", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10" } ], "part_number" : "410-000300-001", "net_name" : "PWR_NDIMM_VDD_XF", "pin_name" : "VDD_22", "refdes" : "J4_XF" }, "U1_XF.BL48" : { "pin_type" : "INOUT", "pin_number" : "BL48", "node_name" : "U1_XF.BL48", "pin_name" : "IO_L16N_T2U_N7_QBC_AD3N_19", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "sym_num" : 17, "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30" } ], "pin_name_unsanitized" : "IO_L16N_T2U_N7_QBC_AD3N_19", "pin_group" : "ALL_SIGNAL_PINS_17;" }, "U1_XF.BB35" : { "node_name" : "U1_XF.BB35", "pin_number" : "BB35", "pin_type" : "INOUT", "pin_name_unsanitized" : "VCCINT_203", "pin_group" : "ALL_POWER_PINS_32;", "part_number" : "450-000340-001", "pin_name" : "VCCINT_203", "net_name" : "PWR_VCCINT_XF", "refdes" : "U1_XF", "marker_data" : [ { "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "page_instance" : "I187", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i187", "sym_num" : 32 } ] }, "C333_XF.2" : { "node_name" : "C333_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000015-007", "pin_name" : "B", "net_name" : "GND", "refdes" : "C333_XF", "marker_data" : [ { "page" : "page21", "block" : "top/xc2_fpga_blk", "phys_page" : "page21", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "page_instance" : "I4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i4" } ] }, "U1_XF.AT48" : { "pin_type" : "INOUT", "pin_number" : "AT48", "node_name" : "U1_XF.AT48", "marker_data" : [ { "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "page_instance" : "I51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51", "sym_num" : 18 } ], "pin_name" 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"pin_number" : "C11" }, "PM4_SD_XF.L2" : { "node_name" : "PM4_SD_XF.L2", "pin_type" : "POWER", "pin_number" : "L2", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_39", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i20", "sym_num" : 2, "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3" } ], "part_number" : "462-000304-001", "pin_name" : "GND_39", "refdes" : "PM4_SD_XF", "net_name" : "GND" }, "C198_SP_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_page" : "page11", "block" : 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"@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30" } ], "node_name" : "U1_XF.AK63", "pin_type" : "INOUT", "pin_number" : "AK63" }, "J4_XF.111" : { "pinuse" : "TRI;", "pin_name_unsanitized" : "DQS14_C_TDQS14_C", "part_number" : "410-000300-001", "net_name" : "C3_RDIMM_DQS_C<14>_XF", "pin_name" : "DQS14_C_TDQS14_C", "refdes" : "J4_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10" } ], "node_name" : "J4_XF.111", "pin_type" : "INOUT", "pin_number" : "111" }, "U3_XF.C1" : { "node_name" : "U3_XF.C1", "pin_number" : "C1", "pin_type" : "NC", "pin_name_unsanitized" : "DNU_6", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i39", "sym_num" : 2, "page_instance" : "I39", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "phys_page" : "page15", "block" : "top/xc2_fpga_blk", "page" : "page15" } ], "pin_name" : "DNU_6", "refdes" : "U3_XF", "net_name" : "NC", "part_number" : "450-000341-001" }, "U1_XF.V42" : { "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_265", "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I69", "ppath_without_last_instance" : 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"GND_71", "refdes" : "PM1_SP_XF", "marker_data" : [ { "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7" } ], "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_71" }, "U1_XF.B33" : { "node_name" : "U1_XF.B33", "pin_number" : "B33", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_25;", "pin_name_unsanitized" : "IO_L15P_T2L_N4_AD11P_71", "marker_data" : [ { "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "page_instance" : "I59", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i59", "sym_num" : 25 } ], "pin_name" : "IO_L15P_T2L_N4_AD11P_71", "net_name" : "NC", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "R55_SP_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R55_SP_XF.1", "marker_data" : [ { "page_instance" : "I469", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i469", "sym_num" : 1, "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6" } ], "refdes" : "R55_SP_XF", "pin_name" : "A", "net_name" : "UNNAMED_6_RESISTOR_I469_A_SP", "part_number" : "400-000015-027", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "J3_XF.283" : { "pin_type" : "GROUND", "pin_number" : "283", "node_name" : "J3_XF.283", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8" } ], "net_name" : "GND", "pin_name" : "VSS_84", "refdes" : "J3_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_84", "pinuse" : "UNSPEC;" }, "U1_E3_XF.25" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VDDO_2", "part_number" : "450-000345-001", "refdes" : "U1_E3_XF", "net_name" : "PWR_FPGA_3R3V", "pin_name" : "VDDO_2", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4_i37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4", "page_instance" : "I37", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4" } ], "node_name" : "U1_E3_XF.25", "pin_number" : "25" }, "PM4_SP_XF.K1" : { "node_name" : "PM4_SP_XF.K1", "pin_type" : "POWER", "pin_number" : "K1", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_45", "part_number" : "462-000308-002", "refdes" : "PM4_SP_XF", "pin_name" : "GND_45", "net_name" : "GND", "marker_data" : [ { "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "page_instance" : "I79", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4", "phys_page" : "page4" } ] }, "R13_MP.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "remapped_page" : null, "block" : "top/mgmt_pwr_block", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page18_i1/mgmt_pwr_block/page4_i8", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page4", "page_instance" : "I8" } ], "part_number" : "400-000010-075", "pin_name" : "A", "refdes" : "R13_MP", "net_name" : "UNNAMED_4_RESISTOR_I8_A_MP", "node_name" : "R13_MP.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.AK40" : { "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_521", "refdes" : "U1_XF", "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "sym_num" : 35 } ], "pin_name_unsanitized" : "GND_521", "pin_group" : "ALL_POWER_PINS_35;", "pin_number" : "AK40", "pin_type" : "INOUT", "node_name" : "U1_XF.AK40" }, "R30.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R30.1", "refdes" : "R30", "pin_name" : "A", "net_name" : "UNNAMED_4_MAX116XXQSOP16_I97_AIN1", "part_number" : "400-000010-010", "marker_data" : [ { "ppath" : "top/page4_i151", "sym_num" : 1, "page_instance" : "I151", "ppath_without_last_instance" : "top/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page4", "path" : "@top_lib.top(sch_1):page4", "phys_page" : "page4", "block" : "top", "page" : "page4" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "U1_XF.K17" : { "node_name" : "U1_XF.K17", "pin_number" : "K17", "pin_type" : "INOUT", "pin_group" : "C3_UNIB_1_7_48;", "pin_name_unsanitized" : "C3_DDR4_DQ7", "marker_data" : [ { "sym_num" : 48, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2425", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "remapped_page" : null, "page" : "PAGE9", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE9" } ], "pin_name" : "C3_DDR4_DQ7", "net_name" : "C3_DDR4_DQ<7>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "R156_XF.1" : { "node_name" : "R156_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I773", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i773", "block" : "top/xc2_fpga_blk", "page" : "page11", "phys_page" : "page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null } ], "part_number" : "400-000010-010", "net_name" : "PCIE1_RST_F", "pin_name" : "A", "refdes" : "R156_XF" }, "U1_XF.AN2" : { "node_name" : "U1_XF.AN2", "pin_number" : "AN2", "pin_type" : "INOUT", "pin_name_unsanitized" : "PCIE1_RXP0", "pin_group" : "ALL_SIGNAL_PINS_3;", "net_name" : "PCIE1_RXP<0>_XF", "pin_name" : "PCIE1_RXP0", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I775", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775", "block" : "top/xc2_fpga_blk", "page" : "page11", "phys_page" : "page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null } ] }, "J1_XF.154" : { "pin_type" : "GROUND", "pin_number" : "154", "node_name" : "J1_XF.154", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1 } ], "net_name" : "GND", "pin_name" : "VSS_26", "refdes" : "J1_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_26", "pinuse" : "UNSPEC;" }, "R39_SP_XF.2" : { "node_name" : "R39_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R39_SP_XF", "pin_name" : "B", "net_name" : "UNNAMED_3_LTC2975_I168_WDIRESETF_SP", "part_number" : "400-000010-074", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I65", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i65" } ] }, "R123_XF.2" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27", "page_instance" : "I51", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page27", "phys_page" : "page27" } ], "net_name" : "SDIMM_I2C_ASEL_RESISTOR_XF", "pin_name" : "B", "refdes" : "R123_XF", "part_number" : "400-000010-137", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R123_XF.2" }, "U1_XF.BB39" : { "node_name" : "U1_XF.BB39", "pin_type" : "INOUT", "pin_number" : "BB39", "pin_group" : "ALL_POWER_PINS_32;", "pin_name_unsanitized" : "VCCINT_205", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i187", "sym_num" : 32, "page_instance" : "I187", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "VCCINT_205", "net_name" : "PWR_VCCINT_XF" }, "R255_XF.2" : { "marker_data" : [ { "page" : "page9", "block" : "top/xc2_fpga_blk", "phys_page" : "page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2156", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2156" } ], "pin_name" : "B", "net_name" : "C3_DDR4_ALERT_N_XF", "refdes" : "R255_XF", "part_number" : "400-000010-007", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R255_XF.2" }, "U1_XF.CA26" : { "node_name" : "U1_XF.CA26", "pin_type" : "INOUT", "pin_number" : "CA26", "pin_name_unsanitized" : "C0_DDR4_DQ14", "pin_group" : "C0_UNIB_1_4_66;", "part_number" : "450-000340-001", "pin_name" : "C0_DDR4_DQ14", "net_name" : "C0_DDR4_DQ<14>_XF", "refdes" : "U1_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_page" : "PAGE3", "page" : "PAGE3", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "sym_num" : 67, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3" } ] }, "J3_XF.276" : { "node_name" : "J3_XF.276", "pin_number" : "276", "pin_type" : "GROUND", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_66", "part_number" : "410-000300-001", "net_name" : "GND", "pin_name" : "VSS_66", "refdes" : "J3_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8" } ] }, "PM2_SP_XF.W9" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_93", "part_number" : "462-000309-001", "refdes" : "PM2_SP_XF", "net_name" : "GND", "pin_name" : "GND_93", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I459", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459" } ], "node_name" : "PM2_SP_XF.W9", "pin_number" : "W9" }, "U1_CPLD.E1" : { "pin_number" : "E1", "pin_type" : "INOUT", "node_name" : "U1_CPLD.E1", "part_number" : "450-000313-001", "pin_name" : "TDO_JTAG_CTL0", "net_name" : "TDO_JTAG_CTL", "refdes" : "U1_CPLD", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page5_i61", "sym_num" : 2, "page_instance" : "I61", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page5", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "phys_page" : "page5", "page" : "page5", "block" : "top/cpld_blk" } ], "pinuse" : "BI;", "pin_name_unsanitized" : "TDO_JTAG_CTL0", "pin_group" : "JT_GP_2;" }, "R145_XF.1" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i123", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I123", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page17", "phys_page" : "page17" } ], "part_number" : "400-000010-097", "net_name" : "UNNAMED_17_RESISTOR_I122_A_XF", "pin_name" : "A", "refdes" : "R145_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R145_XF.1" }, "U1_XF.BR27" : { "node_name" : "U1_XF.BR27", "pin_type" : "INOUT", "pin_number" : "BR27", "pin_name_unsanitized" : "C0_DDR4_DQ67", "pin_group" : "C0_LNIB_1_4_66;", "part_number" : "450-000340-001", "net_name" : "C0_DDR4_DQ<67>_XF", "pin_name" : "C0_DDR4_DQ67", "refdes" : "U1_XF", "marker_data" : [ { "sym_num" : 74, "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "page_instance" : "I2425", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "PAGE3", "phys_page" : "PAGE3" } ] }, "U1_CPLD.R11" : { "node_name" : "U1_CPLD.R11", "pin_type" : "INOUT", "pin_number" : "R11", "pin_group" : "PCTL_POK_3;", "pin_name_unsanitized" : "POK_OD_VCCINT_TLSW_P1", "pinuse" : "BI;", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/cpld_blk", "ppath" : "top/page14_i1/cpld_blk/page4_i211", "sym_num" : 3, "page_instance" : "I211", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4" } ], "net_name" : "POK_OD_VCCINT_TLSW_P<1>", "pin_name" : "POK_OD_VCCINT_TLSW_P1", "refdes" : "U1_CPLD", "part_number" : "450-000313-001" }, "R8.2" : { "node_name" : "R8.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "ppath" : 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"phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk" } ] }, "J4_XF.67" : { "marker_data" : [ { "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1 } ], "part_number" : "410-000300-001", "pin_name" : "VDD_23", "net_name" : "PWR_NDIMM_VDD_XF", "refdes" : "J4_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_23", "pin_number" : "67", "pin_type" : "POWER", "node_name" : "J4_XF.67" }, "PM7_SP_XF.C2" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT1_12", "part_number" : "462-000308-002", "net_name" : "PWR_VCCINT_XF", "pin_name" : "VOUT1_12", "refdes" : "PM7_SP_XF", "marker_data" : [ { "page" : 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"top/page14_i1/cpld_blk/page4_i211", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "page_instance" : "I211" } ], "pinuse" : "BI;", "pin_name_unsanitized" : "POK_OD_VCCAUX_B_LIN", "pin_group" : "PCTL_POK_3;", "pin_type" : "INOUT", "pin_number" : "N9", "node_name" : "U1_CPLD.N9" }, "J4_XF.279" : { "net_name" : "GND", "pin_name" : "VSS_74", "refdes" : "J4_XF", "part_number" : "410-000300-001", "marker_data" : [ { "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1 } ], "pin_name_unsanitized" : "VSS_74", "pinuse" : "UNSPEC;", "pin_type" : "GROUND", "pin_number" : "279", "node_name" : "J4_XF.279" }, "C406_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i167", "sym_num" : 1, "page_instance" : "I167", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4" } ], "pin_name" : "B", "refdes" : "C406_XF", "net_name" : "PWR_SDIMM_VDD_XF", "part_number" : "402-000010-001", "node_name" : "C406_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_XF.BH42" : { "pin_name_unsanitized" : "IO_L22P_T3U_N6_DBC_AD0P_19", "pin_group" : "ALL_SIGNAL_PINS_17;", "part_number" : "450-000340-001", "pin_name" : "IO_L22P_T3U_N6_DBC_AD0P_19", "net_name" : "NC", "refdes" : "U1_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I50", "sym_num" : 17, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50" } ], "node_name" : "U1_XF.BH42", "pin_number" : "BH42", "pin_type" : "INOUT" }, "J1_O3_XF.MH4" : { "pin_name_unsanitized" : "MH4", "pinuse" : "GROUND;", "net_name" : "GND", "refdes" : "J1_O3_XF", "pin_name" : "MH4", "part_number" : "410-000324-001", "marker_data" : [ { "page_instance" : "I84", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i52/ocl_x4_conn_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i52/ocl_x4_conn_blk/page3_i84", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i52@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i52@top_lib.ocl_x4_conn_blk(sch_1):page3" } ], "node_name" : "J1_O3_XF.MH4", "pin_number" : "MH4" }, "J2_XF.227" : { "pinuse" : "BI;", "pin_name_unsanitized" : "NC_3", "part_number" : "410-000300-001", "pin_name" : "NC_3", "net_name" : "NC", "refdes" : "J2_XF", "marker_data" : [ { "phys_page" : "page6", "block" : "top/xc2_fpga_blk", "page" : "page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1 } ], "node_name" : "J2_XF.227", "pin_number" : "227", "pin_type" : "UNSPECIFIED" }, "Q2.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "Q2.2", "part_number" : "405-000010-001", "pin_name" : "S", "refdes" : "Q2", "net_name" : "FPGA_1R8V_SDA", "marker_data" : [ { "phys_page" : "page13", "block" : "top", "page" : "page13", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page13", "path" : "@top_lib.top(sch_1):page13", "page_instance" : "I99", "ppath_without_last_instance" : "top/page13", "ppath" : "top/page13_i99", "sym_num" : 1 } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "S" }, "PM4_SP_XF.G4" : { "pinuse" : "IN;", "pin_name_unsanitized" : "PHASMD", "part_number" : "462-000308-002", "refdes" : "PM4_SP_XF", "pin_name" : "PHASMD", "net_name" : "PHASMD_4650_TL_SP", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i78", "sym_num" : 3, "page_instance" : "I78", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4" } ], "node_name" : "PM4_SP_XF.G4", "pin_number" : "G4", "pin_type" : "INPUT" }, "C462_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C462_XF.2", "part_number" : "402-000010-001", "pin_name" : "B", "net_name" : "GND", "refdes" : "C462_XF", "marker_data" : [ { "phys_page" : "page20", "page" : "page20", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i69", "sym_num" : 1 } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "M13.MTG3" : { "part_number" : "HOLE_RING", "pin_name" : "MTG3", "net_name" : "GND", "refdes" : "M13", "marker_data" : [ { "ppath" : "top/page1_i71", "sym_num" : 1, "page_instance" : "I71", "ppath_without_last_instance" : "top/page1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page1", "phys_path" : "@top_lib.top(sch_1):page1", "phys_page" : "page1", "page" : "page1", "block" : "top" } ], "pinuse" : "NC;", "pin_name_unsanitized" : "MTG3", "pin_number" : "MTG3", "node_name" : "M13.MTG3" }, "C163_XF.2" : { "node_name" : "C163_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000015-008", "refdes" : "C163_XF", "pin_name" : "B", "net_name" : "FPGA_VCCAUX_P1R8V", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I167", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i167", "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null } ] }, "U1_XF.BN11" : { "node_name" : "U1_XF.BN11", "pin_number" : "BN11", "pin_type" : "INOUT", "pin_name_unsanitized" : "OCL2_PET_P0", "pin_group" : "ALL_SIGNAL_PINS_12;", "pin_name" : "OCL2_PET_P0", "net_name" : "AC_OCL2_PET_P<0>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I275", "sym_num" : 12, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i275", "block" : "top/xc2_fpga_blk", "page" : "page14", "phys_page" : "page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null } ] }, "U1_XF.BC20" : { "pin_type" : "INOUT", "pin_number" : "BC20", "node_name" : "U1_XF.BC20", "pin_name" : "VCCINT_208", "refdes" : "U1_XF", "net_name" : "PWR_VCCINT_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I187", "sym_num" : 32, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i187" } ], "pin_name_unsanitized" : "VCCINT_208", "pin_group" : "ALL_POWER_PINS_32;" }, "U12.7" : { "pinuse" : "IN;", "pin_name_unsanitized" : "EVENT", "part_number" : "450-000094-001", "net_name" : "TSE2002_EVENT_OD_F", "pin_name" : "EVENT", "refdes" : "U12", "marker_data" : [ { "page_instance" : "I3", "ppath_without_last_instance" : "top/page17", "ppath" : "top/page17_i3", "sym_num" : 1, "phys_page" : "page17", "block" : "top", "page" : "page17", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page17", "path" : "@top_lib.top(sch_1):page17" } ], "node_name" : "U12.7", "pin_number" : "7", "pin_type" : "INPUT" }, "J3_XF.206" : { "part_number" : "410-000300-001", "pin_name" : "VDD_20", "net_name" : "PWR_NDIMM_VDD_XF", "refdes" : "J3_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_20", "pin_type" : "POWER", "pin_number" : "206", "node_name" : "J3_XF.206" }, "U1_CPLD.N5" : { "marker_data" : [ { "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7" } ], "part_number" : "450-000313-001", "net_name" : "CPLD_P3R3V", "pin_name" : "VCCIO2_3", "refdes" : "U1_CPLD", "pinuse" : "POWER;", "pin_name_unsanitized" : "VCCIO2_3", "pin_number" : "N5", "node_name" : "U1_CPLD.N5" }, "PM2_SP_XF.H3" : { "pin_name_unsanitized" : "VOUT1_5", "pinuse" : "POWER;", "refdes" : "PM2_SP_XF", "net_name" : "PWR_AVCC_SW_XF", "pin_name" : "VOUT1_5", "part_number" : "462-000309-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i457", "sym_num" : 2, "page_instance" : "I457", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6" } ], "node_name" : "PM2_SP_XF.H3", "pin_number" : "H3" }, "J4_XF.1" : { "pin_type" : "UNSPECIFIED", "pin_number" : "1", "node_name" : "J4_XF.1", "part_number" : "410-000300-001", "net_name" : "NC", "pin_name" : "NC_1", "refdes" : "J4_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "path" : 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}, "C98_FL_XF.1" : { "node_name" : "C98_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I71", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i71" } ], "pin_name" : "A", "net_name" : "PWR_VCCAUX_SW_XF", "refdes" : "C98_FL_XF", "part_number" : "402-000010-001" }, "R19_FL_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "net_name" : "POK_OD_AVTT_RN_LIN", "pin_name" : "B", "refdes" : "R19_FL_XF", "part_number" : "400-000014-011", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7_i29", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7", "page_instance" : "I29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page7", "phys_page" : "page7" } ], "node_name" : "R19_FL_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C20_SP_XF.1" : { "node_name" : "C20_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "net_name" : "UNNAMED_4_CAPACITOR_I11_A_SP", "refdes" : "C20_SP_XF", "part_number" : "402-000202-001", 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"462-000304-001", "pin_name" : "GND_24", "net_name" : "GND", "refdes" : "PM4_SD_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I20", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i20" } ], "node_name" : "PM4_SD_XF.F1", "pin_number" : "F1", "pin_type" : "POWER" }, "U1_XF.BK53" : { "pin_type" : "INOUT", "pin_number" : "BK53", "node_name" : "U1_XF.BK53", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "sym_num" : 46, "page_instance" : "I2425", "ppath_without_last_instance" : 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"phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null } ], "net_name" : "E1S1_FPGA_REFCLK_N<1>_XF", "pin_name" : "B", "refdes" : "C22_E1_XF", "part_number" : "402-000010-035", "node_name" : "C22_E1_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "C253_XF.1" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i45", "sym_num" : 1, "page_instance" : "I45", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23" } ], "pin_name" : "A", "refdes" : "C253_XF", "net_name" : "PWR_VCCINT_XF", "part_number" : "402-000015-008", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C253_XF.1" }, "U2_SD_XF.8" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "GND", "marker_data" : [ { "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4", "page_instance" : "I19", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4_i19" } ], "part_number" : "450-000059-001", "net_name" : "GND", "pin_name" : "GND", "refdes" : "U2_SD_XF", "node_name" : "U2_SD_XF.8", "pin_number" : "8", "pin_type" : "POWER" }, "U1_CPLD.B2" : { "node_name" : "U1_CPLD.B2", "pin_number" : "B2", "pin_name_unsanitized" : "GND_1", "pinuse" : "GROUND;", "marker_data" : [ { "phys_page" : "page7", "page" : "page7", "block" : "top/cpld_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "page_instance" : "I151", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "ppath" : "top/page14_i1/cpld_blk/page7_i151", "sym_num" : 7 } ], "net_name" : "GND", "pin_name" : "GND_1", "refdes" : "U1_CPLD", "part_number" : "450-000313-001" }, "C125_XF.1" : { "node_name" : "C125_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-035", "pin_name" : "A", "net_name" : "AC_E1S0_PET_N<4>_XF", "refdes" : "C125_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page12", "phys_page" : "page12", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i67", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I67" } ] }, "C111_SP_XF.2" : { "node_name" : "C111_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i23", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7" } ], "net_name" : "GND", "pin_name" : "B", "refdes" : "C111_SP_XF", "part_number" : "402-000010-031" }, "PM7_SP_XF.A8" : { "node_name" : "PM7_SP_XF.A8", "pin_number" : "A8", "pin_type" : "POWER", "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT2_1", "part_number" : "462-000308-002", "refdes" : "PM7_SP_XF", "pin_name" : "VOUT2_1", "net_name" : "PWR_VCCINT_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I80", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "phys_page" : "page11" } ] }, "J3_XF.103" : { "node_name" : "J3_XF.103", "pin_type" : "GROUND", "pin_number" : "103", "pin_name_unsanitized" : "VSS_83", "pinuse" : "UNSPEC;", "pin_name" : "VSS_83", "net_name" : "GND", "refdes" : "J3_XF", "part_number" : "410-000300-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page8", "phys_page" : "page8" } ] }, "J2_XF.63" : { "pin_number" : "63", "pin_type" : "INPUT", "node_name" : "J2_XF.63", "pin_name" : "BG0", "refdes" : "J2_XF", "net_name" : "C1_DDR4_BG<0>_XF", "part_number" : "410-000300-001", "marker_data" : [ { "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1 } ], "pin_name_unsanitized" : "BG0", "pinuse" : "IN;" }, "C59_SP_XF.2" : { "pin_name_unsanitized" : "B1", "pinuse" : "UNSPEC;", "pin_name" : "B1", "net_name" : "NC_BL_1_SP", "refdes" : "C59_SP_XF", "part_number" : "402-000500-008", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i115", "sym_num" : 1, "page_instance" : "I115", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10" } ], "node_name" : "C59_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "R11.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "refdes" : "R11", "net_name" : "GND", "part_number" : "400-000010-006", "marker_data" : [ { "page_instance" : "I133", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i133", "sym_num" : 1, "phys_page" : "page10", "block" : "top", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10" } ], "node_name" : "R11.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_XF.W53" : { "pin_type" : "INOUT", "pin_number" : "W53", "node_name" : "U1_XF.W53", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "sym_num" : 34, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I69" } ], "part_number" : "450-000340-001", "pin_name" : "GND_288", "refdes" : "U1_XF", "net_name" : "GND", "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_288" }, "J4_XF.189" : { "pin_type" : "GROUND", "pin_number" : "189", "node_name" : "J4_XF.189", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10" } ], "refdes" : "J4_XF", "pin_name" : "VSS_22", "net_name" : "GND", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_22", "pinuse" : "UNSPEC;" }, "U1_CPLD.P4" : { "node_name" : "U1_CPLD.P4", "pin_type" : "INOUT", "pin_number" : "P4", "pinuse" : "BI;", "pin_name_unsanitized" : "IO4_PB3A_2", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page7_i152", "sym_num" : 8, "page_instance" : "I152", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top/cpld_blk" } ], "part_number" : "450-000313-001", "net_name" : "NC", "pin_name" : "IO4_PB3A_2", "refdes" : "U1_CPLD" }, "C196_SP_XF.1" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "phys_page" : "page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I112", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i112" } ], "pin_name" : "A", "net_name" : "PWR_VCCINT_XF", "refdes" : "C196_SP_XF", "part_number" : "402-000010-033", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C196_SP_XF.1" }, "FPNL_CONN.18" : { "pin_type" : "INOUT", "pin_number" : "18", "node_name" : "FPNL_CONN.18", "part_number" : "410-000327-001", "pin_name" : "SMBUS_SCL", "net_name" : "NC", "refdes" : "FPNL_CONN", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page3_i65", "ppath_without_last_instance" : "top/page3", "page_instance" : "I65", "phys_path" : "@top_lib.top(sch_1):page3", "path" : "@top_lib.top(sch_1):page3", "remapped_page" : null, "block" : "top", "page" : "page3", "phys_page" : "page3" } ], "pinuse" : "BI;", "pin_name_unsanitized" : "SMBUS_SCL" }, "U11_FL_XF.6" : { "pin_name_unsanitized" : "VIN_6", "pinuse" : "POWER;", "pin_name" : "VIN_6", "net_name" : "PWR_VCCAUX_SW_XF", "refdes" : "U11_FL_XF", "part_number" : "450-000057-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null, "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page9", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i66", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I66" } ], "node_name" : "U11_FL_XF.6", "pin_number" : "6", "pin_type" : "POWER" }, "U1_XF.L30" : { "pin_number" : "L30", "pin_type" : "INOUT", "node_name" : "U1_XF.L30", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I54", "sym_num" : 24, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54" } ], "refdes" : "U1_XF", "pin_name" : "IO_L14N_T2L_N3_GC_72", "net_name" : "NC", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_24;", "pin_name_unsanitized" : "IO_L14N_T2L_N3_GC_72" }, "C371_XF.2" : { "node_name" : "C371_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "C371_XF", "pin_name" : "B", "net_name" : "PWR_VCCINT_XF", "part_number" : "402-000015-008", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i67", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I67", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23" } ] }, "C50.1" : { "marker_data" : [ { "ppath" : "top/page4_i105", "sym_num" : 1, "page_instance" : "I105", "ppath_without_last_instance" : "top/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page4", "path" : "@top_lib.top(sch_1):page4", "phys_page" : "page4", "block" : "top", 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"PWR_AVTT_SW_XF", "part_number" : "402-000010-001", "node_name" : "C48_FL_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "J2_XF.99" : { "pin_name_unsanitized" : "DQS13_T_TDQ13_T", "pinuse" : "TRI;", "net_name" : "C1_RDIMM_DQS_T<13>_XF", "pin_name" : "DQS13_T_TDQ13_T", "refdes" : "J2_XF", "part_number" : "410-000300-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk", "page" : "page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6" } ], "node_name" : "J2_XF.99", "pin_type" : "INOUT", "pin_number" : "99" }, "PM4_SD_XF.L3" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_40", "part_number" : "462-000304-001", "pin_name" : "GND_40", "refdes" : "PM4_SD_XF", "net_name" : "GND", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i20", "sym_num" : 2, "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3" } ], "node_name" : "PM4_SD_XF.L3", "pin_number" : "L3", "pin_type" : "POWER" }, "U1_XF.AY12" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : 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: "ALL_POWER_PINS_33;", "pin_number" : "B22", "pin_type" : "INOUT", "node_name" : "U1_XF.B22" }, "PM2_SP_XF.C3" : { "pin_number" : "C3", "node_name" : "PM2_SP_XF.C3", "pin_name" : "VOUT0_13", "refdes" : "PM2_SP_XF", "net_name" : "PWR_AVTT_SW_XF", "part_number" : "462-000309-001", "marker_data" : [ { "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "page_instance" : "I516", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i516", "sym_num" : 1 } ], "pin_name_unsanitized" : "VOUT0_13", "pinuse" : "POWER;" }, "J1_E2_XF.A40" : { "pinuse" : "OUT;", "pin_name_unsanitized" : "PERP7", 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"pin_name_unsanitized" : "\\24\\", "pinuse" : "POWER;" }, "PM2_SP_XF.A8" : { "pin_number" : "A8", "node_name" : "PM2_SP_XF.A8", "part_number" : "462-000309-001", "refdes" : "PM2_SP_XF", "pin_name" : "GND_17", "net_name" : "GND", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "sym_num" : 5, "page_instance" : "I459", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_17" }, "U1_XF.J8" : { "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_123", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33, "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24" } ], "part_number" : "450-000340-001", "pin_name" : "GND_123", "net_name" : "GND", "refdes" : "U1_XF", "node_name" : "U1_XF.J8", "pin_type" : "INOUT", "pin_number" : "J8" }, "J4_XF.248" : { "marker_data" : [ { "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1 } ], "part_number" : "410-000300-001", "pin_name" : "VSS_86", "net_name" : "GND", "refdes" : "J4_XF", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_86", "pin_type" : "GROUND", "pin_number" : "248", "node_name" : "J4_XF.248" }, "C442_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i154", "sym_num" : 1, "page_instance" : "I154", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk" } ], "part_number" : "402-000010-039", "pin_name" : "B", "refdes" : "C442_XF", "net_name" : "PWR_NDIMM_VDD_XF", "node_name" : "C442_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_CPLD.M7" : { "node_name" : "U1_CPLD.M7", "pin_number" : "M7", "pin_type" : "INOUT", "pin_group" : "FPNL_6;", "pinuse" : "BI;", "pin_name_unsanitized" : "PSU_SMBALERTN_OD", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/cpld_blk", "phys_page" : "page6", "sym_num" : 6, "ppath" : "top/page14_i1/cpld_blk/page6_i130", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page6", "page_instance" : "I130" } ], "part_number" : "450-000313-001", "refdes" : "U1_CPLD", "pin_name" : "PSU_SMBALERTN_OD", "net_name" : "PSU_SMBALERTN_OD" }, "C143_XF.2" : { "marker_data" : [ { "phys_page" : "page17", "block" : "top/xc2_fpga_blk", "page" : "page17", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "page_instance" : "I23", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i23", "sym_num" : 1 } ], "part_number" : "402-000010-001", "pin_name" : "B", "refdes" : "C143_XF", "net_name" : "GNDADC_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C143_XF.2" }, "R4_E3_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3_i80", "sym_num" : 1, "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3" } ], "part_number" : "400-000010-007", "pin_name" : "B", "net_name" : "E1S3_3R3V_SDA_XF", "refdes" : "R4_E3_XF", "node_name" : "R4_E3_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "R6.2" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page13", "page_instance" : "I45", "sym_num" : 1, "ppath" : "top/page13_i45", "page" : "page13", "block" : "top", "phys_page" : "page13", "path" : "@top_lib.top(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page13", "remapped_page" : null } ], "part_number" : "400-000010-002", "refdes" : "R6", "pin_name" : "B", "net_name" : "UNNAMED_13_RESISTOR_I34_A", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R6.2" }, "U1_XF.C7" : { "pin_number" : "C7", "pin_type" : "INOUT", "node_name" : "U1_XF.C7", "pin_name" : "E1S0_PET_P0", "net_name" : "AC_E1S0_PET_P<0>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page12", "block" : "top/xc2_fpga_blk", "page" : "page12", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "page_instance" : "I283", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283", "sym_num" : 9 } ], "pin_name_unsanitized" : "E1S0_PET_P0", "pin_group" : "ALL_SIGNAL_PINS_9;" }, "NS9_FL_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "NET_SHORT", "net_name" : "PWR_AVTT_RUC_XF", "pin_name" : "A", "refdes" : "NS9_FL_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8_i14", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8", "page_instance" : "I14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "remapped_page" : null, "page" : "page8", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page8" } ], "node_name" : "NS9_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "R136.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "refdes" : "R136", "net_name" : "UNNAMED_10_RESISTOR_I66_B", "part_number" : "400-000010-006", "marker_data" : [ { "phys_page" : "page10", "page" : "page10", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "page_instance" : "I66", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i66", "sym_num" : 1 } ], "node_name" : "R136.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_CPLD.G12" : { "part_number" : "450-000313-001", "pin_name" : "IO9_PR5D_1", "net_name" : "NC", "refdes" : "U1_CPLD", "marker_data" : [ { "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152", "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152" } ], "pinuse" : "BI;", "pin_name_unsanitized" : "IO9_PR5D_1", "pin_type" : "INOUT", "pin_number" : "G12", "node_name" : "U1_CPLD.G12" }, "C451_XF.2" : { "refdes" : "C451_XF", "pin_name" : "B", "net_name" : "PWR_NDIMM_VDD_XF", "part_number" : "402-000010-028", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i163", "sym_num" : 1, "page_instance" : "I163", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C451_XF.2" }, "U1_XF.AA23" : { "pin_name" : "GND_323", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I69", "sym_num" : 34, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "pin_name_unsanitized" : "GND_323", "pin_group" : "ALL_POWER_PINS_34;", "pin_type" : "INOUT", "pin_number" : "AA23", "node_name" : "U1_XF.AA23" }, "C71.1" : { "node_name" : "C71.1", "pin_type" : "ANALOG", "pin_number" : "1", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-032", "net_name" : "GND", "pin_name" : "A", "refdes" : "C71", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page19", "path" : "@top_lib.top(sch_1):page19", "phys_page" : "page19", "block" : "top", "page" : "page19", "ppath" : "top/page19_i51", "sym_num" : 1, "page_instance" : "I51", "ppath_without_last_instance" : "top/page19" } ] }, "C321_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "GND", "refdes" : "C321_XF", "part_number" : "402-000015-007", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i141", "sym_num" : 1, "page_instance" : "I141", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23" } ], "node_name" : "C321_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "J2_XF.161" : { "node_name" : "J2_XF.161", "pin_type" : "INOUT", "pin_number" : "161", "pinuse" : "TRI;", "pin_name_unsanitized" : "DQ9", "marker_data" : [ { "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1 } ], "part_number" : "410-000300-001", "pin_name" : "DQ9", "net_name" : "C1_DDR4_DQ<9>_XF", "refdes" : "J2_XF" }, "U1_XF.BM53" : { "pin_name" : "C1_DDR4_DQS_T15", "refdes" : "U1_XF", "net_name" : "C1_RDIMM_DQS_T<16>_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "sym_num" : 46, "phys_page" : "PAGE5", "page" : "PAGE5", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5" } ], "pin_name_unsanitized" : "C1_DDR4_DQS_T15", "pin_group" : "ALL_SIGNAL_PINS_39;", "pin_type" : "INOUT", "pin_number" : "BM53", "node_name" : "U1_XF.BM53" }, "C47_SP_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C47_SP_XF.1", "refdes" : "C47_SP_XF", "pin_name" : "A", "net_name" : "UNNAMED_4_CAPACITOR_I132_A_SP", "part_number" : "402-000202-006", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "page_instance" : "I144", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i144", "sym_num" : 1 } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "U1_XF.BE61" : { "node_name" : "U1_XF.BE61", "pin_type" : "INOUT", "pin_number" : "BE61", "pin_name_unsanitized" : "GND_823", "pin_group" : "ALL_POWER_PINS_37;", "pin_name" : "GND_823", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 37, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I72", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24" } ] }, "PM4_SD_XF.E9" : { "pin_name" : "GND_23", "refdes" : "PM4_SD_XF", "net_name" : "GND", "part_number" : "462-000304-001", "marker_data" : [ { "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i20", "sym_num" : 2, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "remapped_page" : null, "path" : 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"page3", "block" : "top", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page3", "page_instance" : "I65", "sym_num" : 1, "ppath" : "top/page3_i65" } ], "part_number" : "410-000327-001", "net_name" : "UNNAMED_3_RESISTOR_I59_A", "pin_name" : "FAULT_LED2_N", "refdes" : "FPNL_CONN" }, "PM7_SP_XF.C3" : { "pin_name_unsanitized" : "VOUT1_13", "pinuse" : "POWER;", "refdes" : "PM7_SP_XF", "pin_name" : "VOUT1_13", "net_name" : "PWR_VCCINT_XF", "part_number" : "462-000308-002", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I80", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : 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"page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283", "sym_num" : 9, "page_instance" : "I283", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12" } ], "part_number" : "450-000340-001", "pin_name" : "E1S1_PER_N6", "net_name" : "E1S1_PER_N<6>_XF", "refdes" : "U1_XF" }, "U1_XF.AC28" : { "pin_group" : "ALL_POWER_PINS_31;", "pin_name_unsanitized" : "VCCINT_68", "marker_data" : [ { "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "page_instance" : "I186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "sym_num" : 31 } ], "pin_name" : "VCCINT_68", "refdes" : "U1_XF", "net_name" : "PWR_VCCINT_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.AC28", "pin_number" : "AC28", "pin_type" : "INOUT" }, "PM7_SP_XF.H11" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_39", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i151", "sym_num" : 2, "page_instance" : "I151", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11" } ], "part_number" : "462-000308-002", "net_name" : "GND", "pin_name" : "GND_39", "refdes" : "PM7_SP_XF", "node_name" : "PM7_SP_XF.H11", "pin_type" : "POWER", "pin_number" : "H11" }, "U1_XF.P5" : { "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_192", "marker_data" : [ { "page" : "page24", "block" : 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"page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180" } ], "net_name" : "GND", "pin_name" : "VSS_42", "refdes" : "J4_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_42", "pinuse" : "UNSPEC;" }, "J3.15" : { "pin_number" : "15", "node_name" : "J3.15", "marker_data" : [ { "page" : "page19", "block" : "top", "phys_page" : "page19", "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19", "remapped_page" : null, "ppath_without_last_instance" : "top/page19", "page_instance" : "I41", "sym_num" : 1, "ppath" : "top/page19_i41" } ], "refdes" : "J3", "pin_name" : "15", "net_name" : "GND", "part_number" : "410-000105-001", "pin_name_unsanitized" : "\\15\\", "pinuse" : "POWER;" }, "J3_XF.173" : { "part_number" : "410-000300-001", "net_name" : "GND", "pin_name" : "VSS_78", "refdes" : "J3_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : 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"pin_name_unsanitized" : "GND_403", "pin_group" : "ALL_POWER_PINS_35;" }, "C352_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C352_XF.2", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_page" : "page29", "block" : "top/xc2_fpga_blk", "page" : "page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i153", "sym_num" : 1, "page_instance" : "I153", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29" } ], "pin_name" : "B", "net_name" : "PWR_FPGA_3R3V", "refdes" : "C352_XF", "part_number" : "402-000010-001", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "U1_CPLD.F12" : { "node_name" : "U1_CPLD.F12", "pin_number" : "F12", "pin_type" : "INOUT", "pinuse" : "BI;", "pin_name_unsanitized" : "PCIE_X1_RESET_3V_F", "pin_group" : "PCIE_RST_1;", "part_number" : "450-000313-001", "refdes" : "U1_CPLD", "pin_name" : "PCIE_X1_RESET_3V_F", "net_name" : "PCIE_X1_RESET_3V_F", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page3_i447", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page3", "page_instance" : "I447", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "remapped_page" : null, "block" : "top/cpld_blk", "page" : "page3", "phys_page" : "page3" } ] }, "R4_ND_XF.2" : { "net_name" : "VMON_NDIMM_VTT_LIN", "pin_name" : "B", "refdes" : "R4_ND_XF", "part_number" : "400-000014-011", "marker_data" : [ { "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4", "page_instance" : "I28", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4_i28" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R4_ND_XF.2" }, "C422_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C422_XF.2", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I158", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i158", "page" : "page6", "block" : "top/xc2_fpga_blk", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null } ], "pin_name" : "B", "refdes" : "C422_XF", "net_name" : "PWR_SDIMM_VDD_XF", "part_number" : "402-000010-028", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "C255_XF.2" : { "marker_data" : [ { "phys_page" : "page14", "page" : "page14", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "page_instance" : "I147", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i147", "sym_num" : 1 } ], "net_name" : "OCL3_PET_P<2>_XF", "pin_name" : "B", "refdes" : "C255_XF", "part_number" : "402-000010-035", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C255_XF.2" }, "C39_SP_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C39_SP_XF.2", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I148", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i148" } ], "pin_name" : "B", "refdes" : "C39_SP_XF", "net_name" : "GND", "part_number" : "402-000010-006", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "U11_FL_XF.9" : { "pin_type" : "POWER", "pin_number" : "9", "node_name" : "U11_FL_XF.9", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i66", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I66", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null, "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page9" } ], "part_number" : "450-000057-001", "pin_name" : "GND_9", "refdes" : "U11_FL_XF", "net_name" : "GND", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_9" }, "C123_XF.2" : { "part_number" : "402-000010-028", "pin_name" : "B", "net_name" : "GND", "refdes" : "C123_XF", "marker_data" : [ { "phys_page" : "page20", "block" : "top/xc2_fpga_blk", "page" : "page20", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "page_instance" : "I1", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i1", "sym_num" : 1 } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C123_XF.2" }, "U1_XF.H48" : { "refdes" : "U1_XF", "pin_name" : "C2_DDR4_DQ54", "net_name" : "C2_DDR4_DQ<54>_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page" : "PAGE7", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "page_instance" : "I2425", "sym_num" : 63, "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425" } ], "pin_name_unsanitized" : "C2_DDR4_DQ54", "pin_group" : "C2_UNIB_1_6_57;", "pin_number" : "H48", "pin_type" : "INOUT", "node_name" : "U1_XF.H48" }, "U1_XF.BP44" : { "node_name" : "U1_XF.BP44", "pin_type" : "INOUT", "pin_number" : "BP44", "pin_name_unsanitized" : "IO_L9P_T1L_N4_AD12P_19", "pin_group" : "ALL_SIGNAL_PINS_17;", "refdes" : "U1_XF", "pin_name" : "IO_L9P_T1L_N4_AD12P_19", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30", "sym_num" : 17, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I50" } ] }, "J4_XF.57" : { "marker_data" : [ { "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180" } ], "part_number" : "410-000300-001", "refdes" : "J4_XF", "pin_name" : "VSS_54", "net_name" : "GND", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_54", "pin_number" : "57", "pin_type" : "GROUND", "node_name" : "J4_XF.57" }, "C341_XF.2" : { "refdes" : "C341_XF", "pin_name" : "B", "net_name" : "E1S3_PET_P<1>_XF", "part_number" : "402-000010-035", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page13", "phys_page" : "page13", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i95", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I95" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C341_XF.2" }, "U1_XF.AA4" : { "pin_name" : "GND_316", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34, "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "pin_name_unsanitized" : "GND_316", "pin_group" : "ALL_POWER_PINS_34;", "pin_number" : "AA4", "pin_type" : "INOUT", "node_name" : "U1_XF.AA4" }, "U1_XF.N38" : { "pin_name_unsanitized" : "IO_L12P_T1U_N10_GC_70", "pin_group" : "ALL_SIGNAL_PINS_25;", "part_number" : "450-000340-001", "pin_name" : "IO_L12P_T1U_N10_GC_70", "net_name" : "NC", "refdes" : "U1_XF", "marker_data" : [ { "sym_num" : 25, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i59", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I59", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31" } ], "node_name" : "U1_XF.N38", "pin_type" : "INOUT", "pin_number" : "N38" }, "J4_XF.123" : { "node_name" : "J4_XF.123", "pin_type" : "GROUND", "pin_number" : "123", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_39", "part_number" : "410-000300-001", "net_name" : "GND", "pin_name" : "VSS_39", "refdes" : "J4_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10" } ] }, "C96_SP_XF.1" : { "net_name" : "PWR_AVTT_SW_XF", "pin_name" : "A", "refdes" : "C96_SP_XF", "part_number" : "402-000010-031", "marker_data" : [ { "page_instance" : "I485", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i485", "sym_num" : 1, "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C96_SP_XF.1" }, "J1_P1_XF.B1" : { "node_name" : "J1_P1_XF.B1", "pin_number" : "B1", "pinuse" : "POWER;", "pin_name_unsanitized" : "PWR_5R0V_V1", "part_number" : "410-000324-001", "pin_name" : "PWR_5R0V_V1", "refdes" : "J1_P1_XF", "net_name" : "NC", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "page_instance" : "I86", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i86" } ] }, "PM7_SP_XF.C4" : { "pin_type" : "POWER", "pin_number" : "C4", "node_name" : "PM7_SP_XF.C4", "part_number" : "462-000308-002", "pin_name" : "VOUT1_14", "refdes" : "PM7_SP_XF", "net_name" : "PWR_VCCINT_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80", "sym_num" : 1, "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT1_14" }, "PM4_SP_XF.A8" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT2_1", "part_number" : "462-000308-002", "pin_name" : "VOUT2_1", "refdes" : "PM4_SP_XF", "net_name" : "PWR_VCCINT_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "page_instance" : "I80", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i80", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "remapped_page" : null } ], "node_name" : "PM4_SP_XF.A8", "pin_number" : "A8", "pin_type" : "POWER" }, "J1_O2_XF.A11" : { "part_number" : "410-000324-001", "refdes" : "J1_O2_XF", "net_name" : "GND", "pin_name" : "GND_4", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i30/ocl_x4_conn_blk/page3_i84", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i30/ocl_x4_conn_blk/page3", "page_instance" : "I84", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i30@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i30@top_lib.ocl_x4_conn_blk(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "phys_page" : "page3" } ], "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_4", "pin_number" : "A11", "node_name" : "J1_O2_XF.A11" }, "S1.5" : { "node_name" : "S1.5", "pin_number" : "5", "pin_type" : "OUTPUT", "pin_name_unsanitized" : "CMN_2", "pinuse" : "OUT;", "marker_data" : [ { "page_instance" : "I12", "ppath_without_last_instance" : "top/page17", "ppath" : "top/page17_i12", "sym_num" : 1, "phys_page" : "page17", "block" : "top", "page" : "page17", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page17", "path" : "@top_lib.top(sch_1):page17" } ], "pin_name" : "CMN_2", "net_name" : "GND", "refdes" : "S1", "part_number" : "406-000003-001" }, "J3_XF.198" : { "node_name" : "J3_XF.198", "pin_type" : "GROUND", "pin_number" : "198", "pin_name_unsanitized" : "VSS_47", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8" } ], "net_name" : "GND", "pin_name" : "VSS_47", "refdes" : "J3_XF", "part_number" : "410-000300-001" }, "J1_E1_XF.A4" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_4", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "page_instance" : "I101", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i101", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null } ], "part_number" : "410-000317-001", "refdes" : "J1_E1_XF", "pin_name" : "GND_4", "net_name" : "GND", "node_name" : "J1_E1_XF.A4", "pin_number" : "A4" }, "U1_XF.E43" : { "pin_name" : "IO_L23N_T3U_N9_37", "net_name" : "NC", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "page_instance" : "I58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "sym_num" : 26 } ], "pin_name_unsanitized" : "IO_L23N_T3U_N9_37", "pin_group" : "ALL_SIGNAL_PINS_26;", "pin_type" : "INOUT", "pin_number" : "E43", "node_name" : "U1_XF.E43" }, "PM1_SP_XF.N1" : { "node_name" : "PM1_SP_XF.N1", "pin_number" : "N1", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_55", "part_number" : "462-000309-001", "pin_name" : "GND_55", "refdes" : "PM1_SP_XF", "net_name" : "GND", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I11" } ] }, "J1_P0_XF.A15" : { "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1 } ], "part_number" : "410-000324-001", "pin_name" : "PERP2", "refdes" : "J1_P0_XF", "net_name" : "PCIE0_RXP<2>_XF", "pinuse" : "OUT;", "pin_name_unsanitized" : "PERP2", "pin_type" : "OUTPUT", "pin_number" : "A15", "node_name" : "J1_P0_XF.A15" }, "U1_XF.N50" : { "node_name" : "U1_XF.N50", "pin_type" : "INOUT", "pin_number" : "N50", "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_187", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I68", "sym_num" : 33, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "GND_187", "net_name" : "GND" }, "C93_FL_XF.1" : { "node_name" : "C93_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12", "phys_page" : "page11", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i35", "sym_num" : 1, "page_instance" : "I35", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11" } ], "part_number" : "402-000010-001", "pin_name" : "A", "net_name" : "PWR_AVCC_SW_XF", "refdes" : "C93_FL_XF" }, "U1_XF.BM9" : { "pin_type" : "INOUT", "pin_number" : "BM9", "node_name" : "U1_XF.BM9", "marker_data" : [ { "page_instance" : "I275", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i275", "sym_num" : 12, "phys_page" : "page14", "block" : "top/xc2_fpga_blk", "page" : "page14", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14" } ], "net_name" : "AC_OCL2_PET_P<1>_XF", "pin_name" : "OCL2_PET_P1", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_12;", "pin_name_unsanitized" : "OCL2_PET_P1" }, "J1_XF.31" : { "pin_name_unsanitized" : "VSS_82", "pinuse" : "UNSPEC;", "refdes" : "J1_XF", "pin_name" : "VSS_82", "net_name" : "GND", "part_number" : "410-000300-001", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4" } ], "node_name" : "J1_XF.31", "pin_type" : "GROUND", "pin_number" : "31" }, "PM2_SP_XF.A6" : { "pin_number" : "A6", "pin_type" : "INOUT", "node_name" : "PM2_SP_XF.A6", "pin_name" : "TSENSE0_N", "net_name" : "DN2_DP<3>_SP", "refdes" : "PM2_SP_XF", "part_number" : "462-000309-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I516", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i516" } ], "pin_name_unsanitized" : "TSENSE0_N", "pinuse" : "BI;" }, "PM4_ND_XF.A5" : { "node_name" : "PM4_ND_XF.A5", "pin_type" : "POWER", "pin_number" : "A5", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_4", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page3", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I20" } ], "part_number" : "462-000304-001", "pin_name" : "GND_4", "net_name" : "GND", "refdes" : "PM4_ND_XF" }, "J1_XF.121" : { "part_number" : "410-000300-001", "pin_name" : "DQS15_T_TDQS15_T", "refdes" : "J1_XF", "net_name" : "C0_RDIMM_DQS_T<15>_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4" } ], "pinuse" : "TRI;", "pin_name_unsanitized" : "DQS15_T_TDQS15_T", "pin_type" : "INOUT", "pin_number" : "121", "node_name" : "J1_XF.121" }, "J1_XF.204" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4" } ], "refdes" : "J1_XF", "pin_name" : "VDD_18", "net_name" : "PWR_SDIMM_VDD_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VDD_18", "pinuse" : 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}, "U1_CPLD.J13" : { "pin_type" : "INOUT", "pin_number" : "J13", "node_name" : "U1_CPLD.J13", "part_number" : "450-000313-001", "refdes" : "U1_CPLD", "pin_name" : "FP_RST_SW_N", "net_name" : "FP_RST_SW_N", "marker_data" : [ { "phys_page" : "page6", "page" : "page6", "block" : "top/cpld_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page6", "page_instance" : "I130", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page6", "ppath" : "top/page14_i1/cpld_blk/page6_i130", "sym_num" : 6 } ], "pinuse" : "BI;", "pin_name_unsanitized" : "FP_RST_SW_N", "pin_group" : "FPNL_6;" }, "R17.1" : { "part_number" : "400-000014-011", "net_name" : "CPLD_P1R8V_1", "pin_name" : "A", "refdes" : "R17", "marker_data" : [ { "phys_page" : "page10", "block" : "top", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page10", "path" : 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"POWER", "pin_number" : "21", "node_name" : "U1_SP_XF.21", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i168", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I168" } ], "part_number" : "450-000302-001", "pin_name" : "GND21", "net_name" : "GND", "refdes" : "U1_SP_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND21" }, "C216_XF.2" : { "net_name" : "PWR_NDIMM_VDD_XF", "pin_name" : "B", "refdes" : "C216_XF", "part_number" : "402-000010-001", "marker_data" : [ { "remapped_page" : null, "path" : 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"page24", "page" : "page24", "block" : "top/xc2_fpga_blk" } ], "node_name" : "U1_XF.AJ58", "pin_type" : "INOUT", "pin_number" : "AJ58" }, "U1_XF.BJ34" : { "part_number" : "450-000340-001", "pin_name" : "IO_L24N_T3U_N11_DOUT_CSO_B_65", "refdes" : "U1_XF", "net_name" : "NC", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i52", "sym_num" : 21, "page_instance" : "I52", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30" } ], "pin_name_unsanitized" : "IO_L24N_T3U_N11_DOUT_CSO_B_65", "pin_group" : "ALL_SIGNAL_PINS_21;", "pin_number" : "BJ34", "pin_type" : "INOUT", "node_name" : "U1_XF.BJ34" }, "R12.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000014-011", "refdes" : "R12", "pin_name" : "A", "net_name" : "CPLD_P1R8V_1", "marker_data" : [ { "ppath_without_last_instance" : "top/page10", "page_instance" : "I112", "sym_num" : 1, "ppath" : "top/page10_i112", "block" : "top", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "remapped_page" : null } ], "node_name" : "R12.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "NS11_FL_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I49", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i49", "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null } ], "refdes" : "NS11_FL_XF", "pin_name" : "B", "net_name" : "UNNAMED_9_LT3071_I66_SENSE_FL", "part_number" : "NET_SHORT", "node_name" : "NS11_FL_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "PM1_SP_XF.C3" : { "node_name" : "PM1_SP_XF.C3", "pin_number" : "C3", "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT0_13", "part_number" : "462-000309-001", "refdes" : "PM1_SP_XF", "pin_name" : "VOUT0_13", "net_name" : "PWR_VCCAUX_SW_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i87", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I87", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7" } ] }, "R69_FL_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R69_FL_XF", "pin_name" : "A", "net_name" : "UNNAMED_3_LT3071_I32_EN_FL", "part_number" : "400-000010-074", "marker_data" : [ { "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3", "page_instance" : "I21", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3_i21" } ], "node_name" : "R69_FL_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_XF.AL19" : { "node_name" : "U1_XF.AL19", "pin_type" : "INOUT", "pin_number" : "AL19", "pin_name_unsanitized" : "GND_531", "pin_group" : "ALL_POWER_PINS_35;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "GND_531", "net_name" : "GND", "marker_data" : [ { "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I70", "sym_num" : 35, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70" } ] }, "U1_XF.T63" : { "pin_type" : "INOUT", "pin_number" : "T63", "node_name" : "U1_XF.T63", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "sym_num" : 22, "page_instance" : "I46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L2N_T0L_N3_33", "net_name" : "NC", "pin_group" : "ALL_SIGNAL_PINS_22;", "pin_name_unsanitized" : "IO_L2N_T0L_N3_33" }, "U1_XF.C54" : { "pin_type" : "INOUT", "pin_number" : "C54", "node_name" : "U1_XF.C54", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_page" : "PAGE7", "page" : "PAGE7", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425", "sym_num" : 62, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7" } ], "net_name" : "C2_DDR4_DQ<46>_XF", "pin_name" : "C2_DDR4_DQ46", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "C2_UNIB_1_6_57;", "pin_name_unsanitized" : "C2_DDR4_DQ46" }, "U1_XF.BT19" : { "pin_group" : "ALL_POWER_PINS_37;", "pin_name_unsanitized" : "GND_983", "marker_data" : [ { "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "sym_num" : 37, "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "part_number" : "450-000340-001", "pin_name" : "GND_983", "net_name" : "GND", "refdes" : "U1_XF", "node_name" : "U1_XF.BT19", "pin_number" : "BT19", "pin_type" : "INOUT" }, "U1_XF.F46" : { "pin_number" : "F46", "pin_type" : "INOUT", "node_name" : "U1_XF.F46", "marker_data" : [ { "sym_num" : 26, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I58", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31" } ], "pin_name" : "IO_T2U_N12_37", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_26;", "pin_name_unsanitized" : "IO_T2U_N12_37" }, "C90_FL_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C90_FL_XF.1", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page11", "phys_page" : "page11", "page" : "page12", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i31", "sym_num" : 1, "page_instance" : "I31", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11" } ], "refdes" : "C90_FL_XF", "pin_name" : "A", "net_name" : "UNNAMED_12_BYPASSCAPNPOL_I31_A_FL", "part_number" : "402-000010-005", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "U1_XF.R47" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I55", "sym_num" : 15, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i55" } ], "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_T1U_N12_36", "refdes" : "U1_XF", "pin_group" : "ALL_SIGNAL_PINS_15;", "pin_name_unsanitized" : "IO_T1U_N12_36", "pin_type" : "INOUT", "pin_number" : "R47", "node_name" : "U1_XF.R47" }, "U1_XF.AV4" : { "node_name" : "U1_XF.AV4", "pin_type" : "INOUT", "pin_number" : "AV4", "pin_name_unsanitized" : "PCIE0_RXP0", "pin_group" : "ALL_SIGNAL_PINS_3;", "net_name" : "PCIE0_RXP<0>_XF", "pin_name" : "PCIE0_RXP0", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775", "sym_num" : 3, "page_instance" : "I775", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_page" : "page11", "block" : "top/xc2_fpga_blk", "page" : "page11" } ] }, "C19.2" : { "node_name" : "C19.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "net_name" : "GND", "pin_name" : "B", "refdes" : "C19", "part_number" : "402-000010-026", "marker_data" : [ { "phys_page" : "page10", "block" : "top", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "page_instance" : "I131", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i131", "sym_num" : 1 } ] }, "C28_SP_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "path" : 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"phys_page" : "page4", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "page_instance" : "I211", "sym_num" : 3, "ppath" : "top/page14_i1/cpld_blk/page4_i211" } ], "part_number" : "450-000313-001", "net_name" : "ENB3V_SEQ_E", "pin_name" : "ENB3V_SEQ_E", "refdes" : "U1_CPLD" }, "R1_E2_XF.2" : { "node_name" : "R1_E2_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000014-012", "pin_name" : "B", "refdes" : "R1_E2_XF", "net_name" : "UNNAMED_3_RESISTOR_I70_B_E2", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3", "page_instance" : "I70", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i70", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null } ] }, "C22_FL_XF.1" : { "node_name" : "C22_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000020-011", "net_name" : "GND", "pin_name" : "A", "refdes" : "C22_FL_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6_i25", "sym_num" : 1, "page_instance" : "I25", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1" } ] }, "C41_SP_XF.1" : { "node_name" : "C41_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "refdes" : "C41_SP_XF", "net_name" : "PWR_VCCINT_XF", "part_number" : "402-000010-033", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i114", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "page_instance" : "I114" } ] }, "R76.1" : { "pin_name" : "A", "refdes" : "R76", "net_name" : "UNNAMED_4_MAX116XXQSOP16_I97_AIN5", "part_number" : "400-000010-010", "marker_data" : [ { "page" : "page4", "block" : "top", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page4", "page_instance" : "I119", "sym_num" : 1, "ppath" : "top/page4_i119" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R76.1" }, "J1_XF.157" : { "node_name" : "J1_XF.157", "pin_number" : "157", "pin_type" : "INOUT", "pinuse" : "TRI;", "pin_name_unsanitized" : "DQ3", "part_number" : "410-000300-001", "net_name" : "C0_DDR4_DQ<3>_XF", "pin_name" : "DQ3", "refdes" : "J1_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk" } ] }, "C472_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C472_XF.1", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page20", "phys_page" : "page20", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i17", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I17" } ], "part_number" : "402-000010-001", "refdes" : "C472_XF", "pin_name" : "A", "net_name" : "PWR_AVTT_RLC_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "U1_XF.AV47" : { "refdes" : "U1_XF", "pin_name" : "IO_L21N_T3L_N5_AD8N_27", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 18, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I51", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30" } ], "pin_name_unsanitized" : "IO_L21N_T3L_N5_AD8N_27", "pin_group" : "ALL_SIGNAL_PINS_18;", "pin_type" : "INOUT", "pin_number" : "AV47", "node_name" : "U1_XF.AV47" }, "J1_XF.28" : { "pin_name" : "VSS_75", "net_name" : "GND", "refdes" : "J1_XF", "part_number" : "410-000300-001", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4" } ], "pin_name_unsanitized" : "VSS_75", "pinuse" : "UNSPEC;", "pin_number" : "28", "pin_type" : "GROUND", "node_name" : "J1_XF.28" }, "C173_XF.1" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i76", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I76", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "page" : "page13", "block" : "top/xc2_fpga_blk", "phys_page" : "page13" } ], "net_name" : "AC_E1S2_PET_N<0>_XF", "pin_name" : "A", "refdes" : "C173_XF", "part_number" : "402-000010-035", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C173_XF.1" }, "U3_XF.B3" : { "marker_data" : [ { "phys_page" : "page15", "block" : "top/xc2_fpga_blk", "page" : "page15", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "page_instance" : "I39", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i39", "sym_num" : 2 } ], "refdes" : "U3_XF", "pin_name" : "VSS", "net_name" : "GND", "part_number" : "450-000341-001", "pin_name_unsanitized" : "VSS", "pinuse" : "UNSPEC;", "pin_number" : "B3", "pin_type" : "GROUND", "node_name" : "U3_XF.B3" }, "C67_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C67_XF.2", "net_name" : "GND", "pin_name" : "B", "refdes" : "C67_XF", "part_number" : "402-000015-007", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i137", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I137", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "U1_XF.C13" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I86", "sym_num" : 29, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i86", "block" : "top/xc2_fpga_blk", "page" : "page20", "phys_page" : "page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null } ], "part_number" : "450-000340-001", "pin_name" : "MGTAVCC_RN_1", "refdes" : "U1_XF", "net_name" : "PWR_AVCC_RN_XF", "pin_group" : "ALL_POWER_PINS_29;", "pin_name_unsanitized" : "MGTAVCC_RN_1", "pin_number" : "C13", "pin_type" : "INOUT", "node_name" : "U1_XF.C13" }, "R2_MP.1" : { "node_name" : "R2_MP.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/mgmt_pwr_block", "ppath" : "top/page18_i1/mgmt_pwr_block/page3_i25", "sym_num" : 1, "page_instance" : "I25", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page3" } ], "net_name" : "P5VSB", "pin_name" : "A", "refdes" : "R2_MP", "part_number" : "400-000010-010" }, "PM1_SP_XF.H11" : { "net_name" : "UNNAMED_7_LTM4671_I87_COMP0A_SP", "pin_name" : "COMP0B", "refdes" : "PM1_SP_XF", "part_number" : "462-000309-001", "marker_data" : [ { "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "page_instance" : "I87", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i87", "sym_num" : 1 } ], "pin_name_unsanitized" : "COMP0B", "pinuse" : "IN;", "pin_type" : "INPUT", "pin_number" : "H11", "node_name" : "PM1_SP_XF.H11" }, "U1.44" : { "pin_type" : "OUTPUT", "pin_number" : "44", "node_name" : "U1.44", "net_name" : "OCL_REF_CLK_N<1>", "pin_name" : "OUT6_N", "refdes" : "U1", "part_number" : "450-000308-002", "marker_data" : [ { "page" : "page10", "block" : "top", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page10", "page_instance" : "I51", "sym_num" : 1, "ppath" : "top/page10_i51" } ], "pin_name_unsanitized" : "OUT6_N", "pinuse" : "OUT;" }, "U1_XF.T43" : { "pin_name_unsanitized" : "IO_L2N_T0L_N3_38", "pin_group" : "ALL_SIGNAL_PINS_26;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L2N_T0L_N3_38", "net_name" : "NC", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I58", "sym_num" : 26, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58" } ], "node_name" : "U1_XF.T43", "pin_type" : "INOUT", "pin_number" : "T43" }, "R61_SD_XF.2" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4", "page_instance" : "I7", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4_i7", "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "remapped_page" : null } ], "part_number" : "400-000014-011", "pin_name" : "B", "refdes" : "R61_SD_XF", "net_name" : "POK_OD_SDIMM_VTT_LIN", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R61_SD_XF.2" }, "R4_SP_XF.2" : { "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i36", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "page_instance" : "I36" } ], "part_number" : "400-000011-010", "refdes" : "R4_SP_XF", "pin_name" : "B", "net_name" : "FSET_4650_TL_SP", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R4_SP_XF.2" }, "U1_XF.K14" : { "pin_type" : "INOUT", "pin_number" : "K14", "node_name" : "U1_XF.K14", "pin_name" : "GND_138", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33, "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24" } ], "pin_name_unsanitized" : "GND_138", "pin_group" : "ALL_POWER_PINS_33;" }, "C45_CPLD.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : 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"refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.AD50", "pin_number" : "AD50", "pin_type" : "INOUT" }, "R13_CPLD.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-074", "pin_name" : "B", "net_name" : "GND", "refdes" : "R13_CPLD", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "page_instance" : "I77", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page4_i77", "page" : "page4", "block" : "top/cpld_blk", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "remapped_page" : null } ], "node_name" : "R13_CPLD.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_XF.BW32" : { "pin_name_unsanitized" : "VAUX_N6", "pin_group" : "ALL_SIGNAL_PINS_2;", "pin_name" : "VAUX_N6", "refdes" : "U1_XF", "net_name" : "UNNAMED_17_BYPASSCAPNPOL_I116_B_XF", "part_number" : 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null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I36", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i36" } ], "node_name" : "R84_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "PM1_SP_XF.M8" : { "node_name" : "PM1_SP_XF.M8", "pin_number" : "M8", "pin_type" : "OUTPUT", "pin_name_unsanitized" : "PGOOD2", "pinuse" : "OUT;", "marker_data" : [ { "page_instance" : "I39", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i39", "sym_num" : 3, "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7" } ], "net_name" : "POK_OD_SDIMM_VPP_SW", "pin_name" : "PGOOD2", "refdes" : "PM1_SP_XF", "part_number" : "462-000309-001" }, "U3_SP_XF.1_2" : { "pin_type" : "INPUT", "pin_number" : "1_2", "node_name" : "U3_SP_XF.1_2", "part_number" : "450-000162-001", "pin_name" : "IP_P", "net_name" : "P12V_MAIN", "refdes" : "U3_SP_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page9_i28", "sym_num" : 1, "page_instance" : "I28", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page9", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page9", "phys_page" : "page9", "page" : "page9", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "pinuse" : "IN;", "pin_name_unsanitized" : "IP_P" }, "U1_E1_XF.23" : { "part_number" : "450-000345-001", "net_name" : "AC_FPGA_CLK_REF_N<0>", "pin_name" : "Q2_N", "refdes" : "U1_E1_XF", "marker_data" : [ { "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i37", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4" } ], "pinuse" : "OUT;", "pin_name_unsanitized" : "Q2_N", "pin_type" : "OUTPUT", "pin_number" : "23", "node_name" : "U1_E1_XF.23" }, "C145_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_page" : "page17", "block" : "top/xc2_fpga_blk", "page" : "page17", "remapped_page" : null, "phys_path" : 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"pin_name" : "EVENT_N", "net_name" : "DIMM_EVENT_OD_F<3>", "refdes" : "J4_XF", "part_number" : "410-000300-001", "node_name" : "J4_XF.78", "pin_number" : "78", "pin_type" : "INOUT" }, "J2_XF.171" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/xc2_fpga_blk", "phys_page" : "page6" } ], "part_number" : "410-000300-001", "pin_name" : "VSS_72", "net_name" : "GND", "refdes" : "J2_XF", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_72", "pin_number" : "171", "pin_type" : "GROUND", "node_name" : "J2_XF.171" }, "R23_SP_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R23_SP_XF.1", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "page_instance" : "I82", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i82", "sym_num" : 1 } ], "part_number" : "400-000010-033", "pin_name" : "A", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I155_A_SP", "refdes" : "R23_SP_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "C352_XF.1" : { "node_name" : "C352_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "C352_XF", "pin_name" : "A", "net_name" : "GND", "part_number" : "402-000010-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "page_instance" : "I153", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i153", "page" : "page29", "block" : "top/xc2_fpga_blk", "phys_page" : "page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null } ] }, "R29_XF.2" : { "marker_data" : [ { "page_instance" : "I33", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i33", "sym_num" : 1, "phys_page" : "page21", "page" : "page21", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21" } ], "part_number" : "400-000010-090", "refdes" : "R29_XF", "pin_name" : "B", "net_name" : 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], "part_number" : "410-000300-001", "net_name" : "PWR_SDIMM_VDD_XF", "pin_name" : "VDD_19", "refdes" : "J2_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_19", "pin_type" : "POWER", "pin_number" : "61", "node_name" : "J2_XF.61" }, "PM1_SP_XF.P11" : { "marker_data" : [ { "page_instance" : "I11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "sym_num" : 5, "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7" } ], "net_name" : "GND", "refdes" : "PM1_SP_XF", "pin_name" : "GND_74", "part_number" : "462-000309-001", "pin_name_unsanitized" : "GND_74", "pinuse" : "GROUND;", "pin_number" : "P11", "node_name" : "PM1_SP_XF.P11" }, "C2_E1_XF.1" : { "part_number" : "402-000010-001", "pin_name" : "A", "refdes" : "C2_E1_XF", "net_name" : "GND", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "page_instance" : "I20" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C2_E1_XF.1" }, "U6_XF.5" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "GND", "part_number" : "450-000037-001", "net_name" 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"pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "refdes" : "C120_SP_XF", "net_name" : "PWR_NDIMM_VPP_XF", "part_number" : "402-000010-031", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I28", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i28" } ] }, "U1_XF.BU34" : { "pin_type" : "INOUT", "pin_number" : "BU34", "node_name" : "U1_XF.BU34", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "path" : 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"U1_XF.Y26", "pin_type" : "INOUT", "pin_number" : "Y26" }, "U1_CPLD.B6" : { "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7", "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152" } ], "part_number" : "450-000313-001", "net_name" : "NC", "pin_name" : "IO6_PT11B_0", "refdes" : "U1_CPLD", "pinuse" : "BI;", "pin_name_unsanitized" : "IO6_PT11B_0", "pin_number" : "B6", "pin_type" : "INOUT", "node_name" : "U1_CPLD.B6" }, "C6_FL_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "net_name" : "P3R3V", "refdes" : "C6_FL_XF", "part_number" : "402-000010-011", "marker_data" : [ { "ppath" : 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"net_name" : "UNNAMED_3_LTM4675_I40_GPIO1F_SD" }, "U2_XF.C2" : { "node_name" : "U2_XF.C2", "pin_number" : "C2", "pin_type" : "INPUT", "pinuse" : "IN;", "pin_name_unsanitized" : "S_N", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "page_instance" : "I37", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page15", "phys_page" : "page15" } ], "part_number" : "450-000341-001", "pin_name" : "S_N", "net_name" : "UNNAMED_15_MAX4641_I1_NO2_XF", "refdes" : "U2_XF" }, "C9_SP_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C9_SP_XF.2", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : 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"pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "C50_XF", "pin_name" : "B", "net_name" : "PCIE0_TXN<7>_XF", "part_number" : "402-000010-035", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_page" : "page11", "block" : "top/xc2_fpga_blk", "page" : "page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i632", "sym_num" : 1, "page_instance" : "I632", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11" } ] }, "U1_CPLD.R16" : { "marker_data" : [ { "sym_num" : 3, "ppath" : "top/page14_i1/cpld_blk/page4_i211", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "page_instance" : "I211", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "remapped_page" : null, "page" : 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: "INOUT", "pin_number" : "BJ39", "node_name" : "U1_XF.BJ39" }, "U1_XF.BM5" : { "pin_number" : "BM5", "pin_type" : "INOUT", "node_name" : "U1_XF.BM5", "marker_data" : [ { "sym_num" : 37, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I72", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24" } ], "net_name" : "GND", "pin_name" : "GND_922", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_37;", "pin_name_unsanitized" : "GND_922" }, "U1_XF.N7" : { "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_177", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : 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"402-000050-015", "refdes" : "C89_FL_XF", "pin_name" : "B", "net_name" : "GND" }, "R18_E2_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i38", "sym_num" : 1, "page_instance" : "I38", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4" } ], "pin_name" : "A", "refdes" : "R18_E2_XF", "net_name" : "CLKIN_N_E2", "part_number" : "400-000010-010", "node_name" : "R18_E2_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "R11_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-120", "net_name" : "CFG_FLASH_RDWR_FCS_B_0_XF", "pin_name" : "B", "refdes" : "R11_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page18_i49", "sym_num" : 1, "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page18", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "phys_page" : "page18", "page" : "page18", "block" : "top/xc2_fpga_blk" } ], "node_name" : "R11_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U4_FL_XF.22" : { "node_name" : "U4_FL_XF.22", "pin_number" : "22", "pin_type" : "INPUT", "pin_name_unsanitized" : "MARGA", "pinuse" : "IN;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7_i30", "sym_num" : 1, "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page7", "phys_page" : "page7", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page7" } ], "pin_name" : "MARGA", "refdes" : "U4_FL_XF", "net_name" : "UNNAMED_7_LT3071_I30_MARGA_FL", "part_number" : "450-000057-001" }, "R43.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page10_i155", "sym_num" : 1, "page_instance" : "I155", "ppath_without_last_instance" : "top/page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "phys_page" : "page10", "block" : "top", "page" : "page10" } ], "net_name" : "SI5341_LOL_N", "pin_name" : "B", "refdes" : "R43", "part_number" : "400-000014-011", "node_name" : "R43.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "J3_XF.193" : { "node_name" : "J3_XF.193", "pin_type" : "GROUND", "pin_number" : "193", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_34", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page8", "phys_page" : "page8", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180" } ], "part_number" : "410-000300-001", "net_name" : "GND", "pin_name" : "VSS_34", "refdes" : "J3_XF" }, "C237_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C237_XF.1", "pin_name" : "A", "net_name" : "AC_OCL2_PET_P<1>_XF", "refdes" : "C237_XF", "part_number" : "402-000010-035", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null, "page" : "page14", "block" : "top/xc2_fpga_blk", "phys_page" : "page14", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i178", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I178" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "R4_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null, "page" : "page17", "block" : "top/xc2_fpga_blk", "phys_page" : "page17", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I68" } ], "pin_name" : "B", "refdes" : "R4_XF", "net_name" : "UNNAMED_17_RESISTOR_I52_A_XF", "part_number" : "400-000010-010", "node_name" : "R4_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.E48" : { "pin_group" : "ALL_SIGNAL_PINS_26;", "pin_name_unsanitized" : "IO_L9N_T1L_N5_AD12N_37", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I58", "sym_num" : 26, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L9N_T1L_N5_AD12N_37", "net_name" : "NC", "node_name" : "U1_XF.E48", "pin_number" : "E48", "pin_type" : "INOUT" }, "C170_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C170_XF.1", "part_number" : "402-000010-035", "net_name" : "AC_E1S2_PET_N<3>_XF", "pin_name" : "A", "refdes" : "C170_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page13", "phys_page" : "page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I75", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i75" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "U1_XF.BV21" : { "pin_group" : "C0_ACTL_4_4;", "pin_name_unsanitized" : "C0_DDR4_BG1", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "page_instance" : "I2425", "sym_num" : 4, "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "block" : "top/xc2_fpga_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "remapped_page" : null } ], "pin_name" : "C0_DDR4_BG1", "refdes" : "U1_XF", "net_name" : "C0_DDR4_BG<1>_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.BV21", "pin_type" : "INOUT", "pin_number" : "BV21" }, "U5_XF.30" : { "node_name" : "U5_XF.30", "pin_number" : "30", "pin_name_unsanitized" : "NC_7", "pinuse" : "NC;", "refdes" : "U5_XF", "pin_name" : "NC_7", "net_name" : "NC", "part_number" : "450-000345-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i63", "sym_num" : 1, "page_instance" : "I63", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29" } ] }, "D4_CPLD.2" : { "part_number" : "404-000302-001", "net_name" : "UNNAMED_9_LUMEXRGBLED_I92_REDK_CPLD", "pin_name" : "RED_K", "refdes" : "D4_CPLD", "marker_data" : [ { "page_instance" : "I92", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page9", "ppath" : "top/page14_i1/cpld_blk/page9_i92", "sym_num" : 1, "phys_page" : "page9", "block" : "top/cpld_blk", "page" : "page9", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9" } ], "pinuse" : "TRI;", "pin_name_unsanitized" : "RED_K", "pin_number" : "2", "pin_type" : "INOUT", "node_name" : "D4_CPLD.2" }, "U1_XF.BP24" : { "pin_group" : "C0_UNIB_1_4_66;", "pin_name_unsanitized" : "C0_DDR4_DQ44", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_page" : "PAGE3", "page" : "PAGE3", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "sym_num" : 71, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3" } ], "part_number" : "450-000340-001", "pin_name" : "C0_DDR4_DQ44", "net_name" : "C0_DDR4_DQ<44>_XF", "refdes" : "U1_XF", "node_name" : "U1_XF.BP24", "pin_number" : "BP24", "pin_type" : "INOUT" }, "U1_XF.N33" : { "pin_name_unsanitized" : "IO_T1U_N12_72", "pin_group" : "ALL_SIGNAL_PINS_24;", "refdes" : "U1_XF", "pin_name" : "IO_T1U_N12_72", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 24, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I54", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31" } ], "node_name" : "U1_XF.N33", "pin_type" : "INOUT", "pin_number" : "N33" }, "C15.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C15.2", "part_number" : "402-000010-001", "refdes" : "C15", "pin_name" : "B", "net_name" : "FP_JT_VREF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page15", "phys_page" : "page15", "page" : "page15", "block" : "top", "ppath" : "top/page15_i13", "sym_num" : 1, "page_instance" : "I13", "ppath_without_last_instance" : "top/page15" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "U1_CPLD.B1" : { "node_name" : "U1_CPLD.B1", "pin_type" : "INOUT", "pin_number" : "B1", "pin_name_unsanitized" : "IO2_PL2C_5", "pinuse" : "BI;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/cpld_blk", "phys_page" : "page7", "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152" } ], "pin_name" : "IO2_PL2C_5", "refdes" : "U1_CPLD", "net_name" : "NC", "part_number" : "450-000313-001" }, "D1.2" : { "part_number" : "404-000001-008", "pin_name" : "L2C", "refdes" : "D1", "net_name" : "UNNAMED_3_598BICOLORLED_I68_L2C", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top", "ppath" : "top/page3_i68", "sym_num" : 1, "page_instance" : "I68", "ppath_without_last_instance" : "top/page3" } ], "pinuse" : "BI;", "pin_name_unsanitized" : "L2C", "pin_number" : "2", "pin_type" : "INOUT", "node_name" : "D1.2" }, "J4_XF.128" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page10", "phys_page" : "page10" } ], "part_number" : "410-000300-001", "pin_name" : "DQ60", "net_name" : "C3_DDR4_DQ<60>_XF", "refdes" : "J4_XF", "pinuse" : "TRI;", "pin_name_unsanitized" : "DQ60", "pin_number" : "128", "pin_type" : "INOUT", "node_name" : "J4_XF.128" }, "J1_E0_XF.B5" : { "marker_data" : [ { "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3_i101", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3" } ], "part_number" : "410-000317-001", "net_name" : "P12V_MAIN", "pin_name" : "12v_5", "refdes" : "J1_E0_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "\\12v_5\\", "pin_number" : "B5", "node_name" : "J1_E0_XF.B5" }, "U1_XF.AD22" : { "pin_name_unsanitized" : "GND_393", "pin_group" : "ALL_POWER_PINS_34;", "net_name" : "GND", "pin_name" : "GND_393", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I69", "sym_num" : 34, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" 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"refdes" : "U1_XF", "marker_data" : [ { "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425", "sym_num" : 6, "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7" } ] }, "U1_XF.W31" : { "pin_name_unsanitized" : "GND_281", "pin_group" : "ALL_POWER_PINS_34;", "refdes" : "U1_XF", "pin_name" : "GND_281", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I69", "sym_num" : 34, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : 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"A" }, "J2_XF.116" : { "pin_name_unsanitized" : "VSS_20", "pinuse" : "UNSPEC;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/xc2_fpga_blk", "phys_page" : "page6", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180" } ], "pin_name" : "VSS_20", "net_name" : "GND", "refdes" : "J2_XF", "part_number" : "410-000300-001", "node_name" : "J2_XF.116", "pin_type" : "GROUND", "pin_number" : "116" }, "C192_SP_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "GND", "refdes" : "C192_SP_XF", "part_number" : "402-000010-033", "marker_data" : [ { "remapped_page" : null, "phys_path" : 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"IO_L5N_T0U_N9_AD14N_33", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "sym_num" : 22, "page_instance" : "I46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30" } ], "pin_name_unsanitized" : "IO_L5N_T0U_N9_AD14N_33", "pin_group" : "ALL_SIGNAL_PINS_22;", "pin_type" : "INOUT", "pin_number" : "P62", "node_name" : "U1_XF.P62" }, "PM5_SP_XF.M12" : { "pin_number" : "M12", "pin_type" : "POWER", "node_name" : "PM5_SP_XF.M12", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I79", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i79", "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null } ], "part_number" : "462-000308-002", "refdes" : "PM5_SP_XF", "pin_name" : "GND_54", "net_name" : "GND", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_54" }, "U1.60" : { "pin_type" : "POWER", "pin_number" : "60", "node_name" : "U1.60", "marker_data" : [ { "phys_page" : "page10", "block" : "top", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "page_instance" : "I51", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i51", "sym_num" : 1 } ], "part_number" : "450-000308-002", "pin_name" : "VDD_3", "net_name" : "SI5341_VDD", "refdes" : "U1", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_3" }, "J4_XF.243" : { "pin_number" : "243", "pin_type" : "GROUND", "node_name" : "J4_XF.243", "net_name" : "GND", "pin_name" : "VSS_73", "refdes" : "J4_XF", "part_number" : "410-000300-001", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10" } ], "pin_name_unsanitized" : "VSS_73", "pinuse" : "UNSPEC;" }, "U1_XF.A41" : { "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L22N_T3U_N7_DBC_AD0N_37", "net_name" : "NC", "marker_data" : [ { "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "page_instance" : "I58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "sym_num" : 26 } ], "pin_name_unsanitized" : "IO_L22N_T3U_N7_DBC_AD0N_37", "pin_group" : "ALL_SIGNAL_PINS_26;", "pin_number" : "A41", "pin_type" : "INOUT", "node_name" : "U1_XF.A41" }, "C239_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i22", "sym_num" : 1, "page_instance" : "I22", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23" } ], "part_number" : "402-000015-005", "net_name" : "GND", "pin_name" : "B", "refdes" : "C239_XF", "node_name" : "C239_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.BU39" : { "node_name" : "U1_XF.BU39", "pin_number" : "BU39", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_20;", "pin_name_unsanitized" : "IO_L4N_T0U_N7_DBC_AD7N_67", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20, "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30" } ], "part_number" : "450-000340-001", "pin_name" : "IO_L4N_T0U_N7_DBC_AD7N_67", "refdes" : "U1_XF", "net_name" : "NC" }, "J5.5" : { "pin_name" : "3r3v_scl", "refdes" : "J5", "net_name" : "BASE_3R3V_SCL_2", "part_number" : "410-000316-001", "marker_data" : [ { "page_instance" : "I110", "ppath_without_last_instance" : "top/page15", "ppath" : "top/page15_i110", "sym_num" : 1, "phys_page" : "page15", "page" : "page15", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page15" } ], "pin_name_unsanitized" : "\\3r3v_scl\\", "pinuse" : "BI;", "pin_number" : "5", "pin_type" : "INOUT", "node_name" : "J5.5" }, "U1_XF.K32" : { "marker_data" : [ { "page_instance" : "I54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54", "sym_num" : 24, "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : 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"path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30" } ], "pin_name" : "IO_L12P_T1U_N10_GC_26", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_19;", "pin_name_unsanitized" : "IO_L12P_T1U_N10_GC_26" }, "U1_XF.L14" : { "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_153", "marker_data" : [ { "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33 } ], "pin_name" : "GND_153", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.L14", "pin_type" : "INOUT", "pin_number" : "L14" }, "J2_XF.84" : { "part_number" : "410-000300-001", "net_name" : "C1_DDR4_CS_N<0>_XF", "pin_name" : "CS0_N", "refdes" : "J2_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6" } ], "pinuse" : "IN;", "pin_name_unsanitized" : "CS0_N", "pin_number" : "84", "pin_type" : "INPUT", "node_name" : "J2_XF.84" }, "U1_XF.CC40" : { "pin_type" : "INOUT", "pin_number" : "CC40", "node_name" : "U1_XF.CC40", "net_name" : "GND", "pin_name" : "GND_1089", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_path" : 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"net_name" : "SGND_PM4_SP", "refdes" : "PM4_SP_XF", "part_number" : "462-000308-002", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i78", "sym_num" : 3, "page_instance" : "I78", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "pin_name_unsanitized" : "SGND_1", "pinuse" : "POWER;" }, "U1_CPLD.C10" : { "marker_data" : [ { "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152", "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152" } ], "net_name" : "NC", "pin_name" : "IO35_PT23C_JTAGENB_0", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "pin_name_unsanitized" : "IO35_PT23C_JTAGENB_0", "pinuse" : "BI;", "pin_number" : "C10", "pin_type" : "INOUT", "node_name" : "U1_CPLD.C10" }, "U1_XF.AW3" : { "pin_type" : "INOUT", "pin_number" : "AW3", "node_name" : "U1_XF.AW3", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I71", "sym_num" : 36, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71" } ], "refdes" : "U1_XF", "pin_name" : "GND_666", "net_name" : "GND", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_36;", "pin_name_unsanitized" : "GND_666" }, "U1_XF.L29" : { "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_155", "marker_data" : [ { "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "part_number" : "450-000340-001", "pin_name" : "GND_155", "refdes" : "U1_XF", "net_name" : "GND", "node_name" : "U1_XF.L29", "pin_type" : "INOUT", "pin_number" : "L29" }, "C434_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i170", "sym_num" : 1, "page_instance" : "I170", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk" } ], "pin_name" : "A", "refdes" : "C434_XF", "net_name" : "GND", "part_number" : "402-000010-001", "node_name" : "C434_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "PM1_SP_XF.P6" : { "pin_name_unsanitized" : "CLKOUT3", "pinuse" : "OUT;", "pin_name" : "CLKOUT3", "net_name" : "NC", "refdes" : "PM1_SP_XF", "part_number" : "462-000309-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : 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"net_name" : "GND", "part_number" : "450-000340-001", "node_name" : "U1_XF.W12", "pin_number" : "W12", "pin_type" : "INOUT" }, "U1_XF.BY60" : { "node_name" : "U1_XF.BY60", "pin_type" : "INOUT", "pin_number" : "BY60", "pin_name_unsanitized" : "C1_DDR4_DQ27", "pin_group" : "C1_LNIB_1_5_39;", "pin_name" : "C1_DDR4_DQ27", "refdes" : "U1_XF", "net_name" : "C1_DDR4_DQ<27>_XF", "part_number" : "450-000340-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "remapped_page" : null, "page" : "PAGE5", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE5", "sym_num" : 42, "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "page_instance" : "I2425" } ] }, "J2_XF.235" : { "pin_name_unsanitized" : "NC_C2", "pinuse" : "BI;", "net_name" : "NC", "pin_name" : "NC_C2", "refdes" : "J2_XF", "part_number" : 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"node_name" : "R61_SD_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "C9_E3_XF.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3", "page_instance" : "I90", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3_i90" } ], "part_number" : "402-000010-028", "pin_name" : "A", "refdes" : "C9_E3_XF", "net_name" : "GND", "node_name" : "C9_E3_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "C110_XF.2" : { "node_name" : "C110_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-035", "pin_name" : "B", "refdes" : "C110_XF", "net_name" : "E1S1_PET_P<7>_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i84", "sym_num" : 1, "page_instance" : "I84", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12" } ] }, "U1_XF.BB42" : { "pin_name" : "GND_753", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I71", "sym_num" : 36, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : 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: "BY43", "pin_type" : "INOUT", "node_name" : "U1_XF.BY43" }, "C293_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C293_XF.2", "part_number" : "402-000015-007", "pin_name" : "B", "refdes" : "C293_XF", "net_name" : "GND", "marker_data" : [ { "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "page_instance" : "I140", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i140", "sym_num" : 1 } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "R434.1" : { "pin_name" : "A", "net_name" : "UNNAMED_10_RESISTOR_I48_A", "refdes" : "R434", "part_number" : "400-000014-011", "marker_data" : [ { "ppath" : "top/page10_i48", "sym_num" : 1, "page_instance" : "I48", "ppath_without_last_instance" : "top/page10", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R434.1" }, "U1_XF.P42" : { "node_name" : "U1_XF.P42", "pin_type" : "INOUT", "pin_number" : "P42", "pin_group" : "ALL_SIGNAL_PINS_26;", "pin_name_unsanitized" : "IO_L9N_T1L_N5_AD12N_38", "marker_data" : [ { "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "page_instance" : "I58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "sym_num" : 26 } ], "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L9N_T1L_N5_AD12N_38", "refdes" : "U1_XF" }, "U1_CPLD.K15" : { "node_name" : "U1_CPLD.K15", "pin_type" : "INOUT", "pin_number" : "K15", "pin_name_unsanitized" : "LTC2975_CPLD_ENB_A", "pinuse" : "BI;", "pin_group" : "PCTL_POK_3;", "pin_name" : "LTC2975_CPLD_ENB_A", "net_name" : "LTC2975_CPLD_ENB_A", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/cpld_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "page_instance" : "I211", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "ppath" : "top/page14_i1/cpld_blk/page4_i211", "sym_num" : 3 } ] }, "J1_XF.241" : { "pin_name" : "VSS_68", "net_name" : "GND", "refdes" : "J1_XF", "part_number" : "410-000300-001", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4" } ], "pin_name_unsanitized" : "VSS_68", "pinuse" : "UNSPEC;", "pin_number" : "241", "pin_type" : "GROUND", "node_name" : "J1_XF.241" }, "U4_SP_XF.14" : { "pin_name_unsanitized" : "DN6_DP7", "pinuse" : "BI;", "marker_data" : [ { "page" : "page12", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page12", "remapped_page" : null, "ppath_without_last_instance" : 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"remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4" } ], "pin_name_unsanitized" : "GND_DIG", "pinuse" : "GROUND;" }, "J4_XF.263" : { "pin_name_unsanitized" : "VSS_29", "pinuse" : "UNSPEC;", "refdes" : "J4_XF", "pin_name" : "VSS_29", "net_name" : "GND", "part_number" : "410-000300-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10" } ], "node_name" : "J4_XF.263", "pin_type" : "GROUND", "pin_number" : "263" }, "C9_XF.2" : { "node_name" : "C9_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-028", "net_name" : "PWR_SDIMM_VDD_XF", "pin_name" : "B", "refdes" : "C9_XF", "marker_data" : [ { "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I162", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i162" } ] }, "J1_XF.71" : { "node_name" : "J1_XF.71", "pin_number" : "71", "pin_type" : "INPUT", "pinuse" : "IN;", "pin_name_unsanitized" : "A3", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : 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"block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i101", "sym_num" : 1 } ], "part_number" : "410-000317-001", "pin_name" : "GND_14", "refdes" : "J1_E1_XF", "net_name" : "GND", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_14", "pin_number" : "A32", "node_name" : "J1_E1_XF.A32" }, "U1_XF.M36" : { "node_name" : "U1_XF.M36", "pin_number" : "M36", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_25;", "pin_name_unsanitized" : "IO_L7N_T1L_N1_QBC_AD13N_70", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page31", 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: "450-000340-001", "pin_name" : "E1S0_PER_N5", "net_name" : "E1S0_PER_N<5>_XF", "refdes" : "U1_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283", "sym_num" : 9, "page_instance" : "I283", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk" } ] }, "C7_E2_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C7_E2_XF.1", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3", "page_instance" : "I99", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i99", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "phys_page" : "page3", "phys_path" : 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: "VCCAUX_IO_9", "net_name" : "FPGA_VCCAUX_P1R8V", "refdes" : "U1_XF", "pin_group" : "ALL_POWER_PINS_30;", "pin_name_unsanitized" : "VCCAUX_IO_9" }, "PM4_SD_XF.F9" : { "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "page_instance" : "I13", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i13", "sym_num" : 1 } ], "part_number" : "462-000304-001", "pin_name" : "SVIN", "net_name" : "P12V_FUSED_4675_SD", "refdes" : "PM4_SD_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "SVIN", "pin_type" : "POWER", "pin_number" : "F9", "node_name" : "PM4_SD_XF.F9" }, "U1_XF.AD55" : { "pin_number" : "AD55", "pin_type" : "INOUT", "node_name" : "U1_XF.AD55", "marker_data" : [ { "page_instance" : "I53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53", "sym_num" : 23, "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31" } ], "net_name" : "NC", "pin_name" : "IO_L6N_T0U_N11_AD6N_30", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_23;", "pin_name_unsanitized" : "IO_L6N_T0U_N11_AD6N_30" }, "C72_XF.2" : { "node_name" : "C72_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "PWR_VCCINT_XF", "refdes" : "C72_XF", "part_number" : "402-000015-008", "marker_data" : [ { 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35, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70" } ], "pin_name_unsanitized" : "GND_545", "pin_group" : "ALL_POWER_PINS_35;" }, "U1_XF.N4" : { "pin_number" : "N4", "pin_type" : "INOUT", "node_name" : "U1_XF.N4", "marker_data" : [ { "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33, "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "pin_name" : "GND_176", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_176" }, "U1_XF.W11" : { "part_number" : "450-000340-001", "pin_name" : "E1S2_PET_P0", "refdes" : "U1_XF", "net_name" : "AC_E1S2_PET_P<0>_XF", "marker_data" : [ { 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"IO_L3N_T0L_N5_AD15N_20", "pin_group" : "ALL_SIGNAL_PINS_17;", "pin_type" : "INOUT", "pin_number" : "BV46", "node_name" : "U1_XF.BV46" }, "C63_CPLD.2" : { "node_name" : "C63_CPLD.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_page" : "page8", "page" : "page8", "block" : "top/cpld_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page8", "page_instance" : "I7", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page8", "ppath" : "top/page14_i1/cpld_blk/page8_i7", "sym_num" : 1 } ], "refdes" : "C63_CPLD", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000010-001" }, "U1_SP_XF.62" : { "pinuse" : "IN;", "pin_name_unsanitized" : "VSENSEM2", "part_number" : "450-000302-001", "refdes" : "U1_SP_XF", "pin_name" : "VSENSEM2", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I153_A_SP", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "page_instance" : "I168", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i168", "sym_num" : 1 } ], "node_name" : "U1_SP_XF.62", "pin_number" : "62", "pin_type" : "INPUT" }, "U1_XF.BF49" : { "pin_group" : "ALL_POWER_PINS_20;", "pin_name_unsanitized" : "VCCO_24_1", "marker_data" : [ { "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20, "phys_page" : "page30", "page" : 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"pin_type" : "INOUT", "pin_number" : "P41", "node_name" : "U1_XF.P41", "pin_name" : "IO_L9P_T1L_N4_AD12P_38", "net_name" : "NC", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I58", "sym_num" : 26, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58" } ], "pin_name_unsanitized" : "IO_L9P_T1L_N4_AD12P_38", "pin_group" : "ALL_SIGNAL_PINS_26;" }, "R94_XF.1" : { "node_name" : "R94_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R94_XF", "pin_name" : "A", "net_name" : "UNNAMED_17_RESISTOR_I40_A_XF", "part_number" : "400-000010-097", "marker_data" : [ { "page_instance" : "I40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i40", "sym_num" : 1, "phys_page" : "page17", "page" : "page17", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17" } ] }, "U1_XF.BB50" : { "pin_type" : "INOUT", "pin_number" : "BB50", "node_name" : "U1_XF.BB50", "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L12N_T1U_N11_GC_26", "refdes" : "U1_XF", "marker_data" : [ { "sym_num" : 19, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i47", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I47", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30" } ], "pin_name_unsanitized" : "IO_L12N_T1U_N11_GC_26", "pin_group" : "ALL_SIGNAL_PINS_19;" }, "C77_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "PCIE0_TXN<5>_XF", "refdes" : "C77_XF", "part_number" : "402-000010-035", "marker_data" : [ { "page_instance" : "I628", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i628", "sym_num" : 1, "phys_page" : "page11", "block" : "top/xc2_fpga_blk", "page" : "page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11" } ], "node_name" : "C77_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "J1_XF.270" : { "pin_number" : "270", "pin_type" : "GROUND", "node_name" : "J1_XF.270", "part_number" : "410-000300-001", "net_name" : "GND", "pin_name" : "VSS_48", "refdes" : "J1_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_48" }, "C55_SP_XF.2" : { "pin_name" : "B", "refdes" : "C55_SP_XF", "net_name" : "GND", "part_number" : "402-000010-033", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i28", "sym_num" : 1, "page_instance" : "I28", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C55_SP_XF.2" }, "U1_SP_XF.11" : { "node_name" : "U1_SP_XF.11", "pin_type" : "POWER", "pin_number" : "11", "pin_name_unsanitized" : "VDD33_11", "pinuse" : "POWER;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i168", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I168" } ], "net_name" : "P3R3V", "pin_name" : "VDD33_11", "refdes" : "U1_SP_XF", "part_number" : "450-000302-001" }, "U1_CPLD.T10" : { "pin_group" : "PCTL_POK_3;", "pin_name_unsanitized" : "POK_OD_AVTT_RN_LIN", "pinuse" : "BI;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/cpld_blk", "phys_page" : "page4", "sym_num" : 3, "ppath" : "top/page14_i1/cpld_blk/page4_i211", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "page_instance" : "I211" } ], "net_name" : "POK_OD_AVTT_RN_LIN", "pin_name" : "POK_OD_AVTT_RN_LIN", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "node_name" : "U1_CPLD.T10", "pin_type" : "INOUT", "pin_number" : "T10" }, "R244_XF.1" : { "node_name" : "R244_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R244_XF", "pin_name" : "A", "net_name" : "C1_SYS_CLK_N_XF", "part_number" : "400-000010-010", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_page" : "page5", "page" : "page5", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2417", "sym_num" : 1, "page_instance" : "I2417", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5" } ] }, "U7_XF.33" : { "node_name" : "U7_XF.33", "pin_number" : "33", "pin_name_unsanitized" : "EPAD", "pinuse" : "POWER;", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i89", "sym_num" : 1, "page_instance" : "I89", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29" } ], "pin_name" : "EPAD", "net_name" : "GND", "refdes" : "U7_XF", "part_number" : "450-000345-001" }, "U1_CPLD.P5" : { "marker_data" : [ { "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/cpld_blk", "phys_page" : "page7" } ], "refdes" : "U1_CPLD", "pin_name" : "IO5_PB4B_2", "net_name" : "NC", "part_number" : "450-000313-001", "pin_name_unsanitized" : "IO5_PB4B_2", "pinuse" : "BI;", "pin_type" : "INOUT", "pin_number" : "P5", "node_name" : "U1_CPLD.P5" }, "C467_XF.1" : { "marker_data" : [ { "phys_page" : "page20", "page" : "page20", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "page_instance" : "I10", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i10", "sym_num" : 1 } ], "part_number" : "402-000010-028", "refdes" : "C467_XF", "pin_name" : "A", "net_name" : "PWR_AVTT_RLC_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C467_XF.1" }, "U1_XF.BA42" : { "node_name" : "U1_XF.BA42", "pin_number" : "BA42", "pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_31;", "pin_name_unsanitized" : "VCCINT_195", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "sym_num" : 31, "page_instance" : "I186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "VCCINT_195", "net_name" : "PWR_VCCINT_XF" }, "J2_XF.144" : { "pin_type" : "UNSPECIFIED", "pin_number" : "144", "node_name" : "J2_XF.144", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180" } ], "pin_name" : "NC_6", "refdes" : "J2_XF", "net_name" : "NC", "part_number" : "410-000300-001", "pin_name_unsanitized" : "NC_6", "pinuse" : "BI;" }, "R2_P0_XF.1" : { "node_name" : "R2_P0_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i157", "sym_num" : 1, "page_instance" : "I157", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3" } ], "refdes" : "R2_P0_XF", "pin_name" : "A", "net_name" : "UNNAMED_3_OCULINKX4CONN_I86_REFCLKN_P0", "part_number" : "400-000014-011" }, "U1_XF.CC52" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "sym_num" : 5, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_page" : "page5", "block" : "top/xc2_fpga_blk", "page" : "page5" } ], "pin_name" : "C1_DDR4_BG1", "net_name" : "C1_DDR4_BG<1>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "C1_ACTL_5_5;", "pin_name_unsanitized" : "C1_DDR4_BG1", "pin_number" : "CC52", "pin_type" : "INOUT", "node_name" : "U1_XF.CC52" }, "C33_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-035", "pin_name" : "B", "net_name" : "PCIE1_TXP<0>_XF", "refdes" : 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"block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3", "page_instance" : "I101" } ], "node_name" : "J1_E2_XF.A42", "pin_type" : "INPUT", "pin_number" : "A42" }, "U1_CPLD.F11" : { "net_name" : "GND", "refdes" : "U1_CPLD", "pin_name" : "GND_10", "part_number" : "450-000313-001", "marker_data" : [ { "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I151", "sym_num" : 7, "ppath" : "top/page14_i1/cpld_blk/page7_i151" } ], "pin_name_unsanitized" : "GND_10", "pinuse" : "GROUND;", "pin_number" : "F11", "node_name" : "U1_CPLD.F11" }, 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"pin_name" : "B", "net_name" : "OCL2_FPGA_REFCLK_P_XF", "refdes" : "R214_XF" }, "U1_XF.D48" : { "pin_type" : "INOUT", "pin_number" : "D48", "node_name" : "U1_XF.D48", "marker_data" : [ { "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "net_name" : "GND", "pin_name" : "GND_60", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_60" }, "J4_XF.42" : { "part_number" : "410-000300-001", "pin_name" : "VSS_14", "refdes" : "J4_XF", "net_name" : "GND", "marker_data" : [ { "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", 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: "33", "pinuse" : "POWER;", "pin_name_unsanitized" : "EPAD", "part_number" : "450-000345-001", "net_name" : "GND", "refdes" : "U1_E0_XF", "pin_name" : "EPAD", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "page_instance" : "I37" } ] }, "R69.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-006", "net_name" : "P3R3V", "pin_name" : "B", "refdes" : "R69", "marker_data" : [ { "phys_page" : "page3", "block" : "top", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page3", "path" : "@top_lib.top(sch_1):page3", "page_instance" : "I60", "ppath_without_last_instance" : "top/page3", "ppath" : "top/page3_i60", "sym_num" : 1 } ], "node_name" : "R69.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "R98_FL_XF.2" : { "marker_data" : [ { "phys_page" : "page11", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page12", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12", "page_instance" : "I24", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i24", "sym_num" : 1 } ], "net_name" : "P3R3V", "pin_name" : "B", "refdes" : "R98_FL_XF", "part_number" : "400-000010-010", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R98_FL_XF.2" }, "R20_SP_XF.2" : { "net_name" : "VS_VCCINT_N_SP", "pin_name" : "B", "refdes" : "R20_SP_XF", "part_number" : "400-000010-033", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i113", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I113", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R20_SP_XF.2" }, "J3_XF.65" : { "pin_name" : "A12_BC_N", "refdes" : "J3_XF", "net_name" : "C2_DDR4_ADR<12>_XF", "part_number" : "410-000300-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "block" : "top/xc2_fpga_blk", "page" : "page8", "phys_page" : "page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null } ], "pin_name_unsanitized" : "A12_BC_N", "pinuse" : "IN;", "pin_number" : "65", "pin_type" : "INPUT", "node_name" : "J3_XF.65" }, "C19_FL_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C19_FL_XF.1", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i31", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "page_instance" : "I31" } ], "pin_name" : "A", "refdes" : "C19_FL_XF", "net_name" : "UNNAMED_4_BYPASSCAPNPOL_I31_A_FL", "part_number" : "402-000010-005", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "R92_SP_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I135", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i135", "sym_num" : 1, "phys_page" : "page5", "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5" } ], "net_name" : "POK_OD_VCCINT_TRSW_P<1>", "pin_name" : "B", "refdes" : "R92_SP_XF", "part_number" : "400-000014-011", "node_name" : "R92_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C22.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C22.2", "marker_data" : [ { "phys_page" : "page10", "block" : "top", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "page_instance" : "I103", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i103", "sym_num" : 1 } ], "net_name" : "GND", "pin_name" : "B", "refdes" : "C22", "part_number" : "402-000010-026", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "PM2_SP_XF.W1" : { "pin_number" : "W1", "node_name" : "PM2_SP_XF.W1", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "sym_num" : 4, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i456", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I456" } ], "net_name" : "PWR_AVTT_SW_XF", "refdes" : "PM2_SP_XF", "pin_name" : "VOUT3_6", "part_number" : "462-000309-001", "pin_name_unsanitized" : "VOUT3_6", "pinuse" : "POWER;" }, "PM7_SP_XF.M11" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_32", "part_number" : "462-000308-002", "pin_name" : "VIN_32", "refdes" : "PM7_SP_XF", "net_name" : "P12V_4650_BR_SP", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I80", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "phys_page" : "page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null } ], "node_name" : "PM7_SP_XF.M11", "pin_type" : "POWER", "pin_number" : "M11" }, "C62.1" : { "net_name" : "P12V_MAIN", "pin_name" : "A", "refdes" : "C62", "part_number" : "402-000500-005", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page19", "path" : "@top_lib.top(sch_1):page19", "phys_page" : "page19", "block" : "top", "page" : "page19", "ppath" : "top/page19_i66", "sym_num" : 1, "page_instance" : "I66", "ppath_without_last_instance" : "top/page19" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C62.1" }, "U1_XF.AL10" : { "pin_number" : "AL10", "pin_type" : "INOUT", "node_name" : "U1_XF.AL10", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_page" : "page13", "page" : "page13", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i251", "sym_num" : 10, "page_instance" : "I251", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13" } ], "part_number" : "450-000340-001", "pin_name" : "E1S3_PET_N4", "net_name" : "AC_E1S3_PET_N<4>_XF", "refdes" : "U1_XF", "pin_group" : "ALL_SIGNAL_PINS_10;", "pin_name_unsanitized" : "E1S3_PET_N4" }, "U1_XF.BT10" : { "net_name" : "GND", "pin_name" : "GND_981", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "sym_num" : 37, "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "pin_name_unsanitized" : "GND_981", "pin_group" : "ALL_POWER_PINS_37;", "pin_number" : "BT10", "pin_type" : "INOUT", "node_name" : "U1_XF.BT10" }, "C16_XF.2" : { "part_number" : "402-000015-008", "net_name" : "GND", "pin_name" : "B", "refdes" : "C16_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I91", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i91" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C16_XF.2" }, "U1_XF.BB46" : { "pin_type" : "INOUT", "pin_number" : "BB46", "node_name" : "U1_XF.BB46", "pin_name" : "IO_L6N_T0U_N11_AD6N_26", "net_name" : "NC", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "sym_num" : 19, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i47", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I47" } ], "pin_name_unsanitized" : "IO_L6N_T0U_N11_AD6N_26", "pin_group" : "ALL_SIGNAL_PINS_19;" }, "J2_P0_XF.B2" : { "node_name" : "J2_P0_XF.B2", "pin_number" : "B2", "pin_name_unsanitized" : "GND_8", "pinuse" : "GROUND;", "net_name" : "GND", "refdes" : "J2_P0_XF", "pin_name" : "GND_8", "part_number" : "410-000324-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i85", "sym_num" : 1, "page_instance" : "I85", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk" } ] }, "J1_XF.200" : { "pin_number" : "200", "pin_type" : "GROUND", "node_name" : "J1_XF.200", "part_number" : "410-000300-001", "pin_name" : "VSS_52", "net_name" : "GND", "refdes" : "J1_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_52" }, "C54_CPLD.1" : { "node_name" : "C54_CPLD.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "page_instance" : "I28", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "ppath" : "top/page14_i1/cpld_blk/page7_i28", "sym_num" : 1, "phys_page" : "page7", "block" : "top/cpld_blk", "page" : "page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7" } ], "part_number" : "402-000010-001", "refdes" : "C54_CPLD", "pin_name" : "A", "net_name" : "GND" }, "R29.1" : { "node_name" : "R29.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "block" : "top", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page3", "path" : "@top_lib.top(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page3", "page_instance" : "I55", "sym_num" : 1, "ppath" : "top/page3_i55" } ], "refdes" : "R29", "pin_name" : "A", "net_name" : "P3R3V", "part_number" : "400-000010-006" }, "J1_E3_XF.B7" : { "pinuse" : "IN;", "pin_name_unsanitized" : "MFG", "marker_data" : [ { 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"page_instance" : "I37" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "C22_SP_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C22_SP_XF.2", "part_number" : "402-000010-033", "pin_name" : "B", "net_name" : "GND", "refdes" : "C22_SP_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i114", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I114", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page5" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "C4.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "block" : "top", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page10", "page_instance" : "I119", "sym_num" : 1, "ppath" : "top/page10_i119" } ], "part_number" : "402-000010-026", "refdes" : "C4", "pin_name" : "A", "net_name" : "GND", "node_name" : "C4.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "PM4_SD_XF.J5" : { "node_name" : "PM4_SD_XF.J5", "pin_type" : "POWER", "pin_number" : "J5", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD33", "part_number" : "462-000304-001", "pin_name" : "VDD33", "net_name" : "NC", "refdes" : "PM4_SD_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I13", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i13", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null } ] }, "U1_XF.CA9" : { "pin_number" : "CA9", "pin_type" : "INOUT", "node_name" : "U1_XF.CA9", "part_number" : "450-000340-001", "pin_name" : "MGTAVTT_RS_15", "net_name" : "PWR_AVTT_RS_XF", "refdes" : "U1_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page20", "phys_page" : "page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I86", "sym_num" : 29, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i86" } ], "pin_name_unsanitized" : "MGTAVTT_RS_15", "pin_group" : "ALL_POWER_PINS_29;" }, "J2_XF.273" : { "pin_name_unsanitized" : "DQ61", "pinuse" : "TRI;", "net_name" : "C1_DDR4_DQ<61>_XF", "pin_name" : "DQ61", "refdes" : "J2_XF", "part_number" : "410-000300-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6" } ], "node_name" : "J2_XF.273", "pin_type" : "INOUT", "pin_number" : "273" }, "R60.1" : { "pin_name" : "A", "refdes" : "R60", "net_name" : "GND", "part_number" : "400-000010-006", "marker_data" : [ { "phys_page" : "page15", "block" : "top", "page" : "page15", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page15", "path" : "@top_lib.top(sch_1):page15", "page_instance" : "I50", "ppath_without_last_instance" : "top/page15", "ppath" : "top/page15_i50", "sym_num" : 1 } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R60.1" }, "J1_XF.178" : { "pin_type" : "GROUND", "pin_number" : "178", "node_name" : "J1_XF.178", "part_number" : "410-000300-001", "refdes" : "J1_XF", "pin_name" : "VSS_89", "net_name" : "GND", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_89" }, "R217_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R217_XF.2", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i241", "sym_num" : 1, "page_instance" : "I241", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_page" : "page14", "block" : "top/xc2_fpga_blk", "page" : "page14" } ], "part_number" : "400-000010-010", "pin_name" : "B", "refdes" : "R217_XF", "net_name" : "OCL3_FPGA_REFCLK_N_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "J3_XF.71" : { "part_number" : "410-000300-001", "net_name" : "C2_DDR4_ADR<3>_XF", "pin_name" : "A3", "refdes" : "J3_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8" } ], "pinuse" : "IN;", "pin_name_unsanitized" : "A3", "pin_type" : "INPUT", "pin_number" : "71", "node_name" : "J3_XF.71" }, "U5_FL_XF.14" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_14", "part_number" : "450-000057-001", "refdes" : "U5_FL_XF", "pin_name" : "GND_14", "net_name" : "GND", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8", "page_instance" : "I30", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8_i30", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page8", "phys_page" : "page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "remapped_page" : null } ], "node_name" : "U5_FL_XF.14", "pin_number" : "14", "pin_type" : "POWER" }, "J3_XF.241" : { "pin_number" : "241", "pin_type" : "GROUND", "node_name" : "J3_XF.241", "marker_data" : [ { "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1 } ], "part_number" : "410-000300-001", "net_name" : "GND", "pin_name" : "VSS_68", "refdes" : "J3_XF", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_68" }, "R9_E1_XF.2" : { "part_number" : "400-000010-020", "pin_name" : "B", "refdes" : "R9_E1_XF", "net_name" : "UNNAMED_4_PI6CB33401_I37_SDATA_E1", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i33", "sym_num" : 1, "page_instance" : "I33", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R9_E1_XF.2" }, "U1_XF.BC2" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_page" : "page11", "block" : "top/xc2_fpga_blk", "page" : "page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775", "sym_num" : 3, "page_instance" : "I775", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11" } ], "refdes" : "U1_XF", "pin_name" : "PCIE0_RXP7", "net_name" : "PCIE0_RXP<7>_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_3;", "pin_name_unsanitized" : "PCIE0_RXP7", "pin_type" : "INOUT", "pin_number" : "BC2", "node_name" : "U1_XF.BC2" }, "C2_CPLD.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C2_CPLD.1", "part_number" : "402-000010-001", "refdes" : "C2_CPLD", "pin_name" : "A", "net_name" : "GND", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page7_i126", "sym_num" : 1, "page_instance" : "I126", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top/cpld_blk" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "U1_XF.AB36" : { "pin_type" : "INOUT", "pin_number" : "AB36", "node_name" : "U1_XF.AB36", "part_number" : "450-000340-001", "pin_name" : "GND_352", "net_name" : "GND", "refdes" : "U1_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34, "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24" } ], "pin_name_unsanitized" : "GND_352", "pin_group" : "ALL_POWER_PINS_34;" }, "J4_XF.215" : { "pin_type" : "POWER", "pin_number" : "215", "node_name" : "J4_XF.215", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10" } ], "part_number" : "410-000300-001", "refdes" : "J4_XF", "pin_name" : "VDD_26", "net_name" : "PWR_NDIMM_VDD_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_26" }, "U1_XF.T39" : { "pin_number" : "T39", "pin_type" : "INOUT", "node_name" : "U1_XF.T39", "part_number" : "450-000340-001", "pin_name" : "GND_229", "net_name" : "GND", "refdes" : "U1_XF", "marker_data" : [ { "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34 } ], "pin_name_unsanitized" : "GND_229", "pin_group" : "ALL_POWER_PINS_34;" }, "U1_XF.P59" : { "pin_name_unsanitized" : "IO_L7P_T1L_N0_QBC_AD13P_33", "pin_group" : "ALL_SIGNAL_PINS_22;", "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L7P_T1L_N0_QBC_AD13P_33", "refdes" : "U1_XF", "marker_data" : [ { "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "page_instance" : "I46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "sym_num" : 22 } ], "node_name" : "U1_XF.P59", "pin_type" : "INOUT", "pin_number" : "P59" }, "U1_XF.BU61" : { "node_name" : "U1_XF.BU61", "pin_number" : "BU61", "pin_type" : "INOUT", "pin_group" : "C1_UNIB_1_5_39;", "pin_name_unsanitized" : "C1_DDR4_DQ39", "marker_data" : [ { "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "sym_num" : 43, "phys_page" : "PAGE5", "block" : "top/xc2_fpga_blk", "page" : "PAGE5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5" } ], "pin_name" : "C1_DDR4_DQ39", "net_name" : "C1_DDR4_DQ<39>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "U1_XF.G20" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : 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"part_number" : "462-000309-001", "refdes" : "PM1_SP_XF", "net_name" : "GND", "pin_name" : "GND_24", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "sym_num" : 5, "page_instance" : "I11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7" } ], "node_name" : "PM1_SP_XF.B10", "pin_number" : "B10" }, "C52_SD_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I10", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i10", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null } ], "part_number" : "402-000010-033", "pin_name" : "B", "refdes" : "C52_SD_XF", "net_name" : "GND", "node_name" : "C52_SD_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_XF.AJ10" : { "pin_type" : "INOUT", "pin_number" : "AJ10", "node_name" : "U1_XF.AJ10", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_page" : "page13", "block" : "top/xc2_fpga_blk", "page" : "page13", "ppath" : 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"@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4" } ], "pin_name_unsanitized" : "VDD_R", "pinuse" : "POWER;", "pin_number" : "4", "node_name" : "U1_E0_XF.4" }, "C89_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C89_XF.1", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page15", "phys_page" : "page15", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "page_instance" : "I15", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i15" } ], "part_number" : "402-000010-001", "pin_name" : "A", "net_name" : "FPGA_VCCAUX_P1R8V", "refdes" : "C89_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "J4_XF.18" : { "net_name" : "C3_RDIMM_DQS_T<10>_XF", "pin_name" : "DQS10_T_TDQS10_T", "refdes" : "J4_XF", "part_number" : "410-000300-001", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10" } ], "pin_name_unsanitized" : "DQS10_T_TDQS10_T", "pinuse" : "TRI;", "pin_number" : "18", "pin_type" : "INOUT", "node_name" : "J4_XF.18" }, "R158_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R158_XF.2", "marker_data" : [ { "page" : "page11", "block" : "top/xc2_fpga_blk", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I774", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i774" } ], "part_number" : "400-000010-133", "pin_name" : "B", "refdes" : "R158_XF", "net_name" : "UNNAMED_11_RESISTOR_I773_B_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "U1_XF.AH51" : { "node_name" : "U1_XF.AH51", "pin_type" : "INOUT", "pin_number" : "AH51", "pin_name_unsanitized" : "IO_T2U_N12_30", "pin_group" : "ALL_SIGNAL_PINS_23;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_T2U_N12_30", "net_name" : "NC", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53", "sym_num" : 23, "page_instance" : "I53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31" } ] }, "U1_E1_XF.25" : { "pin_number" : "25", "node_name" : "U1_E1_XF.25", "part_number" : "450-000345-001", "refdes" : "U1_E1_XF", "net_name" : "PWR_FPGA_3R3V", "pin_name" : "VDDO_2", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "page_instance" : "I37", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page4" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VDDO_2" }, "PM4_SD_XF.J1" : { "pin_name_unsanitized" : "VOUT1_1", "pinuse" : "POWER;", "pin_name" : "VOUT1_1", "net_name" : "PWR_SDIMM_VDD_XF", "refdes" : "PM4_SD_XF", "part_number" : "462-000304-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i13", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I13" } ], "node_name" : "PM4_SD_XF.J1", "pin_number" : "J1", "pin_type" : "POWER" }, "C44.2" : { "marker_data" : [ { "ppath" : "top/page20_i41", "sym_num" : 1, "page_instance" : "I41", "ppath_without_last_instance" : "top/page20", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page20", "path" : "@top_lib.top(sch_1):page20", "phys_page" : "page20", "block" : "top", "page" : "page20" } ], "part_number" : "402-000010-041", "net_name" : "GND", "pin_name" : "B", "refdes" : "C44", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C44.2" }, "J4_XF.257" : { "pin_name_unsanitized" : "VSS_12", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "block" : "top/xc2_fpga_blk", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null } ], "net_name" : "GND", "pin_name" : "VSS_12", "refdes" : "J4_XF", "part_number" : "410-000300-001", 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"top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "sym_num" : 5, "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7" } ], "net_name" : "GND", "pin_name" : "GND_40", "refdes" : "PM1_SP_XF", "part_number" : "462-000309-001", "node_name" : "PM1_SP_XF.K4", "pin_number" : "K4" }, "C291_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C291_XF.2", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i164", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I164" } ], "pin_name" : "B", "refdes" : "C291_XF", "net_name" : "GND", "part_number" : "402-000015-007", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "C3.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "refdes" : "C3", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000500-005", "marker_data" : [ { "page_instance" : "I101", "ppath_without_last_instance" : "top/page19", "ppath" : "top/page19_i101", "sym_num" : 1, "phys_page" : "page19", "page" : "page19", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19" } ], "node_name" : "C3.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U11.10" : { "part_number" : "450-000333-001", "refdes" : "U11", "pin_name" : "AIN5", "net_name" : "UNNAMED_4_MAX116XXQSOP16_I97_AIN5", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page4_i97", "ppath_without_last_instance" : "top/page4", "page_instance" : "I97", "path" : "@top_lib.top(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top", "phys_page" : "page4" } ], "pinuse" : "IN;", "pin_name_unsanitized" : "AIN5", "pin_type" : "INPUT", "pin_number" : "10", "node_name" : "U11.10" }, "R94.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-010", "pin_name" : "B", "net_name" : "VMON_SDIMM_VTT_LIN", "refdes" : "R94", "marker_data" : [ { "page_instance" : "I64", "ppath_without_last_instance" : "top/page4", "ppath" : "top/page4_i64", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page4" } ], "node_name" : "R94.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.U51" : { "node_name" : "U1_XF.U51", "pin_number" : "U51", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_57;", "pin_name_unsanitized" : "C2_DDR4_DQS_C1", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425", "sym_num" : 57, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_page" : "PAGE7", "block" : "top/xc2_fpga_blk", "page" : "PAGE7" } ], "part_number" : "450-000340-001", "pin_name" : "C2_DDR4_DQS_C1", "net_name" : "C2_RDIMM_DQS_C<9>_XF", "refdes" : "U1_XF" }, "C24_SP_XF.2" : { "part_number" : "402-000010-006", "pin_name" : "B", "net_name" : "GND", "refdes" : "C24_SP_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i150", "sym_num" : 1, "page_instance" : "I150", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C24_SP_XF.2" }, "C180_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C180_XF.1", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page14", "phys_page" : "page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I117", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i117" } ], "net_name" : "AC_OCL0_PET_P<0>_XF", "pin_name" : "A", "refdes" : "C180_XF", "part_number" : "402-000010-035", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "C11_CPLD.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I118", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page7_i118", "block" : "top/cpld_blk", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null } ], "pin_name" : "A", "refdes" : "C11_CPLD", "net_name" : "GND", "part_number" : "402-000010-001", "node_name" : "C11_CPLD.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "C12_E0_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "net_name" : "GND", "refdes" : "C12_E0_XF", "part_number" : "402-000010-028", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3_i95", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3", "page_instance" : "I95", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3" } ], "node_name" : "C12_E0_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_XF.BR6" : { "node_name" : "U1_XF.BR6", "pin_type" : "INOUT", "pin_number" : "BR6", "pin_name_unsanitized" : "OCL1_PER_P3", "pin_group" : "ALL_SIGNAL_PINS_11;", "refdes" : "U1_XF", "pin_name" : "OCL1_PER_P3", "net_name" : "OCL1_PER_P<3>_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I274", "sym_num" : 11, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i274", "block" : "top/xc2_fpga_blk", "page" : "page14", "phys_page" : "page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null } ] }, "PM4_SD_XF.B5" : { "pin_number" : "B5", "pin_type" : "POWER", "node_name" : "PM4_SD_XF.B5", "pin_name" : "GND_11", "net_name" : "GND", "refdes" : "PM4_SD_XF", "part_number" : "462-000304-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I20", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i20" } ], "pin_name_unsanitized" : "GND_11", "pinuse" : "POWER;" }, "NS11_FL_XF.1" : { "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page9", "phys_page" : "page9", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I49" } ], "refdes" : "NS11_FL_XF", "pin_name" : "A", "net_name" : "PWR_VCCAUX_B_FL", "part_number" : "NET_SHORT", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "NS11_FL_XF.1" }, "U1_XF.J59" : { "pin_type" : "INOUT", "pin_number" : "J59", "node_name" : "U1_XF.J59", "part_number" : "450-000340-001", "pin_name" : "C2_SYS_CLK_P", "net_name" : "C2_SYS_CLK_P_XF", "refdes" : "U1_XF", "marker_data" : [ { "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425", "sym_num" : 6 } ], "pin_name_unsanitized" : "C2_SYS_CLK_P", "pin_group" : "ALL_SIGNAL_PINS_6;" }, "R17_E2_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000010-004", "net_name" : "CLKIN_P_E2", "pin_name" : "A", "refdes" : "R17_E2_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i40", "sym_num" : 1, "page_instance" : "I40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4" } ], "node_name" : "R17_E2_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "J2_XF.38" : { "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1, "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6" } ], "part_number" : "410-000300-001", "refdes" : "J2_XF", "pin_name" : "DQ24", "net_name" : "C1_DDR4_DQ<24>_XF", "pinuse" : "TRI;", "pin_name_unsanitized" : "DQ24", "pin_type" : "INOUT", "pin_number" : "38", "node_name" : "J2_XF.38" }, "J1_XF.9" : { "node_name" : "J1_XF.9", "pin_type" : "GROUND", "pin_number" : "9", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_21", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : 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"pin_type" : "OUTPUT", "node_name" : "U1_MP.12", "part_number" : "450-000329-001", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I7_B_MP", "pin_name" : "PH_2", "refdes" : "U1_MP", "marker_data" : [ { "page_instance" : "I2", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page3", "ppath" : "top/page18_i1/mgmt_pwr_block/page3_i2", "sym_num" : 1, "phys_page" : "page3", "block" : "top/mgmt_pwr_block", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page3", "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page3" } ], "pinuse" : "OUT;", "pin_name_unsanitized" : "PH_2" }, "U1_CPLD.H2" : { "pin_group" : "FP_CFG_4;", "pinuse" : "BI;", "pin_name_unsanitized" : "FPGA_CFG_MODE0", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page6", "page_instance" : "I129", "sym_num" : 4, "ppath" : "top/page14_i1/cpld_blk/page6_i129", "page" : "page6", "block" : "top/cpld_blk", "phys_page" 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"C89_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U2_FL_XF.8" : { "node_name" : "U2_FL_XF.8", "pin_type" : "POWER", "pin_number" : "8", "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_8", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6_i30", "sym_num" : 1, "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6" } ], "part_number" : "450-000057-001", "net_name" : "PWR_AVTT_SW_XF", "pin_name" : "VIN_8", "refdes" : "U2_FL_XF" }, "J4_XF.287" : { "pin_number" : "287", "pin_type" : "POWER", "node_name" : "J4_XF.287", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page10", "phys_page" : "page10" } ], "net_name" : "PWR_NDIMM_VPP_XF", "pin_name" : "VPP_4", "refdes" : "J4_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VPP_4", "pinuse" : "POWER;" }, "C192_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C192_XF.1", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i177", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I177" } ], "part_number" : "402-000010-028", "net_name" : "GND", "pin_name" : "A", "refdes" : "C192_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "U1_XF.BK12" : { "pin_type" : "INOUT", "pin_number" : "BK12", "node_name" : "U1_XF.BK12", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i57", "sym_num" : 13, "page_instance" : "I57", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31" } ], "net_name" : "NC", "pin_name" : "MGTREFCLK1N_222", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_13;", "pin_name_unsanitized" : "MGTREFCLK1N_222" }, "PM1_SP_XF.H5" : { "marker_data" : [ { "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7" } ], "part_number" : "462-000309-001", "refdes" : "PM1_SP_XF", "pin_name" : "GND_43", "net_name" : "GND", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_43", "pin_number" : "H5", "node_name" : "PM1_SP_XF.H5" }, "R100_FL_XF.1" : { "node_name" : "R100_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000010-010", "pin_name" : "A", "net_name" : "GND", "refdes" : "R100_FL_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i17", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11", "page_instance" : "I17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page12", "phys_page" : "page11" } ] }, "U1_XF.M17" : { "node_name" : "U1_XF.M17", "pin_number" : "M17", "pin_type" : "INOUT", "pin_name_unsanitized" : "VCCO_98_1", "pin_group" : "ALL_POWER_PINS_16;", "net_name" : "PWR_FPGA_3R3V", "pin_name" : "VCCO_98_1", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i68", "sym_num" : 16, "phys_page" : "page21", "block" : "top/xc2_fpga_blk", "page" : "page21", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21" } ] }, "U1_XF.BG46" : { "pin_group" : "ALL_SIGNAL_PINS_20;", "pin_name_unsanitized" : "IO_L1N_T0L_N1_DBC_24", "marker_data" : [ { "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20, "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30" } ], "part_number" : "450-000340-001", "pin_name" : "IO_L1N_T0L_N1_DBC_24", "refdes" : "U1_XF", "net_name" : "NC", "node_name" : "U1_XF.BG46", "pin_number" : "BG46", "pin_type" : "INOUT" }, "U1_XF.BR14" : { "pin_type" : "INOUT", "pin_number" : "BR14", "node_name" : "U1_XF.BR14", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "GND_968", "net_name" : "GND", "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "sym_num" : 37 } ], "pin_name_unsanitized" : "GND_968", "pin_group" : "ALL_POWER_PINS_37;" }, "C396_XF.2" : { "marker_data" : [ { "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I155", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i155" } ], "part_number" : "402-000010-039", "pin_name" : "B", "refdes" : "C396_XF", "net_name" : "PWR_SDIMM_VDD_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C396_XF.2" }, "U1_E2_XF.31" : { "node_name" : "U1_E2_XF.31", "pin_type" : "INPUT", "pin_number" : "31", "pin_name_unsanitized" : "PD_F", "pinuse" : "IN;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i37", "sym_num" : 1, "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4" } ], "pin_name" : "PD_F", "net_name" : "UNNAMED_4_PI6CB33401_I37_PDF_E2", "refdes" : "U1_E2_XF", "part_number" : "450-000345-001" }, "U1_XF.H15" : { "pin_name" : "VCCO_77_2", "refdes" : "U1_XF", "net_name" : "PWR_NDIMM_VDD_XF", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 28, "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i62", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "page_instance" : "I62", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page22", "phys_page" : "page22" } ], "pin_name_unsanitized" : "VCCO_77_2", "pin_group" : "ALL_POWER_PINS_28;", "pin_type" : "INOUT", "pin_number" : "H15", "node_name" : "U1_XF.H15" }, "U1_CPLD.T15" : { "node_name" : "U1_CPLD.T15", "pin_number" : "T15", "pin_type" : "INOUT", "pin_group" : "ALRT_1;", "pinuse" : "BI;", "pin_name_unsanitized" : "POK_OD_LTC2975", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page3_i447", "sym_num" : 1, "page_instance" : "I447", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/cpld_blk", "page" : "page3" } ], "part_number" : "450-000313-001", "net_name" : "POK_OD_LTC2975", "pin_name" : "POK_OD_LTC2975", "refdes" : "U1_CPLD" }, "U1_XF.BJ61" : { "part_number" : "450-000340-001", "pin_name" : "IO_L5P_T0U_N8_AD14P_25", "net_name" : "NC", "refdes" : "U1_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "sym_num" : 19, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i47", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I47" } ], "pin_name_unsanitized" : "IO_L5P_T0U_N8_AD14P_25", "pin_group" : "ALL_SIGNAL_PINS_19;", "pin_type" : "INOUT", "pin_number" : "BJ61", "node_name" : "U1_XF.BJ61" }, "Q13.4" : { "node_name" : "Q13.4", "pin_number" : "4", "pin_type" : "INPUT", "pin_name_unsanitized" : "G", "pinuse" : "IN;", "refdes" : "Q13", "pin_name" : "G", "net_name" : "UNNAMED_7_NMOSFETVMT3_I2_D", "part_number" : "405-000003-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top", "ppath" : "top/page7_i1", "sym_num" : 1, "page_instance" : "I1", "ppath_without_last_instance" : "top/page7" } ] }, "C80.1" : { "marker_data" : [ { "page_instance" : "I86", "ppath_without_last_instance" : "top/page19", "ppath" : "top/page19_i86", "sym_num" : 1, "phys_page" : "page19", "page" : "page19", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19" } ], "part_number" : "402-000500-005", "net_name" : "P12V_MAIN", "pin_name" : "A", "refdes" : "C80", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C80.1" }, "J4_XF.96" : { "pin_name_unsanitized" : "VSS_65", "pinuse" : "UNSPEC;", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_page" : "page10", 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"pinuse" : "TRI;", "pin_name" : "D1", "net_name" : "PWR_FPGA_3R3V", "refdes" : "Q13", "part_number" : "405-000003-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page7", "path" : "@top_lib.top(sch_1):page7", "remapped_page" : null, "block" : "top", "page" : "page7", "phys_page" : "page7", "sym_num" : 1, "ppath" : "top/page7_i1", "ppath_without_last_instance" : "top/page7", "page_instance" : "I1" } ] }, "C370_XF.1" : { "node_name" : "C370_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-035", "pin_name" : "A", "refdes" : "C370_XF", "net_name" : "AC_OCL0_FPGA_REFCLK_N_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page29", "phys_page" : "page29", "sym_num" : 1, "ppath" : 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"pin_name_unsanitized" : "VSS_34", "pinuse" : "UNSPEC;", "pin_type" : "GROUND", "pin_number" : "193", "node_name" : "J1_XF.193" }, "U1_CPLD.B12" : { "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "phys_page" : "page5", "page" : "page5", "block" : "top/cpld_blk", "ppath" : "top/page14_i1/cpld_blk/page5_i61", "sym_num" : 2, "page_instance" : "I61", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page5" } ], "net_name" : "HOST_3R3V_SDA", "pin_name" : "HOST_3R3V_SDA", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "pin_name_unsanitized" : "HOST_3R3V_SDA", "pinuse" : "BI;", "pin_number" : "B12", "pin_type" : "INOUT", "node_name" : "U1_CPLD.B12" }, "U1_XF.G21" : { "pin_number" : "G21", "pin_type" : "INOUT", "node_name" : "U1_XF.G21", "marker_data" : [ { "remapped_page" : null, "path" : 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"pin_name_unsanitized" : "C2_DDR4_ALERT_N", "pin_group" : "ALL_SIGNAL_PINS_6;" }, "R9.1" : { "node_name" : "R9.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "page_instance" : "I3", "ppath_without_last_instance" : "top/page12", "ppath" : "top/page12_i3", "sym_num" : 1, "phys_page" : "page12", "block" : "top", "page" : "page12", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page12", "path" : "@top_lib.top(sch_1):page12" } ], "part_number" : "400-000010-046", "pin_name" : "A", "refdes" : "R9", "net_name" : "PSU_1R8V_SCL" }, "R91_FL_XF.2" : { "part_number" : "400-000014-011", "pin_name" : "B", "refdes" : "R91_FL_XF", "net_name" : "IMON_AVCC_LIN_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12", "phys_path" : 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"marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i175", "sym_num" : 1, "page_instance" : "I175", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R40_SP_XF.2" }, "U1_XF.F2" : { "pin_name_unsanitized" : "GND_77", "pin_group" : "ALL_POWER_PINS_33;", "part_number" : "450-000340-001", "pin_name" : "GND_77", "refdes" : "U1_XF", "net_name" : "GND", "marker_data" : [ { "page_instance" : "I68", "ppath_without_last_instance" : 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"node_name" : "PM4_SD_XF.B1" }, "U1_XF.BA48" : { "node_name" : "U1_XF.BA48", "pin_number" : "BA48", "pin_type" : "INOUT", "pin_name_unsanitized" : "IO_L5N_T0U_N9_AD14N_26", "pin_group" : "ALL_SIGNAL_PINS_19;", "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L5N_T0U_N9_AD14N_26", "refdes" : "U1_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I47", "sym_num" : 19, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i47" } ] }, "PM1_SP_XF.W8" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I11", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null } ], "net_name" : "GND", "pin_name" : "GND_90", "refdes" : "PM1_SP_XF", "part_number" : "462-000309-001", "pin_name_unsanitized" : "GND_90", "pinuse" : "GROUND;", "pin_number" : "W8", "node_name" : "PM1_SP_XF.W8" }, "C35.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C35.2", "marker_data" : [ { "phys_page" : "page7", "page" : "page7", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page7", "page_instance" : "I17", "ppath_without_last_instance" : "top/page7", "ppath" : "top/page7_i17", "sym_num" : 1 } ], "part_number" : "402-000010-018", "refdes" : "C35", "pin_name" : "B", "net_name" : "GND", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "R227_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "refdes" : "R227_XF", "net_name" : "OCL3_FPGA_REFCLK_P_XF", "part_number" : "400-000010-010", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I234", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i234", "block" : "top/xc2_fpga_blk", "page" : "page14", "phys_page" : "page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null } ], "node_name" : "R227_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "R278_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R278_XF.1", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i149", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "page_instance" : "I149", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page29", "phys_page" : "page29" } ], "part_number" : "400-000010-010", "net_name" : "PWR_FPGA_3R3V", "pin_name" : "A", "refdes" : "R278_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "PM1_SP_XF.J10" : { "pin_name_unsanitized" : "VOSNS1_P", "pinuse" : "IN;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I37", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i37", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null } ], "net_name" : "PWR_NDIMM_VPP_XF", "pin_name" : "VOSNS1_P", "refdes" : "PM1_SP_XF", "part_number" : "462-000309-001", "node_name" : "PM1_SP_XF.J10", "pin_type" : "INPUT", "pin_number" : "J10" }, "U6_FL_XF.4" : { "node_name" : "U6_FL_XF.4", "pin_number" : "4", "pin_type" : "POWER", "pin_name_unsanitized" : "GND_4", "pinuse" : "POWER;", "marker_data" : [ { "page" : "page4", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "page_instance" : "I30", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i30" } ], "pin_name" : "GND_4", "refdes" : "U6_FL_XF", "net_name" : "GND", "part_number" : "450-000057-001" }, "U1_XF.J23" : { "node_name" : "U1_XF.J23", "pin_number" : "J23", "pin_type" : "INOUT", "pin_name_unsanitized" : "GND_126", "pin_group" : "ALL_POWER_PINS_33;", "pin_name" : "GND_126", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33, "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24" } ] }, "U1_XF.AJ51" : { "node_name" : "U1_XF.AJ51", "pin_type" : "INOUT", "pin_number" : "AJ51", "pin_name_unsanitized" : "IO_L9P_T1L_N4_AD12P_29", "pin_group" : "ALL_SIGNAL_PINS_24;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L9P_T1L_N4_AD12P_29", "net_name" : "NC", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54", "sym_num" : 24, "page_instance" : "I54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31" } ] }, "FB9.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "401-000001-002", "net_name" : "UNNAMED_20_FERRITEBEAD_I72_B", "pin_name" : "B", "refdes" : "FB9", "marker_data" : [ { "ppath" : "top/page20_i72", "sym_num" : 1, "page_instance" : "I72", "ppath_without_last_instance" : "top/page20", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page20", "phys_page" : "page20", "page" : "page20", "block" : "top" } ], "node_name" : "FB9.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C27_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I647", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i647", "page" : "page11", "block" : "top/xc2_fpga_blk", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null } ], "pin_name" : "A", "refdes" : "C27_XF", "net_name" : "AC_PCIE1_TXP<6>_XF", "part_number" : "402-000010-035", "node_name" : "C27_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "C37_SD_XF.2" : { "node_name" : "C37_SD_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-027", "pin_name" : "B", "refdes" : "C37_SD_XF", "net_name" : "GND", "marker_data" : [ { "page_instance" : "I9", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4_i9", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4" } ] }, "R31_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-090", "refdes" : "R31_XF", "pin_name" : "B", "net_name" : "UNNAMED_21_RESISTOR_I40_B_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "remapped_page" : null, "page" : "page21", "block" : "top/xc2_fpga_blk", "phys_page" : "page21", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "page_instance" : "I40" } ], "node_name" : "R31_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "PM1_SP_XF.P1" : { "marker_data" : [ { "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7" } ], "refdes" : "PM1_SP_XF", "net_name" : "GND", "pin_name" : "GND_56", "part_number" : "462-000309-001", "pin_name_unsanitized" : "GND_56", "pinuse" : "GROUND;", "pin_number" : "P1", "node_name" : "PM1_SP_XF.P1" }, "U1_XF.BN57" : { "pin_number" : "BN57", "pin_type" : "INOUT", "node_name" : "U1_XF.BN57", "marker_data" : [ { "phys_page" : "PAGE5", "block" : "top/xc2_fpga_blk", "page" : "PAGE5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "sym_num" : 45 } ], "refdes" : "U1_XF", "pin_name" : "C1_DDR4_DQS_C12", "net_name" : "C1_RDIMM_DQS_C<6>_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_39;", "pin_name_unsanitized" : "C1_DDR4_DQS_C12" }, "U1_XF.BR49" : { "pin_number" : "BR49", "pin_type" : "INOUT", "node_name" : "U1_XF.BR49", "pin_name" : "VREF_22", "net_name" : "UNNAMED_21_RESISTOR_I32_B_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I67", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i67", "sym_num" : 27, "phys_page" : "page21", "block" : "top/xc2_fpga_blk", "page" : "page21", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21" } ], "pin_name_unsanitized" : "VREF_22", "pin_group" : "ALL_POWER_PINS_27;" }, "R105_SP_XF.1" : { "part_number" : "400-000014-011", "net_name" : "PM1_SP_AGND_SP", "pin_name" : "A", "refdes" : "R105_SP_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i65", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I65" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R105_SP_XF.1" }, "U1_XF.C26" : { "pin_group" : "ALL_SIGNAL_PINS_48;", "pin_name_unsanitized" : "C3_DDR4_DQS_C8", "marker_data" : [ { "sym_num" : 52, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2425", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "remapped_page" : null, "page" : "PAGE9", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE9" } ], "refdes" : "U1_XF", "pin_name" : "C3_DDR4_DQS_C8", "net_name" : "C3_RDIMM_DQS_C<4>_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.C26", "pin_number" : "C26", "pin_type" : "INOUT" }, "U1_XF.AU10" : { "pin_number" : "AU10", "pin_type" : "INOUT", "node_name" : "U1_XF.AU10", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I775", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775", "block" : "top/xc2_fpga_blk", "page" : "page11", "phys_page" : "page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : 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"net_name" : "UNNAMED_7_LT3071_I30_PWRGD_FL", "pin_name" : "PWRGD", "refdes" : "U4_FL_XF", "pinuse" : "OUT;", "pin_name_unsanitized" : "PWRGD" }, "U1_XF.AN14" : { "marker_data" : [ { "sym_num" : 10, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i251", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I251", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "page" : "page13", "block" : "top/xc2_fpga_blk", "phys_page" : "page13" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "E1S3_REFCLK_N1", "net_name" : "E1S3_FPGA_REFCLK_N<1>_XF", "pin_group" : "ALL_SIGNAL_PINS_10;", "pin_name_unsanitized" : "E1S3_REFCLK_N1", "pin_number" : "AN14", "pin_type" : "INOUT", "node_name" : "U1_XF.AN14" }, "U1_XF.R25" : { "node_name" : "U1_XF.R25", "pin_type" : "INOUT", "pin_number" : "R25", "pin_group" : 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"PM5_SP_XF.J8" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_43", "marker_data" : [ { "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I79", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5", "phys_page" : "page5" } ], "part_number" : "462-000308-002", "net_name" : "GND", "pin_name" : "GND_43", "refdes" : "PM5_SP_XF", "node_name" : "PM5_SP_XF.J8", "pin_number" : "J8", "pin_type" : "POWER" }, "J4_XF.116" : { "node_name" : "J4_XF.116", "pin_number" : "116", "pin_type" : "GROUND", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_20", "part_number" : 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"page30", "block" : "top/xc2_fpga_blk", "page" : "page30" } ], "net_name" : "NC", "pin_name" : "IO_L3P_T0L_N4_AD15P_26", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_19;", "pin_name_unsanitized" : "IO_L3P_T0L_N4_AD15P_26" }, "U1_XF.AK13" : { "pin_name_unsanitized" : "E1S3_PET_P5", "pin_group" : "ALL_SIGNAL_PINS_10;", "part_number" : "450-000340-001", "pin_name" : "E1S3_PET_P5", "net_name" : "AC_E1S3_PET_P<5>_XF", "refdes" : "U1_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I251", "sym_num" : 10, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i251", "page" : "page13", "block" : "top/xc2_fpga_blk", "phys_page" : "page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null } ], "node_name" : "U1_XF.AK13", "pin_number" : "AK13", "pin_type" : "INOUT" }, "U1_XF.BL35" : { "part_number" : "450-000340-001", "pin_name" : "IO_L18P_T2U_N10_AD2P_67", "net_name" : "NC", "refdes" : "U1_XF", "marker_data" : [ { "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20, "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30" } ], "pin_name_unsanitized" : "IO_L18P_T2U_N10_AD2P_67", "pin_group" : "ALL_SIGNAL_PINS_20;", "pin_type" : "INOUT", "pin_number" : "BL35", "node_name" : "U1_XF.BL35" }, "PM4_ND_XF.G8" : { "pin_type" : "POWER", "pin_number" : "G8", "node_name" : "PM4_ND_XF.G8", "part_number" : "462-000304-001", "pin_name" : "GND_27", "net_name" : "GND", "refdes" : "PM4_ND_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I20", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i20", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_27" }, "J1_XF.40" : { "pin_name_unsanitized" : "DQS12_T_TDQS12_T", "pinuse" : "TRI;", "net_name" : "C0_RDIMM_DQS_T<12>_XF", "pin_name" : "DQS12_T_TDQS12_T", "refdes" : "J1_XF", "part_number" : "410-000300-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180" } ], "node_name" : "J1_XF.40", "pin_number" : "40", "pin_type" : "INOUT" }, "U1_XF.U27" : { "pin_number" : "U27", "pin_type" : "INOUT", "node_name" : "U1_XF.U27", "marker_data" : [ { "sym_num" : 34, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I69", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24" } ], "pin_name" : "GND_238", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_238" }, "PM7_SP_XF.K3" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_8", "part_number" : "462-000308-002", "net_name" : "P12V_4650_BR_SP", "pin_name" : "VIN_8", "refdes" : "PM7_SP_XF", "marker_data" : [ { "phys_page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80", "sym_num" : 1 } ], "node_name" : "PM7_SP_XF.K3", "pin_number" : "K3", "pin_type" : "POWER" }, "C320_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C320_XF.2", "marker_data" : [ { "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "page_instance" : "I131", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i131", "sym_num" : 1 } ], "refdes" : "C320_XF", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000015-006", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "PM1_SP_XF.N2" : { "node_name" : "PM1_SP_XF.N2", "pin_number" : "N2", "pin_name_unsanitized" : "GND_57", "pinuse" : "GROUND;", "marker_data" : [ { "phys_page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "page_instance" : "I11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "sym_num" : 5 } ], "net_name" : "GND", "refdes" : "PM1_SP_XF", "pin_name" : "GND_57", "part_number" : "462-000309-001" }, "J1_XF.8" : { "pin_number" : "8", "pin_type" : "INOUT", "node_name" : "J1_XF.8", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4" } ], "part_number" : "410-000300-001", "pin_name" : "DQS9_C_TDQS9_C", "net_name" : "C0_RDIMM_DQS_C<9>_XF", "refdes" : "J1_XF", "pinuse" : "TRI;", "pin_name_unsanitized" : "DQS9_C_TDQS9_C" }, "C450_XF.2" : { "node_name" : "C450_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I162", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i162" } ], "part_number" : "402-000010-028", "pin_name" : "B", "refdes" : "C450_XF", "net_name" : "PWR_NDIMM_VDD_XF" }, "U1_SP_XF.34" : { "node_name" : "U1_SP_XF.34", "pin_type" : "INOUT", "pin_number" : "34", "pin_name_unsanitized" : "TSENSE3", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I168", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i168", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3" } ], "pin_name" : "TSENSE3", "net_name" : "TS_LT4650_TR_SP", "refdes" : "U1_SP_XF", "part_number" : "450-000302-001" }, "C47_FL_XF.2" : { "marker_data" : [ { "phys_page" : "page5", "page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "page_instance" : "I34", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i34", "sym_num" : 1 } ], "part_number" : "402-000010-001", "net_name" : "GND", "pin_name" : "B", "refdes" : "C47_FL_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C47_FL_XF.2" }, "U1_XF.BG42" : { "pin_number" : "BG42", "pin_type" : "INOUT", "node_name" : "U1_XF.BG42", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I72", "sym_num" : 37, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "part_number" : "450-000340-001", "pin_name" : "GND_858", "net_name" : "GND", "refdes" : "U1_XF", "pin_group" : "ALL_POWER_PINS_37;", "pin_name_unsanitized" : "GND_858" }, "U5_FL_XF.7" : { "node_name" : "U5_FL_XF.7", "pin_type" : "POWER", "pin_number" : "7", "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_7", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8", "page_instance" : "I30", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8_i30", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page8", "phys_page" : "page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "remapped_page" : null } ], "part_number" : "450-000057-001", "pin_name" : "VIN_7", "refdes" : "U5_FL_XF", "net_name" : "PWR_AVTT_SW_XF" }, "R284_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R284_XF.1", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "page_instance" : "I148", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i148", "page" : "page29", "block" : "top/xc2_fpga_blk", "phys_page" : "page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null } ], "net_name" : "OCL_REF_CLK_N<1>", "pin_name" : "A", "refdes" : "R284_XF", "part_number" : "400-000010-010", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "J1_O1_XF.A2" : { "pin_number" : "A2", "node_name" : "J1_O1_XF.A2", "part_number" : "410-000324-001", "refdes" : "J1_O1_XF", "pin_name" : "GND_1", "net_name" : "GND", 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"P12V_4650_BL_SP", "refdes" : "PM3_SP_XF", "node_name" : "PM3_SP_XF.M3", "pin_number" : "M3", "pin_type" : "POWER" }, "C35_FL_XF.2" : { "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page6", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6_i32", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6", "page_instance" : "I32" } ], "part_number" : "402-000050-015", "pin_name" : "B", "refdes" : "C35_FL_XF", "net_name" : "GND", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C35_FL_XF.2" }, "J1_E0_XF.A2" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_2", "part_number" : "410-000317-001", "net_name" : "GND", "refdes" : "J1_E0_XF", "pin_name" : "GND_2", "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3_i101", "sym_num" : 1 } ], "node_name" : "J1_E0_XF.A2", "pin_number" : "A2" }, "C48_SP_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i148", "sym_num" : 1, "page_instance" : "I148", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5" } ], "refdes" : "C48_SP_XF", "pin_name" : "B", "net_name" : "SGND_PM5_SP", "part_number" : "402-000202-001", "node_name" : "C48_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "J4_XF.220" : { "part_number" : "410-000300-001", "pin_name" : "VDD_4", "net_name" : "PWR_NDIMM_VDD_XF", "refdes" : "J4_XF", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "phys_page" : "page10", "block" : "top/xc2_fpga_blk", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_4", "pin_type" : "POWER", "pin_number" : "220", "node_name" : "J4_XF.220" }, "C56_XF.2" : { "marker_data" : [ { "phys_page" : "page22", "page" : "page22", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "page_instance" : "I6", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i6", "sym_num" : 1 } ], "refdes" : "C56_XF", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000015-008", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C56_XF.2" }, "U1_XF.K2" : { "node_name" : "U1_XF.K2", "pin_type" : "INOUT", "pin_number" : "K2", "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_133", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I68", "sym_num" : 33, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_133", "refdes" : "U1_XF" }, "C110_SP_XF.2" : { "node_name" : "C110_SP_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7", "path" : 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"phys_page" : "page23" } ], "node_name" : "U1_XF.V29", "pin_type" : "INOUT", "pin_number" : "V29" }, "U1_XF.BR24" : { "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_T0U_N12_VRP_62", "net_name" : "UNNAMED_22_RESISTOR_I41_B_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "remapped_page" : null, "page" : "page22", "block" : "top/xc2_fpga_blk", "phys_page" : "page22", "sym_num" : 28, "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i62", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "page_instance" : "I62" } ], "pin_name_unsanitized" : "IO_T0U_N12_VRP_62", "pin_group" : "ALL_SIGNAL_PINS_28;", "pin_type" : "INOUT", "pin_number" : "BR24", "node_name" : "U1_XF.BR24" }, "C396_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "page_instance" : "I155", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i155", "sym_num" : 1 } ], "pin_name" : "A", "net_name" : "GND", "refdes" : "C396_XF", "part_number" : "402-000010-039", "node_name" : "C396_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "J2_XF.263" : { "node_name" : "J2_XF.263", "pin_type" : "GROUND", "pin_number" : "263", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_29", "part_number" : "410-000300-001", "net_name" : "GND", "pin_name" : "VSS_29", "refdes" : "J2_XF", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1, "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6" } ] }, "SI5335_TP_P.1" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "\\1\\", "part_number" : "TP_020_VIA", "refdes" : "SI5335_TP_P", "pin_name" : "1", "net_name" : "SI5334_TP_CLK_P<3>", "marker_data" : [ { "phys_page" : "page10", "page" : "page10", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "page_instance" : "I160", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i160", "sym_num" : 1 } ], "node_name" : "SI5335_TP_P.1", "pin_number" : "1", "pin_type" : "POWER" }, "J1_XF.168" : { "pin_type" : "INOUT", "pin_number" : "168", "node_name" : "J1_XF.168", "marker_data" : [ { "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4", "path" : 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"I54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31" } ], "pin_name_unsanitized" : "IO_L6P_T0U_N10_AD6P_72", "pin_group" : "ALL_SIGNAL_PINS_24;", "pin_number" : "R30", "pin_type" : "INOUT", "node_name" : "U1_XF.R30" }, "U1_XF.Y33" : { "pin_name_unsanitized" : "VCCINT_34", "pin_group" : "ALL_POWER_PINS_31;", "part_number" : "450-000340-001", "pin_name" : "VCCINT_34", "net_name" : "PWR_VCCINT_XF", "refdes" : "U1_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23", "sym_num" : 31, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I186" } ], "node_name" : "U1_XF.Y33", "pin_type" : "INOUT", "pin_number" : "Y33" }, "PM4_SD_XF.F4" : { "pin_number" : "F4", "pin_type" : "INPUT", "node_name" : "PM4_SD_XF.F4", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I40", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i40", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null } ], "part_number" : "462-000304-001", "pin_name" : "RUN1", "refdes" : "PM4_SD_XF", "net_name" : "UNNAMED_3_LTM4675_I40_RUN0_SD", "pinuse" : "IN;", "pin_name_unsanitized" : "RUN1" }, "U1_CPLD.G6" : { "node_name" : "U1_CPLD.G6", "pin_number" : "G6", "pin_type" : "INOUT", "pinuse" : "BI;", "pin_name_unsanitized" : "SI5341_FINC", "pin_group" : "SI5341_1;", "part_number" : "450-000313-001", "refdes" : "U1_CPLD", "pin_name" : "SI5341_FINC", "net_name" : "SI5341_FINC", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page3", "page_instance" : "I447", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page3_i447", "block" : "top/cpld_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "remapped_page" : null } ] }, "M3.MTG2" : { "pin_name_unsanitized" : "MTG2", "pinuse" : "NC;", "pin_name" : "MTG2", "refdes" : "M3", "net_name" : "GND", "part_number" : "HOLE_RING", "marker_data" : [ { "page" : "page1", "block" : "top", "phys_page" : "page1", "path" : "@top_lib.top(sch_1):page1", "phys_path" : "@top_lib.top(sch_1):page1", "remapped_page" : null, "ppath_without_last_instance" : "top/page1", "page_instance" : "I59", "sym_num" : 1, "ppath" : "top/page1_i59" } ], "node_name" : "M3.MTG2", "pin_number" : "MTG2" }, "C15_SP_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "C15_SP_XF", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000010-006", "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "page_instance" : "I154", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i154", "sym_num" : 1 } ], "node_name" : "C15_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U5_SP_XF.11" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page8", "phys_page" : "page8", "phys_path" : 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"pin_name" : "C0_DDR4_DQ34", "net_name" : "C0_DDR4_DQ<34>_XF", "refdes" : "U1_XF", "node_name" : "U1_XF.BK22", "pin_type" : "INOUT", "pin_number" : "BK22" }, "R135_SP_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R135_SP_XF.1", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i154", "sym_num" : 1, "page_instance" : "I154", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1" } ], "part_number" : "400-000010-003", "net_name" : "UNNAMED_10_LTM4650FIXED_I151_CLKOUT_SP", "pin_name" : "A", "refdes" : "R135_SP_XF", "pin_group" : "1;", "pinuse" : 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"page_instance" : "I85", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "phys_page" : "page3" } ], "pin_name" : "GND_7", "refdes" : "J2_P1_XF", "net_name" : "GND", "part_number" : "410-000324-001", "pin_name_unsanitized" : "GND_7", "pinuse" : "GROUND;" }, "U6_XF.8" : { "pinuse" : "IN;", "pin_name_unsanitized" : "EN4", "part_number" : "450-000037-001", "pin_name" : "EN4", "refdes" : "U6_XF", "net_name" : "UNNAMED_29_RESISTOR_I15_B_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_page" : "page29", "block" : "top/xc2_fpga_blk", "page" : "page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i1", "sym_num" : 1, "page_instance" : "I1", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29" } ], "node_name" : "U6_XF.8", "pin_number" : "8", "pin_type" : "INPUT" }, "C55_FL_XF.2" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page8", "phys_page" : "page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8", "page_instance" : "I34", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8_i34" } ], "pin_name" : "B", "net_name" : "GND", "refdes" : "C55_FL_XF", "part_number" : "402-000010-001", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C55_FL_XF.2" }, "R2_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R2_XF.2", "marker_data" : [ { "page" : "page17", "block" : "top/xc2_fpga_blk", "phys_page" : "page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I67", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i67" } ], "pin_name" : "B", "refdes" : "R2_XF", "net_name" : "UNNAMED_17_RESISTOR_I51_A_XF", "part_number" : "400-000010-010", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "J3_XF.200" : { "pin_name_unsanitized" : "VSS_52", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : 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"I173" } ], "net_name" : "PWR_SDIMM_VPP_XF", "pin_name" : "A", "refdes" : "C437_XF", "part_number" : "402-000010-028", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "U1_XF.BW4" : { "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "GND_1020", "net_name" : "GND", "marker_data" : [ { "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I73", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73", "sym_num" : 38 } ], "pin_name_unsanitized" : "GND_1020", "pin_group" : "ALL_POWER_PINS_38;", "pin_type" : "INOUT", "pin_number" : "BW4", "node_name" : "U1_XF.BW4" }, "D2_CPLD.2" : { "pin_name_unsanitized" : "RED_K", "pinuse" : "TRI;", "net_name" : "UNNAMED_9_LUMEXRGBLED_I90_REDK_CPLD", "pin_name" : "RED_K", "refdes" : "D2_CPLD", "part_number" : "404-000302-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page9", "page_instance" : "I90", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page9_i90", "page" : "page9", "block" : "top/cpld_blk", "phys_page" : "page9", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "remapped_page" : null } ], "node_name" : "D2_CPLD.2", "pin_number" : "2", "pin_type" : "INOUT" }, "C36_XF.2" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i629", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I629", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page11", "phys_page" : "page11" } ], "net_name" : "PCIE0_TXP<5>_XF", "pin_name" : "B", "refdes" : "C36_XF", "part_number" : "402-000010-035", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C36_XF.2" }, "PM5_SP_XF.L7" : { "node_name" : "PM5_SP_XF.L7", "pin_number" : "L7", "pin_type" : "POWER", "pin_name_unsanitized" : "VIN_18", "pinuse" : "POWER;", "refdes" : "PM5_SP_XF", "pin_name" : "VIN_18", "net_name" : "P12V_4650_TR_SP", "part_number" : "462-000308-002", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page5", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I80" } ] }, "U1_XF.AH14" : { "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "sym_num" : 35 } ], "pin_name" : "GND_476", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_35;", "pin_name_unsanitized" : "GND_476", "pin_number" : "AH14", "pin_type" : "INOUT", "node_name" : "U1_XF.AH14" }, "J1_O2_XF.B7" : { "node_name" : "J1_O2_XF.B7", "pin_type" : "INPUT", "pin_number" : "B7", "pin_name_unsanitized" : "PETN1", "pinuse" : "IN;", "refdes" : "J1_O2_XF", "pin_name" : "PETN1", "net_name" : "OCL2_PET_N<1>_XF", "part_number" : "410-000324-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i30@top_lib.ocl_x4_conn_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i30@top_lib.ocl_x4_conn_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i30/ocl_x4_conn_blk/page3", "page_instance" : "I84", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i30/ocl_x4_conn_blk/page3_i84" } ] }, "U1_XF.A59" : { "pin_type" : "INOUT", "pin_number" : "A59", "node_name" : "U1_XF.A59", "marker_data" : [ { "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33, "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "refdes" : "U1_XF", "pin_name" : "GND_16", "net_name" : "GND", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_16" }, "R279_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R279_XF.1", "marker_data" : [ { "page_instance" : "I138", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i138", "sym_num" : 1, "phys_page" : "page29", "block" : "top/xc2_fpga_blk", "page" : "page29", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29" } ], "part_number" : "400-000010-010", "net_name" : "OCL_REF_CLK_P<0>", "pin_name" : "A", "refdes" : "R279_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "PM5_SP_XF.B8" : { "pin_type" : "POWER", "pin_number" : "B8", "node_name" : "PM5_SP_XF.B8", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i80", "sym_num" : 1, "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5" } ], "part_number" : "462-000308-002", "net_name" : "PWR_VCCINT_XF", "pin_name" : "VOUT2_6", "refdes" : "PM5_SP_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT2_6" }, "PM4_ND_XF.H6" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i40", "sym_num" : 3, "page_instance" : "I40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk" } ], "pin_name" : "COMP1A", "refdes" : "PM4_ND_XF", "net_name" : "UNNAMED_3_LTM4675_I40_COMP1A_ND", "part_number" : "462-000304-001", "pin_name_unsanitized" : "COMP1A", "pinuse" : "IN;", "pin_type" : "INPUT", "pin_number" : "H6", "node_name" : "PM4_ND_XF.H6" }, "PM2_SP_XF.H5" : { "node_name" : "PM2_SP_XF.H5", "pin_number" : "H5", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_43", "marker_data" : [ { "page_instance" : "I459", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "sym_num" : 5, "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6" } ], "part_number" : "462-000309-001", "refdes" : "PM2_SP_XF", "net_name" : "GND", "pin_name" : "GND_43" }, "C93_SP_XF.2" : { "pin_name" : "B", "refdes" : "C93_SP_XF", "net_name" : "GND", "part_number" : "402-000010-031", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i488", "sym_num" : 1, "page_instance" : "I488", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C93_SP_XF.2" }, "R103_SP_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R103_SP_XF.1", "net_name" : "PM1_SP_AGND_SP", "pin_name" : "A", "refdes" : "R103_SP_XF", "part_number" : "400-000014-011", "marker_data" : [ { "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I74", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i74" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "R23.2" : { "part_number" : "400-000010-010", "pin_name" : "B", "refdes" : "R23", "net_name" : "GND", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page7", "path" : "@top_lib.top(sch_1):page7", "remapped_page" : null, "block" : "top", "page" : "page7", "phys_page" : "page7", "sym_num" : 1, "ppath" : "top/page7_i12", "ppath_without_last_instance" : "top/page7", "page_instance" : "I12" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R23.2" }, "U2_FL_XF.22" : { "pin_number" : "22", "pin_type" : "INPUT", "node_name" : "U2_FL_XF.22", "pin_name" : "MARGA", "net_name" : "UNNAMED_6_LT3071_I30_MARGA_FL", "refdes" : "U2_FL_XF", "part_number" : "450-000057-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6", "page_instance" : "I30", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6_i30" } ], "pin_name_unsanitized" : "MARGA", "pinuse" : "IN;" }, "PM4_ND_XF.K9" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN1_2", "marker_data" : [ { "page_instance" : "I13", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i13", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3" } ], "part_number" : "462-000304-001", "refdes" : "PM4_ND_XF", "pin_name" : "VIN1_2", "net_name" : "P12V_FUSED_4675_ND", "node_name" : "PM4_ND_XF.K9", "pin_type" : "POWER", "pin_number" : "K9" }, "U1_XF.BH57" : { "pin_name_unsanitized" : "IO_L21P_T3L_N4_AD8P_24", "pin_group" : "ALL_SIGNAL_PINS_20;", "part_number" : "450-000340-001", "pin_name" : "IO_L21P_T3L_N4_AD8P_24", "net_name" : "NC", "refdes" : "U1_XF", "marker_data" : [ { "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I49", "sym_num" : 20, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49" } ], "node_name" : "U1_XF.BH57", "pin_number" : "BH57", "pin_type" : "INOUT" }, "C340_XF.2" : { "part_number" : "402-000010-035", "net_name" : "E1S3_PET_P<2>_XF", "pin_name" : "B", "refdes" : "C340_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I94", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i94", "block" : "top/xc2_fpga_blk", "page" : "page13", "phys_page" : "page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C340_XF.2" }, "R18_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page16", "phys_page" : "page16", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page16", "page_instance" : "I74", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page16_i74" } ], "pin_name" : "B", "net_name" : "C0_DDR4_SA<1>_XF", "refdes" : "R18_XF", "part_number" : "400-000014-011", "node_name" : "R18_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "R11_E2_XF.1" : { "node_name" : "R11_E2_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "net_name" : "PWR_FPGA_3R3V", "refdes" : "R11_E2_XF", "part_number" : "400-000010-020", "marker_data" : [ { "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i30", "sym_num" : 1, "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4" } ] }, "U1_XF.BY36" : { "pin_name_unsanitized" : "GND_1041", "pin_group" : "ALL_POWER_PINS_38;", "net_name" : "GND", "pin_name" : "GND_1041", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I73", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73", "sym_num" : 38 } ], "node_name" : "U1_XF.BY36", "pin_number" : "BY36", "pin_type" : "INOUT" }, "PM5_SP_XF.J6" : { "pin_name_unsanitized" : "TEMP", "pinuse" : "OUT;", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i78", "sym_num" : 3, "page_instance" : "I78", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5" } ], "pin_name" : "TEMP", "refdes" : "PM5_SP_XF", "net_name" : "TS_LT4650_TR_SP", "part_number" : "462-000308-002", "node_name" : "PM5_SP_XF.J6", "pin_type" : "OUTPUT", "pin_number" : "J6" }, "R63.1" : { "part_number" : "400-000010-007", "net_name" : "JT_FPGA_TMS", "pin_name" : "A", "refdes" : "R63", "marker_data" : [ { "page_instance" : "I106", "ppath_without_last_instance" : "top/page15", "ppath" : "top/page15_i106", "sym_num" : 1, "phys_page" : "page15", "page" : "page15", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page15" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R63.1" }, "U1_XF.AG17" : { "pin_number" : "AG17", "pin_type" : "INOUT", "node_name" : "U1_XF.AG17", "marker_data" : [ { "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "sym_num" : 35, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "part_number" : "450-000340-001", "pin_name" : "GND_459", "refdes" : "U1_XF", "net_name" : "GND", "pin_group" : "ALL_POWER_PINS_35;", "pin_name_unsanitized" : "GND_459" }, "PM2_SP_XF.G5" : { "refdes" : "PM2_SP_XF", "net_name" : "GND", "pin_name" : "GND_42", "part_number" : "462-000309-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I459", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null } ], "pin_name_unsanitized" : "GND_42", "pinuse" : "GROUND;", "pin_number" : "G5", "node_name" : "PM2_SP_XF.G5" }, "PM4_ND_XF.G6" : { "node_name" : "PM4_ND_XF.G6", "pin_number" : "G6", "pin_type" : "POWER", "pin_name_unsanitized" : "SGND_4", "pinuse" : "POWER;", "pin_name" : "SGND_4", "refdes" : "PM4_ND_XF", "net_name" : "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF", "part_number" : "462-000304-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i13", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3" } ] }, "C96_FL_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C96_FL_XF.2", "part_number" : "402-000010-028", "pin_name" : "B", "net_name" : "GND", "refdes" : "C96_FL_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page11", "phys_page" : "page11", "page" : "page12", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i12", "sym_num" : 1, "page_instance" : "I12", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "PM3_SP_XF.F12" : { "node_name" : "PM3_SP_XF.F12", "pin_type" : "POWER", "pin_number" : "F12", "pin_name_unsanitized" : "GND_25", "pinuse" : "POWER;", "net_name" : "GND", "pin_name" : "GND_25", "refdes" : "PM3_SP_XF", "part_number" : "462-000308-002", "marker_data" : [ { "phys_page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "page_instance" : "I153", "ppath_without_last_instance" : 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"net_name" : "GND", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "sym_num" : 33, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I68" } ], "pin_name_unsanitized" : "GND_113", "pin_group" : "ALL_POWER_PINS_33;", "pin_type" : "INOUT", "pin_number" : "H20", "node_name" : "U1_XF.H20" }, "U3_FL_XF.7" : { "pin_name_unsanitized" : "VIN_7", "pinuse" : "POWER;", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "phys_page" : "page3", "page" : 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"sym_num" : 1, "page_instance" : "I73", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_page" : "page20", "block" : "top/xc2_fpga_blk", "page" : "page20" } ], "part_number" : "402-000010-028", "refdes" : "C464_XF", "pin_name" : "B", "net_name" : "GND", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C464_XF.2" }, "U1_XF.AC54" : { "node_name" : "U1_XF.AC54", "pin_number" : "AC54", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_22;", "pin_name_unsanitized" : "IO_L7P_T1L_N0_QBC_AD13P_32", "marker_data" : [ { "sym_num" : 22, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I46", "phys_path" : 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"1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "J1_E3_XF.A25" : { "node_name" : "J1_E3_XF.A25", "pin_number" : "A25", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_11", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3_i101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page3", "page_instance" : "I101", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3" } ], "part_number" : "410-000317-001", "net_name" : "GND", "pin_name" : "GND_11", "refdes" : "J1_E3_XF" }, "C78_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C78_XF.2", "marker_data" : [ { "ppath" : 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"pin_group" : "1;" }, "PM3_SP_XF.M4" : { "node_name" : "PM3_SP_XF.M4", "pin_number" : "M4", "pin_type" : "POWER", "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_25", "part_number" : "462-000308-002", "pin_name" : "VIN_25", "net_name" : "P12V_4650_BL_SP", "refdes" : "PM3_SP_XF", "marker_data" : [ { "page_instance" : "I152", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i152", "sym_num" : 1, "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10" } ] }, "PM2_SP_XF.P5" : { "pin_number" : "P5", "node_name" : "PM2_SP_XF.P5", "marker_data" : [ { "page_instance" : "I459", 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"pin_number" : "270", "pin_type" : "GROUND", "node_name" : "J3_XF.270" }, "U1_XF.AH45" : { "pin_type" : "INOUT", "pin_number" : "AH45", "node_name" : "U1_XF.AH45", "net_name" : "GND", "pin_name" : "GND_486", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I70", "sym_num" : 35, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70" } ], "pin_name_unsanitized" : "GND_486", "pin_group" : "ALL_POWER_PINS_35;" }, "U1_XF.AA36" : { "pin_name" : "VCCINT_48", "net_name" : "PWR_VCCINT_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", 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"part_number" : "402-000015-007", "pin_name" : "B", "refdes" : "C13_XF", "net_name" : "GND", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i122", "sym_num" : 1, "page_instance" : "I122", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23" } ], "node_name" : "C13_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "C41.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "net_name" : "GND", "pin_name" : "B", "refdes" : "C41", "part_number" : "402-000500-005", "marker_data" : [ { "ppath" : "top/page19_i63", "sym_num" : 1, "page_instance" : "I63", "ppath_without_last_instance" : "top/page19", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page19", "path" : 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"pin_name" : "MTG2", "marker_data" : [ { "ppath" : "top/page1_i66", "sym_num" : 1, "page_instance" : "I66", "ppath_without_last_instance" : "top/page1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page1", "phys_path" : "@top_lib.top(sch_1):page1", "phys_page" : "page1", "page" : "page1", "block" : "top" } ], "pinuse" : "NC;", "pin_name_unsanitized" : "MTG2" }, "U2_SD_XF.1" : { "node_name" : "U2_SD_XF.1", "pin_number" : "1", "pin_type" : "INPUT", "pinuse" : "IN;", "pin_name_unsanitized" : "REFIN", "part_number" : "450-000059-001", "net_name" : "UNNAMED_4_RESISTOR_I14_A_SD", "pin_name" : "REFIN", "refdes" : "U2_SD_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page4", 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"pin_name_unsanitized" : "B" }, "U1_XF.AH49" : { "pin_group" : "ALL_SIGNAL_PINS_23;", "pin_name_unsanitized" : "IO_L15P_T2L_N4_AD11P_30", "marker_data" : [ { "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I53", "sym_num" : 23, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53" } ], "part_number" : "450-000340-001", "pin_name" : "IO_L15P_T2L_N4_AD11P_30", "net_name" : "NC", "refdes" : "U1_XF", "node_name" : "U1_XF.AH49", "pin_type" : "INOUT", "pin_number" : "AH49" }, "J4_XF.97" : { "pin_number" : "97", "pin_type" : "INOUT", "node_name" : "J4_XF.97", "part_number" : "410-000300-001", "refdes" : "J4_XF", "pin_name" : "DQ32", "net_name" : "C3_DDR4_DQ<32>_XF", "marker_data" : [ { "phys_page" : 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"page_instance" : "I47", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i47", "sym_num" : 1 } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "J1_XF.259" : { "marker_data" : [ { "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180" } ], "pin_name" : "VSS_18", "refdes" : "J1_XF", "net_name" : "GND", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_18", "pinuse" : "UNSPEC;", "pin_number" : "259", "pin_type" : "GROUND", "node_name" : "J1_XF.259" }, "C269_XF.1" : { "node_name" : "C269_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null, "page" : "page17", "block" : "top/xc2_fpga_blk", "phys_page" : "page17", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i183", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I183" } ], "part_number" : "402-000010-001", "refdes" : "C269_XF", "pin_name" : "A", "net_name" : "UNNAMED_17_RESISTOR_I121_A_XF" }, "C408_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "net_name" : "PWR_SDIMM_VDD_XF", "pin_name" : "B", "refdes" : "C408_XF", "part_number" : "402-000010-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i168", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I168", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4" } ], "node_name" : "C408_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.AG1" : { "pin_group" : "ALL_SIGNAL_PINS_14;", "pin_name_unsanitized" : "MGTYRXN0_231", "marker_data" : [ { "page_instance" : "I56", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i56", "sym_num" : 14, "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31" } ], "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "MGTYRXN0_231", "refdes" : "U1_XF", "node_name" : "U1_XF.AG1", "pin_type" : "INOUT", "pin_number" : "AG1" }, "U1_XF.BD31" : { "pin_group" : "ALL_POWER_PINS_32;", "pin_name_unsanitized" : "VCCINT_226", "marker_data" : [ { "page_instance" : "I187", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i187", "sym_num" : 32, "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23" } ], "refdes" : "U1_XF", "pin_name" : "VCCINT_226", "net_name" : "PWR_VCCINT_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.BD31", "pin_type" : "INOUT", "pin_number" : "BD31" }, "U3_FL_XF.27" : { "marker_data" : [ { "page_instance" : "I32", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3_i32", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3" } ], "pin_name" : "BIAS", "net_name" : "P3R3V", "refdes" : "U3_FL_XF", "part_number" : "450-000057-001", "pin_name_unsanitized" : "BIAS", "pinuse" : "POWER;", "pin_number" : "27", "pin_type" : "POWER", "node_name" : "U3_FL_XF.27" }, "C2.3" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page10", "page_instance" : "I123", "sym_num" : 1, "ppath" : "top/page10_i123", "page" : "page10", "block" : "top", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "remapped_page" : null } ], "pin_name" : "C", "refdes" : "C2", "net_name" : "GND", "part_number" : "402-000041-001", "pin_name_unsanitized" : "C", "pinuse" : "POWER;", "pin_type" : "POWER", "pin_number" : "3", "node_name" : "C2.3" }, "C2_CPLD.2" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I126", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page7_i126", "page" : "page7", "block" : "top/cpld_blk", "phys_page" : "page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null } ], "part_number" : "402-000010-001", "refdes" : "C2_CPLD", "pin_name" : "B", "net_name" : "CPLD_P1R8V_1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C2_CPLD.2" }, "PM3_SP_XF.A4" : { "pin_type" : "POWER", "pin_number" : "A4", "node_name" : "PM3_SP_XF.A4", "net_name" : "PWR_VCCINT_XF", "pin_name" : "VOUT1_4", "refdes" : "PM3_SP_XF", "part_number" : "462-000308-002", "marker_data" : [ { "phys_page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "page_instance" : "I152", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i152", "sym_num" : 1 } ], "pin_name_unsanitized" : "VOUT1_4", "pinuse" : "POWER;" }, "U1_CPLD.F6" : { "node_name" : "U1_CPLD.F6", "pin_number" : "F6", "pin_name_unsanitized" : "GND_9", "pinuse" : "GROUND;", "marker_data" : [ { "path" : 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"UNNAMED_12_LT3071_I30_V01_FL", "part_number" : "400-000010-010", "node_name" : "R97_FL_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "R73_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-065", "net_name" : "UNNAMED_17_RESISTOR_I53_A_XF", "pin_name" : "B", "refdes" : "R73_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i71", "sym_num" : 1, "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_page" : "page17", "page" : "page17", "block" : "top/xc2_fpga_blk" } ], "node_name" : "R73_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_XF.AV32" : { "pin_name_unsanitized" : "GND_656", "pin_group" : "ALL_POWER_PINS_36;", "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_656", "refdes" : "U1_XF", "marker_data" : [ { "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "sym_num" : 36, "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "node_name" : "U1_XF.AV32", "pin_number" : "AV32", "pin_type" : "INOUT" }, "U3_CPLD.6" : { "pin_type" : "INPUT", "pin_number" : "6", "node_name" : "U3_CPLD.6", "pin_name" : "S0", "net_name" : "JT_CPLD_INST_F", "refdes" : "U3_CPLD", "part_number" : "450-000331-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page8_i16", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page8", "page_instance" : "I16", "phys_path" : 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"1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R79_SP_XF.1" }, "J1_O0_XF.A17" : { "refdes" : "J1_O0_XF", "net_name" : "GND", "pin_name" : "GND_6", "part_number" : "410-000324-001", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i6@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i6@top_lib.ocl_x4_conn_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i6/ocl_x4_conn_blk/page3", "page_instance" : "I84", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i6/ocl_x4_conn_blk/page3_i84" } ], "pin_name_unsanitized" : "GND_6", "pinuse" : "GROUND;", "pin_number" : "A17", "node_name" : "J1_O0_XF.A17" }, "C21_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C21_XF.1", "marker_data" : [ { "page_instance" : "I98", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i98", "sym_num" : 1, "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23" } ], "pin_name" : "A", "refdes" : "C21_XF", "net_name" : "PWR_VCCINT_XF", "part_number" : "402-000015-006", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "C31_SD_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C31_SD_XF.2", "marker_data" : [ { "page_instance" : "I21", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4_i21", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4" } ], "refdes" : "C31_SD_XF", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000050-015", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "PM7_SP_XF.J10" : { "pin_type" : "POWER", "pin_number" : "J10", "node_name" : "PM7_SP_XF.J10", "refdes" : "PM7_SP_XF", "pin_name" : "VIN_5", "net_name" : "P12V_4650_BR_SP", "part_number" : "462-000308-002", "marker_data" : [ { "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I80", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80" } ], "pin_name_unsanitized" : "VIN_5", "pinuse" : "POWER;" }, "U1_XF.BW47" : { "pin_name_unsanitized" : "IO_L6N_T0U_N11_AD6N_20", "pin_group" : "ALL_SIGNAL_PINS_17;", "part_number" : "450-000340-001", "pin_name" : "IO_L6N_T0U_N11_AD6N_20", "net_name" : "NC", "refdes" : "U1_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30", "sym_num" : 17, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I50" } ], "node_name" : "U1_XF.BW47", "pin_type" : "INOUT", "pin_number" : "BW47" }, "PM2_SP_XF.H1" : { "pin_number" : "H1", "node_name" : "PM2_SP_XF.H1", "part_number" : "462-000309-001", "pin_name" : "VOUT1_1", "net_name" : "PWR_AVCC_SW_XF", "refdes" : "PM2_SP_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i457", "sym_num" : 2, "page_instance" : "I457", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT1_1" }, "C48_XF.1" : { "node_name" : "C48_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I636", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i636", "page" : "page11", "block" : "top/xc2_fpga_blk", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null } ], "refdes" : "C48_XF", "pin_name" : "A", "net_name" : "AC_PCIE1_TXN<1>_XF", "part_number" : "402-000010-035" }, "M6.MTG5" : { "node_name" : "M6.MTG5", "pin_number" : "MTG5", "pin_name_unsanitized" : "MTG5", "pinuse" : "NC;", "marker_data" : [ { "page" : "page1", "block" : "top", "phys_page" : "page1", "path" : "@top_lib.top(sch_1):page1", "phys_path" : "@top_lib.top(sch_1):page1", "remapped_page" : null, "ppath_without_last_instance" : "top/page1", "page_instance" : "I67", "sym_num" : 1, "ppath" : "top/page1_i67" } ], "net_name" : "GND", "pin_name" : "MTG5", "refdes" : "M6", "part_number" : "HOLE_RING" }, "J4_XF.104" : { "net_name" : "C3_DDR4_DQ<34>_XF", "pin_name" : "DQ34", "refdes" : "J4_XF", "part_number" : "410-000300-001", "marker_data" : [ { "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180" } ], "pin_name_unsanitized" : "DQ34", "pinuse" : "TRI;", "pin_number" : "104", "pin_type" : "INOUT", "node_name" : "J4_XF.104" }, "R218_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R218_XF.1", "marker_data" : [ { "page_instance" : "I210", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i210", "sym_num" : 1, "phys_page" : "page14", "page" : "page14", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14" } ], "part_number" : "400-000010-010", "net_name" : "OCL0_FPGA_REFCLK_P_XF", "pin_name" : "A", "refdes" : "R218_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "J4_XF.221" : { "node_name" : "J4_XF.221", "pin_number" : "221", "pin_type" : "POWER", "pinuse" : "POWER;", "pin_name_unsanitized" : "VTT_2", "part_number" : "410-000300-001", "refdes" : "J4_XF", "pin_name" : "VTT_2", "net_name" : "PWR_NDIMM_VTT_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null } ] }, "U1_XF.A23" : { "node_name" : "U1_XF.A23", "pin_number" : "A23", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_48;", "pin_name_unsanitized" : "C3_DDR4_DQS_T11", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_page" : "PAGE9", "block" : "top/xc2_fpga_blk", "page" : "PAGE9", "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "sym_num" : 53, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "C3_DDR4_DQS_T11", "net_name" : "C3_RDIMM_DQS_T<14>_XF" }, "U1_XF.BU5" : { "node_name" : "U1_XF.BU5", "pin_number" : "BU5", "pin_type" : "INOUT", "pin_name_unsanitized" : "OCL1_PER_N0", "pin_group" : "ALL_SIGNAL_PINS_11;", "refdes" : "U1_XF", "pin_name" : "OCL1_PER_N0", "net_name" : "OCL1_PER_N<0>_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I274", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i274", "sym_num" : 11, "phys_page" : "page14", "page" : "page14", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14" } ] }, "J2_XF.155" : { "pin_number" : "155", "pin_type" : "INOUT", "node_name" : "J2_XF.155", "part_number" : "410-000300-001", "pin_name" : "DQ7", "net_name" : "C1_DDR4_DQ<7>_XF", "refdes" : "J2_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "page" : "page6", "block" : "top/xc2_fpga_blk", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null } ], "pinuse" : "TRI;", "pin_name_unsanitized" : "DQ7" }, "R16_CPLD.1" : { "refdes" : "R16_CPLD", "pin_name" : "A", "net_name" : "ENB3V_SEQ_A", "part_number" : "400-000010-074", "marker_data" : [ { "phys_page" : "page4", "block" : "top/cpld_blk", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "page_instance" : "I83", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "ppath" : "top/page14_i1/cpld_blk/page4_i83", "sym_num" : 1 } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R16_CPLD.1" }, "PM4_SD_XF.F3" : { "pin_name_unsanitized" : "RUN0", "pinuse" : "IN;", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I40" } ], "pin_name" : "RUN0", "refdes" : "PM4_SD_XF", "net_name" : "UNNAMED_3_LTM4675_I40_RUN0_SD", "part_number" : "462-000304-001", "node_name" : "PM4_SD_XF.F3", "pin_type" : "INPUT", "pin_number" : "F3" }, "PM2_SP_XF.G1" : { "node_name" : "PM2_SP_XF.G1", "pin_number" : "G1", "pin_name_unsanitized" : "GND_30", "pinuse" : "GROUND;", "refdes" : "PM2_SP_XF", "net_name" : "GND", "pin_name" : "GND_30", "part_number" : "462-000309-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I459" } ] }, "J1_P0_XF.B7" : { "node_name" : "J1_P0_XF.B7", "pin_type" : "INPUT", "pin_number" : "B7", "pinuse" : "IN;", "pin_name_unsanitized" : "PETN1", "part_number" : "410-000324-001", "net_name" : "PCIE0_TXN<1>_XF", "pin_name" : "PETN1", "refdes" : "J1_P0_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1, "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "page" : "page3" } ] }, "U1_XF.D24" : { "node_name" : "U1_XF.D24", "pin_number" : "D24", "pin_type" : "INOUT", "pin_name_unsanitized" : "C3_DDR4_DQ41", "pin_group" : "C3_LNIB_1_7_48;", "pin_name" : "C3_DDR4_DQ41", "net_name" : "C3_DDR4_DQ<41>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I2425", 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"node_name" : "R17_MP.1", "part_number" : "400-000010-009", "net_name" : "UNNAMED_4_RESISTOR_I23_B_MP", "pin_name" : "A", "refdes" : "R17_MP", "marker_data" : [ { "ppath" : "top/page18_i1/mgmt_pwr_block/page4_i24", "sym_num" : 1, "page_instance" : "I24", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/mgmt_pwr_block" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "J1_XF.237" : { "node_name" : "J1_XF.237", "pin_number" : "237", "pin_type" : "INPUT", "pinuse" : "IN;", "pin_name_unsanitized" : "CS3_N_C1", "part_number" : "410-000300-001", "pin_name" : "CS3_N_C1", "net_name" : "C0_DDR4_CS_N<3>_XF", "refdes" : "J1_XF", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : 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"pin_type" : "INOUT", "pin_number" : "BV3" }, "J4_XF.162" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk" } ], "part_number" : "410-000300-001", "refdes" : "J4_XF", "pin_name" : "VSS_46", "net_name" : "GND", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_46", "pin_type" : "GROUND", "pin_number" : "162", "node_name" : "J4_XF.162" }, "C113_SP_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "refdes" : "C113_SP_XF", "net_name" : "GND", "part_number" : "402-000010-031", "marker_data" : [ { "sym_num" : 1, "ppath" : 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"pin_type" : "POWER" }, "U1_XF.AH15" : { "part_number" : "450-000340-001", "pin_name" : "MGTAVCC_RUC_8", "refdes" : "U1_XF", "net_name" : "PWR_AVCC_RUC_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page20", "phys_page" : "page20", "sym_num" : 29, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I86" } ], "pin_name_unsanitized" : "MGTAVCC_RUC_8", "pin_group" : "ALL_POWER_PINS_29;", "pin_type" : "INOUT", "pin_number" : "AH15", "node_name" : "U1_XF.AH15" }, "R79_XF.1" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i56", "sym_num" : 1, "page_instance" : "I56", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "remapped_page" : null, "phys_path" : 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"pin_type" : "INOUT", "pin_number" : "255" }, "PM5_SP_XF.L4" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5", "phys_page" : "page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I80", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i80" } ], "part_number" : "462-000308-002", "refdes" : "PM5_SP_XF", "pin_name" : "VIN_15", "net_name" : "P12V_4650_TR_SP", "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_15", "pin_number" : "L4", "pin_type" : "POWER", "node_name" : "PM5_SP_XF.L4" }, "U1_XF.D15" : { "marker_data" : [ { "sym_num" : 54, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", 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"UNSPEC;", "marker_data" : [ { "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "page_instance" : "I143", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i143", "sym_num" : 1 } ], "pin_name" : "A", "net_name" : "PWR_VCCINT_XF", "refdes" : "C323_XF", "part_number" : "402-000015-007" }, "C85_SP_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C85_SP_XF.2", "pin_name" : "B", "net_name" : "UNNAMED_6_BYPASSCAPNPOL_I465_B_SP", "refdes" : "C85_SP_XF", "part_number" : "402-000016-001", "marker_data" : [ { "page_instance" : "I465", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i465", "sym_num" : 1, "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "U1_XF.AH63" : { "pin_group" : "ALL_SIGNAL_PINS_23;", "pin_name_unsanitized" : "IO_L3P_T0L_N4_AD15P_31", "marker_data" : [ { "sym_num" : 23, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I53", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31" } ], "refdes" : "U1_XF", "pin_name" : "IO_L3P_T0L_N4_AD15P_31", "net_name" : "NC", "part_number" : "450-000340-001", "node_name" : "U1_XF.AH63", "pin_number" : "AH63", "pin_type" : "INOUT" }, "U1_XF.BA37" : { "pin_name" : "GND_728", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "sym_num" : 36, "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk" } ], "pin_name_unsanitized" : "GND_728", "pin_group" : "ALL_POWER_PINS_36;", "pin_type" : "INOUT", "pin_number" : "BA37", "node_name" : "U1_XF.BA37" }, "C152_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C152_XF.1", "part_number" : "402-000010-035", "refdes" : "C152_XF", "pin_name" : "A", "net_name" : "AC_E1S2_PET_P<3>_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_page" : "page13", "page" : "page13", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i71", "sym_num" : 1, "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "U1_XF.AC22" : { "pin_group" : "ALL_POWER_PINS_31;", "pin_name_unsanitized" : "VCCINT_65", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "sym_num" : 31, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I186" } ], "part_number" : "450-000340-001", "pin_name" : "VCCINT_65", "net_name" : "PWR_VCCINT_XF", "refdes" : "U1_XF", "node_name" : "U1_XF.AC22", "pin_number" : "AC22", "pin_type" : "INOUT" }, "C453_XF.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page20", "phys_page" : "page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I54", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i54" } ], "part_number" : "402-000010-028", "pin_name" : "A", "net_name" : "PWR_AVCC_RUC_XF", "refdes" : "C453_XF", "node_name" : "C453_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "J1_E1_XF.A13" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i101", "sym_num" : 1, "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3" } ], "refdes" : "J1_E1_XF", "net_name" : "GND", "pin_name" : "GND_7", "part_number" : "410-000317-001", "pin_name_unsanitized" : "GND_7", "pinuse" : "GROUND;", "pin_number" : "A13", "node_name" : "J1_E1_XF.A13" }, "Q9.2" : { "marker_data" : [ { "ppath" : "top/page20_i8", "sym_num" : 1, "page_instance" : "I8", "ppath_without_last_instance" : "top/page20", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page20", "path" : "@top_lib.top(sch_1):page20", "phys_page" : "page20", "block" : "top", "page" : "page20" } ], "net_name" : "GND", "pin_name" : "S", "refdes" : "Q9", "part_number" : "405-000010-001", "pin_name_unsanitized" : "S", "pinuse" : "UNSPEC;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "Q9.2" }, "C356_XF.2" : { "node_name" : "C356_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-035", "net_name" : "OCL0_CONN_REFCLK_P_XF", "pin_name" : "B", "refdes" : "C356_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i161", "sym_num" : 1, "page_instance" : "I161", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29" } ] }, "M7.MTG5" : { "pin_name_unsanitized" : "MTG5", "pinuse" : "NC;", "marker_data" : [ { "page_instance" : "I61", "ppath_without_last_instance" : "top/page1", "ppath" : "top/page1_i61", "sym_num" : 1, "phys_page" : "page1", "block" : "top", "page" : "page1", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page1", "path" : "@top_lib.top(sch_1):page1" } ], "net_name" : "GND", "refdes" : "M7", "pin_name" : "MTG5", "part_number" : "HOLE_RING", "node_name" : "M7.MTG5", "pin_number" : "MTG5" }, "C426_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i162", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I162", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page6", "phys_page" : "page6" } ], "part_number" : "402-000010-028", "net_name" : "PWR_SDIMM_VDD_XF", "pin_name" : "B", "refdes" : "C426_XF", "node_name" : "C426_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "PM4_SD_XF.D9" : { "pin_number" : "D9", "pin_type" : "POWER", "node_name" : "PM4_SD_XF.D9", "part_number" : "462-000304-001", "pin_name" : "VIN0_4", "refdes" : "PM4_SD_XF", "net_name" : "P12V_FUSED_4675_SD", "marker_data" : [ { "page_instance" : "I13", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i13", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN0_4" }, "J1_O0_XF.A8" : { "pin_number" : "A8", "node_name" : "J1_O0_XF.A8", "part_number" : "410-000324-001", "refdes" : "J1_O0_XF", "net_name" : "GND", "pin_name" : "GND_3", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i6/ocl_x4_conn_blk/page3_i84", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i6/ocl_x4_conn_blk/page3", "page_instance" : "I84", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i6@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i6@top_lib.ocl_x4_conn_blk(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "phys_page" : "page3" } ], "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_3" }, "R8_SD_XF.2" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i67", "sym_num" : 1, "page_instance" : "I67", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3" } ], "part_number" : "400-000014-011", "refdes" : "R8_SD_XF", "pin_name" : "B", "net_name" : "UNNAMED_3_LTM4675_I40_VTRIM1CFG_SD", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R8_SD_XF.2" }, "C27_SP_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C27_SP_XF.1", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i145", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I145", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3" } ], "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I145_A_SP", "pin_name" : "A", "refdes" : "C27_SP_XF", "part_number" : "402-000010-006", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "U1_XF.AW46" : { "net_name" : "NC", "pin_name" : "IO_L19P_T3L_N0_DBC_AD9P_27", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I51", "sym_num" : 18, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51", "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null } ], "pin_name_unsanitized" : "IO_L19P_T3L_N0_DBC_AD9P_27", "pin_group" : "ALL_SIGNAL_PINS_18;", "pin_number" : "AW46", "pin_type" : "INOUT", "node_name" : "U1_XF.AW46" }, "U1_XF.P37" : { "marker_data" : [ { "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "page_instance" : "I59", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i59", "sym_num" : 25 } ], "pin_name" : "IO_L11P_T1U_N8_GC_70", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_25;", "pin_name_unsanitized" : "IO_L11P_T1U_N8_GC_70", "pin_type" : "INOUT", "pin_number" : "P37", "node_name" : "U1_XF.P37" }, "U1_XF.BG22" : { "part_number" : "450-000340-001", "pin_name" : "GND_854", "refdes" : "U1_XF", "net_name" : "GND", "marker_data" : [ { "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "sym_num" : 37 } ], "pin_name_unsanitized" : "GND_854", "pin_group" : "ALL_POWER_PINS_37;", "pin_type" : "INOUT", "pin_number" : "BG22", "node_name" : "U1_XF.BG22" }, "U1_XF.T57" : { "pin_number" : "T57", "pin_type" : "INOUT", "node_name" : "U1_XF.T57", "part_number" : "450-000340-001", "pin_name" : "IO_L12P_T1U_N10_GC_33", "net_name" : "NC", "refdes" : "U1_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "sym_num" : 22, "page_instance" : "I46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30" } ], "pin_name_unsanitized" : "IO_L12P_T1U_N10_GC_33", "pin_group" : "ALL_SIGNAL_PINS_22;" }, "R2_E3_XF.2" : { "node_name" : "R2_E3_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "remapped_page" : null, "path" : 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"refdes" : "U1_XF", "pin_name" : "IO_L24P_T3U_N10_31", "net_name" : "NC", "pin_group" : "ALL_SIGNAL_PINS_23;", "pin_name_unsanitized" : "IO_L24P_T3U_N10_31", "pin_type" : "INOUT", "pin_number" : "V58", "node_name" : "U1_XF.V58" }, "U1_XF.BW43" : { "pin_number" : "BW43", "pin_type" : "INOUT", "node_name" : "U1_XF.BW43", "pin_name" : "GND_1028", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I73", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73", "sym_num" : 38, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "pin_name_unsanitized" : "GND_1028", "pin_group" : "ALL_POWER_PINS_38;" }, "R5_FL_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : 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"node_name" : "C12_CPLD.2" }, "C476_XF.2" : { "node_name" : "C476_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "GND", "refdes" : "C476_XF", "part_number" : "402-000010-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page20", "phys_page" : "page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I43", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i43" } ] }, "J1_XF.11" : { "pin_name" : "VSS_27", "refdes" : "J1_XF", "net_name" : "GND", "part_number" : "410-000300-001", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "remapped_page" : null, "phys_path" : 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"phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "page_instance" : "I221", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i221", "sym_num" : 1 } ], "pin_name" : "A", "net_name" : "P3R3V", "refdes" : "R213_XF", "part_number" : "400-000010-010", "node_name" : "R213_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.N8" : { "pin_type" : "INOUT", "pin_number" : "N8", "node_name" : "U1_XF.N8", "part_number" : "450-000340-001", "pin_name" : "GND_178", "net_name" : "GND", "refdes" : "U1_XF", "marker_data" : [ { "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : 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{ "pin_type" : "INOUT", "pin_number" : "BG52", "node_name" : "U1_XF.BG52", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20, "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk" } ], "pin_name" : "VCCO_24_2", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_20;", "pin_name_unsanitized" : "VCCO_24_2" }, "U1_XF.H46" : { "pin_name_unsanitized" : "IO_L18N_T2U_N11_AD2N_38", "pin_group" : "ALL_SIGNAL_PINS_26;", "net_name" : "NC", "pin_name" : "IO_L18N_T2U_N11_AD2N_38", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 26, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I58", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31" } ], "node_name" : "U1_XF.H46", "pin_number" : "H46", "pin_type" : "INOUT" }, "R43.1" : { "marker_data" : [ { "page" : "page10", "block" : "top", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page10", "page_instance" : "I155", "sym_num" : 1, "ppath" : "top/page10_i155" } ], "part_number" : "400-000014-011", "refdes" : "R43", "pin_name" : "A", "net_name" : "UNNAMED_10_RESISTOR_I155_A", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R43.1" }, "U1_XF.AH12" : { "pin_type" : "INOUT", "pin_number" : "AH12", "node_name" : "U1_XF.AH12", "pin_name" : "E1S3_PET_N0", "net_name" : "AC_E1S3_PET_N<0>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 10, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i251", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I251", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page13", "phys_page" : "page13" } ], "pin_name_unsanitized" : "E1S3_PET_N0", "pin_group" : "ALL_SIGNAL_PINS_10;" }, "PM7_SP_XF.F6" : { "node_name" : "PM7_SP_XF.F6", "pin_number" : "F6", "pin_type" : "POWER", "pin_name_unsanitized" : "SGND_3", "pinuse" : "POWER;", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "phys_page" : "page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I150", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i150" } ], "pin_name" : "SGND_3", "refdes" : "PM7_SP_XF", "net_name" : "SGND_PM7_SP", "part_number" : "462-000308-002" }, "J2_P1_XF.B5" : { "node_name" : "J2_P1_XF.B5", "pin_number" : "B5", "pin_name_unsanitized" : "GND_9", "pinuse" : "GROUND;", "refdes" : "J2_P1_XF", "net_name" : "GND", "pin_name" : "GND_9", "part_number" : "410-000324-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "page_instance" : "I85", "sym_num" : 1, "ppath" : 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"U1_XF.AN41", "pin_number" : "AN41", "pin_type" : "INOUT", "pin_name_unsanitized" : "GND_566", "pin_group" : "ALL_POWER_PINS_35;", "refdes" : "U1_XF", "pin_name" : "GND_566", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "sym_num" : 35, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ] }, "U1_XF.R19" : { "node_name" : "U1_XF.R19", "pin_number" : "R19", "pin_type" : "INOUT", "pin_name_unsanitized" : "E1S_3R3V_SMB_RST_F2", "pin_group" : "E1S_SB_2_3_10_10;", "net_name" : "E1S2_3R3V_SMB_RST_F_XF", "pin_name" : "E1S_3R3V_SMB_RST_F2", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page13", "page" : "page13", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "page_instance" : "I251", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i251", "sym_num" : 10 } ] }, "PM3_SP_XF.L3" : { "net_name" : "P12V_4650_BL_SP", "pin_name" : "VIN_14", "refdes" : "PM3_SP_XF", "part_number" : "462-000308-002", "marker_data" : [ { "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : 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: 1 } ] }, "C166_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i35", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "page_instance" : "I35", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "remapped_page" : null, "page" : "page21", "block" : "top/xc2_fpga_blk", "phys_page" : "page21" } ], "net_name" : "GND", "pin_name" : "B", "refdes" : "C166_XF", "part_number" : "402-000015-008", "node_name" : "C166_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C102_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-035", "pin_name" : "B", "net_name" : "E1S0_PET_P<7>_XF", "refdes" : "C102_XF", "marker_data" : [ { "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "page_instance" : "I64", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i64", "sym_num" : 1 } ], "node_name" : "C102_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "R31_SP_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R31_SP_XF.1", "marker_data" : [ { "phys_page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "page_instance" : "I135", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i135", "sym_num" : 1 } ], "pin_name" : "A", "net_name" : "UNNAMED_10_LTM4650FIXED_I151_PGOOD2_SP", "refdes" : "R31_SP_XF", "part_number" : "400-000014-011", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "C403_XF.2" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I164", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i164" } ], "part_number" : "402-000010-001", "net_name" : "PWR_SDIMM_VDD_XF", "pin_name" : "B", "refdes" : "C403_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C403_XF.2" }, "U1_XF.R24" : { "pin_name" : "C3_DDR4_PARITY", "net_name" : "C3_DDR4_PARITY_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2425", "sym_num" : 7, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "block" : "top/xc2_fpga_blk", "page" : "page9", "phys_page" : "page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "remapped_page" : null } ], "pin_name_unsanitized" : "C3_DDR4_PARITY", "pin_group" : "C3_ACTL_7_7;", "pin_number" : "R24", "pin_type" : "INOUT", "node_name" : "U1_XF.R24" }, "R25_FL_XF.1" : { "node_name" : "R25_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6", "page_instance" : "I38", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6_i38" } ], "pin_name" : "A", "net_name" : "UNNAMED_6_LT3071_I30_IMON_FL", "refdes" : "R25_FL_XF", "part_number" : "400-000014-011" }, "C362_XF.1" : { "part_number" : "402-000010-035", "refdes" : "C362_XF", "pin_name" : "A", "net_name" : "DDR4_SYS_CLK_P<1>_XF", "marker_data" : [ { "page" : "page5", "block" : "top/xc2_fpga_blk", "phys_page" : "page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "page_instance" : "I2419", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2419" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C362_XF.1" }, "J4_XF.34" : { "pin_name" : "DQ18", "net_name" : "C3_DDR4_DQ<18>_XF", "refdes" : "J4_XF", "part_number" : "410-000300-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180" } ], "pin_name_unsanitized" : "DQ18", "pinuse" : "TRI;", "pin_type" : "INOUT", "pin_number" : "34", "node_name" : "J4_XF.34" }, "C265_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C265_XF.1", "part_number" : "402-000015-007", "refdes" : "C265_XF", "pin_name" : "A", "net_name" : "PWR_VCCINT_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I51", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "U4_XF.8" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VCC", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i1", "sym_num" : 1, "page_instance" : "I1", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "phys_page" : "page15", "page" : "page15", "block" : "top/xc2_fpga_blk" } ], "part_number" : "450-000325-001", "pin_name" : "VCC", "refdes" : "U4_XF", "net_name" : "FPGA_VCCAUX_P1R8V", "node_name" : "U4_XF.8", "pin_number" : "8", "pin_type" : "POWER" }, "U1_XF.N36" : { "pin_type" : "INOUT", "pin_number" : "N36", "node_name" : "U1_XF.N36", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L9N_T1L_N5_AD12N_70", "net_name" : "NC", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i59", "sym_num" : 25, "page_instance" : "I59", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31" } ], "pin_name_unsanitized" : "IO_L9N_T1L_N5_AD12N_70", "pin_group" : "ALL_SIGNAL_PINS_25;" }, "U1_XF.AU12" : { "pin_type" : "INOUT", "pin_number" : "AU12", "node_name" : "U1_XF.AU12", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "sym_num" : 36, "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk" } ], "refdes" : "U1_XF", "pin_name" : "GND_629", "net_name" : "GND", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_36;", "pin_name_unsanitized" : "GND_629" }, "FB3.2" : { "part_number" : "400-000014-011", "refdes" : "FB3", "pin_name" : "B", "net_name" : "VDDO2", "marker_data" : [ { "block" : "top", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page10", "page_instance" : "I99", "sym_num" : 1, "ppath" : "top/page10_i99" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "FB3.2" }, "C16_E1_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C16_E1_XF.2", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "page_instance" : "I45", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i45", "sym_num" : 1 } ], "part_number" : "402-000010-001", "net_name" : "CLKIN_P_E1", "pin_name" : "B", "refdes" : "C16_E1_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "U1_XF.AB34" : { "node_name" : "U1_XF.AB34", "pin_number" : "AB34", "pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_351", "marker_data" : [ { "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "refdes" : "U1_XF", "pin_name" : "GND_351", "net_name" : "GND", "part_number" : "450-000340-001" }, "U1_XF.BB58" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i47", "sym_num" : 19, "page_instance" : "I47", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30" } ], "part_number" : "450-000340-001", "pin_name" : "IO_L17P_T2U_N8_AD10P_25", "refdes" : "U1_XF", "net_name" : "NC", "pin_group" : "ALL_SIGNAL_PINS_19;", "pin_name_unsanitized" : "IO_L17P_T2U_N8_AD10P_25", "pin_number" : "BB58", "pin_type" : "INOUT", "node_name" : "U1_XF.BB58" }, "PM4_ND_XF.L2" : { "pin_name_unsanitized" : "GND_39", "pinuse" : "POWER;", "refdes" : "PM4_ND_XF", "pin_name" : "GND_39", "net_name" : "GND", "part_number" : "462-000304-001", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I20", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i20" } ], "node_name" : "PM4_ND_XF.L2", "pin_type" : "POWER", "pin_number" : "L2" }, "C306_XF.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i56", "sym_num" : 1, "page_instance" : "I56", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23" } ], "part_number" : "402-000015-008", "pin_name" : "A", "refdes" : "C306_XF", "net_name" : "GND", "node_name" : "C306_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "C15.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page15", "phys_page" : "page15", "page" : "page15", "block" : "top", "ppath" : "top/page15_i13", "sym_num" : 1, "page_instance" : "I13", "ppath_without_last_instance" : "top/page15" } ], "refdes" : "C15", "pin_name" : "A", "net_name" : "GND", "part_number" : "402-000010-001", "node_name" : "C15.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "PM4_SP_XF.E2" : { "node_name" : "PM4_SP_XF.E2", "pin_type" : "POWER", "pin_number" : "E2", "pin_name_unsanitized" : "GND_14", "pinuse" : "POWER;", "refdes" : "PM4_SP_XF", "pin_name" : "GND_14", "net_name" : "GND", "part_number" : "462-000308-002", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page4", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "page_instance" : "I79" } ] }, "PM4_SP_XF.F8" : { "pin_type" : "OUTPUT", "pin_number" : "F8", "node_name" : "PM4_SP_XF.F8", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i80", "sym_num" : 1, "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "remapped_page" : null, "phys_path" : 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"pinuse" : "UNSPEC;" }, "U1_XF.C42" : { "pin_group" : "ALL_SIGNAL_PINS_26;", "pin_name_unsanitized" : "IO_L19N_T3L_N1_DBC_AD9N_37", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I58", "sym_num" : 26, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L19N_T3L_N1_DBC_AD9N_37", "net_name" : "NC", "node_name" : "U1_XF.C42", "pin_number" : "C42", "pin_type" : "INOUT" }, "U1_XF.D31" : { "pin_name_unsanitized" : "IO_L23P_T3U_N8_71", "pin_group" : "ALL_SIGNAL_PINS_25;", "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L23P_T3U_N8_71", "refdes" : "U1_XF", "marker_data" : [ { "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I59", "sym_num" : 25, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i59" } ], "node_name" : "U1_XF.D31", "pin_number" : "D31", "pin_type" : "INOUT" }, "PM1_SP_XF.J9" : { "pin_name_unsanitized" : "GND_52", "pinuse" : "GROUND;", "refdes" : "PM1_SP_XF", "net_name" : "GND", "pin_name" : "GND_52", "part_number" : "462-000309-001", "marker_data" : [ { "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7" } ], "node_name" : "PM1_SP_XF.J9", "pin_number" : "J9" }, "C132_XF.1" : { "marker_data" : [ { "page" : "page12", "block" : "top/xc2_fpga_blk", "phys_page" : "page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I85", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i85" } ], "refdes" : "C132_XF", "pin_name" : "A", "net_name" : "AC_E1S1_PET_N<5>_XF", "part_number" : "402-000010-035", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C132_XF.1" }, "C83_SP_XF.2" : { "node_name" : "C83_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "page_instance" : "I402", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i402", "sym_num" : 1 } ], "pin_name" : "B", "net_name" : "UNNAMED_6_BYPASSCAPNPOL_I402_B_SP", "refdes" : "C83_SP_XF", "part_number" : "402-000016-001" }, "C433_XF.1" : { "node_name" : "C433_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-001", "pin_name" : "A", "net_name" : "GND", "refdes" : "C433_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i168", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I168", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page6", "phys_page" : "page6" } ] }, "J3_XF.125" : { "node_name" : "J3_XF.125", "pin_type" : "GROUND", "pin_number" : "125", "pin_name_unsanitized" : "VSS_45", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8" } ], "refdes" : "J3_XF", "pin_name" : "VSS_45", "net_name" : "GND", "part_number" : "410-000300-001" }, "M14.MTG2" : { "pin_name" : "MTG2", "net_name" : "GND", "refdes" : "M14", "part_number" : "HOLE_RING", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page1", "phys_path" : "@top_lib.top(sch_1):page1", "phys_page" : "page1", "page" : "page1", "block" : "top", "ppath" : "top/page1_i72", "sym_num" : 1, "page_instance" : "I72", "ppath_without_last_instance" : "top/page1" } ], "pin_name_unsanitized" : "MTG2", "pinuse" : "NC;", "pin_number" : "MTG2", "node_name" : "M14.MTG2" }, "R11_FL_XF.1" : { "node_name" : "R11_FL_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R11_FL_XF", "pin_name" : "A", "net_name" : "DAC_AVCC_LIN_XF", "part_number" : "400-000010-006", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3", "page_instance" : "I1", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3_i1" } ] }, "C3_SP_XF.2" : { "part_number" : "402-000010-003", "refdes" : "C3_SP_XF", "pin_name" : "B", "net_name" : "GND", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i41", "sym_num" : 1, "page_instance" : "I41", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C3_SP_XF.2" }, "C68_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000015-008", "pin_name" : "A", "refdes" : "C68_XF", "net_name" : "PWR_SDIMM_VDD_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i25", "sym_num" : 1, "page_instance" : "I25", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "phys_page" : "page22", "block" : "top/xc2_fpga_blk", "page" : "page22" } ], "node_name" : "C68_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "R108_SP_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R108_SP_XF.1", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i48", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I48", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7" } ], "part_number" : "400-000014-011", "net_name" : "UNNAMED_7_LTM4671_I87_FREQ0_SP", "pin_name" : "A", "refdes" : "R108_SP_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "R176_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R176_XF.2", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_page" : "page12", "block" : "top/xc2_fpga_blk", "page" : "page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i249", "sym_num" : 1, "page_instance" : "I249", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12" } ], "part_number" : "400-000010-010", "pin_name" : "B", "net_name" : "GND", "refdes" : "R176_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "PM5_SP_XF.F10" : { "pin_number" : "F10", "pin_type" : "POWER", "node_name" : "PM5_SP_XF.F10", "refdes" : "PM5_SP_XF", "pin_name" : "GND_23", "net_name" : "GND", "part_number" : "462-000308-002", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5", "phys_page" : "page5", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I79" } ], "pin_name_unsanitized" : "GND_23", "pinuse" : "POWER;" }, "U1.32" : { "node_name" : "U1.32", "pin_type" : "POWER", "pin_number" : "32", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_1", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top", "ppath" : "top/page10_i51", "sym_num" : 1, "page_instance" : "I51", "ppath_without_last_instance" : "top/page10" } ], "part_number" : "450-000308-002", "refdes" : "U1", "pin_name" : "VDD_1", "net_name" : "SI5341_VDD" }, "C231_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C231_XF.2", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page11", "phys_page" : "page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I683", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i683" } ], "pin_name" : "B", "refdes" : "C231_XF", "net_name" : "AC_PCIE1_REFN_XF", "part_number" : "402-000010-035", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "U1_XF.V22" : { "node_name" : "U1_XF.V22", "pin_number" : "V22", "pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_255", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "sym_num" : 34, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I69" } ], "part_number" : "450-000340-001", "pin_name" : "GND_255", "net_name" : "GND", "refdes" : "U1_XF" }, "M4.MTG5" : { "node_name" : "M4.MTG5", "pin_number" : "MTG5", "pinuse" : "NC;", "pin_name_unsanitized" : "MTG5", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page1", "path" : "@top_lib.top(sch_1):page1", "remapped_page" : null, "block" : "top", "page" : "page1", "phys_page" : "page1", "sym_num" : 1, "ppath" : "top/page1_i65", "ppath_without_last_instance" : "top/page1", "page_instance" : "I65" } ], "part_number" : "HOLE_RING", "pin_name" : "MTG5", "refdes" : "M4", "net_name" : "GND" }, "U1_XF.AH26" : { "pin_number" : "AH26", "pin_type" : "INOUT", "node_name" : "U1_XF.AH26", "marker_data" : [ { "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "sym_num" : 35, "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "refdes" : "U1_XF", "pin_name" : "GND_481", "net_name" : "GND", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_35;", "pin_name_unsanitized" : "GND_481" }, "R275_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R275_XF", "pin_name" : "A", "net_name" : "PWR_FPGA_3R3V", "part_number" : "400-000010-010", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page29", "phys_page" : "page29", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i139", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29", "page_instance" : "I139" } ], "node_name" : "R275_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "C294_XF.2" : { "node_name" : "C294_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-035", "net_name" : "PCIE_X1_TXN_XF", "pin_name" : "B", "refdes" : "C294_XF", "marker_data" : [ { "phys_page" : "page11", "block" : "top/xc2_fpga_blk", "page" : "page11", "remapped_page" : null, "phys_path" : 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"refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.E31", "pin_type" : "INOUT", "pin_number" : "E31" }, "U1.52" : { "pin_number" : "52", "pin_type" : "POWER", "node_name" : "U1.52", "part_number" : "450-000308-002", "pin_name" : "VDDO8", "refdes" : "U1", "net_name" : "VDDO8", "marker_data" : [ { "ppath_without_last_instance" : "top/page10", "page_instance" : "I51", "sym_num" : 1, "ppath" : "top/page10_i51", "block" : "top", "page" : "page10", "phys_page" : "page10", "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10", "remapped_page" : null } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VDDO8" }, "U1_XF.BC9" : { "node_name" : "U1_XF.BC9", "pin_number" : "BC9", "pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_29;", "pin_name_unsanitized" : "MGTAVTT_RLC_12", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I86", "sym_num" : 29, "ppath" : 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], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R26.1" }, "U1_XF.C60" : { "pin_type" : "INOUT", "pin_number" : "C60", "node_name" : "U1_XF.C60", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "GND_48", "net_name" : "GND", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "sym_num" : 33, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I68" } ], "pin_name_unsanitized" : "GND_48", "pin_group" : "ALL_POWER_PINS_33;" }, "J2_XF.277" : { "node_name" : "J2_XF.277", "pin_type" : "INOUT", "pin_number" : "277", "pin_name_unsanitized" : "DQS7_C", "pinuse" : "TRI;", "marker_data" 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"pin_name_unsanitized" : "GND_368", "pin_group" : "ALL_POWER_PINS_34;", "pin_name" : "GND_368", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34, "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk" } ], "node_name" : "U1_XF.AC25", "pin_type" : "INOUT", "pin_number" : "AC25" }, "R223_XF.1" : { "node_name" : "R223_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "R223_XF", "pin_name" : "A", "net_name" : "OCL1_FPGA_REFCLK_N_XF", "part_number" : "400-000010-010", "marker_data" : [ { "phys_path" : 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"net_name" : "GND", "refdes" : "C19_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "R8.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R8.1", "marker_data" : [ { "ppath" : "top/page12_i5", "sym_num" : 1, "page_instance" : "I5", "ppath_without_last_instance" : "top/page12", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page12", "path" : "@top_lib.top(sch_1):page12", "phys_page" : "page12", "block" : "top", "page" : "page12" } ], "net_name" : "UNNAMED_12_RESISTOR_I13_A", "pin_name" : "A", "refdes" : "R8", "part_number" : "400-000010-010", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "J1_O1_XF.A21" : { "pin_number" : "A21", "node_name" : "J1_O1_XF.A21", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i29@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_path" : 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"top/page6_i428/xc2_fpga_blk/page11_i770", "sym_num" : 1 } ], "pin_name" : "A", "refdes" : "R155_XF", "net_name" : "GND", "part_number" : "400-000010-133", "node_name" : "R155_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "R81_FL_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page9", "phys_page" : "page9", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i24", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I24" } ], "part_number" : "400-000014-011", "refdes" : "R81_FL_XF", "pin_name" : "B", "net_name" : "UNNAMED_9_LT3071_I30_MARGA_FL", "node_name" : "R81_FL_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "J1_O3_XF.A17" : { "pin_name_unsanitized" : "GND_6", "pinuse" : "GROUND;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i52/ocl_x4_conn_blk/page3_i84", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i52/ocl_x4_conn_blk/page3", "page_instance" : "I84", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i52@top_lib.ocl_x4_conn_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i52@top_lib.ocl_x4_conn_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "page" : "page3", "phys_page" : "page3" } ], "net_name" : "GND", "refdes" : "J1_O3_XF", "pin_name" : "GND_6", "part_number" : "410-000324-001", "node_name" : "J1_O3_XF.A17", "pin_number" : "A17" }, "C13_SP_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I156", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i156", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3" } ], "pin_name" : "A", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I156_A_SP", "refdes" : "C13_SP_XF", "part_number" : "402-000010-006", "node_name" : "C13_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "R7_MP.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I16", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page4", 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"top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "page_instance" : "I98", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "phys_page" : "page3" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "R2_E0_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R2_E0_XF.1", "pin_name" : "A", "refdes" : "R2_E0_XF", "net_name" : "GND", "part_number" : "400-000010-006", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i14", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "page_instance" : "I14", "path" : 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4" } ], "part_number" : "402-000010-001", "net_name" : "PWR_FPGA_3R3V", "pin_name" : "B", "refdes" : "C2_E2_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "J1_E2_XF.B12" : { "pin_type" : "INPUT", "pin_number" : "B12", "node_name" : "J1_E2_XF.B12", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3", "page_instance" : "I101", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i101" } ], "part_number" : "410-000317-001", "pin_name" : "PWRDIS", "refdes" : "J1_E2_XF", "net_name" : "E1S2_3R3V_PWRDIS_XF", "pinuse" : "IN;", "pin_name_unsanitized" : "PWRDIS" }, "R12_FL_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000014-011", "refdes" : "R12_FL_XF", "pin_name" : "A", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I31_B_FL", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3_i30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3", "page_instance" : "I30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page3" } ], "node_name" : "R12_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "R29.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "UNNAMED_3_RESISTOR_I55_B", "refdes" : "R29", "part_number" : "400-000010-006", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top", "ppath" : "top/page3_i55", "sym_num" : 1, "page_instance" : "I55", "ppath_without_last_instance" : "top/page3" } ], "node_name" : "R29.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "C405_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C405_XF.2", "marker_data" : [ { "page_instance" : "I166", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i166", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4" } ], "pin_name" : "B", "refdes" : "C405_XF", "net_name" : "PWR_SDIMM_VDD_XF", "part_number" : "402-000010-001", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "C99_SP_XF.2" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I506", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i506", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null } ], "part_number" : "402-000010-031", "pin_name" : "B", "refdes" : "C99_SP_XF", "net_name" : "GND", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C99_SP_XF.2" }, "U1_XF.P27" : { "pin_group" : "C3_ACTL_7_7;", "pin_name_unsanitized" : "C3_DDR4_ADR4", "marker_data" : [ { "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "sym_num" : 7, "phys_page" : "page9", "page" : "page9", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9" } ], "net_name" : "C3_DDR4_ADR<4>_XF", "pin_name" : "C3_DDR4_ADR4", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.P27", "pin_number" : "P27", "pin_type" : "INOUT" }, "R18_SP_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I159", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i159", "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null } ], "refdes" : "R18_SP_XF", "pin_name" : "A", "net_name" : "GND", "part_number" : "400-000010-006", "node_name" : "R18_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.Y55" : { "pin_name_unsanitized" : "IO_L6P_T0U_N10_AD6P_32", "pin_group" : "ALL_SIGNAL_PINS_22;", "net_name" : "NC", "pin_name" : "IO_L6P_T0U_N10_AD6P_32", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 22, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I46", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30" } ], "node_name" : "U1_XF.Y55", "pin_number" : "Y55", "pin_type" : "INOUT" }, "U2_SD_XF.9" : { "marker_data" : [ { "page_instance" : "I19", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page4_i19", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page4" } ], "part_number" : "450-000059-001", "pin_name" : "PGOOD", "refdes" : "U2_SD_XF", "net_name" : "UNNAMED_4_RESISTOR_I7_A_SD", "pinuse" : "OUT;", "pin_name_unsanitized" : "PGOOD", "pin_number" : "9", "pin_type" : "OUTPUT", "node_name" : "U2_SD_XF.9" }, "J3_XF.45" : { "pin_number" : "45", "pin_type" : "INOUT", "node_name" : "J3_XF.45", "refdes" : "J3_XF", "pin_name" : "DQ26", "net_name" : "C2_DDR4_DQ<26>_XF", "part_number" : "410-000300-001", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8" } ], "pin_name_unsanitized" : "DQ26", "pinuse" : "TRI;" }, "R60_SP_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R60_SP_XF.2", "net_name" : "UNNAMED_11_LTM4650FIXED_I150_MODEPLLIN_SP", "pin_name" : "B", "refdes" : "R60_SP_XF", "part_number" : "400-000014-011", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i138", "sym_num" : 1, "page_instance" : "I138", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "J5.4" : { "node_name" : "J5.4", "pin_number" : "4", "pin_name_unsanitized" : "GND_1", "pinuse" : "GROUND;", "marker_data" : [ { "block" : "top", "page" : "page15", "phys_page" : "page15", "phys_path" : "@top_lib.top(sch_1):page15", "path" : "@top_lib.top(sch_1):page15", "remapped_page" : null, "ppath_without_last_instance" : "top/page15", "page_instance" : "I110", "sym_num" : 1, "ppath" : "top/page15_i110" } ], "pin_name" : "GND_1", "refdes" : "J5", "net_name" : "GND", "part_number" : "410-000316-001" }, "PM4_SP_XF.B9" : { "part_number" : "462-000308-002", "pin_name" : "VOUT2_7", "refdes" : "PM4_SP_XF", "net_name" : "PWR_VCCINT_XF", "marker_data" : [ { "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : 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"top/page6_i428/xc2_fpga_blk/page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_page" : "PAGE7", "block" : "top/xc2_fpga_blk", "page" : "PAGE7" } ], "pin_name_unsanitized" : "C2_DDR4_DQ27", "pin_group" : "C2_LNIB_1_6_57;", "pin_type" : "INOUT", "pin_number" : "H53", "node_name" : "U1_XF.H53" }, "U1_XF.AR4" : { "pin_type" : "INOUT", "pin_number" : "AR4", "node_name" : "U1_XF.AR4", "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_592", "refdes" : "U1_XF", "marker_data" : [ { "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "sym_num" : 35, "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "pin_name_unsanitized" : "GND_592", "pin_group" : "ALL_POWER_PINS_35;" }, "U1_CPLD.F4" : { "pin_number" : "F4", "pin_type" : "INOUT", "node_name" : "U1_CPLD.F4", "pin_name" : "SI5341_FDEC", "net_name" : "SI5341_FDEC", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/cpld_blk", "page" : "page3", "ppath" : "top/page14_i1/cpld_blk/page3_i447", "sym_num" : 1, "page_instance" : "I447", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page3" } ], "pin_name_unsanitized" : "SI5341_FDEC", "pinuse" : "BI;", "pin_group" : "SI5341_1;" }, "C53_FL_XF.1" : { "node_name" : "C53_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null, "page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page5", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I20" } ], "part_number" : "402-000010-028", "net_name" : "PWR_AVTT_RLC_XF", "pin_name" : "A", "refdes" : "C53_FL_XF" }, "R8_E1_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "refdes" : "R8_E1_XF", "net_name" : "E1S1_3R3V_PRSNT_F<0>_XF", "part_number" : "400-000010-007", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i85", "sym_num" : 1, "page_instance" : "I85", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3" } ], "node_name" : "R8_E1_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "C306_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "page_instance" : "I56", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i56", "sym_num" : 1 } ], "part_number" : "402-000015-008", "net_name" : "PWR_VCCINT_XF", "pin_name" : "B", "refdes" : "C306_XF", "node_name" : "C306_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "J3_XF.279" : { "marker_data" : [ { "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180" } ], "net_name" : "GND", "pin_name" : "VSS_74", "refdes" : "J3_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_74", "pinuse" : "UNSPEC;", "pin_number" : "279", "pin_type" : "GROUND", "node_name" : "J3_XF.279" }, "C56_SP_XF.1" : { "node_name" : "C56_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "page_instance" : "I11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i11", "sym_num" : 1, "phys_page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10" } ], "part_number" : "402-000202-001", "refdes" : "C56_SP_XF", "pin_name" : "A", "net_name" : "UNNAMED_10_CAPACITOR_I11_A_SP" }, "R17_MP.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page18_i1/mgmt_pwr_block/page4_i24", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page4", "page_instance" : "I24", "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "remapped_page" : null, "block" : "top/mgmt_pwr_block", "page" : "page4", "phys_page" : "page4" } ], "part_number" : "400-000010-009", "pin_name" : "B", "refdes" : "R17_MP", "net_name" : "P5VSB", "node_name" : "R17_MP.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.BM31" : { "pin_number" : "BM31", "pin_type" : "INOUT", "node_name" : "U1_XF.BM31", "marker_data" : [ { "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "page_instance" : "I52", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i52", "sym_num" : 21 } ], "pin_name" : "IO_L14P_T2L_N2_GC_A04_D20_65", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_21;", "pin_name_unsanitized" : "IO_L14P_T2L_N2_GC_A04_D20_65" }, "U1_E1_XF.27" : { "pin_number" : "27", "pin_type" : "OUTPUT", "node_name" : "U1_E1_XF.27", "part_number" : "450-000345-001", "pin_name" : "Q3_P", "net_name" : "AC_FPGA_CLK_REF_P<1>", "refdes" : "U1_E1_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i37", "sym_num" : 1, "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4" } ], "pinuse" : "OUT;", "pin_name_unsanitized" : "Q3_P" }, "C166_XF.1" : { "node_name" : "C166_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I35", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i35", "sym_num" : 1, "phys_page" : "page21", "block" : "top/xc2_fpga_blk", "page" : "page21", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21" } ], "refdes" : "C166_XF", "pin_name" : "A", "net_name" : "PWR_SDIMM_VDD_XF", "part_number" : "402-000015-008" }, "U1_SP_XF.4" : { "node_name" : "U1_SP_XF.4", "pin_type" : "OUTPUT", "pin_number" : "4", "pinuse" : "OUT;", "pin_name_unsanitized" : "VOUT_EN1", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i168", "sym_num" : 1, "page_instance" : "I168", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3" } ], "part_number" : "450-000302-001", "net_name" : "LTC2975_CPLD_ENB_B", "pin_name" : "VOUT_EN1", "refdes" : "U1_SP_XF" }, "C403_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C403_XF.1", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I164", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i164", "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null } ], "part_number" : "402-000010-001", "pin_name" : "A", "refdes" : "C403_XF", "net_name" : "GND", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "J2_XF.88" : { "refdes" : "J2_XF", "pin_name" : "VDD_12", "net_name" : "PWR_SDIMM_VDD_XF", "part_number" : "410-000300-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6" } ], "pin_name_unsanitized" : "VDD_12", "pinuse" : "POWER;", "pin_type" : "POWER", "pin_number" : "88", "node_name" : "J2_XF.88" }, "C102_XF.1" : { "part_number" : "402-000010-035", "pin_name" : "A", "net_name" : "AC_E1S0_PET_P<7>_XF", "refdes" : "C102_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_page" : "page12", "block" : "top/xc2_fpga_blk", "page" : "page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i64", "sym_num" : 1, "page_instance" : "I64", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C102_XF.1" }, "C80_SP_XF.2" : { "part_number" : "402-000020-003", "refdes" : "C80_SP_XF", "pin_name" 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"pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i24", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "page_instance" : "I24" } ], "part_number" : "400-000010-010", "pin_name" : "B", "net_name" : "P3R3V", "refdes" : "R58_FL_XF", "node_name" : "R58_FL_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "R107_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R107_XF.2", "marker_data" : [ { "phys_page" : "page17", "block" : "top/xc2_fpga_blk", "page" : "page17", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "page_instance" : "I94", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i94", "sym_num" : 1 } ], "pin_name" : "B", "refdes" : "R107_XF", "net_name" : "UNNAMED_17_RESISTOR_I61_A_XF", "part_number" : "400-000010-097", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "U1_XF.BL36" : { "pin_type" : "INOUT", "pin_number" : "BL36", "node_name" : "U1_XF.BL36", "refdes" : "U1_XF", "pin_name" : "IO_L16P_T2U_N6_QBC_AD3P_67", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20, "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30" } ], "pin_name_unsanitized" : "IO_L16P_T2U_N6_QBC_AD3P_67", "pin_group" : "ALL_SIGNAL_PINS_20;" }, "C50.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C50.2", "net_name" : "UNNAMED_4_BYPASSCAPNPOL_I105_B", "pin_name" : "B", "refdes" : "C50", "part_number" : "402-000010-001", "marker_data" : [ { "ppath" : "top/page4_i105", "sym_num" : 1, "page_instance" : "I105", "ppath_without_last_instance" : "top/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "R126_SP_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page12", "phys_page" : "page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page12", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page12", "page_instance" : "I35", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page12_i35" } ], "pin_name" : "A", "refdes" : "R126_SP_XF", "net_name" : "EMC1428_ALERT_OD_F", "part_number" : "400-000010-015", "node_name" : "R126_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_XF.A4" : { "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_1", "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "sym_num" : 33 } ], "net_name" : "GND", "pin_name" : "GND_1", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.A4", "pin_number" : "A4", "pin_type" : "INOUT" }, "C124_XF.2" : { "part_number" : "402-000010-035", "net_name" : "E1S0_PET_N<5>_XF", "pin_name" : "B", "refdes" : "C124_XF", "marker_data" : [ { "page_instance" : "I65", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i65", "sym_num" : 1, "phys_page" : "page12", "block" : "top/xc2_fpga_blk", "page" : "page12", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C124_XF.2" }, "U1_XF.AC51" : { "pin_group" : "ALL_SIGNAL_PINS_22;", "pin_name_unsanitized" : "IO_T2U_N12_32", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I46", "sym_num" : 22, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null } ], "part_number" : "450-000340-001", "pin_name" : "IO_T2U_N12_32", "refdes" : "U1_XF", "net_name" : "NC", "node_name" : "U1_XF.AC51", "pin_number" : "AC51", "pin_type" : "INOUT" }, "PM5_SP_XF.A4" : { "node_name" : "PM5_SP_XF.A4", "pin_type" : "POWER", "pin_number" : "A4", "pin_name_unsanitized" : "VOUT1_4", "pinuse" : "POWER;", "pin_name" : "VOUT1_4", "refdes" : "PM5_SP_XF", "net_name" : "PWR_VCCINT_XF", "part_number" : "462-000308-002", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page5", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I80" } ] }, "U1_XF.C36" : { "node_name" : "U1_XF.C36", "pin_type" : "INOUT", "pin_number" : "C36", "pin_name_unsanitized" : "IO_L11N_T1U_N9_GC_71", "pin_group" : "ALL_SIGNAL_PINS_25;", "pin_name" : "IO_L11N_T1U_N9_GC_71", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 25, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i59", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I59", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31" } ] }, "F1_SP_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "F1_SP_XF.2", "marker_data" : [ { "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I136", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i136" } ], "part_number" : "403-000006-003", "net_name" : "P12V_4650_BL_SP", "pin_name" : "B", "refdes" : "F1_SP_XF", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "U1_XF.CB47" : { "pin_type" : "INOUT", "pin_number" : "CB47", "node_name" : "U1_XF.CB47", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "sym_num" : 38, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I73" } ], "net_name" : "GND", "pin_name" : "GND_1073", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_38;", "pin_name_unsanitized" : "GND_1073" }, "J1_XF.26" : { "node_name" : "J1_XF.26", "pin_number" : "26", "pin_type" : "GROUND", "pin_name_unsanitized" : "VSS_69", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4" } ], "net_name" : "GND", "pin_name" : "VSS_69", "refdes" : "J1_XF", "part_number" : "410-000300-001" }, "PM2_SP_XF.V6" : { "part_number" : "462-000309-001", "net_name" : "GND", "refdes" : "PM2_SP_XF", "pin_name" : "GND_85", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I459", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459" } ], "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_85", "pin_number" : "V6", "node_name" : "PM2_SP_XF.V6" }, "J1_O3_XF.B11" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_11", "part_number" : "410-000324-001", "net_name" : "GND", "refdes" : "J1_O3_XF", "pin_name" : "GND_11", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i52/ocl_x4_conn_blk/page3_i84", "sym_num" : 1, "page_instance" : "I84", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i52/ocl_x4_conn_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i52@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i52@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk" } ], "node_name" : "J1_O3_XF.B11", "pin_number" : "B11" }, "C319_XF.1" : { "part_number" : "402-000015-006", "pin_name" : "A", "net_name" : "PWR_VCCINT_XF", "refdes" : "C319_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i130", "sym_num" : 1, "page_instance" : "I130", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C319_XF.1" }, "U1_XF.BU27" : { "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "VCCO_62_1", "net_name" : "PWR_SDIMM_VDD_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i62", "sym_num" : 28, "page_instance" : "I62", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "phys_page" : "page22", "block" : "top/xc2_fpga_blk", "page" : "page22" } ], "pin_name_unsanitized" : "VCCO_62_1", "pin_group" : "ALL_POWER_PINS_28;", "pin_number" : "BU27", "pin_type" : "INOUT", "node_name" : "U1_XF.BU27" }, "U1_CPLD.H5" : { "marker_data" : [ { "block" : "top/cpld_blk", "page" : "page5", "phys_page" : "page5", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page5", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page5", "page_instance" : "I61", "sym_num" : 2, "ppath" : "top/page14_i1/cpld_blk/page5_i61" } ], "part_number" : "450-000313-001", "net_name" : "CLK125M_FROM_CPLD", "pin_name" : "CLK125M_FROM_CPLD", "refdes" : "U1_CPLD", "pin_group" : "JT_GP_2;", "pinuse" : "BI;", "pin_name_unsanitized" : "CLK125M_FROM_CPLD", "pin_number" : "H5", "pin_type" : "INOUT", "node_name" : "U1_CPLD.H5" }, "C260_XF.1" : { "node_name" : "C260_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I116", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i116", "block" : "top/xc2_fpga_blk", "page" : "page14", "phys_page" : "page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null } ], "pin_name" : "A", "net_name" : "AC_OCL0_PET_N<1>_XF", "refdes" : "C260_XF", "part_number" : "402-000010-035" }, "R75_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R75_XF.2", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I73", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i73", "block" : "top/xc2_fpga_blk", "page" : "page17", "phys_page" : "page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null } ], "pin_name" : "B", "refdes" : "R75_XF", "net_name" : "UNNAMED_17_RESISTOR_I54_A_XF", "part_number" : "400-000010-065", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "C46_CPLD.1" : { "node_name" : "C46_CPLD.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/cpld_blk", "phys_page" : "page7", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page7_i15", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I15" } ], "part_number" : "402-000010-001", "refdes" : "C46_CPLD", "pin_name" : "A", "net_name" : "GND" }, "C23_E0_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C23_E0_XF.1", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "page_instance" : "I51", "sym_num" : 1, "ppath" : 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"sym_num" : 33, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I68" } ], "pin_name_unsanitized" : "GND_128", "pin_group" : "ALL_POWER_PINS_33;" }, "U1_XF.BW9" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i86", "sym_num" : 29, "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_page" : "page20", "page" : "page20", "block" : "top/xc2_fpga_blk" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "MGTAVTT_RS_13", "net_name" : "PWR_AVTT_RS_XF", "pin_group" : "ALL_POWER_PINS_29;", "pin_name_unsanitized" : "MGTAVTT_RS_13", "pin_type" : "INOUT", "pin_number" : "BW9", "node_name" : "U1_XF.BW9" }, "U5_FL_XF.29" : { "marker_data" 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"pin_name_unsanitized" : "E1S0_PER_N0", "pin_group" : "ALL_SIGNAL_PINS_9;", "pin_type" : "INOUT", "pin_number" : "F3", "node_name" : "U1_XF.F3" }, "U1_CPLD.H9" : { "node_name" : "U1_CPLD.H9", "pin_number" : "H9", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_12", "part_number" : "450-000313-001", "net_name" : "GND", "refdes" : "U1_CPLD", "pin_name" : "GND_12", "marker_data" : [ { "page" : "page7", "block" : "top/cpld_blk", "phys_page" : "page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I151", "sym_num" : 7, "ppath" : "top/page14_i1/cpld_blk/page7_i151" } ] }, "C71.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "P3R3V", "refdes" : "C71", "part_number" : "402-000010-032", "marker_data" : [ { "phys_path" : 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: "INOUT", "node_name" : "U1_XF.A54" }, "PM4_SP_XF.D1" : { "node_name" : "PM4_SP_XF.D1", "pin_type" : "POWER", "pin_number" : "D1", "pin_name_unsanitized" : "GND_5", "pinuse" : "POWER;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page4", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "page_instance" : "I79" } ], "refdes" : "PM4_SP_XF", "pin_name" : "GND_5", "net_name" : "GND", "part_number" : "462-000308-002" }, "J1_P0_XF.B6" : { "pin_number" : "B6", "pin_type" : "INPUT", "node_name" : "J1_P0_XF.B6", "part_number" : "410-000324-001", "net_name" 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"net_name" : "NC", "part_number" : "450-000340-001" }, "U1_XF.D14" : { "pin_name" : "GND_56", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I68", "sym_num" : 33, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "pin_name_unsanitized" : "GND_56", "pin_group" : "ALL_POWER_PINS_33;", "pin_number" : "D14", "pin_type" : "INOUT", "node_name" : "U1_XF.D14" }, "C378_XF.1" : { "node_name" : "C378_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "remapped_page" : null, "phys_path" : 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"J1_O3_XF.B15", "pin_type" : "INPUT", "pin_number" : "B15" }, "J1_XF.254" : { "pin_type" : "GROUND", "pin_number" : "254", "node_name" : "J1_XF.254", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4" } ], "net_name" : "GND", "pin_name" : "VSS_5", "refdes" : "J1_XF", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_5", "pinuse" : "UNSPEC;" }, "C327_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C327_XF.1", "net_name" : "AC_E1S3_PET_P<5>_XF", "pin_name" : "A", "refdes" : "C327_XF", "part_number" : "402-000010-035", "marker_data" : [ { "phys_path" : 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"part_number" : "400-000010-090", "refdes" : "R54_XF", "pin_name" : "A", "net_name" : "GND", "marker_data" : [ { "page" : "page22", "block" : "top/xc2_fpga_blk", "phys_page" : "page22", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "page_instance" : "I41", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i41" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "C102_SP_XF.1" : { "node_name" : "C102_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i492", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : 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"C80_SP_XF", "net_name" : "INTVCC_4650_BL_SP" }, "U1_XF.BH2" : { "pin_number" : "BH2", "pin_type" : "INOUT", "node_name" : "U1_XF.BH2", "pin_name" : "GND_863", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "sym_num" : 37, "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24" } ], "pin_name_unsanitized" : "GND_863", "pin_group" : "ALL_POWER_PINS_37;" }, "U1_XF.BJ60" : { "pin_number" : "BJ60", "pin_type" : "INOUT", "node_name" : "U1_XF.BJ60", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L3N_T0L_N5_AD15N_25", "net_name" : "NC", "marker_data" : [ { "ppath" : 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"IO_L15P_T2L_N4_AD11P_28", "pin_group" : "ALL_SIGNAL_PINS_18;" }, "U1_XF.BN38" : { "pin_number" : "BN38", "pin_type" : "INOUT", "node_name" : "U1_XF.BN38", "marker_data" : [ { "sym_num" : 20, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I49", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30" } ], "net_name" : "NC", "pin_name" : "IO_L12N_T1U_N11_GC_67", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_20;", "pin_name_unsanitized" : "IO_L12N_T1U_N11_GC_67" }, "U1_XF.AU50" : { "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L13N_T2L_N1_GC_QBC_27", "refdes" : "U1_XF", "marker_data" : [ { "page_instance" : "I51", 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"pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C178_SP_XF.2" }, "U7_XF.12" : { "pin_name" : "OE0_F", "net_name" : "OCL0_3R3V_CKEN_F<1>_XF", "refdes" : "U7_XF", "part_number" : "450-000345-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_page" : "page29", "block" : "top/xc2_fpga_blk", "page" : "page29", "ppath" : "top/page6_i428/xc2_fpga_blk/page29_i89", "sym_num" : 1, "page_instance" : "I89", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page29" } ], "pin_name_unsanitized" : "OE0_F", "pinuse" : "IN;", "pin_type" : "INPUT", "pin_number" : "12", "node_name" : "U7_XF.12" }, "J1_XF.147" : { "pin_name_unsanitized" : "VSS_7", "pinuse" : "UNSPEC;", "pin_name" : "VSS_7", "refdes" : "J1_XF", "net_name" : "GND", "part_number" : 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"refdes" : "J3_XF", "net_name" : "C2_DDR4_ODT<1>_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null, "page" : "page8", "block" : "top/xc2_fpga_blk", "phys_page" : "page8" } ], "pinuse" : "IN;", "pin_name_unsanitized" : "ODT1_NC", "pin_number" : "91", "pin_type" : "INPUT", "node_name" : "J3_XF.91" }, "U1_XF.AL8" : { "pin_type" : "INOUT", "pin_number" : "AL8", "node_name" : "U1_XF.AL8", "marker_data" : [ { "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" 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"INOUT", "node_name" : "U1_XF.BT8" }, "U1_XF.BY39" : { "pin_type" : "INOUT", "pin_number" : "BY39", "node_name" : "U1_XF.BY39", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L24P_T3U_N10_66", "net_name" : "NC", "marker_data" : [ { "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I55", "sym_num" : 15, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i55" } ], "pin_name_unsanitized" : "IO_L24P_T3U_N10_66", "pin_group" : "ALL_SIGNAL_PINS_15;" }, "C10_E3_XF.1" : { "node_name" : "C10_E3_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "phys_path" : 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"pin_name_unsanitized" : "VIN_SNS", "pinuse" : "IN;", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I168", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i168" } ], "pin_name" : "VIN_SNS", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I177_A_SP", "refdes" : "U1_SP_XF", "part_number" : "450-000302-001" }, "U1_XF.T14" : { "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_223", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I69", "sym_num" : 34, "ppath" : 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"167", "pin_type" : "GROUND" }, "J1_P0_XF.GH1" : { "node_name" : "J1_P0_XF.GH1", "pin_number" : "GH1", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GH1", "marker_data" : [ { "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3" } ], "part_number" : "410-000324-001", "refdes" : "J1_P0_XF", "pin_name" : "GH1", "net_name" : "GND" }, "U1_XF.AW63" : { "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_687", "refdes" : "U1_XF", "marker_data" : [ { "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "sym_num" : 36 } ], "pin_name_unsanitized" : "GND_687", "pin_group" : "ALL_POWER_PINS_36;", "pin_type" : "INOUT", "pin_number" : "AW63", "node_name" : "U1_XF.AW63" }, "U5_FL_XF.15" : { "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page8", "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8_i30", "sym_num" : 1, "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page8" } ], "part_number" : "450-000057-001", "refdes" : "U5_FL_XF", "pin_name" : "VOUT_15", "net_name" : "PWR_AVTT_RUC_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT_15", "pin_type" : "POWER", "pin_number" : "15", "node_name" : "U5_FL_XF.15" }, "U1_XF.U55" : { "node_name" : "U1_XF.U55", "pin_type" : "INOUT", "pin_number" : "U55", "pin_name_unsanitized" : "IO_L17P_T2U_N8_AD10P_33", "pin_group" : "ALL_SIGNAL_PINS_22;", "net_name" : "NC", "pin_name" : "IO_L17P_T2U_N8_AD10P_33", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "page_instance" : "I46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "sym_num" : 22 } ] }, "PM7_SP_XF.D5" : { "pin_name_unsanitized" : "VFB1", "pinuse" : "IN;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I150", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i150", "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null } ], "pin_name" : "VFB1", "net_name" : "VFB_4650_SP", "refdes" : "PM7_SP_XF", "part_number" : "462-000308-002", "node_name" : "PM7_SP_XF.D5", "pin_type" : "INPUT", "pin_number" : "D5" }, "R60_SP_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000014-011", "pin_name" : "A", "net_name" : "CKO_LTM4650_PM3_SP", "refdes" : "R60_SP_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "phys_page" : "page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I138", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i138" } ], "node_name" : "R60_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_XF.AF32" : { "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "GND_444", "net_name" : "GND", "marker_data" : [ { "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I70", "sym_num" : 35, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70" } ], "pin_name_unsanitized" : "GND_444", "pin_group" : "ALL_POWER_PINS_35;", "pin_type" : "INOUT", "pin_number" : "AF32", "node_name" : "U1_XF.AF32" }, "C379_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000015-007", "refdes" : "C379_XF", "pin_name" : "B", "net_name" : "GND", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I65", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i65" } ], "node_name" : "C379_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_CPLD.F9" : { "pin_group" : "FP_CFG_4;", "pin_name_unsanitized" : "CPLD_FPGA_DVAL", "pinuse" : "BI;", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page6", "page_instance" : "I129", "sym_num" : 4, "ppath" : "top/page14_i1/cpld_blk/page6_i129", "block" : "top/cpld_blk", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page6", "remapped_page" : null } ], "pin_name" : "CPLD_FPGA_DVAL", "refdes" : "U1_CPLD", "net_name" : "CPLD_FPGA_DVAL_1", "part_number" : "450-000313-001", "node_name" : "U1_CPLD.F9", "pin_type" : "INOUT", "pin_number" : "F9" }, "U1_XF.R57" : { "pin_number" : "R57", "pin_type" : "INOUT", "node_name" : "U1_XF.R57", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "sym_num" : 22, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I46" } ], "net_name" : "NC", "pin_name" : "IO_L14P_T2L_N2_GC_33", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_22;", "pin_name_unsanitized" : "IO_L14P_T2L_N2_GC_33" }, "C77_FL_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-028", "net_name" : "GND", "pin_name" : "B", "refdes" : "C77_FL_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page9", "phys_page" : "page9", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I20" } ], "node_name" : "C77_FL_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "J3_XF.129" : { "part_number" : "410-000300-001", "refdes" : "J3_XF", "pin_name" : "VSS_55", "net_name" : "GND", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "block" : "top/xc2_fpga_blk", "page" : "page8", "phys_page" : "page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "remapped_page" : null } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_55", "pin_type" : "GROUND", "pin_number" : "129", "node_name" : "J3_XF.129" }, "J1_E2_XF.B22" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_21", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i101", "sym_num" : 1, "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3" } ], "part_number" : "410-000317-001", "net_name" : "GND", "pin_name" : "GND_21", "refdes" : "J1_E2_XF", "node_name" : "J1_E2_XF.B22", "pin_number" : "B22" }, "R12_FL_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3_i30", "sym_num" : 1, "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page3" } ], "part_number" : "400-000014-011", "refdes" : "R12_FL_XF", "pin_name" : "B", "net_name" : "UNNAMED_3_LT3071_I32_MARGA_FL", "node_name" : "R12_FL_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C93_XF.2" : { "part_number" : "402-000010-028", "pin_name" : "B", "net_name" : "GND", "refdes" : "C93_XF", "marker_data" : [ { "phys_page" : "page20", "page" : "page20", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i70", "sym_num" : 1 } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C93_XF.2" }, "U1_XF.F56" : { "pin_type" : "INOUT", "pin_number" : "F56", "node_name" : "U1_XF.F56", "part_number" : "450-000340-001", "pin_name" : "C2_DDR4_DQ34", "net_name" : "C2_DDR4_DQ<34>_XF", "refdes" : "U1_XF", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "PAGE7", "phys_page" : "PAGE7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page7", "page_instance" : "I2425", "sym_num" : 61, "ppath" : "top/page6_i428/xc2_fpga_blk/page7_i2425" } ], "pin_name_unsanitized" : "C2_DDR4_DQ34", "pin_group" : "C2_LNIB_1_6_57;" }, "U1_XF.C44" : { "node_name" : "U1_XF.C44", "pin_type" : "INOUT", "pin_number" : "C44", "pin_group" : "ALL_SIGNAL_PINS_26;", "pin_name_unsanitized" : "IO_L15P_T2L_N4_AD11P_37", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "sym_num" : 26, "page_instance" : "I58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" 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: "INOUT", "pin_name_unsanitized" : "IO_L24P_T3U_N10_71", "pin_group" : "ALL_SIGNAL_PINS_25;", "part_number" : "450-000340-001", "pin_name" : "IO_L24P_T3U_N10_71", "refdes" : "U1_XF", "net_name" : "NC", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i59", "sym_num" : 25, "page_instance" : "I59", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk" } ] }, "PM4_ND_XF.B7" : { "pin_type" : "POWER", "pin_number" : "B7", "node_name" : "PM4_ND_XF.B7", "part_number" : "462-000304-001", "pin_name" : "GND_13", "refdes" : "PM4_ND_XF", "net_name" : "GND", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i20", "sym_num" : 2, "page_instance" : "I20", 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"node_name" : "C3_E3_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "R84_FL_XF.1" : { "part_number" : "400-000014-011", "refdes" : "R84_FL_XF", "pin_name" : "A", "net_name" : "VS_AVCC_RN_LIN_FL", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "page_instance" : "I40" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R84_FL_XF.1" }, "PM4_SP_XF.F11" : { "node_name" : "PM4_SP_XF.F11", "pin_type" : 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"pin_number" : "1", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "net_name" : "DAC_AVTT_LIN_XF", "pin_name" : "A", "refdes" : "R29_FL_XF", "part_number" : "400-000010-006", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i26", "sym_num" : 1, "page_instance" : "I26", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5" } ] }, "C11_SP_XF.3" : { "pin_name_unsanitized" : "B2", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : 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"top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5_i41", "sym_num" : 1, "phys_page" : "page5", "page" : "page5", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5" } ], "node_name" : "C10_SP_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_XF.K56" : { "pin_number" : "K56", "pin_type" : "INOUT", "node_name" : "U1_XF.K56", "part_number" : "450-000340-001", "net_name" : "PWR_NDIMM_VDD_XF", "pin_name" : "VCCO_34_2", "refdes" : "U1_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "phys_page" : "page21", "page" : "page21", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i67", "sym_num" : 27, "page_instance" : "I67", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21" } ], "pin_name_unsanitized" : "VCCO_34_2", "pin_group" : "ALL_POWER_PINS_27;" }, "C68_SP_XF.1" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I181", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i181" } ], "part_number" : "402-000010-016", "refdes" : "C68_SP_XF", "pin_name" : "A", "net_name" : "GND", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C68_SP_XF.1" }, "U1_XF.BR11" : { "pin_group" : "ALL_SIGNAL_PINS_14;", "pin_name_unsanitized" : "MGTYTXP2_221", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i56", "sym_num" : 14, "page_instance" : "I56", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "MGTYTXP2_221", "net_name" : "NC", "node_name" : "U1_XF.BR11", "pin_number" : "BR11", "pin_type" : "INOUT" }, "C200_SP_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page11", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i147", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I147" } ], "refdes" : "C200_SP_XF", "pin_name" : "B", "net_name" : "CMP_4650_SP", "part_number" : "402-000202-005", "node_name" : "C200_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_XF.BB7" : { "part_number" : "450-000340-001", "pin_name" : "GND_738", "refdes" : "U1_XF", "net_name" : "GND", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "sym_num" : 36, "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk" } ], "pin_name_unsanitized" : "GND_738", "pin_group" : "ALL_POWER_PINS_36;", "pin_number" : "BB7", "pin_type" : "INOUT", "node_name" : "U1_XF.BB7" }, "U1_XF.AB35" : { "pin_number" : "AB35", "pin_type" : "INOUT", "node_name" : "U1_XF.AB35", "pin_name" : "VCCINT_60", "net_name" : "PWR_VCCINT_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "sym_num" : 31, "page_instance" : "I186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23" } ], "pin_name_unsanitized" : "VCCINT_60", "pin_group" : "ALL_POWER_PINS_31;" }, "U1_XF.BT48" : { "node_name" : "U1_XF.BT48", "pin_number" : "BT48", "pin_type" : "INOUT", "pin_name_unsanitized" : "IO_L5N_T0U_N9_AD14N_20", "pin_group" : "ALL_SIGNAL_PINS_17;", "pin_name" : "IO_L5N_T0U_N9_AD14N_20", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "page_instance" : "I50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "sym_num" : 17 } ] }, "C62_FL_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "net_name" : "PWR_AVTT_RS_XF", "refdes" : "C62_FL_XF", "part_number" : "402-000010-028", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page6", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6_i18", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page6", "page_instance" : "I18" } ], "node_name" : "C62_FL_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_XF.AL48" : { "node_name" : "U1_XF.AL48", "pin_type" : "INOUT", "pin_number" : "AL48", "pin_group" : "ALL_SIGNAL_PINS_24;", "pin_name_unsanitized" : "IO_L18N_T2U_N11_AD2N_29", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54", "sym_num" : 24, "page_instance" : "I54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk" } ], "pin_name" : "IO_L18N_T2U_N11_AD2N_29", "refdes" : "U1_XF", "net_name" : "NC", "part_number" : "450-000340-001" }, "C77.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "ppath_without_last_instance" : "top/page19", "page_instance" : "I92", "sym_num" : 1, "ppath" : "top/page19_i92", "page" : "page19", "block" : "top", "phys_page" : "page19", "path" : "@top_lib.top(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page19", "remapped_page" : null } ], "part_number" : "402-000500-005", "refdes" : "C77", "pin_name" : "B", "net_name" : "GND", "node_name" : "C77.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "R116_SP_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R116_SP_XF.1", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I26", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i26", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null } ], "part_number" : "400-000014-011", "pin_name" : "A", "refdes" : "R116_SP_XF", "net_name" : "UNNAMED_7_LTM4671_I36_MODECLKIN3_SP", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "R1_E1_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R1_E1_XF.2", "net_name" : "UNNAMED_3_RESISTOR_I70_B_E1", "pin_name" : "B", "refdes" : "R1_E1_XF", "part_number" : "400-000014-012", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "page_instance" : "I70", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i70" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "U1_XF.F43" : { "pin_type" : "INOUT", "pin_number" : "F43", "node_name" : "U1_XF.F43", "marker_data" : [ { "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "page_instance" : "I58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "sym_num" : 26 } ], "refdes" : "U1_XF", "pin_name" : "IO_L24N_T3U_N11_38", "net_name" : "NC", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_26;", "pin_name_unsanitized" : "IO_L24N_T3U_N11_38" }, "U1_XF.A7" : { "pin_number" : "A7", "pin_type" : "INOUT", "node_name" : "U1_XF.A7", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page12", "phys_page" : "page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I283", "sym_num" : 9, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283" } ], "net_name" : "AC_E1S0_PET_P<3>_XF", "pin_name" : "E1S0_PET_P3", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_9;", "pin_name_unsanitized" : "E1S0_PET_P3" }, "C19.1" : { "part_number" : "402-000010-026", "pin_name" : "A", "refdes" : "C19", "net_name" : "VDDO9", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page10", "phys_page" : "page10", "page" : "page10", "block" : "top", "ppath" : "top/page10_i131", "sym_num" : 1, "page_instance" : "I131", "ppath_without_last_instance" : "top/page10" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C19.1" }, "R51_SP_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R51_SP_XF.2", "part_number" : "400-000010-010", "net_name" : "IS_VCCINTLL_SW_N_SP", "pin_name" : "B", "refdes" : "R51_SP_XF", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "page_instance" : "I39", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i39" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "C3_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C3_XF.2", "marker_data" : [ { "phys_page" : "page23", "block" : "top/xc2_fpga_blk", "page" : "page23", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : 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"node_name" : "C5_E3_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_XF.BG49" : { "node_name" : "U1_XF.BG49", "pin_number" : "BG49", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_20;", "pin_name_unsanitized" : "IO_L3N_T0L_N5_AD15N_24", "marker_data" : [ { "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20, "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30" } ], "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L3N_T0L_N5_AD15N_24", "refdes" : "U1_XF" }, "R164_XF.1" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : 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: "J1_PX1_XF", "net_name" : "GND", "pin_name" : "MH2", "part_number" : "410-000328-001", "pin_name_unsanitized" : "MH2", "pinuse" : "GROUND;" }, "U1_XF.CA4" : { "node_name" : "U1_XF.CA4", "pin_type" : "INOUT", "pin_number" : "CA4", "pin_group" : "ALL_POWER_PINS_38;", "pin_name_unsanitized" : "GND_1049", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73", "sym_num" : 38, "page_instance" : "I73", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24" } ], "net_name" : "GND", "pin_name" : "GND_1049", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "R116_CPLD.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "refdes" : "R116_CPLD", "net_name" : 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} ], "part_number" : "400-000010-097", "pin_name" : "B", "refdes" : "R138_XF", "net_name" : "GND", "node_name" : "R138_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "TP17.1" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "\\1\\", "part_number" : "410-000021-001", "net_name" : "GND", "pin_name" : "1", "refdes" : "TP17", "marker_data" : [ { "ppath" : "top/page2_i57", "sym_num" : 1, "page_instance" : "I57", "ppath_without_last_instance" : "top/page2", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page2", "phys_path" : "@top_lib.top(sch_1):page2", "phys_page" : "page2", "page" : "page2", "block" : "top" } ], "node_name" : "TP17.1", "pin_number" : "1", "pin_type" : "POWER" }, "J1_E0_XF.B13" : { "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, 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"pin_number" : "2", "pin_type" : "ANALOG", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "refdes" : "R20_XF", "net_name" : "C1_DDR4_SA<2>_XF", "part_number" : "400-000014-011", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page16_i76", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page16", "page_instance" : "I76", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "remapped_page" : null, "page" : "page16", "block" : "top/xc2_fpga_blk", "phys_page" : "page16" } ] }, "U1_XF.K57" : { "pin_group" : "C2_ACTL_6_6;", "pin_name_unsanitized" : "C2_DDR4_BG0", "marker_data" : [ { "page" : "page7", "block" : "top/xc2_fpga_blk", "phys_page" : "page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page7", "phys_path" : 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"pin_type" : "ANALOG", "pin_number" : "2" }, "U1_FL_XF.29" : { "node_name" : "U1_FL_XF.29", "pin_type" : "POWER", "pin_number" : "29", "pin_name_unsanitized" : "GND_TAB", "pinuse" : "POWER;", "pin_name" : "GND_TAB", "net_name" : "GND", "refdes" : "U1_FL_XF", "part_number" : "450-000057-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null, "page" : "page5", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page5", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I30" } ] }, "PM1_SP_XF.B7" : { "refdes" : "PM1_SP_XF", "net_name" : "GND", "pin_name" : "GND_15", "part_number" : "462-000309-001", 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: "page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I70", "sym_num" : 35, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70" } ], "pin_name" : "GND_538", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.AL54", "pin_number" : "AL54", "pin_type" : "INOUT" }, "C44_XF.2" : { "node_name" : "C44_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_page" : "page11", "block" : "top/xc2_fpga_blk", "page" : "page11", "ppath" : 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"INOUT" }, "J3_XF.284" : { "net_name" : "P3R3V", "pin_name" : "VDDSPD", "refdes" : "J3_XF", "part_number" : "410-000300-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk" } ], "pin_name_unsanitized" : "VDDSPD", "pinuse" : "POWER;", "pin_number" : "284", "pin_type" : "POWER", "node_name" : "J3_XF.284" }, "R17_SP_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : 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"U1_XF.B34", "pin_number" : "B34", "pin_type" : "INOUT" }, "U1_XF.T47" : { "pin_group" : "ALL_SIGNAL_PINS_27;", "pin_name_unsanitized" : "IO_T0U_N12_VRP_36", "marker_data" : [ { "sym_num" : 27, "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i67", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "page_instance" : "I67", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "remapped_page" : null, "page" : "page21", "block" : "top/xc2_fpga_blk", "phys_page" : "page21" } ], "refdes" : "U1_XF", "pin_name" : "IO_T0U_N12_VRP_36", "net_name" : "UNNAMED_21_RESISTOR_I25_B_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.T47", "pin_number" : "T47", "pin_type" : "INOUT" }, "C389_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i48", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "page_instance" : "I48", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page15", "phys_page" : "page15" } ], "refdes" : "C389_XF", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000010-001", "node_name" : "C389_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "C78_FL_XF.2" : { "part_number" : "402-000010-028", "pin_name" : "B", "refdes" : "C78_FL_XF", "net_name" : "GND", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null, "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page9", "phys_page" : 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: "PWR_3R3V_VACT_RX", "refdes" : "J2_P1_XF" }, "J2_XF.231" : { "node_name" : "J2_XF.231", "pin_type" : "POWER", "pin_number" : "231", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_11", "marker_data" : [ { "phys_page" : "page6", "block" : "top/xc2_fpga_blk", "page" : "page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1 } ], "part_number" : "410-000300-001", "pin_name" : "VDD_11", "net_name" : "PWR_SDIMM_VDD_XF", "refdes" : "J2_XF" }, "J1_E0_XF.A22" : { "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3_i101", "sym_num" : 1, "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3", 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"marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4_i5", "sym_num" : 1, "page_instance" : "I5", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "NS3_ND_XF.1" }, "U1_XF.Y61" : { "pin_name" : "GND_314", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : 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"page8", "block" : "top/xc2_fpga_blk", "page" : "page8" } ], "node_name" : "J3_XF.254", "pin_number" : "254", "pin_type" : "GROUND" }, "J1_XF.176" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_85", "part_number" : "410-000300-001", "pin_name" : "VSS_85", "refdes" : "J1_XF", "net_name" : "GND", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1 } ], "node_name" : "J1_XF.176", "pin_number" : "176", "pin_type" : "GROUND" }, "J1_O3_XF.B10" : { "marker_data" : [ { "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "remapped_page" : null, "path" : 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I154", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23" } ], "node_name" : "C72_XF.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_SP_XF.41" : { "node_name" : "U1_SP_XF.41", "pin_number" : "41", "pin_type" : "INPUT", "pin_name_unsanitized" : "ISENSEP0", "pinuse" : "IN;", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "page_instance" : "I168", "ppath_without_last_instance" : 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"part_number" : "450-000162-001", "pin_name" : "GND", "refdes" : "U5_SP_XF", "net_name" : "GND", "marker_data" : [ { "phys_page" : "page8", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page8", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "page_instance" : "I102", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8_i102", "sym_num" : 1 } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "GND", "pin_type" : "POWER", "pin_number" : "5", "node_name" : "U5_SP_XF.5" }, "PM1_SP_XF.U6" : { "node_name" : "PM1_SP_XF.U6", "pin_number" : "U6", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_84", "part_number" : "462-000309-001", "refdes" : "PM1_SP_XF", "pin_name" : "GND_84", "net_name" : "GND", "marker_data" : [ { "page_instance" : "I11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "sym_num" : 5, "phys_page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7" } ] }, "U1_XF.AD29" : { "pin_type" : "INOUT", "pin_number" : "AD29", "node_name" : "U1_XF.AD29", "marker_data" : [ { "sym_num" : 31, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I186", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : 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"phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8" } ] }, "R14_SP_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000014-011", "pin_name" : "B", "net_name" : "UNNAMED_3_LTC2975_I168_VINISP2975_SP", "refdes" : "R14_SP_XF", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "page_instance" : "I193", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i193", "sym_num" : 1 } ], "node_name" : "R14_SP_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "R21_CPLD.1" : { "node_name" : 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"J4_XF", "part_number" : "410-000300-001", "node_name" : "J4_XF.150", "pin_type" : "INOUT", "pin_number" : "150" }, "U1_XF.AC7" : { "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_362", "marker_data" : [ { "phys_page" : "page24", "block" : "top/xc2_fpga_blk", "page" : "page24", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34 } ], "part_number" : "450-000340-001", "pin_name" : "GND_362", "net_name" : "GND", "refdes" : "U1_XF", "node_name" : "U1_XF.AC7", "pin_number" : "AC7", "pin_type" : "INOUT" }, "J2_XF.39" : { "part_number" : "410-000300-001", "pin_name" : "VSS_6", "net_name" : "GND", "refdes" : "J2_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : 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"pin_number" : "2", "pin_type" : "ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-061", "refdes" : "R9_MP", "pin_name" : "B", "net_name" : "UNNAMED_4_RESISTOR_I2_B_MP", "marker_data" : [ { "page_instance" : "I2", "ppath_without_last_instance" : "top/page18_i1/mgmt_pwr_block/page4", "ppath" : "top/page18_i1/mgmt_pwr_block/page4_i2", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/mgmt_pwr_block", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page18_i1@top_lib.mgmt_pwr_block(sch_1):page4" } ] }, "J2_XF.77" : { "node_name" : "J2_XF.77", "pin_type" : "POWER", "pin_number" : "77", "pinuse" : "POWER;", "pin_name_unsanitized" : "VTT_1", "part_number" : "410-000300-001", "refdes" : "J2_XF", "pin_name" : "VTT_1", "net_name" : "PWR_SDIMM_VTT_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : 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"node_name" : "U1_XF.AY20" }, "IMON_VCCAUX_TP_FL_XF.1" : { "refdes" : "IMON_VCCAUX_TP_FL_XF", "pin_name" : "1", "net_name" : "IMON_VCCAUX_LIN_XF", "part_number" : "SM_050_TP", "marker_data" : [ { "phys_page" : "page9", "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "page_instance" : "I79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i79", "sym_num" : 1 } ], "pin_name_unsanitized" : "\\1\\", "pinuse" : "POWER;", "pin_number" : "1", "pin_type" : "POWER", "node_name" : "IMON_VCCAUX_TP_FL_XF.1" }, "U1_XF.AF17" : { "pin_type" : "INOUT", "pin_number" : "AF17", "node_name" : "U1_XF.AF17", "part_number" : "450-000340-001", "pin_name" : "E1S_3R3V_LED1", "net_name" : "E1S1_3R3V_LED_XF", "refdes" : "U1_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page12", "phys_page" : "page12", "sym_num" : 9, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i283", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I283" } ], "pin_name_unsanitized" : "E1S_3R3V_LED1", "pin_group" : "E1S_SB_0_1_9_9;" }, "U1_XF.CC26" : { "node_name" : "U1_XF.CC26", "pin_number" : "CC26", "pin_type" : "INOUT", "pin_name_unsanitized" : "C0_DDR4_DQ12", "pin_group" : "C0_UNIB_1_4_66;", "pin_name" : "C0_DDR4_DQ12", "net_name" : "C0_DDR4_DQ<12>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "page_instance" : "I2425", "sym_num" : 67, "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "page" : "PAGE3", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "remapped_page" : null } ] }, "C13_E1_XF.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i96", "sym_num" : 1, "page_instance" : "I96", "ppath_without_last_instance" : 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"pin_name_unsanitized" : "GND_46", "pinuse" : "POWER;" }, "J1_E2_XF.A35" : { "node_name" : "J1_E2_XF.A35", "pin_number" : "A35", "pin_name_unsanitized" : "GND_15", "pinuse" : "GROUND;", "net_name" : "GND", "pin_name" : "GND_15", "refdes" : "J1_E2_XF", "part_number" : "410-000317-001", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i101", "sym_num" : 1 } ] }, "U1_XF.K35" : { "pin_type" : "INOUT", "pin_number" : "K35", "node_name" : "U1_XF.K35", "refdes" : "U1_XF", "pin_name" : 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"ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i81", "sym_num" : 1 } ], "pin_name" : "B", "net_name" : "VS_VCCAUX_LIN_P_XF", "refdes" : "R25_SP_XF", "part_number" : "400-000010-033" }, "C374_XF.1" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000015-008", "pin_name" : "A", "net_name" : "GND", "refdes" : "C374_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i69", "sym_num" : 1, "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk" } ], "node_name" : "C374_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "J2_XF.58" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "page" : "page6", "block" : "top/xc2_fpga_blk", "phys_page" : "page6" } ], "part_number" : "410-000300-001", "pin_name" : "RESET_N", "refdes" : "J2_XF", "net_name" : "C1_DDR4_RESET_N_XF", "pinuse" : "IN;", "pin_name_unsanitized" : "RESET_N", "pin_number" : "58", "pin_type" : "INPUT", "node_name" : "J2_XF.58" }, "U1_XF.BN32" : { "node_name" : "U1_XF.BN32", "pin_number" : "BN32", "pin_type" : "INOUT", "pin_group" : "ALL_SIGNAL_PINS_8;", "pin_name_unsanitized" : "FPGA_REF_CLK_P", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page16_i96", "sym_num" : 8, "page_instance" : "I96", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page16", "remapped_page" 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"sym_num" : 1 } ], "node_name" : "R104_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U10_FL_XF.26" : { "pin_number" : "26", "pin_type" : "POWER", "node_name" : "U10_FL_XF.26", "part_number" : "450-000057-001", "pin_name" : "GND_26", "net_name" : "GND", "refdes" : "U10_FL_XF", "marker_data" : [ { "phys_page" : "page11", "page" : "page12", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page11", "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i30", "sym_num" : 1 } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_26" }, "PM4_SP_XF.J7" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "EXTVCC", "part_number" : "462-000308-002", "net_name" : "NC", "pin_name" : "EXTVCC", "refdes" : "PM4_SP_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i80", "sym_num" : 1, "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4" } ], "node_name" : "PM4_SP_XF.J7", "pin_number" : "J7", "pin_type" : "POWER" }, "U1_XF.BB10" : { "pin_name_unsanitized" : "GND_739", "pin_group" : "ALL_POWER_PINS_36;", "pin_name" : "GND_739", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "page" : "page24", "block" : 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"page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24" } ], "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_429", "refdes" : "U1_XF" }, "U1_XF.P45" : { "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L1N_T0L_N1_DBC_38", "refdes" : "U1_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "sym_num" : 26, "page_instance" : "I58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31" } ], "pin_name_unsanitized" : "IO_L1N_T0L_N1_DBC_38", "pin_group" : "ALL_SIGNAL_PINS_26;", "pin_number" : "P45", "pin_type" : "INOUT", "node_name" : "U1_XF.P45" }, "U1_XF.BT46" : { "part_number" : "450-000340-001", "pin_name" : "VREF_20", "net_name" : "NC", "refdes" : "U1_XF", "marker_data" : [ { "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "page_instance" : "I50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "sym_num" : 17 } ], "pin_name_unsanitized" : "VREF_20", "pin_group" : "ALL_POWER_PINS_17;", "pin_number" : "BT46", "pin_type" : "INOUT", "node_name" : "U1_XF.BT46" }, "PM2_SP_XF.B7" : { "node_name" : "PM2_SP_XF.B7", "pin_number" : "B7", "pin_name_unsanitized" : "GND_15", "pinuse" : "GROUND;", "net_name" : "GND", "refdes" : "PM2_SP_XF", "pin_name" : "GND_15", "part_number" : "462-000309-001", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "path" : 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: "page31", "phys_page" : "page31" } ], "node_name" : "U1_XF.AL46", "pin_number" : "AL46", "pin_type" : "INOUT" }, "U10_FL_XF.12" : { "node_name" : "U10_FL_XF.12", "pin_type" : "POWER", "pin_number" : "12", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_12", "part_number" : "450-000057-001", "pin_name" : "GND_12", "refdes" : "U10_FL_XF", "net_name" : "GND", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page11", "phys_page" : "page11", "page" : "page12", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11_i30", "sym_num" : 1, "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page11" } ] }, "PM1_SP_XF.V5" : { "pin_number" : "V5", "node_name" : "PM1_SP_XF.V5", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I11" } ], "part_number" : "462-000309-001", "pin_name" : "GND_81", "refdes" : "PM1_SP_XF", "net_name" : "GND", "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_81" }, "U1_XF.K20" : { "marker_data" : [ { "sym_num" : 48, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2425", "path" : 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"ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73", "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "node_name" : "U1_XF.CC12", "pin_type" : "INOUT", "pin_number" : "CC12" }, "U1_XF.AT43" : { "pin_group" : "ALL_POWER_PINS_30;", "pin_name_unsanitized" : "VCCAUX_7", "marker_data" : [ { "sym_num" : 30, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i188", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I188", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23" } ], "part_number" : "450-000340-001", "pin_name" : "VCCAUX_7", "refdes" : "U1_XF", "net_name" : "FPGA_VCCAUX_P1R8V", "node_name" : "U1_XF.AT43", "pin_type" : "INOUT", "pin_number" : "AT43" }, "U11_FL_XF.19" : { "marker_data" : [ { "page_instance" : "I66", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i66", "sym_num" : 1, "phys_page" : "page9", "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9" } ], "part_number" : "450-000057-001", "pin_name" : "SENSE", "net_name" : "UNNAMED_9_LT3071_I66_SENSE_FL", "refdes" : "U11_FL_XF", "pinuse" : "IN;", "pin_name_unsanitized" : "SENSE", "pin_number" : "19", "pin_type" : "INPUT", "node_name" : "U11_FL_XF.19" }, "J1_P1_XF.A14" : { "pin_number" : "A14", "node_name" : "J1_P1_XF.A14", "refdes" : "J1_P1_XF", "net_name" : "GND", "pin_name" : "GND_5", "part_number" : "410-000324-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "page_instance" : "I86", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i86" } ], "pin_name_unsanitized" : "GND_5", "pinuse" : "GROUND;" }, "U1_XF.BL43" : { "pin_type" : "INOUT", "pin_number" : "BL43", "node_name" : "U1_XF.BL43", "marker_data" : [ { "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", 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"part_number" : "462-000304-001", "pin_name" : "VOUT1_3", "refdes" : "PM4_ND_XF", "net_name" : "PWR_NDIMM_VDD_XF", "node_name" : "PM4_ND_XF.L1", "pin_type" : "POWER", "pin_number" : "L1" }, "C16_E3_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C16_E3_XF.1", "refdes" : "C16_E3_XF", "pin_name" : "A", "net_name" : "E1S_REF_CLK_P<3>", "part_number" : "402-000010-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4_i45", "sym_num" : 1, "page_instance" : "I45", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4" } ], "pin_name_unsanitized" : "A", "pinuse" : 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"J1_XF.146", "pin_number" : "146", "pin_type" : "INPUT" }, "R1_CPLD.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-074", "refdes" : "R1_CPLD", "pin_name" : "B", "net_name" : "GND", "marker_data" : [ { "page_instance" : "I169", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "ppath" : "top/page14_i1/cpld_blk/page4_i169", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top/cpld_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4" } ], "node_name" : "R1_CPLD.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "J3_XF.233" : { "pin_type" : "POWER", "pin_number" : "233", "node_name" : "J3_XF.233", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, 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"phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i438", "sym_num" : 1, "page_instance" : "I438", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6" } ] }, "U11.6" : { "pin_name_unsanitized" : "AIN1", "pinuse" : "IN;", "refdes" : "U11", "pin_name" : "AIN1", "net_name" : "UNNAMED_4_MAX116XXQSOP16_I97_AIN1", "part_number" : "450-000333-001", "marker_data" : [ { "phys_page" : "page4", "block" : "top", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page4", "path" : "@top_lib.top(sch_1):page4", "page_instance" : "I97", "ppath_without_last_instance" : "top/page4", "ppath" : "top/page4_i97", "sym_num" : 1 } ], "node_name" : "U11.6", "pin_type" : "INPUT", "pin_number" : "6" }, "R19_CPLD.2" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page8_i29", "ppath_without_last_instance" : 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"top/page6_i428/xc2_fpga_blk/page20" } ], "part_number" : "450-000340-001", "net_name" : "PWR_AVCC_RS_RLC_XF", "pin_name" : "MGTAVCC_RLC_7", "refdes" : "U1_XF", "pin_group" : "ALL_POWER_PINS_29;", "pin_name_unsanitized" : "MGTAVCC_RLC_7", "pin_type" : "INOUT", "pin_number" : "BE13", "node_name" : "U1_XF.BE13" }, "U1_XF.BF42" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I72", "sym_num" : 37, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "net_name" : "GND", "pin_name" : "GND_844", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_37;", "pin_name_unsanitized" : "GND_844", "pin_type" : "INOUT", "pin_number" : "BF42", "node_name" : "U1_XF.BF42" }, "C118_XF.1" : { "node_name" : "C118_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page12", "phys_page" : "page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I63", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i63" } ], "part_number" : "402-000010-035", "refdes" : "C118_XF", "pin_name" : "A", "net_name" : "AC_E1S0_PET_N<7>_XF" }, "U1_XF.AY6" : { "pin_type" : "INOUT", "pin_number" : "AY6", "node_name" : "U1_XF.AY6", "marker_data" : [ { "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : 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"remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4" } ] }, "R11_XF.1" : { "node_name" : "R11_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "net_name" : "FPGA_VCCAUX_P1R8V", "refdes" : "R11_XF", "part_number" : "400-000010-120", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page18", "phys_page" : "page18", "page" : "page18", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page18_i49", "sym_num" : 1, "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page18" } ] }, "PM4_SD_XF.M4" : { "pin_name_unsanitized" : "GND_47", "pinuse" : "POWER;", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i20", "sym_num" : 2, "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3" } ], "refdes" : "PM4_SD_XF", "pin_name" : "GND_47", "net_name" : "GND", "part_number" : "462-000304-001", "node_name" : "PM4_SD_XF.M4", "pin_number" : "M4", "pin_type" : "POWER" }, "U1_XF.BV51" : { "pin_name_unsanitized" : "C1_DDR4_DQ15", "pin_group" : "C1_UNIB_1_5_39;", "part_number" : "450-000340-001", "pin_name" : "C1_DDR4_DQ15", "net_name" : "C1_DDR4_DQ<15>_XF", "refdes" : "U1_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "page_instance" : "I2425", "sym_num" : 40, "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "block" : "top/xc2_fpga_blk", "page" : "PAGE5", "phys_page" : "PAGE5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "remapped_page" : null } ], "node_name" : "U1_XF.BV51", "pin_number" : "BV51", "pin_type" : "INOUT" }, "U1_XF.BW30" : { "pin_name" : "MST_SLV_I2C_SCL", "net_name" : "FPGA_1R8V_SCL", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "phys_page" : "page16", "page" : "page16", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page16_i96", "sym_num" : 8, "page_instance" : "I96", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page16" } ], "pin_name_unsanitized" : "MST_SLV_I2C_SCL", "pin_group" : "MGMT_8_8;", "pin_number" : "BW30", "pin_type" : "INOUT", "node_name" : "U1_XF.BW30" }, "U1_XF.BP54" : { "pin_group" : "ALL_SIGNAL_PINS_15;", "pin_name_unsanitized" : "IO_T1U_N12_23", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31", "sym_num" : 15, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i55", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I55" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_T1U_N12_23", "net_name" : "NC", "node_name" : "U1_XF.BP54", "pin_number" : "BP54", "pin_type" : "INOUT" }, "U1_XF.AP38" : { "pin_name" : "GND_584", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "sym_num" : 35, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I70" } ], "pin_name_unsanitized" : "GND_584", "pin_group" : "ALL_POWER_PINS_35;", "pin_number" : "AP38", "pin_type" : "INOUT", "node_name" : "U1_XF.AP38" }, "J1_E0_XF.B38" : { "pin_number" : "B38", "node_name" : "J1_E0_XF.B38", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3", "page_instance" : "I101", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3_i101", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null } ], "refdes" : "J1_E0_XF", "net_name" : "GND", "pin_name" : "GND_27", "part_number" : "410-000317-001", "pin_name_unsanitized" : "GND_27", "pinuse" : "GROUND;" }, "J3_XF.27" : { "refdes" : "J3_XF", "pin_name" : "DQ16", "net_name" : "C2_DDR4_DQ<16>_XF", "part_number" : "410-000300-001", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "block" : "top/xc2_fpga_blk", "page" : "page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8" } ], "pin_name_unsanitized" : "DQ16", "pinuse" : "TRI;", "pin_number" : "27", "pin_type" : "INOUT", "node_name" : "J3_XF.27" }, "C389_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C389_XF.1", "pin_name" : "A", "net_name" : "FPGA_VCCAUX_P1R8V", "refdes" : "C389_XF", "part_number" : "402-000010-001", "marker_data" : [ { "page_instance" : "I48", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i48", "sym_num" : 1, "phys_page" : "page15", "page" : "page15", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page15" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, 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"node_name" : "J1_P1_XF.A8" }, "U1_XF.AN48" : { "pin_group" : "ALL_SIGNAL_PINS_24;", "pin_name_unsanitized" : "IO_L16P_T2U_N6_QBC_AD3P_29", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i54", "sym_num" : 24, "page_instance" : "I54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk" } ], "net_name" : "NC", "pin_name" : "IO_L16P_T2U_N6_QBC_AD3P_29", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.AN48", "pin_number" : "AN48", "pin_type" : "INOUT" }, "R3_E1_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R3_E1_XF.2", "part_number" : "400-000010-007", "pin_name" : "B", "net_name" : "E1S1_3R3V_SCL_XF", "refdes" : "R3_E1_XF", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page3", "page_instance" : "I79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page3_i79", "sym_num" : 1 } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "PM4_SD_XF.C6" : { "pin_number" : "C6", "pin_type" : "POWER", "node_name" : "PM4_SD_XF.C6", "pin_name" : "GND_17", "refdes" : "PM4_SD_XF", "net_name" : "GND", "part_number" : "462-000304-001", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page3", "path" : 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"ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-035", "pin_name" : "A", "refdes" : "C21_E2_XF", "net_name" : "AC_CONN_CLK_REFP<0>_3", "marker_data" : [ { "page_instance" : "I54", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page4_i54", "sym_num" : 1, "phys_page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page4" } ] }, "U1_CPLD.R3" : { "marker_data" : [ { "sym_num" : 8, "ppath" : "top/page14_i1/cpld_blk/page7_i152", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I152", "path" : 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"pin_number" : "10", "pin_type" : "POWER", "node_name" : "U3_FL_XF.10" }, "C13.2" : { "node_name" : "C13.2", "pin_type" : "ANALOG", "pin_number" : "2", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-026", "refdes" : "C13", "pin_name" : "B", "net_name" : "GND", "marker_data" : [ { "page_instance" : "I129", "ppath_without_last_instance" : "top/page10", "ppath" : "top/page10_i129", "sym_num" : 1, "phys_page" : "page10", "block" : "top", "page" : "page10", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page10", "path" : "@top_lib.top(sch_1):page10" } ] }, "C41_XF.2" : { "node_name" : "C41_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "page" : 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"UNNAMED_29_PI6CB33401_I89_BWSELTRI_XF", "part_number" : "450-000345-001" }, "U1_XF.H2" : { "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "sym_num" : 33, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i68", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I68" } ], "refdes" : "U1_XF", "pin_name" : "GND_107", "net_name" : "GND", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_33;", "pin_name_unsanitized" : "GND_107", "pin_number" : "H2", "pin_type" : "INOUT", "node_name" : "U1_XF.H2" }, "J1_XF.205" : { "net_name" : "NC", "pin_name" : "NC_5", "refdes" : "J1_XF", "part_number" : "410-000300-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "phys_path" : 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"node_name" : "U1_XF.BL2" }, "PM4_SP_XF.B7" : { "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "page_instance" : "I79", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i79", "sym_num" : 2 } ], "pin_name" : "GND_4", "refdes" : "PM4_SP_XF", "net_name" : "GND", "part_number" : "462-000308-002", "pin_name_unsanitized" : "GND_4", "pinuse" : "POWER;", "pin_type" : "POWER", "pin_number" : "B7", "node_name" : "PM4_SP_XF.B7" }, "U1_XF.BA14" : { "marker_data" : [ { "phys_page" : "page31", "block" : "top/xc2_fpga_blk", "page" : "page31", "remapped_page" : null, "phys_path" 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"pin_type" : "INOUT" }, "J1_XF.166" : { "node_name" : "J1_XF.166", "pin_number" : "166", "pin_type" : "INOUT", "pinuse" : "TRI;", "pin_name_unsanitized" : "DQ15", "part_number" : "410-000300-001", "net_name" : "C0_DDR4_DQ<15>_XF", "pin_name" : "DQ15", "refdes" : "J1_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4" } ] }, "PM2_SP_XF.J7" : { "node_name" : "PM2_SP_XF.J7", "pin_number" : "J7", "pin_name_unsanitized" : "GND_50", "pinuse" : "GROUND;", "refdes" : "PM2_SP_XF", "net_name" : "GND", "pin_name" : "GND_50", "part_number" : "462-000309-001", "marker_data" : [ { "ppath" : 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: "U2_ND_XF.10" }, "R54.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R54.2", "part_number" : "400-000010-010", "pin_name" : "B", "net_name" : "VMON_NDIMM_VPP_SW", "refdes" : "R54", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page4_i61", "ppath_without_last_instance" : "top/page4", "page_instance" : "I61", "phys_path" : "@top_lib.top(sch_1):page4", "path" : "@top_lib.top(sch_1):page4", "remapped_page" : null, "block" : "top", "page" : "page4", "phys_page" : "page4" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;" }, "R37.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page14_i146", "ppath_without_last_instance" : "top/page14", "page_instance" : "I146", "phys_path" : "@top_lib.top(sch_1):page14", "path" : "@top_lib.top(sch_1):page14", "remapped_page" : null, "block" : "top", "page" : "page14", "phys_page" : "page14" } ], "part_number" : "400-000010-020", "pin_name" : "B", "net_name" : "HOST_3R3V_SCL", "refdes" : "R37", "node_name" : "R37.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "C147_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C147_XF.2", "pin_name" : "B", "net_name" : "UNNAMED_17_BYPASSCAPNPOL_I46_B_XF", "refdes" : "C147_XF", "part_number" : "402-000010-001", "marker_data" : [ { "page_instance" : "I46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i46", "sym_num" : 1, "phys_page" : "page17", "page" : "page17", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "C10_ND_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "C10_ND_XF", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000010-041", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i14", "sym_num" : 1, "page_instance" : "I14", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3" } ], "node_name" : "C10_ND_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U7_XF.32" : { "pin_name_unsanitized" : "SADR_TRI", "pinuse" : "IN;", "marker_data" : [ { "phys_page" : "page29", "page" : "page29", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page29", "phys_path" : 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"pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R7_XF.2" }, "U1_XF.BA6" : { "pin_number" : "BA6", "pin_type" : "INOUT", "node_name" : "U1_XF.BA6", "marker_data" : [ { "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "page_instance" : "I775", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page11", "phys_page" : "page11" } ], "pin_name" : "PCIE0_RXP5", "refdes" : "U1_XF", "net_name" : "PCIE0_RXP<5>_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_3;", "pin_name_unsanitized" : "PCIE0_RXP5" }, "PM7_SP_XF.L6" : { "marker_data" : [ { "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80", "sym_num" : 1, "phys_page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11" } ], "part_number" : "462-000308-002", "net_name" : "P12V_4650_BR_SP", "pin_name" : "VIN_17", "refdes" : "PM7_SP_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_17", "pin_number" : "L6", "pin_type" : "POWER", "node_name" : "PM7_SP_XF.L6" }, "R22_CPLD.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R22_CPLD.1", "marker_data" : [ { "ppath" : "top/page14_i1/cpld_blk/page9_i78", "sym_num" : 1, "page_instance" : "I78", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page9", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "phys_page" : "page9", "page" : "page9", "block" : "top/cpld_blk" } ], "pin_name" : "A", "net_name" : "UNNAMED_9_LUMEXRGBLED_I91_GREENK_CPLD", "refdes" : "R22_CPLD", "part_number" : "400-000010-006", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "C314_XF.2" : { "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page13", "phys_page" : "page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "page_instance" : "I93", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i93" } ], "part_number" : "402-000010-035", "net_name" : "E1S3_PET_N<0>_XF", "pin_name" : "B", "refdes" : "C314_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C314_XF.2" }, "U1_XF.BB24" : { "node_name" : "U1_XF.BB24", "pin_number" : "BB24", "pin_type" : "INOUT", "pin_group" : "ALL_POWER_PINS_36;", "pin_name_unsanitized" : "GND_744", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "sym_num" : 36, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I71" } ], "net_name" : "GND", "pin_name" : "GND_744", "refdes" : "U1_XF", "part_number" : "450-000340-001" }, "J3_XF.20" : { "pin_type" : "GROUND", "pin_number" : "20", "node_name" : "J3_XF.20", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8" } ], "pin_name" : "VSS_51", "refdes" : "J3_XF", "net_name" : "GND", "part_number" : "410-000300-001", "pin_name_unsanitized" : "VSS_51", "pinuse" : "UNSPEC;" }, "U1_XF.J45" : { "pin_name_unsanitized" : "IO_L16N_T2U_N7_QBC_AD3N_38", "pin_group" : "ALL_SIGNAL_PINS_26;", "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L16N_T2U_N7_QBC_AD3N_38", "refdes" : "U1_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i58", "sym_num" : 26, "page_instance" : "I58", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk" } ], "node_name" : "U1_XF.J45", "pin_type" : "INOUT", "pin_number" : "J45" }, "U1_XF.BD62" : { "pin_group" : "ALL_SIGNAL_PINS_19;", "pin_name_unsanitized" : "IO_L13N_T2L_N1_GC_QBC_25", "marker_data" : [ { "sym_num" : 19, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i47", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I47", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30" } ], "part_number" : "450-000340-001", "pin_name" : "IO_L13N_T2L_N1_GC_QBC_25", "net_name" : "NC", "refdes" : "U1_XF", "node_name" : "U1_XF.BD62", "pin_type" : "INOUT", "pin_number" : "BD62" }, "J1_XF.81" : { "pinuse" : "IN;", "pin_name_unsanitized" : "BA0", "part_number" : "410-000300-001", "pin_name" : "BA0", "net_name" : "C0_DDR4_BA<0>_XF", "refdes" : "J1_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_page" : "page4", "block" : "top/xc2_fpga_blk", "page" : "page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4" } ], "node_name" : "J1_XF.81", "pin_number" : "81", "pin_type" : "INPUT" }, "PM3_SP_XF.F3" : { "pin_name_unsanitized" : "GND_22", "pinuse" : "POWER;", "pin_name" : "GND_22", "refdes" : "PM3_SP_XF", "net_name" : "GND", "part_number" : "462-000308-002", "marker_data" : [ { "page_instance" : "I153", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i153", "sym_num" : 2, "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10" } ], "node_name" : "PM3_SP_XF.F3", "pin_number" : "F3", "pin_type" : "POWER" }, "R73.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I117", "ppath_without_last_instance" : "top/page4", "ppath" : "top/page4_i117", "sym_num" : 1, "phys_page" : "page4", "page" : "page4", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page4" } ], "refdes" : "R73", "pin_name" : "B", "net_name" : "UNNAMED_4_BYPASSCAPNPOL_I99_B", "part_number" : "400-000010-010", "node_name" : "R73.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "R107_SP_XF.2" : { "marker_data" : [ { "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "page_instance" : "I75", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i75", "sym_num" : 1 } ], "part_number" : "400-000014-011", "pin_name" : "B", "refdes" : "R107_SP_XF", "net_name" : "ENB3V_SEQ_F", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R107_SP_XF.2" }, "U7_FL_XF.22" : { "node_name" : "U7_FL_XF.22", "pin_number" : "22", "pin_type" : "INPUT", "pin_name_unsanitized" : "MARGA", "pinuse" : "IN;", "net_name" : "UNNAMED_9_LT3071_I30_MARGA_FL", "pin_name" : "MARGA", "refdes" : "U7_FL_XF", "part_number" : "450-000057-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null, "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page9", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I30" } ] }, "C129_XF.1" : { "node_name" : "C129_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I76", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i76", "sym_num" : 1, "phys_page" : "page12", "page" : "page12", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12" } ], "net_name" : "AC_E1S0_PET_N<0>_XF", "pin_name" : "A", "refdes" : "C129_XF", "part_number" : "402-000010-035" }, "U1_XF.BY5" : { "pin_number" : "BY5", "pin_type" : "INOUT", "node_name" : "U1_XF.BY5", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73", "sym_num" : 38, "page_instance" : "I73", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "GND_1035", "net_name" : "GND", "pin_group" : "ALL_POWER_PINS_38;", "pin_name_unsanitized" : "GND_1035" }, "C1_E3_XF.1" : { "node_name" : "C1_E3_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4_i19", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4", "page_instance" : "I19" } ], "part_number" : "402-000010-001", "refdes" : "C1_E3_XF", "pin_name" : "A", "net_name" : "GND" }, "J2_XF.55" : { "pin_type" : "GROUND", "pin_number" : "55", "node_name" : "J2_XF.55", "part_number" : "410-000300-001", "pin_name" : "VSS_49", "refdes" : "J2_XF", "net_name" : "GND", "marker_data" : [ { "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180", "sym_num" : 1 } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_49" }, "C258_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C258_XF.1", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page14", "phys_page" : "page14", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i112", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I112" } ], "part_number" : "402-000010-035", "refdes" : "C258_XF", "pin_name" : "A", "net_name" : "AC_OCL0_PET_N<3>_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "R12_E3_XF.1" : { "node_name" : "R12_E3_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "net_name" : "GND", "pin_name" : "A", "refdes" : "R12_E3_XF", "part_number" : "400-000010-006", "marker_data" : [ { "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4", "phys_path" : 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: "page7", "block" : "top/xc2_fpga_blk", "page" : "page7" } ] }, "R29_SP_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "POK_OD_VCCINT_BLSW_P<0>", "refdes" : "R29_SP_XF", "part_number" : "400-000014-011", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i134", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I134", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page10", "phys_page" : "page10" } ], "node_name" : "R29_SP_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "C10_FL_XF.1" : { "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3_i18", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3", "page_instance" : "I18", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page3" } ], "part_number" : "402-000010-011", "refdes" : "C10_FL_XF", "pin_name" : "A", "net_name" : "P3R3V", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C10_FL_XF.1" }, "J2_XF.276" : { "refdes" : "J2_XF", "pin_name" : "VSS_66", "net_name" : "GND", "part_number" : "410-000300-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page6", "phys_page" : "page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page6", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page6_i180" } ], "pin_name_unsanitized" : "VSS_66", "pinuse" : "UNSPEC;", "pin_number" : "276", "pin_type" : "GROUND", "node_name" : "J2_XF.276" }, "U1_XF.AD45" : { "pin_type" : "INOUT", "pin_number" : "AD45", "node_name" : "U1_XF.AD45", "part_number" : "450-000340-001", "net_name" : "NC", "pin_name" : "IO_L21P_T3L_N4_AD8P_30", "refdes" : "U1_XF", "marker_data" : [ { "page_instance" : "I53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53", "sym_num" : 23, "phys_page" : "page31", "page" : "page31", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31" } ], "pin_name_unsanitized" : "IO_L21P_T3L_N4_AD8P_30", "pin_group" : "ALL_SIGNAL_PINS_23;" }, "U1_XF.AV53" : { "pin_type" : "INOUT", "pin_number" : "AV53", "node_name" : "U1_XF.AV53", "marker_data" : [ { "page_instance" : "I51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i51", "sym_num" : 18, "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L1P_T0L_N0_DBC_27", "net_name" : "NC", "pin_group" : "ALL_SIGNAL_PINS_18;", "pin_name_unsanitized" : "IO_L1P_T0L_N0_DBC_27" }, "PM2_SP_XF.R6" : { "pin_name_unsanitized" : "PHMODE3", "pinuse" : "IN;", "pin_name" : "PHMODE3", "refdes" : "PM2_SP_XF", "net_name" : "UNNAMED_6_LTM4671_I456_PHMODE3_SP", "part_number" : "462-000309-001", "marker_data" : [ { "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "page_instance" : "I456", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i456", "sym_num" : 4 } ], "node_name" : "PM2_SP_XF.R6", "pin_number" : "R6", "pin_type" : "INPUT" }, "R60.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R60.2", "marker_data" : [ { "ppath_without_last_instance" : "top/page15", "page_instance" : "I50", "sym_num" : 1, "ppath" : "top/page15_i50", "page" : "page15", "block" : "top", "phys_page" : "page15", "path" : "@top_lib.top(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page15", "remapped_page" : null } ], "pin_name" : "B", "net_name" : "JT_FPGA_TCK", "refdes" : "R60", "part_number" : "400-000010-006", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "PM1_SP_XF.D11" : { "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_6", "part_number" : "462-000309-001", "refdes" : "PM1_SP_XF", "net_name" : "P12V_MAIN", "pin_name" : "VIN_6", "marker_data" : [ { "page_instance" : "I11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "sym_num" : 5, "phys_page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7" } ], "node_name" : "PM1_SP_XF.D11", "pin_number" : "D11" }, "R241_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "page_instance" : "I2156", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2156", "sym_num" : 1, "phys_page" : "page5", "block" : "top/xc2_fpga_blk", "page" : "page5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5" } ], "part_number" : "400-000010-007", "refdes" : "R241_XF", "pin_name" : "B", "net_name" : "C1_DDR4_ALERT_N_XF", "node_name" : "R241_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "C68_FL_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C68_FL_XF.2", "marker_data" : [ { "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3", "page_instance" : "I23", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page3_i23" } ], "refdes" : "C68_FL_XF", "pin_name" : "B", "net_name" : "GND", "part_number" : "402-000010-028", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "J2_P1_XF.MH4" : { "pinuse" : "GROUND;", "pin_name_unsanitized" : "MH4", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i85", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "page_instance" : "I85", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "phys_page" : "page3" } ], "part_number" : "410-000324-001", "pin_name" : "MH4", "refdes" : "J2_P1_XF", "net_name" : "GND", "node_name" : "J2_P1_XF.MH4", "pin_number" : "MH4" }, "R190_SP_XF.2" : { "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page9", "phys_page" : "page9", "page" : "page9", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page9_i10", "sym_num" : 1, "page_instance" : "I10", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page9" } ], "refdes" : "R190_SP_XF", "pin_name" : "B", "net_name" : "IS_VCCINTUR_SW_N_SP", "part_number" : "400-000015-037", "node_name" : "R190_SP_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U6_FL_XF.11" : { "node_name" : "U6_FL_XF.11", "pin_number" : "11", "pin_type" : "POWER", "pin_name_unsanitized" : "GND_11", "pinuse" : "POWER;", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page4", "page_instance" : "I30", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page4_i30", "sym_num" : 1 } ], "refdes" : "U6_FL_XF", "pin_name" : "GND_11", "net_name" : "GND", "part_number" : "450-000057-001" }, "U1_XF.AE11" : { "node_name" : "U1_XF.AE11", "pin_number" : "AE11", "pin_type" : "INOUT", "pin_name_unsanitized" : "MGTYTXP1_231", "pin_group" : "ALL_SIGNAL_PINS_14;", "part_number" : "450-000340-001", "pin_name" : "MGTYTXP1_231", "refdes" : "U1_XF", "net_name" : "NC", "marker_data" : [ { "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I56", "sym_num" : 14, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i56" } ] }, "C62_SP_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C62_SP_XF.2", "marker_data" : [ { "page_instance" : "I112", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i112", "sym_num" : 1, "phys_page" : "page10", "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10" } ], "net_name" : "GND", "pin_name" : "B", "refdes" : "C62_SP_XF", "part_number" : "402-000010-033", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "J1_XF.131" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "VSS_61", "part_number" : "410-000300-001", "pin_name" : "VSS_61", "refdes" : "J1_XF", "net_name" : "GND", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180" } ], "node_name" : "J1_XF.131", "pin_type" : "GROUND", "pin_number" : "131" }, "U1_E0_XF.8" : { "pin_number" : "8", "node_name" : "U1_E0_XF.8", "part_number" : "450-000345-001", "net_name" : "GND", "pin_name" : "GND_DIG", "refdes" : "U1_E0_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "page_instance" : "I37" } ], "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_DIG" }, "J5.7" : { "node_name" : "J5.7", "pin_number" : "7", "pin_name_unsanitized" : "GND_2", "pinuse" : "GROUND;", "refdes" : "J5", "pin_name" : "GND_2", "net_name" : "GND", "part_number" : "410-000316-001", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page15", "phys_path" : "@top_lib.top(sch_1):page15", "remapped_page" : null, "page" : "page15", "block" : "top", "phys_page" : "page15", "sym_num" : 1, "ppath" : "top/page15_i110", "ppath_without_last_instance" : "top/page15", "page_instance" : "I110" } ] }, "PM2_SP_XF.U11" : { "pin_name_unsanitized" : "GND_97", "pinuse" : "GROUND;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "sym_num" : 5, "page_instance" : "I459", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6" } ], "refdes" : "PM2_SP_XF", "net_name" : "GND", "pin_name" : "GND_97", "part_number" : "462-000309-001", "node_name" : "PM2_SP_XF.U11", "pin_number" : "U11" }, "R151_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R151_XF.1", "refdes" : "R151_XF", "pin_name" : "A", "net_name" : "PWR_SDIMM_VDD_XF", "part_number" : "400-000010-010", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2424", "sym_num" : 1, "page_instance" : "I2424", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "phys_page" : "page5", "block" : "top/xc2_fpga_blk", "page" : "page5" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "PM1_SP_XF.J4" : { "marker_data" : [ { "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i37", "sym_num" : 2 } ], "part_number" : "462-000309-001", "net_name" : "PWR_NDIMM_VPP_XF", "refdes" : "PM1_SP_XF", "pin_name" : "VOUT1_8", "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT1_8", "pin_number" : "J4", "node_name" : "PM1_SP_XF.J4" }, "U1_XF.AM22" : { "pin_type" : "INOUT", "pin_number" : "AM22", "node_name" : "U1_XF.AM22", "part_number" : "450-000340-001", "net_name" : "GND", "pin_name" : "GND_549", "refdes" : "U1_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page24", "phys_page" : "page24", "sym_num" : 35, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I70" } ], "pin_name_unsanitized" : "GND_549", "pin_group" : "ALL_POWER_PINS_35;" }, "R84_SP_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "UNNAMED_6_BYPASSCAPNPOL_I401_B_SP", "refdes" : "R84_SP_XF", "part_number" : "400-000014-011", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I438", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i438" } ], "node_name" : "R84_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "PM7_SP_XF.F1" : { "pin_number" : "F1", "pin_type" : "POWER", "node_name" : "PM7_SP_XF.F1", "part_number" : "462-000308-002", "refdes" : "PM7_SP_XF", "pin_name" : "GND_20", "net_name" : "GND", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page11", "sym_num" : 2, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i151", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I151" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_20" }, "U1_XF.BL13" : { "marker_data" : [ { "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i86", "sym_num" : 29, "phys_page" : "page20", "block" : "top/xc2_fpga_blk", "page" : "page20", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20" } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "MGTAVCC_RS_3", "net_name" : "PWR_AVCC_RS_RLC_XF", "pin_group" : "ALL_POWER_PINS_29;", "pin_name_unsanitized" : "MGTAVCC_RS_3", "pin_number" : "BL13", "pin_type" : "INOUT", "node_name" : "U1_XF.BL13" }, "R142_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R142_XF.1", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_page" : "page17", "page" : "page17", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i120", "sym_num" : 1, "page_instance" : "I120", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17" } ], "part_number" : "400-000010-010", "pin_name" : "A", "net_name" : "UNNAMED_17_RESISTOR_I119_A_XF", "refdes" : "R142_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "U1_XF.AT13" : { "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775", "sym_num" : 3, "page_instance" : "I775", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11" } ], "refdes" : "U1_XF", "pin_name" : "PCIE1_TXP7", "net_name" : "AC_PCIE1_TXP<7>_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_3;", "pin_name_unsanitized" : "PCIE1_TXP7", "pin_type" : "INOUT", "pin_number" : "AT13", "node_name" : "U1_XF.AT13" }, "C118_SP_XF.1" : { "node_name" : "C118_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-031", "pin_name" : "A", "net_name" : "GND", "refdes" : "C118_SP_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i17", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I17" } ] }, "U1_XF.BK7" : { "node_name" : "U1_XF.BK7", "pin_type" : "INOUT", "pin_number" : "BK7", "pin_name_unsanitized" : "GND_893", "pin_group" : "ALL_POWER_PINS_37;", "part_number" : "450-000340-001", "pin_name" : "GND_893", "net_name" : "GND", "refdes" : "U1_XF", "marker_data" : [ { "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I72", "sym_num" : 37, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72" } ] }, "U1_XF.BP26" : { "pin_number" : "BP26", "pin_type" : "INOUT", "node_name" : "U1_XF.BP26", "part_number" : "450-000340-001", "net_name" : "C0_RDIMM_DQS_C<5>_XF", "pin_name" : "C0_DDR4_DQS_C10", "refdes" : "U1_XF", "marker_data" : [ { "sym_num" : 71, "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "page_instance" : "I2425", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "PAGE3", "phys_page" : "PAGE3" } ], "pin_name_unsanitized" : "C0_DDR4_DQS_C10", "pin_group" : "ALL_SIGNAL_PINS_66;" }, "J1_XF.66" : { "pin_number" : "66", "pin_type" : "INPUT", "node_name" : "J1_XF.66", "part_number" : "410-000300-001", "net_name" : "C0_DDR4_ADR<9>_XF", "pin_name" : "A9", "refdes" : "J1_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4" } ], "pinuse" : "IN;", "pin_name_unsanitized" : "A9" }, "C6_CPLD.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "refdes" : "C6_CPLD", "net_name" : "CPLD_P3R3V", "part_number" : "402-000010-001", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page7_i134", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I134", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/cpld_blk", "phys_page" : "page7" } ], "node_name" : "C6_CPLD.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.CC42" : { "pin_number" : "CC42", "pin_type" : "INOUT", "node_name" : "U1_XF.CC42", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I50", "sym_num" : 17, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null } ], "refdes" : "U1_XF", "pin_name" : "IO_L16N_T2U_N7_QBC_AD3N_20", "net_name" : "NC", "part_number" : "450-000340-001", "pin_group" : "ALL_SIGNAL_PINS_17;", "pin_name_unsanitized" : "IO_L16N_T2U_N7_QBC_AD3N_20" }, "U1_XF.BU31" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I52", "sym_num" : 21, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i52", "block" : "top/xc2_fpga_blk", "page" : "page30", "phys_page" : "page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", 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"pin_name" : "DQS16_C_TDQS16_C", "net_name" : "C3_RDIMM_DQS_C<16>_XF", "refdes" : "J4_XF", "part_number" : "410-000300-001" }, "R12_E3_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "net_name" : "UNNAMED_4_PI6CB33401_I37_SADRTRI_E3", "refdes" : "R12_E3_XF", "part_number" : "400-000010-006", "marker_data" : [ { "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4", "page_instance" : "I31", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4_i31" } ], "node_name" : "R12_E3_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U4_SP_XF.16" : { "pin_name" : "VDD", "refdes" : "U4_SP_XF", "net_name" : "P3R3V", "part_number" : "450-000344-001", "marker_data" : [ { "page" : "page12", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page12", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page12", "page_instance" : "I42", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page12_i42" } ], "pin_name_unsanitized" : "VDD", "pinuse" : "POWER;", "pin_number" : "16", "node_name" : "U4_SP_XF.16" }, "U1_XF.AY52" : { "pin_group" : "ALL_SIGNAL_PINS_19;", "pin_name_unsanitized" : "IO_L14P_T2L_N2_GC_26", "marker_data" : [ { "sym_num" : 19, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i47", 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"node_name" : "U1_XF.AB53", "marker_data" : [ { "phys_page" : "page30", "block" : "top/xc2_fpga_blk", "page" : "page30", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "page_instance" : "I46", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i46", "sym_num" : 22 } ], "part_number" : "450-000340-001", "pin_name" : "IO_L9N_T1L_N5_AD12N_32", "net_name" : "NC", "refdes" : "U1_XF", "pin_group" : "ALL_SIGNAL_PINS_22;", "pin_name_unsanitized" : "IO_L9N_T1L_N5_AD12N_32" }, "C10_ND_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "C10_ND_XF", "pin_name" : "A", "net_name" : "P12V_FUSED_4675_ND", "part_number" : "402-000010-041", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I14", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i14", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null } ], "node_name" : "C10_ND_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "PM7_SP_XF.L2" : { "node_name" : "PM7_SP_XF.L2", "pin_number" : "L2", "pin_type" : "POWER", "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_13", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "page" : "page11", "block" : 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"@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8" } ], "pinuse" : "IN;", "pin_name_unsanitized" : "NC_7", "pin_number" : "7", "pin_type" : "INPUT", "node_name" : "U6_SP_XF.7" }, "C68_ND_XF.2" : { "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "net_name" : "P12V_FUSED_4675_ND", "pin_name" : "B", "refdes" : "C68_ND_XF", "part_number" : "402-000020-011", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "page_instance" : "I46", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i46", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null } ], "node_name" : "C68_ND_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U1_FL_XF.19" : { "pin_name_unsanitized" : "SENSE", "pinuse" : "IN;", "net_name" : "VS_AVTT_RLC_LIN_FL", "pin_name" : "SENSE", "refdes" : "U1_FL_XF", "part_number" : "450-000057-001", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5", "page_instance" : "I30", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page5_i30", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "page" : "page5", "phys_page" : "page5", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page5", "remapped_page" : null } ], "node_name" : "U1_FL_XF.19", "pin_type" : "INPUT", "pin_number" : "19" }, "PM2_SP_XF.L11" : { "net_name" : "GND", "refdes" : "PM2_SP_XF", "pin_name" : "GND_73", "part_number" : "462-000309-001", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6", "phys_page" : "page6", "sym_num" : 5, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i459", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I459" } ], "pin_name_unsanitized" : "GND_73", "pinuse" : "GROUND;", "pin_number" : "L11", "node_name" : "PM2_SP_XF.L11" }, "C299_XF.2" : { "node_name" : "C299_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i28", 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page5", "page_instance" : "I136", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page5", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page5", "phys_page" : "page5" } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "J4_XF.17" : { "node_name" : "J4_XF.17", "pin_type" : "GROUND", "pin_number" : "17", "pin_name_unsanitized" : "VSS_43", "pinuse" : "UNSPEC;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : 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"@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null } ], "node_name" : "R112_FL_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "C401_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "C401_XF.2", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I160", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i160" } ], "part_number" : "402-000010-028", "refdes" : "C401_XF", "pin_name" : "B", "net_name" : "PWR_SDIMM_VDD_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B" }, "C132_SP_XF.2" : { "net_name" : "UNNAMED_6_LTM4671_I457_FB1_SP", "pin_name" : "B", "refdes" : "C132_SP_XF", "part_number" : "402-000200-003", "marker_data" : [ { "phys_page" : "page6", "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "page_instance" : "I519", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i519", "sym_num" : 1 } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C132_SP_XF.2" }, "R82_XF.1" : { "node_name" : "R82_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "page" : "page17", "block" : "top/xc2_fpga_blk", "phys_page" : "page17", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "page_instance" : "I53", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i53" } ], "part_number" : "400-000010-010", "pin_name" : "A", "refdes" : "R82_XF", "net_name" : "UNNAMED_17_RESISTOR_I53_A_XF" }, "J3_XF.53" : { "pin_name_unsanitized" : "VSS_44", "pinuse" : "UNSPEC;", "net_name" : "GND", "pin_name" : "VSS_44", "refdes" : "J3_XF", "part_number" : "410-000300-001", "marker_data" : [ { "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8" } ], "node_name" : "J3_XF.53", "pin_number" : "53", "pin_type" : "GROUND" }, "PM4_SD_XF.H4" : { "node_name" : "PM4_SD_XF.H4", "pin_number" : "H4", "pin_type" : "INPUT", "pinuse" : "IN;", "pin_name_unsanitized" : "VTRIM1CFG", "marker_data" : [ { "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3", "page_instance" : "I40", "sym_num" : 3, "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i40" } ], "part_number" : "462-000304-001", "net_name" : "UNNAMED_3_LTM4675_I40_VTRIM1CFG_SD", "pin_name" : "VTRIM1CFG", "refdes" : "PM4_SD_XF" }, "C200_SP_XF.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "A", "net_name" : "SGND_PM7_SP", "refdes" : "C200_SP_XF", "part_number" : "402-000202-005", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i147", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "page_instance" : "I147", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "phys_page" : "page11" } ], "node_name" : "C200_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.AM41" : { "pin_name_unsanitized" : "VCCINT_132", "pin_group" : "ALL_POWER_PINS_31;", "pin_name" : "VCCINT_132", "refdes" : "U1_XF", "net_name" : "PWR_VCCINT_XF", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 31, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I186", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "page" : "page23", "block" : "top/xc2_fpga_blk", "phys_page" : "page23" } ], "node_name" : "U1_XF.AM41", "pin_type" : "INOUT", "pin_number" : "AM41" }, "J4_XF.85" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page10", "page_instance" : "I180", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page10_i180", "page" : "page10", "block" : "top/xc2_fpga_blk", "phys_page" : "page10", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page10", "remapped_page" : null } ], "part_number" : "410-000300-001", "pin_name" : "VDD_9", "net_name" : "PWR_NDIMM_VDD_XF", "refdes" : "J4_XF", "pinuse" : "POWER;", "pin_name_unsanitized" : "VDD_9", "pin_number" : "85", "pin_type" : "POWER", "node_name" : "J4_XF.85" }, "U1_XF.BP59" : { "node_name" : "U1_XF.BP59", "pin_type" : "INOUT", "pin_number" : "BP59", "pin_name_unsanitized" : "C1_DDR4_DQ67", "pin_group" : "C1_LNIB_1_5_39;", "pin_name" : "C1_DDR4_DQ67", "net_name" : "C1_DDR4_DQ<67>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "sym_num" : 47, "ppath" : "top/page6_i428/xc2_fpga_blk/page5_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page5", "page_instance" : "I2425", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page5", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "PAGE5", "phys_page" : "PAGE5" } ] }, "U1_XF.AE50" : { "pin_type" : "INOUT", "pin_number" : "AE50", "node_name" : "U1_XF.AE50", "part_number" : "450-000340-001", "pin_name" : "IO_L17P_T2U_N8_AD10P_30", "refdes" : "U1_XF", "net_name" : "NC", "marker_data" : [ { "sym_num" : 23, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i53", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I53", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "page" : "page31", "block" : "top/xc2_fpga_blk", "phys_page" : "page31" } ], "pin_name_unsanitized" : "IO_L17P_T2U_N8_AD10P_30", "pin_group" : "ALL_SIGNAL_PINS_23;" }, "C64_SP_XF.2" : { "node_name" : "C64_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I51", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page3_i51", "sym_num" : 1, "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3" } ], "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I51_B_SP", "pin_name" : "B", "refdes" : "C64_SP_XF", "part_number" : "402-000010-005" }, "U1_E0_XF.11" : { "pin_number" : "11", "node_name" : "U1_E0_XF.11", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4_i37", "sym_num" : 1, "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page4", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page4", "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8" } ], "net_name" : "PWR_FPGA_3R3V", "refdes" : "U1_E0_XF", "pin_name" : "VDD_DIG", "part_number" : "450-000345-001", "pin_name_unsanitized" : "VDD_DIG", "pinuse" : "POWER;" }, "J1_E2_XF.A24" : { "node_name" : "J1_E2_XF.A24", "pin_type" : "OUTPUT", "pin_number" : "A24", "pin_name_unsanitized" : "PERP2", "pinuse" : "OUT;", "pin_name" : "PERP2", "net_name" : "E1S2_PER_P<2>_XF", "refdes" : "J1_E2_XF", "part_number" : "410-000317-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3_i101", "sym_num" : 1, "page_instance" : "I101", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i97/cxltc_2c_x8/page3" } ] }, "R221_XF.2" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page14", "phys_page" : "page14", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i214", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I214" } ], "part_number" : "400-000010-010", "pin_name" : "B", "net_name" : "GND", "refdes" : "R221_XF", "node_name" : "R221_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "PM4_SD_XF.G4" : { "pin_type" : "INPUT", "pin_number" : "G4", "node_name" : "PM4_SD_XF.G4", "part_number" : "462-000304-001", "pin_name" : "VOUT1CFG", "net_name" : "UNNAMED_3_LTM4675_I40_VOUT1CFG_SD", "refdes" : "PM4_SD_XF", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i2@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3_i40", "sym_num" : 3, "page_instance" : "I40", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i2/dimm_pwr_blk/page3" } ], "pinuse" : "IN;", "pin_name_unsanitized" : "VOUT1CFG" }, "R8_CPLD.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R8_CPLD.1", "marker_data" : [ { "page" : "page4", "block" : "top/cpld_blk", "phys_page" : "page4", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "page_instance" : "I105", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page4_i105" } ], "part_number" : "400-000010-074", "pin_name" : "A", "net_name" : "ENB3V_SEQ_J_CPLD", "refdes" : "R8_CPLD", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "J8_XF.C" : { "node_name" : "J8_XF.C", "pin_number" : "C", "pin_type" : "INPUT", "pin_name_unsanitized" : "S", "pinuse" : "IN;", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page28", "phys_page" : "page28", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page28", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page28", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page28", "page_instance" : "I11", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page28_i11" } ], "pin_name" : "S", "net_name" : "VCCINT_BNC_XF", "refdes" : "J8_XF", "part_number" : "410-000168-001" }, "PM2_SP_XF.R8" : { "pinuse" : "IN;", "pin_name_unsanitized" : "MODE_CLKIN3", "part_number" : "462-000309-001", "pin_name" : "MODE_CLKIN3", "net_name" : "UNNAMED_6_LTM4671_I456_MODECLKIN3_SP", "refdes" : "PM2_SP_XF", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I456", "sym_num" : 4, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i456" } ], "node_name" : "PM2_SP_XF.R8", "pin_number" : "R8", "pin_type" : "INPUT" }, "R94.1" : { "refdes" : "R94", "pin_name" : "A", "net_name" : "UNNAMED_4_MAX116XXQSOP16_I97_AIN4", "part_number" : "400-000010-010", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page4", "page_instance" : "I64", "ppath_without_last_instance" : "top/page4", "ppath" : "top/page4_i64", "sym_num" : 1 } ], "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R94.1" }, "U1_XF.CC21" : { "pin_group" : "C0_ACTL_4_4;", "pin_name_unsanitized" : "C0_DDR4_ADR7", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk", "phys_page" : "page3", "sym_num" : 4, "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "page_instance" : "I2425" } ], "pin_name" : "C0_DDR4_ADR7", "net_name" : "C0_DDR4_ADR<7>_XF", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.CC21", "pin_number" : "CC21", "pin_type" : "INOUT" }, "U1_XF.CB32" : { "node_name" : "U1_XF.CB32", "pin_type" : "INOUT", "pin_number" : "CB32", "pin_name_unsanitized" : "GND_1070", "pin_group" : "ALL_POWER_PINS_38;", "refdes" : "U1_XF", "pin_name" : "GND_1070", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I73", "sym_num" : 38, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i73" } ] }, "U1_XF.BR3" : { "pin_group" : "ALL_POWER_PINS_37;", "pin_name_unsanitized" : "GND_963", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i72", "sym_num" : 37, "page_instance" : "I72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24" } ], "pin_name" : "GND_963", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.BR3", "pin_number" : "BR3", "pin_type" : "INOUT" }, "J1_PX1_XF.B5" : { "part_number" : "410-000328-001", "pin_name" : "SMCLK", "net_name" : "NC", "refdes" : "J1_PX1_XF", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i73/pcie_x1_conn_blk/page3", "page_instance" : "I14", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i73/pcie_x1_conn_blk/page3_i14", "block" : "top/xc2_fpga_blk/pcie_x1_conn_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i73@top_lib.pcie_x1_conn_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i73@top_lib.pcie_x1_conn_blk(sch_1):page3", "remapped_page" : null } ], "pinuse" : "BI;", "pin_name_unsanitized" : "SMCLK", "pin_type" : "INOUT", "pin_number" : "B5", "node_name" : "J1_PX1_XF.B5" }, "R116_SP_XF.2" : { "node_name" : "R116_SP_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;", "pin_name" : "B", "refdes" : "R116_SP_XF", "net_name" : "UNNAMED_7_BYPASSCAPNPOL_I55_B_SP", "part_number" : "400-000014-011", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i26", "sym_num" : 1, "page_instance" : "I26", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7" } ] }, "J3_XF.12" : { "node_name" : "J3_XF.12", "pin_number" : "12", "pin_type" : "INOUT", "pin_name_unsanitized" : "DQ2", "pinuse" : "TRI;", "refdes" : "J3_XF", "pin_name" : "DQ2", "net_name" : "C2_DDR4_DQ<2>_XF", "part_number" : "410-000300-001", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page8", "phys_page" : "page8", "page" : "page8", "block" : "top/xc2_fpga_blk", "ppath" : "top/page6_i428/xc2_fpga_blk/page8_i180", "sym_num" : 1, "page_instance" : "I180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page8" } ] }, "R66_XF.1" : { "node_name" : "R66_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page15", "page_instance" : "I5", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page15_i5", "block" : "top/xc2_fpga_blk", "page" : "page15", "phys_page" : "page15", "phys_path" : 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"pin_name_unsanitized" : "C1_DDR4_DQS_T5" }, "R191_SP_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R191_SP_XF.1", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page9", "page_instance" : "I23", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page9_i23", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page9", "phys_page" : "page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page9", "remapped_page" : null } ], "part_number" : "400-000015-015", "pin_name" : "A", "refdes" : "R191_SP_XF", "net_name" : "IS_VCCINTLR_SW_N_SP", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "J2_P1_XF.MH3" : { "pin_name_unsanitized" : "MH3", "pinuse" : "GROUND;", "refdes" : "J2_P1_XF", "net_name" : "GND", "pin_name" : "MH3", "part_number" : "410-000324-001", "marker_data" : [ { "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i53@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3", "page_instance" : "I85", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i53/ocl_2x4_pcie_blk/page3_i85" } ], "node_name" : "J2_P1_XF.MH3", "pin_number" : "MH3" }, "U1_CPLD.R14" : { "pin_group" : "ALRT_1;", "pin_name_unsanitized" : "LTC2975_AUXFAULT_F", "pinuse" : "BI;", "marker_data" : [ { "page" : "page3", "block" : "top/cpld_blk", "phys_page" : "page3", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page3", "page_instance" : "I447", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page3_i447" } ], "net_name" : "LTC2975_AUXFAULT_F", "pin_name" : "LTC2975_AUXFAULT_F", "refdes" : "U1_CPLD", "part_number" : "450-000313-001", "node_name" : "U1_CPLD.R14", "pin_type" : "INOUT", "pin_number" : "R14" }, "U1_XF.U42" : { "node_name" : "U1_XF.U42", "pin_type" : "INOUT", "pin_number" : "U42", "pin_group" : "ALL_POWER_PINS_34;", "pin_name_unsanitized" : "GND_241", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i69", "sym_num" : 34, "page_instance" : "I69", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk" } ], "part_number" : "450-000340-001", "pin_name" : "GND_241", "refdes" : "U1_XF", "net_name" : "GND" }, "J1_PX1_XF.A13" : { "pin_name_unsanitized" : "REFCLK_P", "pinuse" : "IN;", "pin_name" : "REFCLK_P", "net_name" : "PCIE_X1_REFP_XF", "refdes" : "J1_PX1_XF", "part_number" : "410-000328-001", "marker_data" : [ { "block" : "top/xc2_fpga_blk/pcie_x1_conn_blk", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i73@top_lib.pcie_x1_conn_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i73@top_lib.pcie_x1_conn_blk(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i73/pcie_x1_conn_blk/page3", "page_instance" : "I14", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i73/pcie_x1_conn_blk/page3_i14" } ], "node_name" : "J1_PX1_XF.A13", "pin_type" : "INPUT", "pin_number" : "A13" }, "R15_CPLD.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "R15_CPLD.2", "refdes" : "R15_CPLD", "pin_name" : "B", "net_name" : "GND", "part_number" : "400-000010-074", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page4", "remapped_page" : null, "block" : "top/cpld_blk", "page" : "page4", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page4_i85", "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page4", "page_instance" : "I85" } ], "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "pin_group" : "1;" }, "C1_SP_XF.2" : { "pin_name_unsanitized" : "B1", "pinuse" : "UNSPEC;", "pin_name" : "B1", "refdes" : "C1_SP_XF", "net_name" : "NC_TR_2_SP", "part_number" : "402-000500-008", "marker_data" : [ { "path" : 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"node_name" : "PM1_SP_XF.J3", "part_number" : "462-000309-001", "refdes" : "PM1_SP_XF", "net_name" : "PWR_NDIMM_VPP_XF", "pin_name" : "VOUT1_6", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i37", "sym_num" : 2, "page_instance" : "I37", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT1_6" }, "C13_E1_XF.2" : { "part_number" : "402-000010-028", "net_name" : "P12V_MAIN", "pin_name" : "B", "refdes" : "C13_E1_XF", "marker_data" : [ { "phys_path" : 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"GROUND;", "pin_name_unsanitized" : "MH3", "part_number" : "410-000324-001", "net_name" : "GND", "refdes" : "J1_P0_XF", "pin_name" : "MH3", "marker_data" : [ { "page_instance" : "I86", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i66/ocl_2x4_pcie_blk/page3_i86", "sym_num" : 1, "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_2x4_pcie_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i66@top_lib.ocl_2x4_pcie_blk(sch_1):page3" } ] }, "PM4_ND_XF.E2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "GPIO0_F", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "remapped_page" : null, "phys_path" : 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"pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C47.1" }, "U1_XF.L20" : { "pin_group" : "ALL_POWER_PINS_28;", "pin_name_unsanitized" : "VREF_77", "marker_data" : [ { "phys_page" : "page22", "block" : "top/xc2_fpga_blk", "page" : "page22", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page22", "page_instance" : "I62", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page22", "ppath" : "top/page6_i428/xc2_fpga_blk/page22_i62", "sym_num" : 28 } ], "net_name" : "UNNAMED_22_RESISTOR_I34_B_XF", "pin_name" : "VREF_77", "refdes" : "U1_XF", "part_number" : "450-000340-001", "node_name" : "U1_XF.L20", "pin_type" : "INOUT", "pin_number" : "L20" }, "U11_FL_XF.29" : { "pin_number" : "29", "pin_type" : "POWER", "node_name" : "U11_FL_XF.29", "part_number" : "450-000057-001", "refdes" : "U11_FL_XF", "pin_name" : "GND_TAB", "net_name" : "GND", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9", "page_instance" : "I66", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page25_i29/fpga_lin_pwr1/page9_i66", "page" : "page9", "block" : "top/xc2_fpga_blk/fpga_lin_pwr1", "phys_page" : "page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page25_i29@top_lib.fpga_lin_pwr1(sch_1):page9", "remapped_page" : null } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_TAB" }, "C65_CPLD.1" : { "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "pin_group" : "1;", "refdes" : "C65_CPLD", "pin_name" : "A", "net_name" : "CPLD_P1R8V_1", "part_number" : "402-000010-001", "marker_data" : [ { "phys_page" : "page8", "block" : "top/cpld_blk", "page" : "page8", "remapped_page" : null, "phys_path" : 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"page_instance" : "I83" } ], "part_number" : "400-000014-011", "pin_name" : "A", "net_name" : "SGND_PM5_SP", "refdes" : "R6_SP_XF", "node_name" : "R6_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "U1_XF.CA36" : { "pin_group" : "MGMT_8_8;", "pin_name_unsanitized" : "BOARD_CFG_SW1", "marker_data" : [ { "page" : "page16", "block" : "top/xc2_fpga_blk", "phys_page" : "page16", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page16", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page16", "page_instance" : "I96", "sym_num" : 8, "ppath" : "top/page6_i428/xc2_fpga_blk/page16_i96" } ], "pin_name" : "BOARD_CFG_SW1", "refdes" : "U1_XF", "net_name" : "BOARD_CFG_SW<1>", "part_number" : "450-000340-001", "node_name" : "U1_XF.CA36", "pin_number" : "CA36", "pin_type" : "INOUT" }, "U1_XF.BF12" : { "node_name" : "U1_XF.BF12", "pin_type" : "INOUT", "pin_number" : "BF12", "pin_group" : "ALL_SIGNAL_PINS_3;", "pin_name_unsanitized" : "MGTREFCLK1N_224", "marker_data" : [ { "phys_page" : "page11", "page" : "page11", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page11", "page_instance" : "I775", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page11_i775", "sym_num" : 3 } ], "refdes" : "U1_XF", "pin_name" : "MGTREFCLK1N_224", "net_name" : "NC", "part_number" : "450-000340-001" }, "U1_XF.BB29" : { "node_name" : "U1_XF.BB29", "pin_type" : "INOUT", "pin_number" : "BB29", "pin_name_unsanitized" : "VCCINT_200", "pin_group" : "ALL_POWER_PINS_31;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "VCCINT_200", "net_name" : "PWR_VCCINT_XF", "marker_data" : [ { "page_instance" : "I186", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i186", "sym_num" : 31, "phys_page" : "page23", "page" : "page23", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23" } ] }, "PM1_SP_XF.T11" : { "pin_number" : "T11", "node_name" : "PM1_SP_XF.T11", "marker_data" : [ { "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "sym_num" : 5, "page_instance" : "I11", "ppath_without_last_instance" : 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"UNSPEC;", "pin_group" : "1;", "net_name" : "GND", "pin_name" : "B", "refdes" : "C205_XF", "part_number" : "402-000015-007", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page23", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page23", "phys_page" : "page23", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page23_i159", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page23", "page_instance" : "I159" } ], "node_name" : "C205_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "R49.2" : { "marker_data" : [ { "block" : "top", "page" : "page3", "phys_page" : "page3", "phys_path" : "@top_lib.top(sch_1):page3", "path" : "@top_lib.top(sch_1):page3", "remapped_page" : null, "ppath_without_last_instance" : "top/page3", "page_instance" : "I62", "sym_num" : 1, "ppath" : "top/page3_i62" } ], "pin_name" : "B", "refdes" : "R49", "net_name" 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"pinuse" : "UNSPEC;", "pin_group" : "1;" }, "U1_XF.BA19" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "page_instance" : "I71", "sym_num" : 36, "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i71", "page" : "page24", "block" : "top/xc2_fpga_blk", "phys_page" : "page24", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "remapped_page" : null } ], "pin_name" : "GND_719", "net_name" : "GND", "refdes" : "U1_XF", "part_number" : "450-000340-001", "pin_group" : "ALL_POWER_PINS_36;", "pin_name_unsanitized" : "GND_719", "pin_type" : "INOUT", "pin_number" : "BA19", "node_name" : "U1_XF.BA19" }, "C4_E2_XF.2" : { "pin_type" : "ANALOG", "pin_number" : "2", "node_name" : "C4_E2_XF.2", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i97@top_lib.cxltc_2c_x8(sch_1):page3", "phys_path" : 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"ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page17", "ppath" : "top/page6_i428/xc2_fpga_blk/page17_i36", "sym_num" : 1, "phys_page" : "page17", "page" : "page17", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page17" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "R84_XF.1" }, "J1_XF.196" : { "node_name" : "J1_XF.196", "pin_number" : "196", "pin_type" : "INOUT", "pinuse" : "TRI;", "pin_name_unsanitized" : "DQS8_C", "part_number" : "410-000300-001", "pin_name" : "DQS8_C", "net_name" : "C0_RDIMM_DQS_C<8>_XF", "refdes" : "J1_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk", "phys_page" : "page4", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i180", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I180" } ] }, "C366_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "402-000010-035", "net_name" : "C3_SYS_CLK_P_XF", "pin_name" : "B", "refdes" : "C366_XF", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_page" : "page9", "block" : "top/xc2_fpga_blk", "page" : "page9", "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2418", "sym_num" : 1, "page_instance" : "I2418", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9" } ], "node_name" : "C366_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "PM3_SP_XF.L9" : { "pin_type" : "POWER", "pin_number" : "L9", "node_name" : "PM3_SP_XF.L9", "part_number" : "462-000308-002", "pin_name" : "VIN_20", "net_name" : "P12V_4650_BL_SP", "refdes" : "PM3_SP_XF", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page10", "remapped_page" : null, "page" : "page10", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page10", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10_i152", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page10", "page_instance" : "I152" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_20" }, "C35.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C35.1", "part_number" : "402-000010-018", "pin_name" : "A", "net_name" : "PWR_FPGA_3R3V", "refdes" : "C35", "marker_data" : [ { "ppath" : "top/page7_i17", "sym_num" : 1, "page_instance" : "I17", "ppath_without_last_instance" : "top/page7", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page7", "phys_page" : "page7", "page" : "page7", "block" : "top" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "R108_ND_XF.1" : { "node_name" : "R108_ND_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i23", "sym_num" : 1, "page_instance" : "I23", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3" } ], "part_number" : "400-000014-011", "refdes" : "R108_ND_XF", "pin_name" : "A", "net_name" : "UNNAMED_3_LTM4675_I40_COMP0B_ND" }, "C106_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C106_XF.1", "marker_data" : [ { "phys_page" : "page12", "block" : "top/xc2_fpga_blk", "page" : "page12", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "page_instance" : "I71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i71", "sym_num" : 1 } ], "part_number" : "402-000010-035", "net_name" : "AC_E1S0_PET_P<3>_XF", "pin_name" : "A", "refdes" : "C106_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A" }, "C42.1" : { "node_name" : "C42.1", "pin_number" : "1", "pin_type" : "ANALOG", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "402-000010-001", "refdes" : "C42", "pin_name" : "A", "net_name" : "GND", "marker_data" : [ { "block" : "top", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page4", "path" : "@top_lib.top(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page4", "page_instance" : "I51", "sym_num" : 1, "ppath" : "top/page4_i51" } ] }, "C50_SP_XF.1" : { "node_name" : "C50_SP_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "phys_page" : "page3", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page3", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page3", 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"phys_page" : "page7" } ], "pinuse" : "POWER;", "pin_name_unsanitized" : "VOUT3_7", "pin_number" : "T2", "node_name" : "PM1_SP_XF.T2" }, "U1_XF.K19" : { "part_number" : "450-000340-001", "pin_name" : "C3_DDR4_DQ3", "net_name" : "C3_DDR4_DQ<3>_XF", "refdes" : "U1_XF", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "PAGE9", "phys_page" : "PAGE9", "sym_num" : 48, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2425" } ], "pin_name_unsanitized" : "C3_DDR4_DQ3", "pin_group" : "C3_LNIB_1_7_48;", "pin_number" : "K19", "pin_type" : "INOUT", "node_name" : "U1_XF.K19" }, "PM4_SP_XF.L11" : { "node_name" : "PM4_SP_XF.L11", "pin_type" : "POWER", "pin_number" : "L11", "pinuse" : "POWER;", "pin_name_unsanitized" : "VIN_22", "marker_data" : [ { "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page4_i80", "sym_num" : 1, "phys_page" : "page4", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page4" } ], "part_number" : "462-000308-002", "net_name" : "P12V_4650_TL_SP", "pin_name" : "VIN_22", "refdes" : "PM4_SP_XF" }, "J1_PX1_XF.B1" : { "net_name" : "NC", "refdes" : "J1_PX1_XF", "pin_name" : "P12V_1", "part_number" : "410-000328-001", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i73/pcie_x1_conn_blk/page3_i14", "sym_num" : 1, "page_instance" : "I14", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i73/pcie_x1_conn_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i73@top_lib.pcie_x1_conn_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i73@top_lib.pcie_x1_conn_blk(sch_1):page3", "phys_page" : "page3", "page" : "page3", "block" : "top/xc2_fpga_blk/pcie_x1_conn_blk" } ], "pin_name_unsanitized" : "P12V_1", "pinuse" : "POWER;", "pin_number" : "B1", "node_name" : "J1_PX1_XF.B1" }, "R4_E0_XF.1" : { "node_name" : "R4_E0_XF.1", "pin_type" : "ANALOG", "pin_number" : "1", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;", "part_number" : "400-000010-007", "pin_name" : "A", "net_name" : "P3R3V", "refdes" : "R4_E0_XF", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3_i80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i206/cxltc_2c_x8/page3", "page_instance" : "I80", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i206@top_lib.cxltc_2c_x8(sch_1):page3", "remapped_page" : null, "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "page" : "page3", "phys_page" : "page3" } ] }, "C463_XF.1" : { "node_name" : "C463_XF.1", "pin_number" : "1", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page20_i72", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page20", "page_instance" : "I72", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page20", "remapped_page" : null, "page" : "page20", "block" : "top/xc2_fpga_blk", "phys_page" : "page20" } ], "pin_name" : "A", "refdes" : "C463_XF", "net_name" : "PWR_AVCC_RS_RLC_XF", "part_number" : "402-000010-028" }, "C86_SP_XF.2" : { "node_name" : "C86_SP_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i472", "sym_num" : 1, "page_instance" : "I472", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page6" } ], "pin_name" : "B", "net_name" : "UNNAMED_6_LTM4671_I457_TRACKSS1_SP", "refdes" : "C86_SP_XF", "part_number" : "402-000050-020" }, "C162_XF.1" : { "pin_number" : "1", "pin_type" : "ANALOG", "node_name" : "C162_XF.1", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page21", "phys_page" : "page21", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page21", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page21", "page_instance" : "I21", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page21_i21" } ], "pin_name" : "A", "refdes" : "C162_XF", "net_name" : "PWR_SDIMM_VDD_XF", "part_number" : "402-000015-008", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "FB9.1" : { "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;", "marker_data" : [ { "page_instance" : "I72", "ppath_without_last_instance" : "top/page20", "ppath" : "top/page20_i72", "sym_num" : 1, "phys_page" : "page20", "page" : "page20", "block" : "top", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page20", "phys_path" : "@top_lib.top(sch_1):page20" } ], "pin_name" : "A", "net_name" : "UNNAMED_20_FERRITEBEAD_I72_A", "refdes" : "FB9", "part_number" : "401-000001-002", "node_name" : "FB9.1", "pin_number" : "1", "pin_type" : "ANALOG" }, "U1_XF.BR37" : { "pin_name_unsanitized" : "IO_L5P_T0U_N8_AD14P_67", "pin_group" : "ALL_SIGNAL_PINS_20;", "pin_name" : "IO_L5P_T0U_N8_AD14P_67", "net_name" : "NC", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "page_instance" : "I49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i49", "sym_num" : 20 } ], "node_name" : "U1_XF.BR37", "pin_type" : "INOUT", "pin_number" : "BR37" }, "Q5.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "S", "marker_data" : [ { "ppath_without_last_instance" : "top/page19", "page_instance" : "I39", "sym_num" : 1, "ppath" : "top/page19_i39", "block" : "top", "page" : "page19", "phys_page" : "page19", "phys_path" : "@top_lib.top(sch_1):page19", "path" : "@top_lib.top(sch_1):page19", "remapped_page" : null } ], "part_number" : "405-000010-001", "net_name" : "GND", "pin_name" : "S", "refdes" : "Q5", "node_name" : "Q5.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_XF.K24" : { "node_name" : "U1_XF.K24", "pin_number" : "K24", "pin_type" : "INOUT", "pin_name_unsanitized" : "C3_DDR4_DQ14", "pin_group" : "C3_UNIB_1_7_48;", "net_name" : "C3_DDR4_DQ<14>_XF", "pin_name" : "C3_DDR4_DQ14", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page" : "PAGE9", "block" : "top/xc2_fpga_blk", "phys_page" : "PAGE9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page9", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page9", "page_instance" : "I2425", "sym_num" : 49, "ppath" : "top/page6_i428/xc2_fpga_blk/page9_i2425" } ] }, "R18_E1_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "400-000010-010", "net_name" : "GND", "pin_name" : "B", "refdes" : "R18_E1_XF", "marker_data" : [ { "phys_page" : "page4", "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12_i183@top_lib.cxltc_2c_x8(sch_1):page4", "page_instance" : "I38", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i183/cxltc_2c_x8/page4_i38", "sym_num" : 1 } ], "node_name" : "R18_E1_XF.2", "pin_number" : "2", "pin_type" : "ANALOG" }, "U2_CPLD.1" : { "pin_name_unsanitized" : "I1", "pinuse" : "IN;", "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page8", "page_instance" : "I17", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page8_i17", "page" : "page8", "block" : "top/cpld_blk", "phys_page" : "page8", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page8", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page8", "remapped_page" : null } ], "pin_name" : "I1", "refdes" : "U2_CPLD", "net_name" : "JT_CPLD_TMS", "part_number" : "450-000331-001", "node_name" : "U2_CPLD.1", "pin_number" : "1", "pin_type" : "INPUT" }, "U1_XF.BT41" : { "node_name" : "U1_XF.BT41", "pin_type" : "INOUT", "pin_number" : "BT41", "pin_name_unsanitized" : "IO_L7P_T1L_N0_QBC_AD13P_20", "pin_group" : "ALL_SIGNAL_PINS_17;", "net_name" : "NC", "pin_name" : "IO_L7P_T1L_N0_QBC_AD13P_20", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "phys_page" : "page30", "page" : "page30", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "page_instance" : "I50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "sym_num" : 17 } ] }, "PM4_ND_XF.F8" : { "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page3", "phys_page" : "page3", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page3", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3_i20", "sym_num" : 2, "page_instance" : "I20", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page3" } ], "part_number" : "462-000304-001", "pin_name" : "GND_25", "refdes" : "PM4_ND_XF", "net_name" : "GND", "pinuse" : "POWER;", "pin_name_unsanitized" : "GND_25", "pin_number" : "F8", "pin_type" : "POWER", "node_name" : "PM4_ND_XF.F8" }, "R285_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R285_XF.1", "part_number" : "400-000010-007", "refdes" : "R285_XF", "pin_name" : "A", "net_name" : "P3R3V", "marker_data" : [ { "page" : "page19", "block" : "top/xc2_fpga_blk", "phys_page" : "page19", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19", "page_instance" : "I84", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i84" } ], "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_group" : "1;" }, "U1_XF.AB9" : { "node_name" : "U1_XF.AB9", "pin_number" : "AB9", "pin_type" : "INOUT", "pin_name_unsanitized" : "E1S2_PET_P5", "pin_group" : "ALL_SIGNAL_PINS_10;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "E1S2_PET_P5", "net_name" : "AC_E1S2_PET_P<5>_XF", "marker_data" : [ { "phys_page" : "page13", "page" : "page13", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13", "page_instance" : "I251", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13", "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i251", "sym_num" : 10 } ] }, "R14_E3_XF.2" : { "pin_number" : "2", "pin_type" : "ANALOG", "node_name" : "R14_E3_XF.2", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4_i42", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page13_i1/cxltc_2c_x8/page4", "page_instance" : "I42", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page13_i1@top_lib.cxltc_2c_x8(sch_1):page4", "remapped_page" : null, "page" : "page4", "block" : "top/xc2_fpga_blk/cxltc_2c_x8", "phys_page" : "page4" } ], "pin_name" : "B", "net_name" : "CLKIN_P_E3", "refdes" : "R14_E3_XF", "part_number" : "400-000010-010", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;" }, "U1_XF.AL41" : { "pin_name" : "GND_535", "refdes" : "U1_XF", "net_name" : "GND", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I70", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page24", "ppath" : "top/page6_i428/xc2_fpga_blk/page24_i70", "sym_num" : 35, "phys_page" : "page24", "page" : "page24", "block" : "top/xc2_fpga_blk", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page24" } ], "pin_name_unsanitized" : "GND_535", "pin_group" : "ALL_POWER_PINS_35;", "pin_type" : "INOUT", "pin_number" : "AL41", "node_name" : "U1_XF.AL41" }, "U1_XF.BR18" : { "part_number" : "450-000340-001", "net_name" : "C0_DDR4_DQ<20>_XF", "pin_name" : "C0_DDR4_DQ20", "refdes" : "U1_XF", "marker_data" : [ { "ppath" : "top/page6_i428/xc2_fpga_blk/page3_i2425", "sym_num" : 68, "page_instance" : "I2425", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page3", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page3", "phys_page" : "PAGE3", "page" : "PAGE3", "block" : "top/xc2_fpga_blk" } ], "pin_name_unsanitized" : "C0_DDR4_DQ20", "pin_group" : "C0_UNIB_1_4_66;", "pin_type" : "INOUT", "pin_number" : "BR18", "node_name" : "U1_XF.BR18" }, "U1_CPLD.A16" : { "pin_number" : "A16", "node_name" : "U1_CPLD.A16", "refdes" : "U1_CPLD", "net_name" : "CPLD_P3R3V", "pin_name" : "VCC_2", "part_number" : "450-000313-001", "marker_data" : [ { "page" : "page7", "block" : "top/cpld_blk", "phys_page" : "page7", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page7", "remapped_page" : null, "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page7", "page_instance" : "I151", "sym_num" : 7, "ppath" : "top/page14_i1/cpld_blk/page7_i151" } ], "pin_name_unsanitized" : "VCC_2", "pinuse" : "POWER;" }, "U1_XF.BA15" : { "pin_number" : "BA15", "pin_type" : "INOUT", "node_name" : "U1_XF.BA15", "marker_data" : [ { "page_instance" : "I57", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", 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"top/page6_i428/xc2_fpga_blk/page23_i47" } ], "part_number" : "402-000015-007", "pin_name" : "A", "net_name" : "PWR_VCCINT_XF", "refdes" : "C261_XF", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C261_XF.1" }, "PM2_SP_XF.D2" : { "node_name" : "PM2_SP_XF.D2", "pin_number" : "D2", "pin_name_unsanitized" : "VOUT0_9", "pinuse" : "POWER;", "marker_data" : [ { "page" : "page6", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page6", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page6", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6", "page_instance" : "I516", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page6_i516" } ], "refdes" : "PM2_SP_XF", "net_name" : "PWR_AVTT_SW_XF", "pin_name" : "VOUT0_9", "part_number" : "462-000309-001" }, "U1_XF.BM4" : { "pin_group" : "ALL_SIGNAL_PINS_12;", "pin_name_unsanitized" : "OCL2_PER_P0", "marker_data" : [ { "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page14", "page_instance" : "I275", "sym_num" : 12, "ppath" : "top/page6_i428/xc2_fpga_blk/page14_i275", "page" : "page14", "block" : "top/xc2_fpga_blk", "phys_page" : "page14", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page14", "remapped_page" : null } ], "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "OCL2_PER_P0", "net_name" : "OCL2_PER_P<0>_XF", "node_name" : "U1_XF.BM4", "pin_type" : "INOUT", "pin_number" : "BM4" }, "R104_SP_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "R104_SP_XF.1", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i49", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I49", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page7", "phys_page" : "page7" } ], "pin_name" : "A", "net_name" : "PM1_SP_AGND_SP", "refdes" : "R104_SP_XF", "part_number" : "400-000014-011", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "NS3_ND_XF.2" : { "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "pin_group" : "1;", "part_number" : "NET_SHORT", "pin_name" : "B", "refdes" : "NS3_ND_XF", "net_name" : "VS_DIMM_VTT_LIN_ND", "marker_data" : [ { "phys_page" : "page4", "block" : "top/xc2_fpga_blk/dimm_pwr_blk", "page" : "page4", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page27_i1@top_lib.dimm_pwr_blk(sch_1):page4", "page_instance" : "I5", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4", "ppath" : "top/page6_i428/xc2_fpga_blk/page27_i1/dimm_pwr_blk/page4_i5", "sym_num" : 1 } ], "node_name" : "NS3_ND_XF.2", "pin_type" : "ANALOG", "pin_number" : "2" }, "U1_XF.BP41" : { "pin_type" : "INOUT", "pin_number" : "BP41", "node_name" : "U1_XF.BP41", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L2P_T0L_N2_19", "net_name" : "NC", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page30", "remapped_page" : null, "page" : "page30", "block" : "top/xc2_fpga_blk", "phys_page" : "page30", "sym_num" : 17, "ppath" : "top/page6_i428/xc2_fpga_blk/page30_i50", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page30", "page_instance" : "I50" } ], "pin_name_unsanitized" : "IO_L2P_T0L_N2_19", "pin_group" : "ALL_SIGNAL_PINS_17;" }, "U1_XF.N37" : { "node_name" : "U1_XF.N37", "pin_number" : "N37", "pin_type" : "INOUT", "pin_name_unsanitized" : "IO_L11N_T1U_N9_GC_70", "pin_group" : "ALL_SIGNAL_PINS_25;", "part_number" : "450-000340-001", "refdes" : "U1_XF", "pin_name" : "IO_L11N_T1U_N9_GC_70", "net_name" : "NC", "marker_data" : [ { "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page31", "remapped_page" : null, "block" : "top/xc2_fpga_blk", "page" : "page31", "phys_page" : "page31", "sym_num" : 25, "ppath" : "top/page6_i428/xc2_fpga_blk/page31_i59", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page31", "page_instance" : "I59" } ] }, "C106_XF.2" : { "node_name" : "C106_XF.2", "pin_number" : "2", "pin_type" : "ANALOG", "pin_group" : "1;", "pin_name_unsanitized" : "B", "pinuse" : "UNSPEC;", "marker_data" : [ { "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page12_i71", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page12", "page_instance" : "I71", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page12", "remapped_page" : null, "page" : "page12", "block" : "top/xc2_fpga_blk", "phys_page" : "page12" } ], "refdes" : "C106_XF", "pin_name" : "B", "net_name" : "E1S0_PET_P<3>_XF", "part_number" : "402-000010-035" }, "C178_SP_XF.1" : { "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "A", "marker_data" : [ { "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page9", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page9", "phys_page" : "page9", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page9", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page9_i3", "sym_num" : 1, "page_instance" : "I3", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page9" } ], "part_number" : "402-000010-001", "net_name" : "P3R3V", "pin_name" : "A", "refdes" : "C178_SP_XF", "node_name" : "C178_SP_XF.1", "pin_type" : "ANALOG", "pin_number" : "1" }, "C127_SP_XF.1" : { "pin_type" : "ANALOG", "pin_number" : "1", "node_name" : "C127_SP_XF.1", "marker_data" : [ { "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page8", "phys_page" : "page8", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page8", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8", "page_instance" : "I97", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page8_i97" } ], "pin_name" : "A", "net_name" : "IS_VCCINTUL_SW_N_SP", "refdes" : "C127_SP_XF", "part_number" : "402-000010-001", "pin_group" : "1;", "pin_name_unsanitized" : "A", "pinuse" : "UNSPEC;" }, "PM1_SP_XF.U2" : { "node_name" : "PM1_SP_XF.U2", "pin_number" : "U2", "pin_name_unsanitized" : "VOUT3_8", "pinuse" : "POWER;", "net_name" : "PWR_SPARE_SW_XF", "refdes" : "PM1_SP_XF", "pin_name" : "VOUT3_8", "part_number" : "462-000309-001", "marker_data" : [ { "sym_num" : 4, "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i36", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "page_instance" : "I36", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "remapped_page" : null, "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "phys_page" : "page7" } ] }, "C8_XF.2" : { "node_name" : "C8_XF.2", "pin_type" : "ANALOG", "pin_number" : "2", "pin_group" : "1;", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "B", "marker_data" : [ { "block" : "top/xc2_fpga_blk", "page" : "page4", "phys_page" : "page4", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page4", "remapped_page" : null, "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page4", "page_instance" : "I161", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page4_i161" } ], "part_number" : "402-000010-028", "refdes" : "C8_XF", "pin_name" : "B", "net_name" : "PWR_SDIMM_VDD_XF" }, "Q12.3" : { "node_name" : "Q12.3", "pin_type" : "ANALOG", "pin_number" : "3", "pinuse" : "UNSPEC;", "pin_name_unsanitized" : "D", "marker_data" : [ { "phys_page" : "page7", "block" : "top", "page" : "page7", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page7", "path" : "@top_lib.top(sch_1):page7", "page_instance" : "I2", "ppath_without_last_instance" : "top/page7", "ppath" : "top/page7_i2", "sym_num" : 1 } ], "part_number" : "405-000010-001", "refdes" : "Q12", "pin_name" : "D", "net_name" : "UNNAMED_7_NMOSFETVMT3_I2_D" }, "PM1_SP_XF.F1" : { "part_number" : "462-000309-001", "net_name" : "GND", "refdes" : "PM1_SP_XF", "pin_name" : "GND_29", "marker_data" : [ { "phys_page" : "page7", "page" : "page7", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "remapped_page" : null, "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page7", "page_instance" : "I11", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page7_i11", "sym_num" : 5 } ], "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_29", "pin_number" : "F1", "node_name" : "PM1_SP_XF.F1" }, "J1_O3_XF.B20" : { "pin_number" : "B20", "node_name" : "J1_O3_XF.B20", "part_number" : "410-000324-001", "pin_name" : "GND_14", "refdes" : "J1_O3_XF", "net_name" : "GND", "marker_data" : [ { "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i52@top_lib.ocl_x4_conn_blk(sch_1):page3", "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page19_i52@top_lib.ocl_x4_conn_blk(sch_1):page3", "remapped_page" : null, "page" : "page3", "block" : "top/xc2_fpga_blk/ocl_x4_conn_blk", "phys_page" : "page3", "sym_num" : 1, "ppath" : "top/page6_i428/xc2_fpga_blk/page19_i52/ocl_x4_conn_blk/page3_i84", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page19_i52/ocl_x4_conn_blk/page3", "page_instance" : "I84" } ], "pinuse" : "GROUND;", "pin_name_unsanitized" : "GND_14" }, "PM7_SP_XF.J4" : { "pin_name" : "VIN_3", "refdes" : "PM7_SP_XF", "net_name" : "P12V_4650_BR_SP", "part_number" : "462-000308-002", "marker_data" : [ { "phys_page" : "page11", "block" : "top/xc2_fpga_blk/sw_pwr_blk1", "page" : "page11", "remapped_page" : null, "phys_path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "path" : "@top_lib.top(sch_1):page6_i428@top_lib.xc2_fpga_blk(sch_1):page26_i169@top_lib.sw_pwr_blk1(sch_1):page11", "page_instance" : "I80", "ppath_without_last_instance" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11", "ppath" : "top/page6_i428/xc2_fpga_blk/page26_i169/sw_pwr_blk1/page11_i80", "sym_num" : 1 } ], "pin_name_unsanitized" : "VIN_3", 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"pin_group" : "ALL_POWER_PINS_35;", "pin_name_unsanitized" : "GND_550", "pin_type" : "INOUT", "pin_number" : "AM26", "node_name" : "U1_XF.AM26" }, "D6_CPLD.2" : { "marker_data" : [ { "ppath_without_last_instance" : "top/page14_i1/cpld_blk/page9", "page_instance" : "I15", "sym_num" : 1, "ppath" : "top/page14_i1/cpld_blk/page9_i15", "block" : "top/cpld_blk", "page" : "page9", "phys_page" : "page9", "phys_path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "path" : "@top_lib.top(sch_1):page14_i1@top_lib.cpld_blk(sch_1):page9", "remapped_page" : null } ], "net_name" : "UNNAMED_9_LED_I15_A_CPLD", "pin_name" : "A", "refdes" : "D6_CPLD", "part_number" : "404-000001-003", "pin_name_unsanitized" : "A", "pinuse" : "BI;", "pin_type" : "INOUT", "pin_number" : "2", "node_name" : "D6_CPLD.2" }, "U1_XF.AY63" : { "net_name" : "NC", "pin_name" : "IO_L20N_T3L_N3_AD1N_25", "refdes" : "U1_XF", "part_number" : "450-000340-001", "marker_data" : [ { "page_instance" : "I47", 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"node_list" : [ "J2_XF.121", "U1_XF.BL57" ], "diff_pair_pol" : "POS", "net_name" : "C1_RDIMM_DQS_T<15>_XF", "diff_pair_mate" : "C1_RDIMM_DQS_C<15>_XF", "voltage" : "" }, "AC_FPGA_CLK_REF_N<0>" : { "diff_pair_mate" : "AC_FPGA_CLK_REF_P<0>", "net_name" : "AC_FPGA_CLK_REF_N<0>", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "C23_E1_XF.1", "U1_E1_XF.23" ] }, "UNNAMED_7_LTM4671_I87_FB0_SP" : { "net_name" : "UNNAMED_7_LTM4671_I87_FB0_SP", "voltage" : "", "node_list" : [ "C135_SP_XF.2", "PM1_SP_XF.G9", "R69_SP_XF.2" ] }, "UNNAMED_17_RESISTOR_I61_A_XF" : { "node_list" : [ "R106_XF.2", "R107_XF.2", "R97_XF.1" ], "voltage" : "", "net_name" : "UNNAMED_17_RESISTOR_I61_A_XF" }, "UNNAMED_22_RESISTOR_I61_B_XF" : { "node_list" : [ "R160_XF.2", "U1_XF.CC31" ], "voltage" : "", "net_name" : "UNNAMED_22_RESISTOR_I61_B_XF" }, "UNNAMED_9_LED_I15_A_CPLD" : { "node_list" : [ "D6_CPLD.2", "R117_CPLD.1" ], "voltage" : "", "net_name" : "UNNAMED_9_LED_I15_A_CPLD" }, "C2_DDR4_DQ<34>_XF" : { "net_name" : "C2_DDR4_DQ<34>_XF", "voltage" : "", "node_list" : [ "J3_XF.104", "U1_XF.F56" ] }, "PCIE0_RXP<6>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "diff_pair_mate" : "PCIE0_RXN<6>_XF", "net_name" : "PCIE0_RXP<6>_XF", "node_list" : [ "J2_P0_XF.A15", "U1_XF.BB4" ] }, "C3_DDR4_DQ<11>_XF" : { "net_name" : "C3_DDR4_DQ<11>_XF", "voltage" : "", "node_list" : [ "J4_XF.168", "U1_XF.J25" ] }, "FP_INTRUSION_N" : { "node_list" : [ "FPNL_CONN.20", "U1_CPLD.K16" ], "net_name" : "FP_INTRUSION_N", "voltage" : "" }, "OCL0_PER_P<0>_XF" : { "node_list" : [ "J1_O0_XF.A3", "U1_XF.BY4" ], "voltage" : "", "diff_pair_pol" : "POS", "diff_pair_mate" : "OCL0_PER_N<0>_XF", "net_name" : "OCL0_PER_P<0>_XF" }, "DIS_1R8V_I2C_XLAT_F" : { "node_list" : [ "R4.1", "R58.1", "U1_CPLD.H3" ], "voltage" : "1.8V", "net_name" : "DIS_1R8V_I2C_XLAT_F" }, "FPGA_CPLD_SSTAT" : { "voltage" : "", "net_name" : "FPGA_CPLD_SSTAT", "node_list" : [ "U1_CPLD.K1", "U1_XF.CC32" ] }, "C1_DDR4_DQ<16>_XF" : { "node_list" : [ "J2_XF.27", "U1_XF.BT56" ], "net_name" : "C1_DDR4_DQ<16>_XF", "voltage" : "" }, "UNNAMED_17_RESISTOR_I95_B_XF" : { "voltage" : "", "net_name" : "UNNAMED_17_RESISTOR_I95_B_XF", "node_list" : [ "R108_XF.2", "R109_XF.2", "R98_XF.1" ] }, "E1S_REF_CLK_N<2>" : { "node_list" : [ "C17_E2_XF.1", "U1.34" ], "diff_pair_mate" : "E1S_REF_CLK_P<2>", "net_name" : "E1S_REF_CLK_N<2>", "diff_pair_pol" : "NEG", "voltage" : "" }, "C1_DDR4_DQ<29>_XF" : { "node_list" : [ "J2_XF.181", "U1_XF.CB59" ], "voltage" : "", "net_name" : "C1_DDR4_DQ<29>_XF" }, "C1_DDR4_ACT_N_XF" : { "voltage" : "", "net_name" : "C1_DDR4_ACT_N_XF", "node_list" : [ "J2_XF.62", "U1_XF.BY53" ] }, "BASE_3R3V_SCL_2" : { "node_list" : [ "J1_XF.141", "J2_XF.141", "J3_XF.141", "J4_XF.141", "J5.5", "PM4_ND_XF.E4", "PM4_SD_XF.E4", "Q1.3", "Q3.3", "R34.2", "U11.13", "U12.6", "U1_CPLD.A9", "U1_SP_XF.30", "U4_SP_XF.12" ], "voltage" : "3.3V", "net_name" : "BASE_3R3V_SCL_2" }, "FPGA_CFG_MODE<0>_1" : { "voltage" : "", "net_name" : "FPGA_CFG_MODE<0>_1", "node_list" : [ "U1_CPLD.H2", "U1_XF.AH17" ] }, "E1S0_3R3V_PERST_CLKREQ_F<1>_XF" : { "net_name" : "E1S0_3R3V_PERST_CLKREQ_F<1>_XF", "voltage" : "3.3V", "node_list" : [ "J1_E0_XF.A11", "R7_E0_XF.2", "U1_XF.Y18" ] }, "C2_DDR4_SA<1>_XF" : { "node_list" : [ "J3_XF.140", "R264_XF.2" ], "net_name" : "C2_DDR4_SA<1>_XF", "voltage" : "" }, "C2_DDR4_ADR<6>_XF" : { "net_name" : "C2_DDR4_ADR<6>_XF", "voltage" : "", "node_list" : [ "J3_XF.69", "U1_XF.M61" ] }, "AC_FPGA_CLK_REF_P<1>_1" : { "voltage" : "", "net_name" : "AC_FPGA_CLK_REF_P<1>_1", "diff_pair_mate" : "AC_FPGA_CLK_REF_N<1>_1", "diff_pair_pol" : "POS", "node_list" : [ "C18_E0_XF.1", "U1_E0_XF.27" ] }, "UNNAMED_10_RESISTOR_I69_B" : { "voltage" : "", "net_name" : "UNNAMED_10_RESISTOR_I69_B", "node_list" : [ "R112.2", "U1.18" ] }, "UNNAMED_15_MAX4641_I1_IN2_XF" : { "node_list" : [ "Q1_XF.3", "R116_XF.1", "U4_XF.3" ], "net_name" : "UNNAMED_15_MAX4641_I1_IN2_XF", "voltage" : "" }, "C3_DDR4_BG<0>_XF" : { "node_list" : [ "J4_XF.63", "U1_XF.U25" ], "net_name" : "C3_DDR4_BG<0>_XF", "voltage" : "" }, "UNNAMED_3_LTM4675_I40_WP_SD" : { "node_list" : [ "PM4_SD_XF.K4", "R26_SD_XF.2" ], "net_name" : "UNNAMED_3_LTM4675_I40_WP_SD", "voltage" : "" }, "PS_ON_N" : { "node_list" : [ "J3.16", "Q5.3" ], "voltage" : "", "net_name" : "PS_ON_N" }, "CFG_FLASH_RST_F" : { "voltage" : "", "net_name" : "CFG_FLASH_RST_F", "node_list" : [ "R34_XF.2", "R37_XF.2", "U1_CPLD.D3", "U2_XF.A4", "U3_XF.A4" ] }, "C0_DDR4_ADR<2>_XF" : { "node_list" : [ "J1_XF.216", "U1_XF.CB21" ], "voltage" : "", "net_name" : "C0_DDR4_ADR<2>_XF" }, "C0_DDR4_DQ<2>_XF" : { "node_list" : [ "J1_XF.12", "U1_XF.BY25" ], "voltage" : "", "net_name" : "C0_DDR4_DQ<2>_XF" }, "FSET_4650_TR_SP" : { "net_name" : "FSET_4650_TR_SP", "voltage" : "", "node_list" : [ "PM5_SP_XF.C6", "R9_SP_XF.2" ] }, "SI5334_TP_CLK_N<3>" : { "node_list" : [ "SI5334_TP_N.1", "U1.58" ], "diff_pair_mate" : "SI5334_TP_CLK_P<3>", "net_name" : "SI5334_TP_CLK_N<3>", "diff_pair_pol" : "NEG", "voltage" : "" }, "E1S3_PER_P<4>_XF" : { "node_list" : [ "J1_E3_XF.A31", "U1_XF.AM4" ], "diff_pair_pol" : "POS", "net_name" : "E1S3_PER_P<4>_XF", "diff_pair_mate" : "E1S3_PER_N<4>_XF", "voltage" : "" }, "UNNAMED_3_BYPASSCAPNPOL_I143_A_SP" : { "node_list" : [ "C25_SP_XF.1", "R46_SP_XF.1", "U1_SP_XF.47" ], "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I143_A_SP", "voltage" : "" }, "UNNAMED_3_LTM4675_I40_WP_ND" : { "net_name" : "UNNAMED_3_LTM4675_I40_WP_ND", "voltage" : "", "node_list" : [ "PM4_ND_XF.K4", "R26_ND_XF.2" ] }, "AC_E1S1_PET_P<5>_XF" : { "node_list" : [ "C112_XF.1", "U1_XF.T9" ], "voltage" : "", "diff_pair_pol" : "POS", "diff_pair_mate" : "AC_E1S1_PET_N<5>_XF", "net_name" : "AC_E1S1_PET_P<5>_XF" }, "AC_E1S0_PET_N<4>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_E1S0_PET_P<4>_XF", "net_name" : "AC_E1S0_PET_N<4>_XF", "node_list" : [ "C125_XF.1", "U1_XF.F8" ] }, "VFB_4650_SP" : { "node_list" : [ "C47_SP_XF.2", "C69_SP_XF.2", "PM3_SP_XF.D5", "PM3_SP_XF.D7", "PM4_SP_XF.D5", "PM4_SP_XF.D7", "PM5_SP_XF.D5", "PM5_SP_XF.D7", "PM7_SP_XF.D5", "PM7_SP_XF.D7", "R11_SP_XF.2", "R61_SP_XF.2" ], "voltage" : "", "net_name" : "VFB_4650_SP" }, "UNNAMED_3_LTM4675_I40_FSWPHCFG_SD" : { "voltage" : "", "net_name" : "UNNAMED_3_LTM4675_I40_FSWPHCFG_SD", "node_list" : [ "PM4_SD_XF.H2", "R9_SD_XF.2" ] }, "OCL2_PET_N<0>_XF" : { "diff_pair_pol" : "NEG", "net_name" : "OCL2_PET_N<0>_XF", "diff_pair_mate" : "OCL2_PET_P<0>_XF", "voltage" : "", "node_list" : [ "C277_XF.2", "J1_O2_XF.B4" ] }, "C2_DDR4_DQ<21>_XF" : { "node_list" : [ "J3_XF.170", "U1_XF.E60" ], "voltage" : "", "net_name" : "C2_DDR4_DQ<21>_XF" }, "C0_DDR4_DQ<15>_XF" : { "net_name" : "C0_DDR4_DQ<15>_XF", "voltage" : "", "node_list" : [ "J1_XF.166", "U1_XF.CC27" ] }, "CPLD_SELF_TDI_CPLD" : { "node_list" : [ "U1_CPLD.A15", "U3_CPLD.3" ], "voltage" : "", "net_name" : "CPLD_SELF_TDI_CPLD" }, "UNNAMED_4_LED_I22_A_MP" : { "node_list" : [ "D1_MP.2", "R8_MP.2" ], "net_name" : "UNNAMED_4_LED_I22_A_MP", "voltage" : "" }, "UNNAMED_3_BYPASSCAPNPOL_I33_A_FL" : { "voltage" : "", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I33_A_FL", "node_list" : [ "C18_FL_XF.1", "U3_FL_XF.3" ] }, "UNNAMED_10_RESISTOR_I134_B" : { "net_name" : "UNNAMED_10_RESISTOR_I134_B", "voltage" : "", "node_list" : [ "R10.2", "U1.19" ] }, "C2_DDR4_DQ<68>_XF" : { "node_list" : [ "J3_XF.47", "U1_XF.D59" ], "voltage" : "", "net_name" : "C2_DDR4_DQ<68>_XF" }, "C1_RDIMM_DQS_T<0>_XF" : { "voltage" : "", "net_name" : "C1_RDIMM_DQS_T<0>_XF", "diff_pair_mate" : "C1_RDIMM_DQS_C<0>_XF", "diff_pair_pol" : "POS", "node_list" : [ "J2_XF.153", "U1_XF.BM49" ] }, "UNNAMED_17_RESISTOR_I101_A_XF" : { "net_name" : "UNNAMED_17_RESISTOR_I101_A_XF", "voltage" : "", "node_list" : [ "R127_XF.2", "R133_XF.1", "R134_XF.1" ] }, "P5V" : { "node_list" : [ "C36.1", "J3.21", "J3.22", "J3.23", "J3.4", "J3.6", "P5V_TP.1" ], "voltage" : "5V", "net_name" : "P5V" }, "C2_RDIMM_DQS_T<17>_XF" : { "diff_pair_pol" : "POS", "net_name" : "C2_RDIMM_DQS_T<17>_XF", "diff_pair_mate" : "C2_RDIMM_DQS_C<17>_XF", "voltage" : "", "node_list" : [ "J3_XF.51", "U1_XF.F58" ] }, "UNNAMED_3_BYPASSCAPNPOL_I27_A_SP" : { "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I27_A_SP", "voltage" : "", "node_list" : [ "C65_SP_XF.1", "R45_SP_XF.1", "U1_SP_XF.48" ] }, "OCL1_PET_N<1>_XF" : { "diff_pair_pol" : "NEG", "diff_pair_mate" : "OCL1_PET_P<1>_XF", "net_name" : "OCL1_PET_N<1>_XF", "voltage" : "", "node_list" : [ "C272_XF.2", "J1_O1_XF.B7" ] }, "C2_DDR4_DQ<38>_XF" : { "net_name" : "C2_DDR4_DQ<38>_XF", "voltage" : "", "node_list" : [ "J3_XF.102", "U1_XF.B56" ] }, "C1_RDIMM_DQS_T<1>_XF" : { "diff_pair_pol" : "POS", "diff_pair_mate" : "C1_RDIMM_DQS_C<1>_XF", "net_name" : "C1_RDIMM_DQS_T<1>_XF", "voltage" : "", "node_list" : [ "J2_XF.164", "U1_XF.BT50" ] }, "AC_PCIE1_TXP<7>_XF" : { "node_list" : [ "C26_XF.1", "U1_XF.AT13" ], "diff_pair_mate" : "AC_PCIE1_TXN<7>_XF", "net_name" : "AC_PCIE1_TXP<7>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "UNNAMED_3_LT3071_I32_IMON_FL" : { "node_list" : [ "R7_FL_XF.1", "U3_FL_XF.21" ], "voltage" : "", "net_name" : "UNNAMED_3_LT3071_I32_IMON_FL" }, "C3_RDIMM_DQS_T<10>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "diff_pair_mate" : "C3_RDIMM_DQS_C<10>_XF", "net_name" : "C3_RDIMM_DQS_T<10>_XF", "node_list" : [ "J4_XF.18", "U1_XF.K28" ] }, "POK_OD_NDIMM_VPP_SW" : { "node_list" : [ "PM1_SP_XF.H8", "U1_CPLD.N8" ], "net_name" : "POK_OD_NDIMM_VPP_SW", "voltage" : "" }, "E1S3_PET_P<1>_XF" : { "diff_pair_pol" : "POS", "net_name" : "E1S3_PET_P<1>_XF", "diff_pair_mate" : "E1S3_PET_N<1>_XF", "voltage" : "", "node_list" : [ "C341_XF.2", "J1_E3_XF.B21" ] }, "UNNAMED_12_NMOSFETVMT3_I4_G" : { "voltage" : "", "net_name" : "UNNAMED_12_NMOSFETVMT3_I4_G", "node_list" : [ "Q10.1", "R8.2" ] }, "VS_DIMM_VTT_LIN_ND" : { "voltage" : "", "net_name" : "VS_DIMM_VTT_LIN_ND", "node_list" : [ "NS3_ND_XF.2", "R4_ND_XF.1", "U2_ND_XF.5" ] }, "UNNAMED_7_BYPASSCAPNPOL_I55_B_SP" : { "net_name" : "UNNAMED_7_BYPASSCAPNPOL_I55_B_SP", "voltage" : "", "node_list" : [ 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"voltage" : "", "node_list" : [ "J2_XF.253", "U1_XF.BK62" ] }, "SW1_4650_BR_SP" : { "voltage" : "12", "net_name" : "SW1_4650_BR_SP", "node_list" : [ "PM7_SP_XF.G2" ] }, "E1S2_PER_P<6>_XF" : { "net_name" : "E1S2_PER_P<6>_XF", "diff_pair_mate" : "E1S2_PER_N<6>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "J1_E2_XF.A37", "U1_XF.AC2" ] }, "E1S0_PET_N<3>_XF" : { "node_list" : [ "C126_XF.2", "J1_E0_XF.B26" ], "voltage" : "", "diff_pair_mate" : "E1S0_PET_P<3>_XF", "net_name" : "E1S0_PET_N<3>_XF", "diff_pair_pol" : "NEG" }, "C2_DDR4_DQ<67>_XF" : { "voltage" : "", "net_name" : "C2_DDR4_DQ<67>_XF", "node_list" : [ "J3_XF.201", "U1_XF.C57" ] }, "VREF_P1R25V_XF" : { "node_list" : [ "C142_XF.1", "R84_XF.1", "U1_XF.AN25", "U9_XF.3", "U9_XF.4" ], "voltage" : "1.25", "net_name" : "VREF_P1R25V_XF" }, "UNNAMED_4_BYPASSCAPNPOL_I51_B" : { "voltage" : "", "net_name" : "UNNAMED_4_BYPASSCAPNPOL_I51_B", "node_list" : [ "C42.2", "R52.2", "R75.2", "U11.11" ] }, "AC_PCIE0_TXP<1>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "diff_pair_mate" : "AC_PCIE0_TXN<1>_XF", "net_name" : "AC_PCIE0_TXP<1>_XF", "node_list" : [ "C40_XF.1", "U1_XF.AV9" ] }, "VDDO4" : { "node_list" : [ "C7.1", "R12.2", "U1.36" ], "net_name" : "VDDO4", "voltage" : "1.8" }, "C2_DDR4_DQ<37>_XF" : { "voltage" : "", "net_name" : "C2_DDR4_DQ<37>_XF", "node_list" : [ "J3_XF.240", "U1_XF.C56" ] }, "C2_RDIMM_DQS_T<13>_XF" : { "voltage" : "", "diff_pair_mate" : "C2_RDIMM_DQS_C<13>_XF", "net_name" : "C2_RDIMM_DQS_T<13>_XF", "diff_pair_pol" : "POS", "node_list" : [ "J3_XF.99", "U1_XF.E55" ] }, "E1S2_PER_P<3>_XF" : { "voltage" : "", "diff_pair_mate" : "E1S2_PER_N<3>_XF", "net_name" : "E1S2_PER_P<3>_XF", "diff_pair_pol" : "POS", "node_list" : [ "J1_E2_XF.A27", "U1_XF.W2" ] }, "E1S0_PET_N<6>_XF" : { "node_list" : [ "C119_XF.2", "J1_E0_XF.B36" ], "net_name" : "E1S0_PET_N<6>_XF", "diff_pair_mate" : "E1S0_PET_P<6>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "AC_PCIE1_REFP_XF" : { "diff_pair_pol" : "POS", "net_name" : "AC_PCIE1_REFP_XF", "diff_pair_mate" : "AC_PCIE1_REFN_XF", "voltage" : "", "node_list" : [ "C230_XF.2", "U1_XF.AU15" ] }, "UNNAMED_8_LT3071_I30_IMON_FL" : { "node_list" : [ "R26_FL_XF.2", "R82_FL_XF.1", "U5_FL_XF.21" ], "voltage" : "", "net_name" : "UNNAMED_8_LT3071_I30_IMON_FL" }, "C2_DDR4_DQ<49>_XF" : { "node_list" : [ "J3_XF.264", "U1_XF.G50" ], "net_name" : "C2_DDR4_DQ<49>_XF", "voltage" : "" }, "E1S3_PET_P<7>_XF" : { "node_list" : [ "C235_XF.2", "J1_E3_XF.B40" ], "voltage" : "", "diff_pair_pol" : "POS", "diff_pair_mate" : "E1S3_PET_N<7>_XF", "net_name" : "E1S3_PET_P<7>_XF" }, "C1_DDR4_BG<1>_XF" : { "node_list" : [ "J2_XF.207", "U1_XF.CC52" ], "net_name" : "C1_DDR4_BG<1>_XF", "voltage" : "" }, "E1S0_3R3V_PWRDIS_XF" : { "node_list" : [ "J1_E0_XF.B12", "U1_XF.AA18" ], "voltage" : "3.3V", "net_name" : "E1S0_3R3V_PWRDIS_XF" }, "CPLD_PWR_ALERT_OD_F" : { "node_list" : [ "J5.1", "U1_CPLD.N6" ], "net_name" : "CPLD_PWR_ALERT_OD_F", "voltage" : "" }, "PWR_SPARE_SW_XF" : { "net_name" : "PWR_SPARE_SW_XF", "voltage" : "Unknown", "node_list" : [ "C111_SP_XF.1", "C115_SP_XF.1", "C119_SP_XF.1", "PM1_SP_XF.N11", "PM1_SP_XF.R1", "PM1_SP_XF.R2", "PM1_SP_XF.T1", "PM1_SP_XF.T2", "PM1_SP_XF.T3", "PM1_SP_XF.U1", "PM1_SP_XF.U2", "PM1_SP_XF.U3", "PM1_SP_XF.V1", "PM1_SP_XF.V2", "PM1_SP_XF.V3", "PM1_SP_XF.W1", "PM1_SP_XF.W2", "PM1_SP_XF.W3", "PWR_SPARE_SW_XF.1", "R122_SP_XF.1" ] }, "DDR4_SYS_CLK_P<3>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "DDR4_SYS_CLK_P<3>_XF", "diff_pair_mate" : "DDR4_SYS_CLK_N<3>_XF", "node_list" : [ "C366_XF.1", "U6_XF.10" ] }, "C0_RDIMM_DQS_C<12>_XF" : { "node_list" : [ "J1_XF.41", "U1_XF.BU23" ], "diff_pair_pol" : "NEG", "diff_pair_mate" : "C0_RDIMM_DQS_T<12>_XF", "net_name" : "C0_RDIMM_DQS_C<12>_XF", "voltage" : "" }, "AC_PCIE0_TXP<0>_XF" : { "node_list" : [ "C41_XF.1", "U1_XF.AU11" ], "net_name" : "AC_PCIE0_TXP<0>_XF", "diff_pair_mate" : "AC_PCIE0_TXN<0>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "C0_DDR4_PARITY_XF" : { "node_list" : [ "J1_XF.222", "U1_XF.CB20" ], "voltage" : "", "net_name" : "C0_DDR4_PARITY_XF" }, "UNNAMED_4_BYPASSCAPNPOL_I13_B_SD" : { "voltage" : "", "net_name" : "UNNAMED_4_BYPASSCAPNPOL_I13_B_SD", "node_list" : [ "C32_SD_XF.2", "U2_SD_XF.6" ] }, "JT_CPLD_INST_F" : { "voltage" : "", "net_name" : "JT_CPLD_INST_F", "node_list" : [ "J5.18", "R88.2", "U2_CPLD.6", "U3_CPLD.6", "U4_CPLD.6" ] }, "UNNAMED_7_RESISTOR_I53_A_SP" : { "node_list" : [ "R59_SP_XF.2", "R71_SP_XF.1" ], "net_name" : "UNNAMED_7_RESISTOR_I53_A_SP", "voltage" : "" }, "C3_RDIMM_DQS_C<2>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "C3_RDIMM_DQS_C<2>_XF", "diff_pair_mate" : "C3_RDIMM_DQS_T<2>_XF", "node_list" : [ "J4_XF.174", "U1_XF.G28" ] }, "C0_DDR4_DQ<55>_XF" : { "node_list" : [ "J1_XF.269", "U1_XF.BK24" ], "voltage" : "", "net_name" : "C0_DDR4_DQ<55>_XF" }, "C2_DDR4_DQ<9>_XF" : { "net_name" : "C2_DDR4_DQ<9>_XF", "voltage" : "", "node_list" : [ "J3_XF.161", "U1_XF.R49" ] }, "E1S2_3R3V_CKEN_F<0>_XF" : { "net_name" : "E1S2_3R3V_CKEN_F<0>_XF", "voltage" : "", "node_list" : [ "U1_E2_XF.12", "U1_XF.M18" ] }, "UNNAMED_12_LT3071_I30_V00_FL" : { "net_name" : "UNNAMED_12_LT3071_I30_V00_FL", "voltage" : "", "node_list" : [ "R100_FL_XF.2", "R95_FL_XF.1", "U10_FL_XF.23" ] }, "OCL3_PER_P<2>_XF" : { "net_name" : "OCL3_PER_P<2>_XF", "diff_pair_mate" : "OCL3_PER_N<2>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "J1_O3_XF.A15", "U1_XF.BH4" ] }, "UNNAMED_4_BYPASSCAPNPOL_I12_A_MP" : { "node_list" : [ "C11_MP.1", "U2_MP.13" ], "net_name" : "UNNAMED_4_BYPASSCAPNPOL_I12_A_MP", "voltage" : "" }, "AC_E1S0_PET_P<3>_XF" : { "node_list" : [ "C106_XF.1", "U1_XF.A7" ], "net_name" : "AC_E1S0_PET_P<3>_XF", "diff_pair_mate" : "AC_E1S0_PET_N<3>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "UNNAMED_6_LTM4671_I456_FB3_SP" : { "node_list" : [ "C131_SP_XF.2", "C134_SP_XF.2", "PM2_SP_XF.G9", "PM2_SP_XF.N10", "R109_SP_XF.2", "R8_SP_XF.2" ], "net_name" : "UNNAMED_6_LTM4671_I456_FB3_SP", "voltage" : "" }, "C0_DDR4_ADR<4>_XF" : { "node_list" : [ "J1_XF.214", "U1_XF.CA20" ], "net_name" : "C0_DDR4_ADR<4>_XF", "voltage" : "" }, "E1S1_PER_N<2>_XF" : { "net_name" : "E1S1_PER_N<2>_XF", "diff_pair_mate" : "E1S1_PER_P<2>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "J1_E1_XF.A23", "U1_XF.N1" ] }, "PCIE0_TXN<0>_XF" : { "diff_pair_pol" : "NEG", "net_name" : "PCIE0_TXN<0>_XF", "diff_pair_mate" : "PCIE0_TXP<0>_XF", "voltage" : "", "node_list" : [ "C86_XF.2", "J1_P0_XF.B4" ] }, "C0_SYS_CLK_P_XF" : { "voltage" : "", "diff_pair_mate" : "C0_SYS_CLK_N_XF", "net_name" : "C0_SYS_CLK_P_XF", "diff_pair_pol" : "POS", "node_list" : [ "C360_XF.2", "R236_XF.1", "R238_XF.1", "R33_XF.2", "U1_XF.BY20" ] }, "AC_OCL2_PET_P<3>_XF" : { "node_list" : [ "C233_XF.1", "U1_XF.BK9" ], "voltage" : "", "diff_pair_pol" : "POS", "diff_pair_mate" : "AC_OCL2_PET_N<3>_XF", "net_name" : "AC_OCL2_PET_P<3>_XF" }, "UNNAMED_4_BYPASSCAPNPOL_I12_B_MP" : { "node_list" : [ "C11_MP.2", "L2_MP.1", "U2_MP.10", "U2_MP.11", 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"net_name" : "AC_FPGA_CLK_REF_P<1>_3", "diff_pair_pol" : "POS", "voltage" : "" }, "C3_DDR4_RESET_N_XF" : { "voltage" : "", "net_name" : "C3_DDR4_RESET_N_XF", "node_list" : [ "J4_XF.58", "U1_XF.T22" ] }, "UNNAMED_7_BYPASSCAPNPOL_I31_A_FL" : { "node_list" : [ "C39_FL_XF.1", "U4_FL_XF.3" ], "net_name" : "UNNAMED_7_BYPASSCAPNPOL_I31_A_FL", "voltage" : "" }, "PCIE0_RXN<4>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "PCIE0_RXP<4>_XF", "net_name" : "PCIE0_RXN<4>_XF", "node_list" : [ "J2_P0_XF.A4", "U1_XF.BA1" ] }, "UNNAMED_18_RESISTOR_I23_A_XF" : { "voltage" : "", "net_name" : "UNNAMED_18_RESISTOR_I23_A_XF", "node_list" : [ "R40_XF.1", "U1_XF.AM18" ] }, "FPGA_CPLD_DQ<0>_1" : { "voltage" : "", "net_name" : "FPGA_CPLD_DQ<0>_1", "node_list" : [ "U1_CPLD.F10", "U1_XF.BU33" ] }, "CONN_CLK_REFN<1>_E0" : { "node_list" : [ "C24_E0_XF.2", "J1_E0_XF.A14" ], "diff_pair_pol" : "NEG", "net_name" : "CONN_CLK_REFN<1>_E0", "diff_pair_mate" : "CONN_CLK_REFP<1>_E0", "voltage" : "" }, "AC_OCL1_FPGA_REFCLK_P_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "diff_pair_mate" : "AC_OCL1_FPGA_REFCLK_N_XF", "net_name" : "AC_OCL1_FPGA_REFCLK_P_XF", "node_list" : [ "C353_XF.1", "U7_XF.27" ] }, "C0_RDIMM_DQS_T<4>_XF" : { "node_list" : [ "J1_XF.245", "U1_XF.BL21" ], "diff_pair_pol" : "POS", "net_name" : "C0_RDIMM_DQS_T<4>_XF", "diff_pair_mate" : "C0_RDIMM_DQS_C<4>_XF", "voltage" : "" }, "AC_FPGA_CLK_REF_N<0>_2" : { "voltage" : "", "diff_pair_mate" : "AC_FPGA_CLK_REF_P<0>_2", "net_name" : "AC_FPGA_CLK_REF_N<0>_2", "diff_pair_pol" : "NEG", "node_list" : [ "C23_E3_XF.1", "U1_E3_XF.23" ] }, "CONN_CLK_REFN<0>_E1" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "CONN_CLK_REFP<0>_E1", "net_name" : "CONN_CLK_REFN<0>_E1", "node_list" : [ "C25_E1_XF.2", "J1_E1_XF.B14" ] }, "UNNAMED_11_RESISTOR_I769_B_XF" : { "node_list" : [ "R154_XF.2", "R155_XF.2", "U1_XF.BK34" ], "voltage" : "", "net_name" : "UNNAMED_11_RESISTOR_I769_B_XF" }, "AC_OCL0_CONN_REFCLK_N_XF" : { "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_OCL0_CONN_REFCLK_P_XF", "net_name" : "AC_OCL0_CONN_REFCLK_N_XF", "voltage" : "", "node_list" : [ "C384_XF.1", "U7_XF.14" ] }, "C3_RDIMM_DQS_C<14>_XF" : { "node_list" : [ "J4_XF.111", "U1_XF.A22" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "C3_RDIMM_DQS_C<14>_XF", "diff_pair_mate" : "C3_RDIMM_DQS_T<14>_XF" }, "C2_DDR4_DQ<10>_XF" : { "node_list" : [ "J3_XF.23", "U1_XF.R48" ], "net_name" : "C2_DDR4_DQ<10>_XF", "voltage" : "" }, "OCL3_CONN_REFCLK_N_XF" : { "node_list" : [ "C387_XF.2", "J1_O3_XF.B13" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "OCL3_CONN_REFCLK_N_XF", "diff_pair_mate" : "OCL3_CONN_REFCLK_P_XF" }, "OCL3_PET_N<3>_XF" : { "node_list" : [ "C278_XF.2", "J1_O3_XF.B19" ], "voltage" : "", "diff_pair_mate" : "OCL3_PET_P<3>_XF", "net_name" : "OCL3_PET_N<3>_XF", "diff_pair_pol" : "NEG" }, "UNNAMED_17_RESISTOR_I55_A_XF" : { "node_list" : [ "R102_XF.2", "R103_XF.2", "R78_XF.1" ], "voltage" : "", "net_name" : "UNNAMED_17_RESISTOR_I55_A_XF" }, "AC_E1S3_PET_P<6>_XF" : { "node_list" : [ "C234_XF.1", "U1_XF.AK9" ], "diff_pair_mate" : "AC_E1S3_PET_N<6>_XF", "net_name" : "AC_E1S3_PET_P<6>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "PCIE0_REFN_XF" : { "node_list" : [ "C288_XF.1", "R2_P0_XF.2" ], "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "PCIE0_REFP_XF", "net_name" : "PCIE0_REFN_XF" }, "UNNAMED_17_RESISTOR_I124_A_XF" : { "node_list" : [ "C269_XF.2", "R132_XF.1", "U1_XF.BY30" ], "net_name" : "UNNAMED_17_RESISTOR_I124_A_XF", "voltage" : "" }, "C1_DDR4_ADR<0>_XF" : { "node_list" : [ "J2_XF.79", "U1_XF.CA52" ], "voltage" : "", "net_name" : "C1_DDR4_ADR<0>_XF" }, "AC_E1S3_PET_N<7>_XF" : { "node_list" : [ "C174_XF.1", "U1_XF.AJ10" ], "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_E1S3_PET_P<7>_XF", "net_name" : "AC_E1S3_PET_N<7>_XF" }, "VMON_VCCAUX_SW" : { "voltage" : "", "net_name" : "VMON_VCCAUX_SW", "node_list" : [ "R121_SP_XF.2", "R48.2" ] }, "C3_DDR4_DQ<33>_XF" : { "net_name" : "C3_DDR4_DQ<33>_XF", "voltage" : "", "node_list" : [ "J4_XF.242", "U1_XF.A25" ] }, "E1S1_PET_P<3>_XF" : { "node_list" : [ "C114_XF.2", "J1_E1_XF.B27" ], "diff_pair_pol" : "POS", "diff_pair_mate" : "E1S1_PET_N<3>_XF", "net_name" : "E1S1_PET_P<3>_XF", "voltage" : "" }, "C0_DDR4_ADR<8>_XF" : { "node_list" : [ "J1_XF.68", "U1_XF.BW20" ], "net_name" : "C0_DDR4_ADR<8>_XF", "voltage" : "" }, "C1_DDR4_DQ<65>_XF" : { "node_list" : [ "J2_XF.194", "U1_XF.BU60" ], "voltage" : "", "net_name" : "C1_DDR4_DQ<65>_XF" }, "UNNAMED_3_LTM4675_I40_COMP1A_ND" : { "node_list" : [ "PM4_ND_XF.H6", "R109_ND_XF.2" ], "voltage" : "0V", "net_name" : "UNNAMED_3_LTM4675_I40_COMP1A_ND" }, "CONN_CLK_REFN<1>_E2" : { "node_list" : [ "C24_E2_XF.2", "J1_E2_XF.A14" ], "voltage" : "", "diff_pair_mate" : "CONN_CLK_REFP<1>_E2", "net_name" : "CONN_CLK_REFN<1>_E2", "diff_pair_pol" : "NEG" }, "E1S1_PET_P<6>_XF" : { "diff_pair_pol" : "POS", "diff_pair_mate" : "E1S1_PET_N<6>_XF", "net_name" : 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"E1S3_3R3V_SCL_XF" : { "node_list" : [ "J1_E3_XF.A7", "R208_XF.2", "R3_E3_XF.2", "U1_XF.U21" ], "voltage" : "3.3V", "net_name" : "E1S3_3R3V_SCL_XF" }, "AC_OCL3_CONN_REFCLK_P_XF" : { "voltage" : "", "net_name" : "AC_OCL3_CONN_REFCLK_P_XF", "diff_pair_mate" : "AC_OCL3_CONN_REFCLK_N_XF", "diff_pair_pol" : "POS", "node_list" : [ "C359_XF.1", "U5_XF.17" ] }, "OCL2_PET_N<3>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "OCL2_PET_P<3>_XF", "net_name" : "OCL2_PET_N<3>_XF", "node_list" : [ "C274_XF.2", "J1_O2_XF.B19" ] }, "C2_DDR4_ADR<15>_XF" : { "net_name" : "C2_DDR4_ADR<15>_XF", "voltage" : "", "node_list" : [ "J3_XF.86", "U1_XF.G59" ] }, "PHASMD_4650_TR_SP" : { "node_list" : [ "PM5_SP_XF.G4", "R5_SP_XF.2", "R6_SP_XF.2" ], "net_name" : "PHASMD_4650_TR_SP", "voltage" : "" }, "OCL2_CONN_REFCLK_N_XF" : { "node_list" : [ "C388_XF.2", "J1_O2_XF.B13" ], "net_name" : "OCL2_CONN_REFCLK_N_XF", "diff_pair_mate" : "OCL2_CONN_REFCLK_P_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "C3_DDR4_ADR<7>_XF" : { "voltage" : "", "net_name" : "C3_DDR4_ADR<7>_XF", "node_list" : [ "J4_XF.211", "U1_XF.T28" ] }, "NC_BL_2_SP" : { "voltage" : "", "net_name" : "NC_BL_2_SP", "node_list" : [ "C21_SP_XF.2" ] }, "C2_RDIMM_DQS_C<17>_XF" : { "node_list" : [ "J3_XF.52", "U1_XF.E58" ], "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "C2_RDIMM_DQS_T<17>_XF", "net_name" : "C2_RDIMM_DQS_C<17>_XF" }, "GND" : { "node_list" : [ "C1.2", "C10.2", "C100_FL_XF.2", "C100_SP_XF.2", "C101_FL_XF.2", "C101_SP_XF.2", "C102_FL_XF.2", "C102_SP_XF.2", "C103_FL_XF.2", "C104_FL_XF.1", "C105_FL_XF.2", "C106_FL_XF.2", "C107_FL_XF.2", "C108_FL_XF.2", "C10_CPLD.1", "C10_E0_XF.1", "C10_E1_XF.1", "C10_E2_XF.1", "C10_E3_XF.1", "C10_FL_XF.2", "C10_MP.2", "C10_ND_XF.2", "C10_SD_XF.2", "C10_SP_XF.2", "C10_XF.2", "C11.2", "C110_SP_XF.2", "C111_SP_XF.2", "C112_SP_XF.2", "C113_SP_XF.2", "C114_SP_XF.2", "C115_SP_XF.2", "C116_SP_XF.2", "C117_SP_XF.2", "C118_SP_XF.1", "C119_SP_XF.2", "C11_CPLD.1", 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"C337_XF.2", "C338_XF.2", "C33_FL_XF.2", "C33_SP_XF.2", "C34.2", "C342_XF.2", "C344_XF.2", "C345_XF.1", "C346_XF.1", "C347_XF.2", "C348_XF.2", "C349_XF.2", "C34_FL_XF.2", "C34_SP_XF.2", "C35.2", "C350_XF.1", "C351_XF.1", "C352_XF.1", "C35_FL_XF.2", "C35_SP_XF.3", "C36.2", "C36_FL_XF.2", "C36_ND_XF.2", "C36_SD_XF.2", "C36_SP_XF.2", "C37.1", "C371_XF.1", "C372_XF.1", "C373_XF.1", "C374_XF.1", "C375_XF.1", "C376_XF.1", "C377_XF.2", "C378_XF.2", "C379_XF.2", "C37_FL_XF.2", "C37_ND_XF.2", "C37_SD_XF.2", "C37_SP_XF.2", "C38.1", "C380_XF.2", "C381_XF.2", "C382_XF.2", "C389_XF.2", "C38_FL_XF.2", "C38_ND_XF.2", "C38_SD_XF.2", "C38_SP_XF.2", "C39.2", "C395_XF.1", "C396_XF.1", "C397_XF.1", "C398_XF.1", "C399_XF.1", "C39_FL_XF.2", "C39_SP_XF.2", "C3_CPLD.1", "C3_E0_XF.1", "C3_E1_XF.1", "C3_E2_XF.1", "C3_E3_XF.1", "C3_FL_XF.2", "C3_SP_XF.2", "C3_XF.1", "C4.1", "C40.2", "C400_XF.1", "C401_XF.1", "C402_XF.1", "C403_XF.1", "C404_XF.1", "C405_XF.1", "C406_XF.1", "C407_XF.1", "C408_XF.1", "C409_XF.1", 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"PM4_SD_XF.F1", "PM4_SD_XF.F8", "PM4_SD_XF.G1", "PM4_SD_XF.G8", "PM4_SD_XF.G9", "PM4_SD_XF.H1", "PM4_SD_XF.H8", "PM4_SD_XF.H9", "PM4_SD_XF.J2", "PM4_SD_XF.J8", "PM4_SD_XF.K2", "PM4_SD_XF.K5", "PM4_SD_XF.K6", "PM4_SD_XF.K7", "PM4_SD_XF.K8", "PM4_SD_XF.L2", "PM4_SD_XF.L3", "PM4_SD_XF.L4", "PM4_SD_XF.L5", "PM4_SD_XF.L6", "PM4_SD_XF.L7", "PM4_SD_XF.M2", "PM4_SD_XF.M3", "PM4_SD_XF.M4", "PM4_SD_XF.M5", "PM4_SD_XF.M6", "PM4_SD_XF.M7", "PM4_SD_XF.M8", "PM4_SP_XF.A6", "PM4_SP_XF.A7", "PM4_SP_XF.B6", "PM4_SP_XF.B7", "PM4_SP_XF.D1", "PM4_SP_XF.D10", "PM4_SP_XF.D11", "PM4_SP_XF.D12", "PM4_SP_XF.D2", "PM4_SP_XF.D3", "PM4_SP_XF.D4", "PM4_SP_XF.D9", "PM4_SP_XF.E1", "PM4_SP_XF.E10", "PM4_SP_XF.E11", "PM4_SP_XF.E12", "PM4_SP_XF.E2", "PM4_SP_XF.E3", "PM4_SP_XF.E4", "PM4_SP_XF.F1", "PM4_SP_XF.F10", "PM4_SP_XF.F11", "PM4_SP_XF.F12", "PM4_SP_XF.F2", "PM4_SP_XF.F3", "PM4_SP_XF.G1", "PM4_SP_XF.G10", "PM4_SP_XF.G12", "PM4_SP_XF.G3", "PM4_SP_XF.H1", "PM4_SP_XF.H10", "PM4_SP_XF.H11", "PM4_SP_XF.H12", "PM4_SP_XF.H2", "PM4_SP_XF.H3", "PM4_SP_XF.H4", "PM4_SP_XF.H5", "PM4_SP_XF.H6", "PM4_SP_XF.H7", "PM4_SP_XF.H9", "PM4_SP_XF.J1", "PM4_SP_XF.J12", "PM4_SP_XF.J5", "PM4_SP_XF.J8", "PM4_SP_XF.K1", "PM4_SP_XF.K12", "PM4_SP_XF.K5", "PM4_SP_XF.K6", "PM4_SP_XF.K7", "PM4_SP_XF.K8", "PM4_SP_XF.L1", "PM4_SP_XF.L12", "PM4_SP_XF.M1", "PM4_SP_XF.M12", "PM5_SP_XF.A6", "PM5_SP_XF.A7", "PM5_SP_XF.B6", "PM5_SP_XF.B7", "PM5_SP_XF.D1", "PM5_SP_XF.D10", "PM5_SP_XF.D11", "PM5_SP_XF.D12", "PM5_SP_XF.D2", "PM5_SP_XF.D3", "PM5_SP_XF.D4", "PM5_SP_XF.D9", "PM5_SP_XF.E1", "PM5_SP_XF.E10", "PM5_SP_XF.E11", "PM5_SP_XF.E12", "PM5_SP_XF.E2", "PM5_SP_XF.E3", "PM5_SP_XF.E4", "PM5_SP_XF.F1", "PM5_SP_XF.F10", "PM5_SP_XF.F11", "PM5_SP_XF.F12", "PM5_SP_XF.F2", "PM5_SP_XF.F3", "PM5_SP_XF.G1", "PM5_SP_XF.G10", "PM5_SP_XF.G12", "PM5_SP_XF.G3", "PM5_SP_XF.H1", "PM5_SP_XF.H10", "PM5_SP_XF.H11", "PM5_SP_XF.H12", "PM5_SP_XF.H2", "PM5_SP_XF.H3", "PM5_SP_XF.H4", "PM5_SP_XF.H5", "PM5_SP_XF.H6", "PM5_SP_XF.H7", "PM5_SP_XF.H9", "PM5_SP_XF.J1", "PM5_SP_XF.J12", "PM5_SP_XF.J5", "PM5_SP_XF.J8", "PM5_SP_XF.K1", "PM5_SP_XF.K12", "PM5_SP_XF.K5", "PM5_SP_XF.K6", "PM5_SP_XF.K7", "PM5_SP_XF.K8", "PM5_SP_XF.L1", "PM5_SP_XF.L12", "PM5_SP_XF.M1", "PM5_SP_XF.M12", "PM7_SP_XF.A6", "PM7_SP_XF.A7", "PM7_SP_XF.B6", "PM7_SP_XF.B7", "PM7_SP_XF.D1", "PM7_SP_XF.D10", "PM7_SP_XF.D11", "PM7_SP_XF.D12", "PM7_SP_XF.D2", "PM7_SP_XF.D3", "PM7_SP_XF.D4", "PM7_SP_XF.D9", "PM7_SP_XF.E1", "PM7_SP_XF.E10", "PM7_SP_XF.E11", "PM7_SP_XF.E12", "PM7_SP_XF.E2", "PM7_SP_XF.E3", "PM7_SP_XF.E4", "PM7_SP_XF.F1", "PM7_SP_XF.F10", "PM7_SP_XF.F11", "PM7_SP_XF.F12", "PM7_SP_XF.F2", "PM7_SP_XF.F3", "PM7_SP_XF.G1", "PM7_SP_XF.G10", "PM7_SP_XF.G12", "PM7_SP_XF.G3", "PM7_SP_XF.H1", "PM7_SP_XF.H10", "PM7_SP_XF.H11", "PM7_SP_XF.H12", "PM7_SP_XF.H2", "PM7_SP_XF.H3", "PM7_SP_XF.H4", "PM7_SP_XF.H5", "PM7_SP_XF.H6", "PM7_SP_XF.H7", "PM7_SP_XF.H9", "PM7_SP_XF.J1", "PM7_SP_XF.J12", "PM7_SP_XF.J5", "PM7_SP_XF.J8", "PM7_SP_XF.K1", "PM7_SP_XF.K12", "PM7_SP_XF.K5", "PM7_SP_XF.K6", "PM7_SP_XF.K7", "PM7_SP_XF.K8", "PM7_SP_XF.L1", "PM7_SP_XF.L12", "PM7_SP_XF.M1", "PM7_SP_XF.M12", "Q12.2", "Q1_XF.2", "Q5.2", "Q6.2", "Q7.2", "Q8.2", "Q9.2", "R10.1", "R100_FL_XF.1", "R101_FL_XF.1", "R103_XF.1", "R104_XF.1", "R107_XF.1", "R108_XF.1", "R109_FL_XF.1", "R109_XF.1", "R10_CPLD.2", "R10_E0_XF.1", "R10_E1_XF.1", "R10_E2_XF.1", "R10_E3_XF.1", "R10_XF.1", "R11.1", "R110_FL_XF.1", "R111_FL_XF.1", "R111_XF.1", "R112_XF.1", "R113_XF.1", "R115_XF.1", "R118_XF.1", "R119_XF.1", "R11_CPLD.2", "R120_XF.2", "R121_XF.2", "R124_XF.1", "R125_SP_XF.1", "R128_SP_XF.1", "R12_CPLD.2", "R12_E0_XF.1", "R12_E1_XF.1", "R12_E2_XF.1", "R12_E3_XF.1", "R12_MP.1", "R12_XF.1", "R130_SP_XF.1", "R132_SP_XF.1", "R134_SP_XF.1", "R135_XF.2", "R136.1", "R137.1", "R138_XF.2", "R139_XF.2", "R13_CPLD.2", "R13_E0_XF.1", "R13_E1_XF.1", "R13_E2_XF.1", "R13_E3_XF.1", "R13_XF.1", "R140_XF.2", "R141_XF.2", "R143_XF.2", "R144_XF.2", "R145_XF.2", "R148_XF.1", "R149_XF.1", "R14_CPLD.2", "R14_FL_XF.1", "R152_XF.1", "R153_XF.1", "R155_XF.1", "R157_XF.2", "R158_XF.1", "R159_XF.1", "R15_CPLD.2", "R15_XF.1", "R160_XF.1", "R165_XF.2", "R16_CPLD.2", "R16_E0_XF.2", "R16_E1_XF.2", "R16_E2_XF.2", "R16_E3_XF.2", "R16_FL_XF.1", "R16_MP.1", "R170_XF.2", "R172_XF.2", "R173_XF.2", "R175_XF.2", "R176_XF.2", "R178_XF.2", "R179_XF.2", "R17_FL_XF.1", "R181_XF.2", "R18_E0_XF.2", "R18_E1_XF.2", "R18_E2_XF.2", "R18_E3_XF.2", "R18_MP.1", "R18_SP_XF.1", "R18_XF.1", "R190_SP_XF.1", "R192_SP_XF.1", "R194_SP_XF.1", "R194_XF.2", "R196_SP_XF.1", "R196_XF.2", "R197_XF.2", "R199_XF.2", "R1_CPLD.2", "R1_E0_XF.1", "R1_E1_XF.1", "R1_E2_XF.1", "R1_E3_XF.1", "R1_FL_XF.1", "R1_MP.1", "R200_XF.2", "R202_XF.2", "R203_XF.2", "R205_XF.2", "R20_XF.1", "R21.1", "R218_XF.2", "R21_SP_XF.1", "R21_XF.1", "R220_XF.2", "R221_XF.2", "R223_XF.2", "R224_XF.2", "R226_XF.2", "R227_XF.2", "R229_XF.2", "R22_XF.1", "R23.2", "R236_XF.2", "R237_XF.2", "R240_XF.2", "R242_XF.2", "R244_XF.2", "R246_XF.2", "R24_XF.1", "R250_XF.2", "R252_XF.2", "R254_XF.2", "R258_XF.2", "R26.1", "R261_XF.2", "R262_XF.1", "R264_XF.1", "R26_FL_XF.1", "R279_XF.2", "R27_XF.1", "R28.2", "R281_XF.2", "R282_XF.2", "R284_XF.2", "R29_XF.1", "R2_CPLD.2", "R2_E0_XF.1", "R2_E1_XF.1", "R2_E2_XF.1", "R2_E3_XF.1", "R2_XF.1", "R30.2", "R30_XF.1", "R31_XF.1", "R32_XF.1", "R33_FL_XF.1", "R36.2", "R36_XF.1", "R38_SP_XF.1", "R3_CPLD.2", "R3_XF.1", "R43_XF.1", "R44_XF.1", "R45_XF.1", "R46_XF.1", "R47_FL_XF.1", "R47_XF.1", "R48_FL_XF.1", "R48_XF.1", "R49_FL_XF.1", "R49_XF.1", "R4_MP.1", "R4_XF.1", "R50_FL_XF.1", "R50_XF.1", "R51_FL_XF.1", "R51_XF.1", "R52_XF.1", "R53_XF.1", "R54_XF.1", "R55_XF.1", "R56_XF.1", "R57_XF.1", "R58_XF.1", "R59_XF.1", "R5_FL_XF.1", "R60.1", "R60_FL_XF.1", "R60_XF.1", "R61.2", "R61_FL_XF.1", "R61_XF.1", "R62_FL_XF.1", "R62_ND_XF.1", "R62_SD_XF.1", "R62_XF.2", "R63_FL_XF.1", "R63_XF.2", "R64.1", "R65.1", "R67.1", "R67_XF.1", "R6_CPLD.2", "R6_FL_XF.1", "R6_MP.1", "R70_XF.2", "R71.1", "R71_FL_XF.1", "R72_FL_XF.1", "R73.1", "R74.1", "R74_XF.1", "R75.1", "R76.2", "R78_FL_XF.1", "R79_FL_XF.1", "R7_CPLD.2", "R7_XF.1", "R80.1", "R80_FL_XF.1", "R81.1", "R87_FL_XF.2", "R89_FL_XF.2", "R89_XF.1", "R8_CPLD.2", "R90_XF.1", "R94_XF.2", "R95_XF.2", "R96_XF.2", "R97_FL_XF.1", "R9_CPLD.2", "R9_XF.1", "S1.2", "S1.5", "S2.1", "S2.4", "TP1.1", "TP10.1", "TP11.1", "TP12.1", "TP13.1", "TP14.1", "TP15.1", "TP16.1", "TP17.1", "TP18.1", "TP2.1", "TP3.1", "TP4.1", "TP5.1", "TP6.1", "TP7.1", "TP8.1", "TP9.1", "U1.65", "U10_FL_XF.10", "U10_FL_XF.11", "U10_FL_XF.12", "U10_FL_XF.13", "U10_FL_XF.14", "U10_FL_XF.20", "U10_FL_XF.26", "U10_FL_XF.29", "U10_FL_XF.4", "U10_FL_XF.9", "U11.15", "U11_FL_XF.10", "U11_FL_XF.11", "U11_FL_XF.12", "U11_FL_XF.13", "U11_FL_XF.14", "U11_FL_XF.20", "U11_FL_XF.26", "U11_FL_XF.29", "U11_FL_XF.4", "U11_FL_XF.9", "U12.4", "U1_CPLD.B15", "U1_CPLD.B2", "U1_CPLD.C14", "U1_CPLD.C3", "U1_CPLD.D13", "U1_CPLD.D4", "U1_CPLD.E12", "U1_CPLD.E5", "U1_CPLD.F11", "U1_CPLD.F6", "U1_CPLD.H8", "U1_CPLD.H9", "U1_CPLD.J8", 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"node_list" : [ "C281_XF.2", "J1_O3_XF.B4" ] }, "C2_DDR4_DQ<39>_XF" : { "node_list" : [ "J3_XF.247", "U1_XF.B55" ], "net_name" : "C2_DDR4_DQ<39>_XF", "voltage" : "" }, "AVCC_S_BNC_XF" : { "net_name" : "AVCC_S_BNC_XF", "voltage" : "", "node_list" : [ "J9_XF.C", "R146_XF.2" ] }, "C1_RDIMM_DQS_C<6>_XF" : { "node_list" : [ "J2_XF.266", "U1_XF.BN57" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "C1_RDIMM_DQS_C<6>_XF", "diff_pair_mate" : "C1_RDIMM_DQS_T<6>_XF" }, "C3_DDR4_ADR<4>_XF" : { "voltage" : "", "net_name" : "C3_DDR4_ADR<4>_XF", "node_list" : [ "J4_XF.214", "U1_XF.P27" ] }, "C2_DDR4_DQ<69>_XF" : { "node_list" : [ "J3_XF.192", "U1_XF.E59" ], "voltage" : "", "net_name" : "C2_DDR4_DQ<69>_XF" }, "C1_DDR4_DQ<31>_XF" : { "net_name" : "C1_DDR4_DQ<31>_XF", "voltage" : "", "node_list" : [ "J2_XF.188", "U1_XF.BW59" ] }, "FAN_TACH_OD<2>" : { "node_list" : [ "P4.3", "U1_CPLD.G11" ], "voltage" : "", "net_name" : "FAN_TACH_OD<2>" }, "E1S0_PET_N<4>_XF" : { "node_list" : [ "C125_XF.2", "J1_E0_XF.B30" ], "diff_pair_mate" : "E1S0_PET_P<4>_XF", "net_name" : "E1S0_PET_N<4>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "UNNAMED_3_BYPASSCAPNPOL_I28_A_ND" : { "node_list" : [ "C81_ND_XF.1", "R111_ND_XF.1" ], "voltage" : "", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I28_A_ND" }, "UNNAMED_3_BYPASSCAPNPOL_I28_A_SD" : { "node_list" : [ "C81_SD_XF.1", "R111_SD_XF.1" ], "voltage" : "", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I28_A_SD" }, "C3_DDR4_DQ<55>_XF" : { "node_list" : [ "J4_XF.269", "U1_XF.E17" ], "voltage" : "", "net_name" : "C3_DDR4_DQ<55>_XF" }, "UNNAMED_8_LT3071_I30_V01_FL" : { "node_list" : [ "R41_FL_XF.1", "R63_FL_XF.2", "U5_FL_XF.24" ], "voltage" : "", "net_name" : "UNNAMED_8_LT3071_I30_V01_FL" }, "UNNAMED_3_RESISTOR_I28_A_MP" : { "voltage" : "", "net_name" : "UNNAMED_3_RESISTOR_I28_A_MP", "node_list" : [ "R10_MP.1", "R1_MP.2" ] }, "C3_RDIMM_DQS_C<12>_XF" : { "node_list" : [ "J4_XF.41", "U1_XF.F23" ], "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "C3_RDIMM_DQS_T<12>_XF", "net_name" : "C3_RDIMM_DQS_C<12>_XF" }, "UNNAMED_4_PI6CB33401_I37_SDATA_E2" : { "node_list" : [ "R9_E2_XF.2", "U1_E2_XF.10" ], "net_name" : "UNNAMED_4_PI6CB33401_I37_SDATA_E2", "voltage" : "" }, "UNNAMED_17_RESISTOR_I187_B_XF" : { "node_list" : [ "R119_XF.2", "R75_XF.1" ], "net_name" : "UNNAMED_17_RESISTOR_I187_B_XF", "voltage" : "" }, "C3_DDR4_PARITY_XF" : { "net_name" : "C3_DDR4_PARITY_XF", "voltage" : "", "node_list" : [ "J4_XF.222", "U1_XF.R24" ] }, "DIMM_EVENT_OD_F<1>" : { "voltage" : "", "net_name" : "DIMM_EVENT_OD_F<1>", "node_list" : [ "J2_XF.78", "U1_CPLD.K12" ] }, "C0_RDIMM_DQS_C<2>_XF" : { "diff_pair_pol" : "NEG", "diff_pair_mate" : "C0_RDIMM_DQS_T<2>_XF", "net_name" : "C0_RDIMM_DQS_C<2>_XF", "voltage" : "", "node_list" : [ "J1_XF.174", "U1_XF.BT15" ] }, "UNNAMED_3_BYPASSCAPNPOL_I148_A_SP" : { "node_list" : [ "C39_SP_XF.1", "R51_SP_XF.1", "U1_SP_XF.42" ], "voltage" : "", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I148_A_SP" }, "C1_RDIMM_DQS_C<8>_XF" : { "node_list" : [ "J2_XF.196", "U1_XF.BV59" ], "diff_pair_mate" : "C1_RDIMM_DQS_T<8>_XF", "net_name" : "C1_RDIMM_DQS_C<8>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "UNNAMED_4_PI6CB33401_I37_PDF_E2" : { "voltage" : "", "net_name" : "UNNAMED_4_PI6CB33401_I37_PDF_E2", "node_list" : [ "R13_E2_XF.2", "U1_E2_XF.31" ] }, "E1S2_PET_P<1>_XF" : { "node_list" : [ "C154_XF.2", "J1_E2_XF.B21" ], "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "E1S2_PET_P<1>_XF", "diff_pair_mate" : "E1S2_PET_N<1>_XF" }, "AC_PCIE1_TXP<4>_XF" : { "node_list" : [ "C29_XF.1", "U1_XF.AP13" ], "diff_pair_pol" : "POS", "diff_pair_mate" : "AC_PCIE1_TXN<4>_XF", "net_name" : "AC_PCIE1_TXP<4>_XF", "voltage" : "" }, "AC_CONN_CLK_REFN<0>_3" : { "net_name" : "AC_CONN_CLK_REFN<0>_3", "diff_pair_mate" : "AC_CONN_CLK_REFP<0>_3", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "C25_E2_XF.1", "U1_E2_XF.14" ] }, "VMON_AVTT_SW_XF" : { "node_list" : [ "R142_XF.2", "R99_SP_XF.2" ], "net_name" : "VMON_AVTT_SW_XF", "voltage" : "" }, "IS_VCCINTUL_SW_P_SP" : { "diff_pair_pol" : "POS", "diff_pair_mate" : "IS_VCCINTUL_SW_N_SP", "net_name" : "IS_VCCINTUL_SW_P_SP", "voltage" : "", "node_list" : [ "C129_SP_XF.1", "R131_SP_XF.1", "R132_SP_XF.2", "R50_SP_XF.2" ] }, "C3_RDIMM_DQS_T<14>_XF" : { "node_list" : [ "J4_XF.110", "U1_XF.A23" ], "diff_pair_mate" : "C3_RDIMM_DQS_C<14>_XF", "net_name" : "C3_RDIMM_DQS_T<14>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "E1S0_PER_N<1>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "E1S0_PER_N<1>_XF", "diff_pair_mate" : "E1S0_PER_P<1>_XF", "node_list" : [ "J1_E0_XF.A20", "U1_XF.E5" ] }, "AC_E1S1_PET_P<7>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "AC_E1S1_PET_P<7>_XF", "diff_pair_mate" : "AC_E1S1_PET_N<7>_XF", "node_list" : [ "C110_XF.1", "U1_XF.R7" ] }, "RGB_LED_BLUE<2>_CPLD" : { "voltage" : "", "net_name" : "RGB_LED_BLUE<2>_CPLD", "node_list" : [ "R20_CPLD.2", "U1_CPLD.B7" ] }, "UNNAMED_3_BYPASSCAPNPOL_I177_A_SP" : { "voltage" : "", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I177_A_SP", "node_list" : [ "C63_SP_XF.1", "R14_SP_XF.1", "R40_SP_XF.2", "R42_SP_XF.1", "U1_SP_XF.9" ] }, "AC_E1S1_PET_N<6>_XF" : { "diff_pair_pol" : "NEG", "net_name" : "AC_E1S1_PET_N<6>_XF", "diff_pair_mate" : "AC_E1S1_PET_P<6>_XF", "voltage" : "", "node_list" : [ "C131_XF.1", "U1_XF.R10" ] }, "C0_DDR4_DQ<20>_XF" : { "node_list" : [ "J1_XF.25", "U1_XF.BR18" ], "voltage" : "", "net_name" : "C0_DDR4_DQ<20>_XF" }, "C1_DDR4_DQ<28>_XF" : { "node_list" : [ "J2_XF.36", "U1_XF.CB60" ], "net_name" : "C1_DDR4_DQ<28>_XF", "voltage" : "" }, "E1S0_3R3V_PRSNT_F<1>_XF" : { "node_list" : [ "J1_E0_XF.B42", "U1_XF.Y19" ], "net_name" : "E1S0_3R3V_PRSNT_F<1>_XF", "voltage" : "3.3V" }, "C2_RDIMM_DQS_C<13>_XF" : { "node_list" : [ "J3_XF.100", "U1_XF.D55" ], "diff_pair_pol" : "NEG", "net_name" : "C2_RDIMM_DQS_C<13>_XF", "diff_pair_mate" : "C2_RDIMM_DQS_T<13>_XF", "voltage" : "" }, "PWR_RS_RLC_MGTVCCAUX_XF" : { "net_name" : "PWR_RS_RLC_MGTVCCAUX_XF", "voltage" : "1.8", "node_list" : [ "C452_XF.1", "C475_XF.1", "C476_XF.1", "C83_FL_XF.1", "C85_FL_XF.2", "C93_XF.1", "R85_FL_XF.1", "R88_FL_XF.2", "U1_XF.AP15", "U1_XF.AT15", "U1_XF.BH15", "U1_XF.BK15", "U9_FL_XF.1" ] }, "C0_DDR4_DQ<51>_XF" : { "node_list" : [ "J1_XF.271", "U1_XF.BH24" ], "net_name" : "C0_DDR4_DQ<51>_XF", "voltage" : "" }, "C3_RDIMM_DQS_T<2>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "C3_RDIMM_DQS_T<2>_XF", "diff_pair_mate" : "C3_RDIMM_DQS_C<2>_XF", "node_list" : [ "J4_XF.175", "U1_XF.H28" ] }, "AC_OCL0_PET_N<3>_XF" : { "node_list" : [ "C258_XF.1", "U1_XF.CA10" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "AC_OCL0_PET_N<3>_XF", "diff_pair_mate" : "AC_OCL0_PET_P<3>_XF" }, "C0_DDR4_DQ<46>_XF" : { "node_list" : [ "J1_XF.113", "U1_XF.BM26" ], "net_name" : "C0_DDR4_DQ<46>_XF", "voltage" : "" }, "C0_RDIMM_DQS_T<12>_XF" : { "diff_pair_pol" : "POS", "net_name" : "C0_RDIMM_DQS_T<12>_XF", "diff_pair_mate" : "C0_RDIMM_DQS_C<12>_XF", "voltage" : "", "node_list" : [ "J1_XF.40", "U1_XF.BU24" ] }, "C2_DDR4_DQ<5>_XF" : { "node_list" : [ "J3_XF.148", "U1_XF.U46" ], "voltage" : "", "net_name" : "C2_DDR4_DQ<5>_XF" }, "C2_DDR4_CKE<0>_XF" : { "node_list" : [ "J3_XF.60", "U1_XF.L55" ], "net_name" : "C2_DDR4_CKE<0>_XF", "voltage" : "" }, "C0_DDR4_DQ<63>_XF" : { "node_list" : [ "J1_XF.280", "U1_XF.BG26" ], "net_name" : "C0_DDR4_DQ<63>_XF", "voltage" : "" }, "UNNAMED_7_LTM4671_I39_TRACKSS2_SP" : { "node_list" : [ "C108_SP_XF.2", "PM1_SP_XF.N7" ], "net_name" : "UNNAMED_7_LTM4671_I39_TRACKSS2_SP", "voltage" : "" }, "UNNAMED_13_NMOSFETVMT3_I99_G" : { "net_name" : "UNNAMED_13_NMOSFETVMT3_I99_G", "voltage" : "", "node_list" : [ "Q2.1", "R31.2" ] }, "C3_DDR4_CK_T<0>_XF" : { "node_list" : [ "J4_XF.74", "U1_XF.N27" ], "diff_pair_pol" : "POS", "diff_pair_mate" : "C3_DDR4_CK_C<0>_XF", "net_name" : "C3_DDR4_CK_T<0>_XF", "voltage" : "" }, "C0_DDR4_DQ<33>_XF" : { "net_name" : "C0_DDR4_DQ<33>_XF", "voltage" : "", "node_list" : [ "J1_XF.242", "U1_XF.BL22" ] }, "C3_DDR4_ADR<8>_XF" : { "node_list" : [ "J4_XF.68", "U1_XF.R25" ], "voltage" : "", "net_name" : "C3_DDR4_ADR<8>_XF" }, "AC_E1S2_PET_N<3>_XF" : { "node_list" : [ "C170_XF.1", "U1_XF.U10" ], "diff_pair_pol" : "NEG", "net_name" : "AC_E1S2_PET_N<3>_XF", "diff_pair_mate" : "AC_E1S2_PET_P<3>_XF", "voltage" : "" }, "C2_SYS_CLK_N_XF" : { "node_list" : [ "C365_XF.2", "R248_XF.2", "R251_XF.2", "R252_XF.1", "U1_XF.J60" ], "diff_pair_pol" : "NEG", "net_name" : "C2_SYS_CLK_N_XF", "diff_pair_mate" : "C2_SYS_CLK_P_XF", "voltage" : "" }, "UNNAMED_3_LT3071_I32_VIOC_FL" : { "voltage" : "", "net_name" : "UNNAMED_3_LT3071_I32_VIOC_FL", "node_list" : [ "C17_FL_XF.1", "U3_FL_XF.1" ] }, "C2_DDR4_DQ<42>_XF" : { "net_name" : "C2_DDR4_DQ<42>_XF", "voltage" : "", "node_list" : [ "J3_XF.115", "U1_XF.B53" ] }, "E1S1_PER_P<1>_XF" : { "diff_pair_pol" : "POS", "diff_pair_mate" : "E1S1_PER_N<1>_XF", "net_name" : "E1S1_PER_P<1>_XF", "voltage" : "", "node_list" : [ "J1_E1_XF.A21", "U1_XF.N6" ] }, "LTC2975_ALERT_OD_F" : { "node_list" : [ "U1_CPLD.P13", "U1_SP_XF.31" ], "net_name" : "LTC2975_ALERT_OD_F", "voltage" : "" }, "VMON_SPARE_SW_XF" : { "node_list" : [ "R122_SP_XF.2", "VMON_SPARE_SW_XF.1" ], "net_name" : "VMON_SPARE_SW_XF", "voltage" : "Unknown" }, "UNNAMED_3_OCULINKX4CONN_I86_REFCLKP_P0" : { "node_list" : [ "J1_P0_XF.B12", "R1_P0_XF.1" ], "voltage" : "", "net_name" : "UNNAMED_3_OCULINKX4CONN_I86_REFCLKP_P0" }, "AC_OCL3_PET_P<0>_XF" : { "node_list" : [ "C257_XF.1", "U1_XF.BJ11" ], "net_name" : "AC_OCL3_PET_P<0>_XF", "diff_pair_mate" : "AC_OCL3_PET_N<0>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "UNNAMED_17_BYPASSCAPNPOL_I50_A_XF" : { "node_list" : [ "C139_XF.1", "R78_XF.2", "U1_XF.CB38" ], "net_name" : "UNNAMED_17_BYPASSCAPNPOL_I50_A_XF", "voltage" : "" }, "UNNAMED_21_RESISTOR_I33_B_XF" : { "voltage" : "", "net_name" : "UNNAMED_21_RESISTOR_I33_B_XF", "node_list" : [ "R29_XF.2", "U1_XF.BR50" ] }, "AC_CONN_CLK_REFP<1>" : { "node_list" : [ "C20_E1_XF.1", "U1_E1_XF.17" ], "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "AC_CONN_CLK_REFP<1>", "diff_pair_mate" : "AC_CONN_CLK_REFN<1>" }, "POK_OD_AVCC_RS_RLC_LIN" : { "node_list" : [ "R70_FL_XF.2", "U1_CPLD.N10" ], "voltage" : "", "net_name" : "POK_OD_AVCC_RS_RLC_LIN" }, "OCL3_PER_N<1>_XF" : { "voltage" : "", "net_name" : "OCL3_PER_N<1>_XF", "diff_pair_mate" : "OCL3_PER_P<1>_XF", "diff_pair_pol" : "NEG", "node_list" : [ "J1_O3_XF.A7", "U1_XF.BJ1" ] }, "C2_DDR4_BA<1>_XF" : { "node_list" : [ "J3_XF.224", "U1_XF.J62" ], "voltage" : "", "net_name" : "C2_DDR4_BA<1>_XF" }, "C0_RDIMM_DQS_C<14>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "C0_RDIMM_DQS_T<14>_XF", "net_name" : "C0_RDIMM_DQS_C<14>_XF", "node_list" : [ "J1_XF.111", "U1_XF.BL27" ] }, "PCIE0_CLKREQ_XF" : { "voltage" : "", "net_name" : "PCIE0_CLKREQ_XF", "node_list" : [ "U1_XF.BC17" ] }, "JT_FPGA_TMS" : { "node_list" : [ "J5.2", "R63.1", "U1_CPLD.A11" ], "net_name" : "JT_FPGA_TMS", "voltage" : "" }, "CONN_CLK_REFN<1>_E3" : { "diff_pair_pol" : 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"voltage" : "", "diff_pair_mate" : "AC_PCIE1_TXP<1>_XF", "net_name" : "AC_PCIE1_TXN<1>_XF", "diff_pair_pol" : "NEG" }, "C1_DDR4_DQ<45>_XF" : { "node_list" : [ "J2_XF.251", "U1_XF.BN62" ], "net_name" : "C1_DDR4_DQ<45>_XF", "voltage" : "" }, "C1_DDR4_CS_N<2>_XF" : { "net_name" : "C1_DDR4_CS_N<2>_XF", "voltage" : "", "node_list" : [ "J2_XF.93", "U1_XF.CA57" ] }, "C3_DDR4_DQ<36>_XF" : { "net_name" : "C3_DDR4_DQ<36>_XF", "voltage" : "", "node_list" : [ "J4_XF.95", "U1_XF.B26" ] }, "PCIE0_RXN<6>_XF" : { "node_list" : [ "J2_P0_XF.A16", "U1_XF.BB3" ], "net_name" : "PCIE0_RXN<6>_XF", "diff_pair_mate" : "PCIE0_RXP<6>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "E1S0_3R3V_SMB_RST_F_XF" : { "node_list" : [ "J1_E0_XF.A9", "R5_E0_XF.2", "U1_XF.AB18" ], "voltage" : "3.3V", "net_name" : "E1S0_3R3V_SMB_RST_F_XF" }, "UNNAMED_4_RESISTOR_I2_B_MP" : { "voltage" : "", "net_name" : "UNNAMED_4_RESISTOR_I2_B_MP", "node_list" : [ "C12_MP.1", "R9_MP.2" ] }, "PCIE1_RXP<7>_XF" : { "node_list" : [ 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"BOARD_CFG_SW<2>" : { "voltage" : "", "net_name" : "BOARD_CFG_SW<2>", "node_list" : [ "S1.3", "U1_CPLD.N3", "U1_XF.BY35" ] }, "AC_FPGA_CLK_REF_N<1>" : { "node_list" : [ "C22_E1_XF.1", "U1_E1_XF.28" ], "diff_pair_pol" : "NEG", "net_name" : "AC_FPGA_CLK_REF_N<1>", "diff_pair_mate" : "AC_FPGA_CLK_REF_P<1>", "voltage" : "" }, "AC_PCIE1_TXN<0>_XF" : { "diff_pair_mate" : "AC_PCIE1_TXP<0>_XF", "net_name" : "AC_PCIE1_TXN<0>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "C49_XF.1", "U1_XF.AM8" ] }, "UNNAMED_12_NMOSFETVMT3_I12_G" : { "node_list" : [ "Q11.1", "R7.2" ], "net_name" : "UNNAMED_12_NMOSFETVMT3_I12_G", "voltage" : "" }, "UNNAMED_7_SM050TP_I161_1_CPLD" : { "node_list" : [ "TP12_CPLD.1", "U1_CPLD.R5" ], "net_name" : "UNNAMED_7_SM050TP_I161_1_CPLD", "voltage" : "" }, "UNNAMED_9_LT3071_I30_V02_FL" : { "voltage" : "", "net_name" : "UNNAMED_9_LT3071_I30_V02_FL", "node_list" : [ "R65_FL_XF.1", "R78_FL_XF.2", "U7_FL_XF.25" ] }, "PCIE0_TXP<1>_XF" : { "voltage" : "", "net_name" : "PCIE0_TXP<1>_XF", "diff_pair_mate" : "PCIE0_TXN<1>_XF", "diff_pair_pol" : "POS", "node_list" : [ "C40_XF.2", "J1_P0_XF.B6" ] }, "UNNAMED_9_LT3071_I66_PWRGD_FL" : { "voltage" : "", "net_name" : "UNNAMED_9_LT3071_I66_PWRGD_FL", "node_list" : [ "R104_FL_XF.1", "U11_FL_XF.2" ] }, "E1S2_PER_P<0>_XF" : { "node_list" : [ "J1_E2_XF.A18", "U1_XF.AA6" ], "diff_pair_pol" : "POS", "net_name" : "E1S2_PER_P<0>_XF", "diff_pair_mate" : "E1S2_PER_N<0>_XF", "voltage" : "" }, "C1_DDR4_DQ<24>_XF" : { "voltage" : "", "net_name" : "C1_DDR4_DQ<24>_XF", "node_list" : [ "J2_XF.38", "U1_XF.BW61" ] }, "UNNAMED_21_RESISTOR_I39_B_XF" : { "voltage" : "", "net_name" : "UNNAMED_21_RESISTOR_I39_B_XF", "node_list" : [ "R32_XF.2", "U1_XF.BV49" ] }, "C0_DDR4_DQ<34>_XF" : { "voltage" : "", "net_name" : "C0_DDR4_DQ<34>_XF", "node_list" : [ "J1_XF.104", "U1_XF.BK22" ] }, "UNNAMED_17_RESISTOR_I202_A_XF" : { "node_list" : [ "R13_XF.2", "R23_XF.1" ], "voltage" : "", "net_name" : "UNNAMED_17_RESISTOR_I202_A_XF" }, "UNNAMED_4_BYPASSCAPNPOL_I23_B_FL" : { "node_list" : [ "C5_FL_XF.2", "R21_FL_XF.2", "R22_FL_XF.1" ], "net_name" : "UNNAMED_4_BYPASSCAPNPOL_I23_B_FL", "voltage" : "" }, "AC_PCIE1_TXP<6>_XF" : { "node_list" : [ "C27_XF.1", "U1_XF.AT9" ], "voltage" : "", "diff_pair_mate" : "AC_PCIE1_TXN<6>_XF", "net_name" : "AC_PCIE1_TXP<6>_XF", "diff_pair_pol" : "POS" }, "UNNAMED_4_RESISTOR_I12_B_SP" : { "net_name" : "UNNAMED_4_RESISTOR_I12_B_SP", "voltage" : "", "node_list" : [ "R11_SP_XF.1", "R12_SP_XF.2" ] }, "OCL0_PET_N<1>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "OCL0_PET_N<1>_XF", "diff_pair_mate" : "OCL0_PET_P<1>_XF", "node_list" : [ "C260_XF.2", "J1_O0_XF.B7" ] }, "C3_DDR4_DQ<1>_XF" : { "net_name" : "C3_DDR4_DQ<1>_XF", "voltage" : "", "node_list" : [ "J4_XF.150", "U1_XF.L16" ] }, "AC_E1S2_PET_N<6>_XF" : { "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_E1S2_PET_P<6>_XF", "net_name" : "AC_E1S2_PET_N<6>_XF", "voltage" : "", "node_list" : [ "C157_XF.1", "U1_XF.AA10" ] }, "UNNAMED_5_CAPACITOR_I148_A_SP" : { "node_list" : [ "C48_SP_XF.1", "R15_SP_XF.1" ], "net_name" : "UNNAMED_5_CAPACITOR_I148_A_SP", "voltage" : "" }, "POK_OD_AVCC_RUC_LIN" : { "net_name" : "POK_OD_AVCC_RUC_LIN", "voltage" : "", "node_list" : [ "R92_FL_XF.2", "U1_CPLD.R10" ] }, "DIMM_VTT_3VFLT_ND" : { "voltage" : "3.3", "net_name" : "DIMM_VTT_3VFLT_ND", "node_list" : [ "C43_ND_XF.1", "FB6_ND_XF.2", "R66_ND_XF.2", "U2_ND_XF.10" ] }, "AC_E1S2_PET_P<7>_XF" : { "node_list" : [ "C148_XF.1", "U1_XF.Y9" ], "diff_pair_pol" : "POS", "diff_pair_mate" : "AC_E1S2_PET_N<7>_XF", "net_name" : "AC_E1S2_PET_P<7>_XF", "voltage" : "" }, "UNNAMED_17_BYPASSCAPNPOL_I216_A_XF" : { "net_name" : "UNNAMED_17_BYPASSCAPNPOL_I216_A_XF", "voltage" : "", "node_list" : [ "C316_XF.1", "R68_XF.1", "U1_XF.CA40" ] }, "UNNAMED_3_LTC2975_I168_VINISN2975_SP" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "UNNAMED_3_LTC2975_I168_VINISN2975_SP", "diff_pair_mate" : "UNNAMED_3_LTC2975_I168_VINISP2975_SP", "node_list" : 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"OCL2_PER_P<1>_XF" : { "node_list" : [ "J1_O2_XF.A6", "U1_XF.BL6" ], "diff_pair_mate" : "OCL2_PER_N<1>_XF", "net_name" : "OCL2_PER_P<1>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "E1S3_FPGA_REFCLK_P<0>_XF" : { "diff_pair_pol" : "POS", "diff_pair_mate" : "E1S3_FPGA_REFCLK_N<0>_XF", "net_name" : "E1S3_FPGA_REFCLK_P<0>_XF", "voltage" : "", "node_list" : [ "C19_E3_XF.2", "R192_XF.2", "R203_XF.1", "R204_XF.1", "U1_XF.AG15" ] }, "PCIE1_RXP<2>_XF" : { "voltage" : "", "diff_pair_mate" : "PCIE1_RXN<2>_XF", "net_name" : "PCIE1_RXP<2>_XF", "diff_pair_pol" : "POS", "node_list" : [ "J1_P1_XF.A15", "U1_XF.AP4" ] }, "OCL_REF_CLK_P<0>" : { "node_list" : [ "R275_XF.2", "R279_XF.1", "R280_XF.1", "U1.42", "U7_XF.5" ], "net_name" : "OCL_REF_CLK_P<0>", "diff_pair_mate" : "OCL_REF_CLK_N<0>", "diff_pair_pol" : "POS", "voltage" : "" }, "UNNAMED_4_MAX116XXQSOP16_I97_AIN5" : { "voltage" : "", "net_name" : "UNNAMED_4_MAX116XXQSOP16_I97_AIN5", "node_list" : [ "C43.1", "R54.1", "R76.1", "U11.10" ] }, "BASE_3R3V_SDA_2" : { "net_name" : "BASE_3R3V_SDA_2", "voltage" : "3.3V", "node_list" : [ "J1_XF.285", "J2_XF.285", "J3_XF.285", "J4_XF.285", "J5.6", "PM4_ND_XF.D4", "PM4_SD_XF.D4", "Q2.3", "Q4.3", "R113.1", "R2.2", "R44_SP_XF.1", "U11.14", "U1_CPLD.C9", "U4_SP_XF.11" ] }, "VS_AVTT_RUC_LIN_FL" : { "node_list" : [ "NS9_FL_XF.2", "R57_FL_XF.1", "U5_FL_XF.19" ], "voltage" : "", "net_name" : "VS_AVTT_RUC_LIN_FL" }, "C0_DDR4_DQ<64>_XF" : { "node_list" : [ "J1_XF.49", "U1_XF.BT27" ], "net_name" : "C0_DDR4_DQ<64>_XF", "voltage" : "" }, "FPGA_P1R8V_TDO" : { "net_name" : "FPGA_P1R8V_TDO", "voltage" : "1.8V", "node_list" : [ "R41_XF.2", "U1_CPLD.H6" ] }, "SI5341_FDEC" : { "net_name" : "SI5341_FDEC", "voltage" : "", "node_list" : [ "U1.25", "U1_CPLD.F4" ] }, "UNNAMED_7_LTM4671_I37_TRACKSS1_SP" : { "net_name" : "UNNAMED_7_LTM4671_I37_TRACKSS1_SP", "voltage" : "", "node_list" : [ "C109_SP_XF.2", "PM1_SP_XF.G7" ] }, "UNNAMED_8_BYPASSCAPNPOL_I25_B_FL" : { "node_list" : [ "C25_FL_XF.2", "R38_FL_XF.2", "R44_FL_XF.1" ], "net_name" : "UNNAMED_8_BYPASSCAPNPOL_I25_B_FL", "voltage" : "" }, "C2_DDR4_CKE<1>_XF" : { "voltage" : "", "net_name" : "C2_DDR4_CKE<1>_XF", "node_list" : [ "J3_XF.203", "U1_XF.M54" ] }, "C2_DDR4_ADR<13>_XF" : { "node_list" : [ "J3_XF.232", "U1_XF.G58" ], "voltage" : "", "net_name" : "C2_DDR4_ADR<13>_XF" }, "UNNAMED_22_RESISTOR_I37_B_XF" : { "voltage" : "", "net_name" : "UNNAMED_22_RESISTOR_I37_B_XF", "node_list" : [ "R53_XF.2", "U1_XF.J27" ] }, "C0_DDR4_ODT<1>_XF" : { "net_name" : "C0_DDR4_ODT<1>_XF", "voltage" : "", "node_list" : [ "J1_XF.91", "U1_XF.BY17" ] }, "C1_DDR4_CS_N<1>_XF" : { "voltage" : "", "net_name" : "C1_DDR4_CS_N<1>_XF", "node_list" : [ "J2_XF.89", "U1_XF.CB56" ] }, "AC_PCIE1_TXN<2>_XF" : { "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_PCIE1_TXP<2>_XF", "net_name" : "AC_PCIE1_TXN<2>_XF", "voltage" : "", "node_list" : [ "C47_XF.1", "U1_XF.AN10" ] }, "C3_DDR4_DQ<44>_XF" : { "node_list" : [ "J4_XF.106", "U1_XF.B23" ], "net_name" : "C3_DDR4_DQ<44>_XF", "voltage" : "" }, "CLKIN_N_E1" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "CLKIN_N_E1", "diff_pair_mate" : "CLKIN_P_E1", "node_list" : [ "C17_E1_XF.2", "R15_E1_XF.2", "R17_E1_XF.2", "R18_E1_XF.1", "U1_E1_XF.6" ] }, "UNNAMED_4_PI6CB33401_I37_SADRTRI_E3" : { "node_list" : [ "R12_E3_XF.2", "U1_E3_XF.32" ], "net_name" : "UNNAMED_4_PI6CB33401_I37_SADRTRI_E3", "voltage" : "" }, "VMON_RS_RLC_MGTVCCAUX" : { "node_list" : [ "R47.2", "R85_FL_XF.2" ], "voltage" : "", "net_name" : "VMON_RS_RLC_MGTVCCAUX" }, "C2_RDIMM_DQS_C<10>_XF" : { "voltage" : "", "diff_pair_mate" : "C2_RDIMM_DQS_T<10>_XF", "net_name" : "C2_RDIMM_DQS_C<10>_XF", "diff_pair_pol" : "NEG", "node_list" : [ "J3_XF.19", "U1_XF.N51" ] }, "FPGA_DCM_LOCK_F" : { "net_name" : "FPGA_DCM_LOCK_F", "voltage" : "", "node_list" : [ "U1_CPLD.H4", "U1_XF.BV39" ] }, "BOARD_CFG_SW<0>" : { "net_name" : "BOARD_CFG_SW<0>", "voltage" : "", "node_list" : [ "S1.1", "U1_CPLD.P2", "U1_XF.CB35" ] }, "UNNAMED_6_BYPASSCAPNPOL_I25_B_FL" : { "node_list" : [ "C22_FL_XF.2", "R36_FL_XF.2", "R42_FL_XF.1" ], "voltage" : "", "net_name" : "UNNAMED_6_BYPASSCAPNPOL_I25_B_FL" }, "C1_DDR4_DQ<23>_XF" : { "node_list" : [ "J2_XF.177", "U1_XF.BP57" ], "voltage" : "", "net_name" : "C1_DDR4_DQ<23>_XF" }, "C1_DDR4_ADR<14>_XF" : { "voltage" : "", "net_name" : "C1_DDR4_ADR<14>_XF", "node_list" : [ "J2_XF.228", "U1_XF.BY57" ] }, "C3_RDIMM_DQS_C<17>_XF" : { "node_list" : [ "J4_XF.52", "U1_XF.H19" ], "diff_pair_mate" : "C3_RDIMM_DQS_T<17>_XF", "net_name" : "C3_RDIMM_DQS_C<17>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "UNNAMED_7_LTM4671_I36_COMP3A_SP" : { "voltage" : "0V", "net_name" : "UNNAMED_7_LTM4671_I36_COMP3A_SP", "node_list" : [ "PM1_SP_XF.N8", "PM1_SP_XF.N9" ] }, "C1_DDR4_CS_N<0>_XF" : { "node_list" : [ "J2_XF.84", "U1_XF.BY52" ], "net_name" : "C1_DDR4_CS_N<0>_XF", "voltage" : "" }, "C3_DDR4_DQ<25>_XF" : { "voltage" : "", "net_name" : "C3_DDR4_DQ<25>_XF", "node_list" : [ "J4_XF.183", "U1_XF.H22" ] }, "E1S2_FPGA_REFCLK_N<0>_XF" : { "diff_pair_pol" : "NEG", "net_name" : "E1S2_FPGA_REFCLK_N<0>_XF", "diff_pair_mate" : "E1S2_FPGA_REFCLK_P<0>_XF", "voltage" : "", "node_list" : [ "C23_E2_XF.2", "R189_XF.2", "R198_XF.2", "R199_XF.1", "U1_XF.W14" ] }, "PCIE0_RXN<0>_XF" : { "diff_pair_pol" : "NEG", "net_name" : "PCIE0_RXN<0>_XF", "diff_pair_mate" : "PCIE0_RXP<0>_XF", "voltage" : "", "node_list" : [ "J1_P0_XF.A4", "U1_XF.AV3" ] }, "C3_DDR4_CS_N<3>_XF" : { "voltage" : "", "net_name" : "C3_DDR4_CS_N<3>_XF", "node_list" : [ "J4_XF.237", "U1_XF.J21" ] }, "C1_DDR4_DQ<17>_XF" : { "node_list" : [ "J2_XF.172", "U1_XF.BT55" ], "voltage" : "", "net_name" : "C1_DDR4_DQ<17>_XF" }, "OCL1_PER_P<0>_XF" : { "node_list" : [ "J1_O1_XF.A3", "U1_XF.BU6" ], "diff_pair_pol" : "POS", "net_name" : "OCL1_PER_P<0>_XF", "diff_pair_mate" : "OCL1_PER_N<0>_XF", "voltage" : "" }, "UNNAMED_3_LTM4675_I40_GPIO1F_ND" : { "node_list" : [ "PM4_ND_XF.F2", "R3_ND_XF.1" ], "net_name" : "UNNAMED_3_LTM4675_I40_GPIO1F_ND", "voltage" : "" }, "C0_DDR4_DQ<70>_XF" : { "voltage" : "", "net_name" : "C0_DDR4_DQ<70>_XF", "node_list" : [ "J1_XF.54", "U1_XF.BV27" ] }, "BOARD_CFG_SW<1>" : { "voltage" : "", "net_name" : "BOARD_CFG_SW<1>", "node_list" : [ "S1.4", "U1_CPLD.R1", "U1_XF.CA36" ] }, "E1S3_PER_N<0>_XF" : { "node_list" : [ "J1_E3_XF.A17", "U1_XF.AJ5" ], "voltage" : "", "diff_pair_mate" : "E1S3_PER_P<0>_XF", "net_name" : "E1S3_PER_N<0>_XF", "diff_pair_pol" : "NEG" }, "C3_DDR4_ADR<15>_XF" : { "node_list" : [ "J4_XF.86", "U1_XF.P22" ], "voltage" : "", "net_name" : "C3_DDR4_ADR<15>_XF" }, "C2_DDR4_ADR<7>_XF" : { "net_name" : "C2_DDR4_ADR<7>_XF", "voltage" : "", "node_list" : [ "J3_XF.211", "U1_XF.M56" ] }, "UNNAMED_5_LT3071_I30_VIOC_FL" : { "voltage" : "", "net_name" : "UNNAMED_5_LT3071_I30_VIOC_FL", "node_list" : [ "C29_FL_XF.1", "U1_FL_XF.1" ] }, "C3_DDR4_ADR<3>_XF" : { "net_name" : "C3_DDR4_ADR<3>_XF", "voltage" : "", "node_list" : [ "J4_XF.71", "U1_XF.N28" ] }, "AC_OCL0_PET_P<0>_XF" : { "node_list" : [ "C180_XF.1", "U1_XF.CC11" ], "net_name" : "AC_OCL0_PET_P<0>_XF", "diff_pair_mate" : "AC_OCL0_PET_N<0>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "UNNAMED_20_FERRITEBEAD_I58_B" : { "node_list" : [ "FB5.2", "P2.2" ], "voltage" : "", "net_name" : "UNNAMED_20_FERRITEBEAD_I58_B" }, "UNNAMED_4_RESISTOR_I16_A_MP" : { "voltage" : "", "net_name" : "UNNAMED_4_RESISTOR_I16_A_MP", "node_list" : [ "R6_MP.2", "R7_MP.1" ] }, "C0_DDR4_DQ<38>_XF" : { "voltage" : "", "net_name" : "C0_DDR4_DQ<38>_XF", "node_list" : [ "J1_XF.102", "U1_XF.BP21" ] }, "PSU_3R3V_SCL" : { "voltage" : "3.3V", "net_name" : "PSU_3R3V_SCL", "node_list" : [ "J4.1", "Q10.3", "R25.2" ] }, "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF" : { "net_name" : "UNNAMED_27_DIMMPWRBLK_I2_ANAGND4675_XF", "voltage" : "0V", "node_list" : [ "C67_SD_XF.1", "C68_SD_XF.1", "C81_SD_XF.2", "NS13_SD_XF.2", "PM4_SD_XF.F5", "PM4_SD_XF.F6", "PM4_SD_XF.G5", "PM4_SD_XF.G6", "R123_XF.1", "R26_SD_XF.1", "R5_SD_XF.1", "R6_SD_XF.1", "R7_SD_XF.1", "R8_SD_XF.1", "R9_SD_XF.1" ] }, "UNNAMED_4_RESISTOR_I7_A_ND" : { "voltage" : "", "net_name" : "UNNAMED_4_RESISTOR_I7_A_ND", "node_list" : [ "R61_ND_XF.1", "U2_ND_XF.9" ] }, "AC_PCIE0_TXP<7>_XF" : { "voltage" : "", "diff_pair_mate" : "AC_PCIE0_TXN<7>_XF", "net_name" : "AC_PCIE0_TXP<7>_XF", "diff_pair_pol" : "POS", "node_list" : [ "C34_XF.1", "U1_XF.BC11" ] }, "PCIE0_TXN<4>_XF" : { "diff_pair_pol" : "NEG", "diff_pair_mate" : "PCIE0_TXP<4>_XF", "net_name" : "PCIE0_TXN<4>_XF", "voltage" : "", "node_list" : [ "C78_XF.2", "J2_P0_XF.B4" ] }, "C1_DDR4_DQ<30>_XF" : { "voltage" : "", "net_name" : "C1_DDR4_DQ<30>_XF", "node_list" : [ "J2_XF.43", "U1_XF.BW60" ] }, "OCL2_PET_P<0>_XF" : { "node_list" : [ "C238_XF.2", "J1_O2_XF.B3" ], "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "OCL2_PET_P<0>_XF", "diff_pair_mate" : "OCL2_PET_N<0>_XF" }, "UNNAMED_17_RESISTOR_I8_B" : { "node_list" : [ "R103.2", "U12.2" ], "net_name" : "UNNAMED_17_RESISTOR_I8_B", "voltage" : "" }, "E1S3_PER_N<4>_XF" : { "node_list" : [ "J1_E3_XF.A30", "U1_XF.AM3" ], "voltage" : "", "net_name" : "E1S3_PER_N<4>_XF", "diff_pair_mate" : "E1S3_PER_P<4>_XF", "diff_pair_pol" : "NEG" }, "UNNAMED_4_CAPACITOR_I132_A_SP" : { "voltage" : "", "net_name" : "UNNAMED_4_CAPACITOR_I132_A_SP", "node_list" : [ "C47_SP_XF.1", "C69_SP_XF.1", "PM4_SP_XF.C8", "PM4_SP_XF.F8" ] }, "UNNAMED_7_LTM4671_I87_VOSNS0N_SP" : { "net_name" : "UNNAMED_7_LTM4671_I87_VOSNS0N_SP", "voltage" : "", "node_list" : [ "NS10_SP_XF.1", "PM1_SP_XF.F8" ] }, "AC_OCL3_PET_N<3>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_OCL3_PET_P<3>_XF", "net_name" : "AC_OCL3_PET_N<3>_XF", "node_list" : [ "C278_XF.1", "U1_XF.BG6" ] }, "UNNAMED_3_LT3071_I32_EN_FL" : { "net_name" : "UNNAMED_3_LT3071_I32_EN_FL", "voltage" : "", "node_list" : [ "R69_FL_XF.1", "U3_FL_XF.28" ] }, "C1_DDR4_DQ<54>_XF" : { "node_list" : [ "J2_XF.124", "U1_XF.BN59" ], "voltage" : "", "net_name" : "C1_DDR4_DQ<54>_XF" }, "UNNAMED_12_LT3071_I30_MARGA_FL" : { "voltage" : "", "net_name" : "UNNAMED_12_LT3071_I30_MARGA_FL", "node_list" : [ "R94_FL_XF.2", "U10_FL_XF.22" ] }, "OCL0_PER_N<0>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "OCL0_PER_P<0>_XF", "net_name" : "OCL0_PER_N<0>_XF", "node_list" : [ "J1_O0_XF.A4", "U1_XF.BY3" ] }, "C2_DDR4_DQ<15>_XF" : { "voltage" : "", "net_name" : "C2_DDR4_DQ<15>_XF", "node_list" : [ "J3_XF.166", "U1_XF.P47" ] }, "AC_E1S2_PET_P<0>_XF" : { "voltage" : "", "net_name" : "AC_E1S2_PET_P<0>_XF", "diff_pair_mate" : "AC_E1S2_PET_N<0>_XF", "diff_pair_pol" : "POS", "node_list" : [ "C155_XF.1", "U1_XF.W11" ] }, "UNNAMED_20_FERRITEBEAD_I55_B" : { "voltage" : "", "net_name" : "UNNAMED_20_FERRITEBEAD_I55_B", "node_list" : [ "FB8.2", "P5.2" ] }, "OCL3_FPGA_REFCLK_P_XF" : { "node_list" : [ "C357_XF.2", "R216_XF.2", "R227_XF.1", "R228_XF.1", "U1_XF.BJ15" ], "voltage" : "", "diff_pair_mate" : "OCL3_FPGA_REFCLK_N_XF", "net_name" : "OCL3_FPGA_REFCLK_P_XF", "diff_pair_pol" : "POS" }, "UNNAMED_20_FERRITEBEAD_I57_B" : { "node_list" : [ "FB6.2", "P3.2" ], "voltage" : "", "net_name" : "UNNAMED_20_FERRITEBEAD_I57_B" }, "C0_RDIMM_DQS_T<17>_XF" : { "node_list" : [ "J1_XF.51", "U1_XF.BW27" ], "diff_pair_mate" : "C0_RDIMM_DQS_C<17>_XF", "net_name" : "C0_RDIMM_DQS_T<17>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "C1_DDR4_DQ<60>_XF" : { "net_name" : "C1_DDR4_DQ<60>_XF", "voltage" : "", "node_list" : [ "J2_XF.128", "U1_XF.BL53" ] }, "C0_DDR4_DQ<68>_XF" : { "voltage" : "", "net_name" : "C0_DDR4_DQ<68>_XF", "node_list" : [ "J1_XF.47", "U1_XF.BV26" ] }, "C1_DDR4_ADR<5>_XF" : { "node_list" : [ "J2_XF.213", "U1_XF.BY49" ], "net_name" : "C1_DDR4_ADR<5>_XF", "voltage" : "" }, "UNNAMED_8_LT3071_I30_MARGA_FL" : { "net_name" : "UNNAMED_8_LT3071_I30_MARGA_FL", "voltage" : "", "node_list" : [ "R44_FL_XF.2", "U5_FL_XF.22" ] }, "PCIE1_TXP<3>_XF" : { "voltage" : "", "net_name" : "PCIE1_TXP<3>_XF", "diff_pair_mate" : "PCIE1_TXN<3>_XF", "diff_pair_pol" : "POS", "node_list" : [ "C30_XF.2", "J1_P1_XF.B18" ] }, "UNNAMED_20_FERRITEBEAD_I56_B" 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"E1S1_3R3V_PWRDIS_XF" : { "voltage" : "3.3V", "net_name" : "E1S1_3R3V_PWRDIS_XF", "node_list" : [ "J1_E1_XF.B12", "U1_XF.AF18" ] }, "UNNAMED_12_BYPASSCAPNPOL_I31_A_FL" : { "net_name" : "UNNAMED_12_BYPASSCAPNPOL_I31_A_FL", "voltage" : "", "node_list" : [ "C90_FL_XF.1", "U10_FL_XF.3" ] }, "C0_DDR4_DQ<62>_XF" : { "node_list" : [ "J1_XF.135", "U1_XF.BG25" ], "net_name" : "C0_DDR4_DQ<62>_XF", "voltage" : "" }, "C1_RDIMM_DQS_C<11>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "C1_RDIMM_DQS_T<11>_XF", "net_name" : "C1_RDIMM_DQS_C<11>_XF", "node_list" : [ "J2_XF.30", "U1_XF.BR55" ] }, "VS_VCCAUX_LIN_P_XF" : { "node_list" : [ "NS12_FL_XF.2", "R25_SP_XF.2" ], "voltage" : "", "net_name" : "VS_VCCAUX_LIN_P_XF", "diff_pair_mate" : "VS_VCCAUX_LIN_N_XF", "diff_pair_pol" : "POS" }, "UNNAMED_29_PI6CB33401_I89_PDF_XF" : { "net_name" : "UNNAMED_29_PI6CB33401_I89_PDF_XF", "voltage" : "", "node_list" : [ "R149_XF.2", "U7_XF.31" ] }, "UNNAMED_4_LT3071_I30_MARGA_FL" : { "node_list" : [ "R22_FL_XF.2", "U6_FL_XF.22" ], "voltage" : "", "net_name" : "UNNAMED_4_LT3071_I30_MARGA_FL" }, "UNNAMED_4_LT3071_I30_V02_FL" : { "node_list" : [ "R58_FL_XF.1", "R60_FL_XF.2", "U6_FL_XF.25" ], "net_name" : "UNNAMED_4_LT3071_I30_V02_FL", "voltage" : "" }, "UNNAMED_5_LTM4650FIXED_I78_RUN1_SP" : { "net_name" : "UNNAMED_5_LTM4650FIXED_I78_RUN1_SP", "voltage" : "", "node_list" : [ "PM5_SP_XF.F5", "PM5_SP_XF.F9", "R199_SP_XF.2" ] }, "E1S1_PET_N<6>_XF" : { "node_list" : [ "C131_XF.2", "J1_E1_XF.B36" ], "diff_pair_pol" : "NEG", "diff_pair_mate" : "E1S1_PET_P<6>_XF", "net_name" : "E1S1_PET_N<6>_XF", "voltage" : "" }, "C2_DDR4_DQ<36>_XF" : { "node_list" : [ "J3_XF.95", "U1_XF.D56" ], "net_name" : "C2_DDR4_DQ<36>_XF", "voltage" : "" }, "UNNAMED_8_BYPASSCAPNPOL_I31_A_FL" : { "voltage" : "", "net_name" : "UNNAMED_8_BYPASSCAPNPOL_I31_A_FL", "node_list" : [ "C40_FL_XF.1", "U5_FL_XF.3" ] }, "C3_DDR4_DQ<7>_XF" : { "voltage" : "", "net_name" : "C3_DDR4_DQ<7>_XF", "node_list" : [ "J4_XF.155", "U1_XF.K17" ] }, "C1_RDIMM_DQS_T<9>_XF" : { "node_list" : [ "J2_XF.7", "U1_XF.BP50" ], "net_name" : "C1_RDIMM_DQS_T<9>_XF", "diff_pair_mate" : "C1_RDIMM_DQS_C<9>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "AC_E1S0_PET_N<1>_XF" : { "node_list" : [ "C128_XF.1", "U1_XF.B8" ], "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_E1S0_PET_P<1>_XF", "net_name" : "AC_E1S0_PET_N<1>_XF", "voltage" : "" }, "DDR4_SYS_CLK_N<1>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "DDR4_SYS_CLK_N<1>_XF", "diff_pair_mate" : "DDR4_SYS_CLK_P<1>_XF", "node_list" : [ "C363_XF.1", "U6_XF.13" ] }, "C2_RDIMM_DQS_T<4>_XF" : { "diff_pair_pol" : "POS", "diff_pair_mate" : "C2_RDIMM_DQS_C<4>_XF", "net_name" : "C2_RDIMM_DQS_T<4>_XF", "voltage" : "", "node_list" : [ "J3_XF.245", "U1_XF.F57" ] }, "E1S2_3R3V_LED_XF" : { "node_list" : [ "J1_E2_XF.A10", "R6_E2_XF.2", "U1_XF.N19" ], "net_name" : "E1S2_3R3V_LED_XF", "voltage" : "3.3V" }, "AC_OCL3_PET_P<2>_XF" : { "node_list" : [ "C255_XF.1", "U1_XF.BG11" ], "voltage" : "", "diff_pair_pol" : "POS", "diff_pair_mate" : "AC_OCL3_PET_N<2>_XF", "net_name" : "AC_OCL3_PET_P<2>_XF" }, "AC_OCL2_PET_N<1>_XF" : { "node_list" : [ "C276_XF.1", "U1_XF.BM8" ], "diff_pair_pol" : "NEG", "net_name" : "AC_OCL2_PET_N<1>_XF", "diff_pair_mate" : "AC_OCL2_PET_P<1>_XF", "voltage" : "" }, "C1_DDR4_ADR<12>_XF" : { "net_name" : "C1_DDR4_ADR<12>_XF", "voltage" : "", "node_list" : [ "J2_XF.65", "U1_XF.CA53" ] }, "UNNAMED_22_RESISTOR_I45_B_XF" : { "net_name" : "UNNAMED_22_RESISTOR_I45_B_XF", "voltage" : "", "node_list" : [ "R60_XF.2", "U1_XF.BG30" ] }, "PCIE0_REFP_XF" : { "voltage" : "", "diff_pair_mate" : "PCIE0_REFN_XF", "net_name" : "PCIE0_REFP_XF", "diff_pair_pol" : "POS", "node_list" : [ "C100_XF.1", "R1_P0_XF.2" ] }, "OCL3_PET_P<3>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "OCL3_PET_P<3>_XF", "diff_pair_mate" : "OCL3_PET_N<3>_XF", "node_list" : [ "C254_XF.2", "J1_O3_XF.B18" ] }, "C1_DDR4_DQ<57>_XF" : { "voltage" : "", "net_name" : "C1_DDR4_DQ<57>_XF", "node_list" : [ "J2_XF.275", "U1_XF.BL55" ] }, "SW2_4650_TL_SP" : { "node_list" : [ "PM4_SP_XF.G11" ], "net_name" : "SW2_4650_TL_SP", "voltage" : "12" }, "DDR4_SYS_CLK_N<0>_XF" : { "diff_pair_mate" : "DDR4_SYS_CLK_P<0>_XF", "net_name" : "DDR4_SYS_CLK_N<0>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "C361_XF.1", "U6_XF.15" ] }, "E1S1_PET_N<3>_XF" : { "diff_pair_mate" : "E1S1_PET_P<3>_XF", "net_name" : "E1S1_PET_N<3>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "C134_XF.2", "J1_E1_XF.B26" ] }, "PWR_AVCC_SW_XF" : { "voltage" : "1.2", "net_name" : "PWR_AVCC_SW_XF", "node_list" : [ "C21_FL_XF.1", "C2_FL_XF.1", "C41_FL_XF.1", "C42_FL_XF.1", "C44_FL_XF.1", "C45_FL_XF.1", "C65_FL_XF.1", "C7_FL_XF.1", "C90_SP_XF.1", "C91_FL_XF.1", "C91_SP_XF.1", "C92_FL_XF.1", "C93_FL_XF.1", "C94_SP_XF.1", "C95_FL_XF.1", "C95_SP_XF.1", "C98_SP_XF.1", "C99_SP_XF.1", "PM2_SP_XF.H1", "PM2_SP_XF.H2", "PM2_SP_XF.H3", "PM2_SP_XF.H4", "PM2_SP_XF.J1", "PM2_SP_XF.J10", "PM2_SP_XF.J2", "PM2_SP_XF.J3", "PM2_SP_XF.J4", "PM2_SP_XF.L1", "PM2_SP_XF.L10", "PM2_SP_XF.L2", "PM2_SP_XF.L3", "PM2_SP_XF.L4", "PM2_SP_XF.M1", "PM2_SP_XF.M2", "PM2_SP_XF.M3", "PM2_SP_XF.M4", "R100_SP_XF.1", "U10_FL_XF.5", "U10_FL_XF.6", "U10_FL_XF.7", "U10_FL_XF.8", "U3_FL_XF.5", "U3_FL_XF.6", "U3_FL_XF.7", "U3_FL_XF.8", "U6_FL_XF.5", "U6_FL_XF.6", "U6_FL_XF.7", "U6_FL_XF.8" ] }, "AC_PCIE1_TXN<4>_XF" : { "node_list" : [ "C45_XF.1", "U1_XF.AP12" ], "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_PCIE1_TXP<4>_XF", "net_name" : "AC_PCIE1_TXN<4>_XF" }, "C2_DDR4_DQ<66>_XF" : { "node_list" : [ "J3_XF.56", "U1_XF.C58" ], "voltage" : "", "net_name" : "C2_DDR4_DQ<66>_XF" }, "C2_DDR4_DQ<43>_XF" : { "voltage" : "", "net_name" : "C2_DDR4_DQ<43>_XF", "node_list" : [ "J3_XF.260", "U1_XF.A52" ] }, "UNNAMED_6_BYPASSCAPNPOL_I402_B_SP" : { "voltage" : "", "net_name" : "UNNAMED_6_BYPASSCAPNPOL_I402_B_SP", "node_list" : [ "C83_SP_XF.2", "PM2_SP_XF.R11", "R85_SP_XF.2", "R88_SP_XF.2", "R94_SP_XF.2" ] }, "C0_DDR4_DQ<32>_XF" : { "net_name" : "C0_DDR4_DQ<32>_XF", "voltage" : "", "node_list" : [ "J1_XF.97", "U1_XF.BM23" ] }, "UNNAMED_13_NMOSFETVMT3_I100_G" : { "node_list" : [ "Q1.1", "R32.2" ], "net_name" : "UNNAMED_13_NMOSFETVMT3_I100_G", "voltage" : "" }, "C0_DDR4_ADR<15>_XF" : { "net_name" : "C0_DDR4_ADR<15>_XF", "voltage" : "", "node_list" : [ "J1_XF.86", "U1_XF.BR20" ] }, "E1S1_PER_N<5>_XF" : { "node_list" : [ "J1_E1_XF.A33", "U1_XF.U1" ], "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "E1S1_PER_P<5>_XF", "net_name" : "E1S1_PER_N<5>_XF" }, "UNNAMED_5_BYPASSCAPNPOL_I25_B_FL" : { "voltage" : "", "net_name" : "UNNAMED_5_BYPASSCAPNPOL_I25_B_FL", "node_list" : [ "C20_FL_XF.2", "R29_FL_XF.2", "R31_FL_XF.1" ] }, "C3_DDR4_DQ<70>_XF" : { "voltage" : "", "net_name" : "C3_DDR4_DQ<70>_XF", "node_list" : [ "J4_XF.54", "U1_XF.G16" ] }, "OCL0_3R3V_BP_TYPE_XF" : { "node_list" : [ "J1_O0_XF.B9", "U1_XF.BJ20" ], "net_name" : "OCL0_3R3V_BP_TYPE_XF", "voltage" : "3.3V" }, "C0_DDR4_CS_N<3>_XF" : { "net_name" : "C0_DDR4_CS_N<3>_XF", "voltage" : "", "node_list" : [ "J1_XF.237", "U1_XF.CC16" ] }, "PWR_VCCAUX_B_FL" : { "voltage" : "1.8", "net_name" : "PWR_VCCAUX_B_FL", "node_list" : [ "C105_FL_XF.1", "C106_FL_XF.1", "C107_FL_XF.1", "C108_FL_XF.1", "NS11_FL_XF.1", "R115_FL_XF.1", "U11_FL_XF.15", "U11_FL_XF.16", "U11_FL_XF.17", "U11_FL_XF.18" ] }, "UNNAMED_4_PI6CB33401_I37_BWSELTRI_E3" : { "voltage" : "", "net_name" : "UNNAMED_4_PI6CB33401_I37_BWSELTRI_E3", "node_list" : [ "R10_E3_XF.2", "U1_E3_XF.1" ] }, "UNNAMED_6_LTM4671_I456_CLKOUT3_SP" : { "voltage" : "", "net_name" : "UNNAMED_6_LTM4671_I456_CLKOUT3_SP", "node_list" : [ "PM2_SP_XF.L9", "PM2_SP_XF.P6", "R98_SP_XF.1" ] }, "PHASMD_4650_BL_SP" : { "node_list" : [ "PM3_SP_XF.G4", "R24_SP_XF.2", "R7_SP_XF.2" ], "voltage" : "", "net_name" : "PHASMD_4650_BL_SP" }, "C0_RDIMM_DQS_C<17>_XF" : { "node_list" : [ "J1_XF.52", "U1_XF.BW26" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "C0_RDIMM_DQS_C<17>_XF", "diff_pair_mate" : "C0_RDIMM_DQS_T<17>_XF" }, "AC_OCL1_PET_P<3>_XF" : { "node_list" : [ "C181_XF.1", "U1_XF.BV9" ], "net_name" : "AC_OCL1_PET_P<3>_XF", "diff_pair_mate" : "AC_OCL1_PET_N<3>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "C0_DDR4_DQ<25>_XF" : { "net_name" : "C0_DDR4_DQ<25>_XF", "voltage" : "", "node_list" : [ "J1_XF.183", "U1_XF.BV22" ] }, "E1S3_3R3V_CKEN_F<1>_XF" : { "node_list" : [ "U1_E3_XF.19", "U1_XF.R18" ], "net_name" : "E1S3_3R3V_CKEN_F<1>_XF", "voltage" : "" }, "AC_CONN_CLK_REFN<1>" : { "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_CONN_CLK_REFP<1>", "net_name" : "AC_CONN_CLK_REFN<1>", "voltage" : "", "node_list" : [ "C24_E1_XF.1", "U1_E1_XF.18" ] }, "MGTRREF_RN_XF" : { "net_name" : "MGTRREF_RN_XF", "voltage" : "", "node_list" : [ "R269_XF.1", "U1_XF.R14" ] }, "OCL0_3R3V_SDA_XF" : { "node_list" : [ "J1_O0_XF.A10", "R231_XF.2", "U1_XF.BL18" ], "voltage" : "3.3V", "net_name" : "OCL0_3R3V_SDA_XF" }, "UNNAMED_3_LTM4675_I40_RUN0_SD" : { "node_list" : [ "D1_SD_XF.2", "PM4_SD_XF.F3", "PM4_SD_XF.F4", "R1_SD_XF.2" ], "net_name" : "UNNAMED_3_LTM4675_I40_RUN0_SD", "voltage" : "" }, "E1S3_PET_P<2>_XF" : { "diff_pair_pol" : "POS", "net_name" : "E1S3_PET_P<2>_XF", "diff_pair_mate" : "E1S3_PET_N<2>_XF", "voltage" : "", "node_list" : [ "C340_XF.2", "J1_E3_XF.B24" ] }, "PWR_RN_RUC_MGTVCCAUX_XF" : { "voltage" : "1.8", "net_name" : "PWR_RN_RUC_MGTVCCAUX_XF", "node_list" : [ "C473_XF.1", "C474_XF.1", "C82_FL_XF.1", "C84_FL_XF.2", "C91_XF.1", "C92_XF.1", "R83_FL_XF.1", "R86_FL_XF.2", "U1_XF.AK15", "U1_XF.AM15", "U1_XF.P15", "U1_XF.T15", "U8_FL_XF.1" ] }, "UNNAMED_3_BYPASSCAPNPOL_I146_A_SP" : { "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I146_A_SP", "voltage" : "", "node_list" : [ "C28_SP_XF.1", "R49_SP_XF.1", "U1_SP_XF.44" ] }, "C0_DDR4_DQ<44>_XF" : { "net_name" : "C0_DDR4_DQ<44>_XF", "voltage" : "", "node_list" : [ "J1_XF.106", "U1_XF.BP24" ] }, "JTAG_CTL_TCK" : { "net_name" : "JTAG_CTL_TCK", "voltage" : "", "node_list" : [ "U1_CPLD.F1", "U1_XF.CA32" ] }, "C3_DDR4_ODT<1>_XF" : { "node_list" : [ "J4_XF.91", "U1_XF.K22" ], "voltage" : "", "net_name" : "C3_DDR4_ODT<1>_XF" }, "UNNAMED_6_RESISTOR_I441_A_SP" : { "node_list" : [ "PM2_SP_XF.P8", "R83_SP_XF.2", "R85_SP_XF.1" ], "voltage" : "", "net_name" : "UNNAMED_6_RESISTOR_I441_A_SP" }, "OCL1_PET_N<2>_XF" : { "net_name" : "OCL1_PET_N<2>_XF", "diff_pair_mate" : "OCL1_PET_P<2>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "C271_XF.2", "J1_O1_XF.B16" ] }, "GNDADC_XF" : { "voltage" : "0V", "net_name" : "GNDADC_XF", "node_list" : [ "C142_XF.2", "C143_XF.2", "FB1_XF.1", "R85_XF.2", "U1_XF.AL24", "U9_XF.5" ] }, "OCL2_PET_P<3>_XF" : { "voltage" : "", "net_name" : "OCL2_PET_P<3>_XF", "diff_pair_mate" : "OCL2_PET_N<3>_XF", "diff_pair_pol" : "POS", "node_list" : [ "C233_XF.2", "J1_O2_XF.B18" ] }, "REF/BYP_FL" : { "net_name" : "REF/BYP_FL", "voltage" : "", "node_list" : [ "C102_FL_XF.1", "C73_FL_XF.1", "U11_FL_XF.3", "U7_FL_XF.3" ] }, "C3_DDR4_DQ<64>_XF" : { "net_name" : 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"OCL0_PET_P<2>_XF" : { "voltage" : "", "diff_pair_mate" : "OCL0_PET_N<2>_XF", "net_name" : "OCL0_PET_P<2>_XF", "diff_pair_pol" : "POS", "node_list" : [ "C177_XF.2", "J1_O0_XF.B15" ] }, "E1S3_3R3V_SDA_XF" : { "voltage" : "3.3V", "net_name" : "E1S3_3R3V_SDA_XF", "node_list" : [ "J1_E3_XF.A8", "R209_XF.2", "R4_E3_XF.2", "U1_XF.U20" ] }, "E1S2_PET_N<5>_XF" : { "voltage" : "", "net_name" : "E1S2_PET_N<5>_XF", "diff_pair_mate" : "E1S2_PET_P<5>_XF", "diff_pair_pol" : "NEG", "node_list" : [ "C168_XF.2", "J1_E2_XF.B33" ] }, "PCIE1_RXN<5>_XF" : { "node_list" : [ "J2_P1_XF.A7", "U1_XF.AT3" ], "net_name" : "PCIE1_RXN<5>_XF", "diff_pair_mate" : "PCIE1_RXP<5>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "IS_VCCINTUL_SW_N_SP" : { "node_list" : [ "C127_SP_XF.1", "R127_SP_XF.1", "R128_SP_XF.2", "R49_SP_XF.2" ], "diff_pair_mate" : "IS_VCCINTUL_SW_P_SP", "net_name" : "IS_VCCINTUL_SW_N_SP", "diff_pair_pol" : "NEG", "voltage" : "" }, "C3_DDR4_DQ<38>_XF" : { "node_list" : [ "J4_XF.102", "U1_XF.A27" ], "voltage" : "", "net_name" : "C3_DDR4_DQ<38>_XF" }, "FPGA_CFG_MODE<2>_1" : { "node_list" : [ "U1_CPLD.J3", "U1_XF.AK17" ], "voltage" : "", "net_name" : "FPGA_CFG_MODE<2>_1" }, "AC_E1S0_PET_P<6>_XF" : { "net_name" : "AC_E1S0_PET_P<6>_XF", "diff_pair_mate" : "AC_E1S0_PET_N<6>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "C103_XF.1", "U1_XF.D9" ] }, "CPLD_FPGA_SSTAT_CLK" : { "node_list" : [ "U1_CPLD.K6", "U1_XF.BW34" ], "net_name" : "CPLD_FPGA_SSTAT_CLK", "voltage" : "" }, "E1S0_PET_P<4>_XF" : { "voltage" : "", "net_name" : "E1S0_PET_P<4>_XF", "diff_pair_mate" : "E1S0_PET_N<4>_XF", "diff_pair_pol" : "POS", "node_list" : [ "C105_XF.2", "J1_E0_XF.B31" ] }, "BP_TYPE_P1" : { "node_list" : [ "J1_P1_XF.B9" ], "net_name" : "BP_TYPE_P1", "voltage" : "" }, "C1_DDR4_CK_C<0>_XF" : { "node_list" : [ "J2_XF.75", "U1_XF.CC49" ], "net_name" : "C1_DDR4_CK_C<0>_XF", "diff_pair_mate" : "C1_DDR4_CK_T<0>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "UNNAMED_4_MAX116XXQSOP16_I97_AIN4" : { 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"POK_OD_VCCAUX_B_LIN" : { "node_list" : [ "R104_FL_XF.2", "U1_CPLD.N9" ], "net_name" : "POK_OD_VCCAUX_B_LIN", "voltage" : "" }, "C2_DDR4_DQ<20>_XF" : { "voltage" : "", "net_name" : "C2_DDR4_DQ<20>_XF", "node_list" : [ "J3_XF.25", "U1_XF.G61" ] }, "AC_E1S3_PET_N<2>_XF" : { "diff_pair_pol" : "NEG", "net_name" : "AC_E1S3_PET_N<2>_XF", "diff_pair_mate" : "AC_E1S3_PET_P<2>_XF", "voltage" : "", "node_list" : [ "C312_XF.1", "U1_XF.AG10" ] }, "UNNAMED_20_MLXKK1004PINBOSS_I30_P4" : { "voltage" : "", "net_name" : "UNNAMED_20_MLXKK1004PINBOSS_I30_P4", "node_list" : [ "P2.4", "Q6.3" ] }, "UNNAMED_21_RESISTOR_I30_B_XF" : { "node_list" : [ "R27_XF.2", "U1_XF.BK49" ], "net_name" : "UNNAMED_21_RESISTOR_I30_B_XF", "voltage" : "" }, "AC_E1S2_PET_P<1>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "AC_E1S2_PET_P<1>_XF", "diff_pair_mate" : "AC_E1S2_PET_N<1>_XF", "node_list" : [ "C154_XF.1", "U1_XF.W7" ] }, "PCIE0_TXP<4>_XF" : { "node_list" : [ "C37_XF.2", "J2_P0_XF.B3" ], "voltage" : "", "diff_pair_pol" : "POS", "diff_pair_mate" : "PCIE0_TXN<4>_XF", "net_name" : "PCIE0_TXP<4>_XF" }, "E1S1_PET_N<0>_XF" : { "node_list" : [ "C137_XF.2", "J1_E1_XF.B17" ], "voltage" : "", "diff_pair_mate" : "E1S1_PET_P<0>_XF", "net_name" : "E1S1_PET_N<0>_XF", "diff_pair_pol" : "NEG" }, "FPGA_CFG_DONE_1" : { "node_list" : [ "R38_XF.2", "U1_CPLD.H1", "U1_XF.AL18" ], "voltage" : "", "net_name" : "FPGA_CFG_DONE_1" }, "C2_RDIMM_DQS_C<2>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "C2_RDIMM_DQS_C<2>_XF", "diff_pair_mate" : "C2_RDIMM_DQS_T<2>_XF", "node_list" : [ "J3_XF.174", "U1_XF.F63" ] }, "ENB3V_SEQ_J_CPLD" : { "node_list" : [ "R8_CPLD.1", "U1_CPLD.L15" ], "voltage" : "", "net_name" : "ENB3V_SEQ_J_CPLD" }, "E1S1_3R3V_SMB_RST_F_XF" : { "voltage" : "3.3V", "net_name" : "E1S1_3R3V_SMB_RST_F_XF", "node_list" : [ "J1_E1_XF.A9", "R5_E1_XF.2", "U1_XF.AH18" ] }, "PWR_AVTT_RN_XF" : { "node_list" : [ "C195_XF.1", "C196_XF.1", "C329_XF.1", "C330_XF.1", "C331_XF.1", "C332_XF.1", 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"UNNAMED_3_RESISTOR_I15_A_MP", "voltage" : "", "node_list" : [ "R4_MP.2", "R5_MP.1", "U1_MP.6" ] }, "P5VSB" : { "voltage" : "5.0", "net_name" : "P5VSB", "node_list" : [ "C1_MP.1", "C37.2", "C38.2", "C6_MP.1", "C7_MP.1", "C8_MP.1", "FPNL_CONN.2", "J3.9", "R15_MP.2", "R17_MP.2", "R2_MP.1", "R82.1", "R8_MP.1", "U1_MP.1", "U1_MP.16", "U1_MP.2", "U2_MP.1", "U2_MP.16", "U2_MP.2" ] }, "BASE_1R8V_SDA" : { "node_list" : [ "Q4.2", "R112.1", "R120.1" ], "voltage" : "1.8V", "net_name" : "BASE_1R8V_SDA" }, "UNNAMED_11_RESISTOR_I773_B_XF" : { "voltage" : "", "net_name" : "UNNAMED_11_RESISTOR_I773_B_XF", "node_list" : [ "R156_XF.2", "R158_XF.2", "U1_XF.BG34" ] }, "OCL1_PET_N<3>_XF" : { "voltage" : "", "net_name" : "OCL1_PET_N<3>_XF", "diff_pair_mate" : "OCL1_PET_P<3>_XF", "diff_pair_pol" : "NEG", "node_list" : [ "C270_XF.2", "J1_O1_XF.B19" ] }, "PCIE0_TXP<3>_XF" : { "net_name" : "PCIE0_TXP<3>_XF", "diff_pair_mate" : "PCIE0_TXN<3>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ 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"voltage" : "", "net_name" : "E1S3_PET_P<3>_XF", "diff_pair_mate" : "E1S3_PET_N<3>_XF", "diff_pair_pol" : "POS" }, "UNNAMED_3_RESISTOR_I70_B_E2" : { "node_list" : [ "J1_E2_XF.MH1", "J1_E2_XF.MH2", "J1_E2_XF.MH3", "R1_E2_XF.2" ], "net_name" : "UNNAMED_3_RESISTOR_I70_B_E2", "voltage" : "" }, "UNNAMED_3_LTM4675_I40_COMP0B_SD" : { "node_list" : [ "PM4_SD_XF.D6", "PM4_SD_XF.J6", "R108_SD_XF.1", "R109_SD_XF.1", "R111_SD_XF.2" ], "voltage" : "0V", "net_name" : "UNNAMED_3_LTM4675_I40_COMP0B_SD" }, "C0_DDR4_DQ<65>_XF" : { "node_list" : [ "J1_XF.194", "U1_XF.BT28" ], "voltage" : "", "net_name" : "C0_DDR4_DQ<65>_XF" }, "UNNAMED_13_RESISTOR_I101_A" : { "net_name" : "UNNAMED_13_RESISTOR_I101_A", "voltage" : "", "node_list" : [ "R27.2", "R31.1", "R32.1", "R58.2" ] }, "VMON_CPLD_P1R8V_SW" : { "node_list" : [ "R11_MP.2", "R59.1" ], "net_name" : "VMON_CPLD_P1R8V_SW", "voltage" : "1.8V" }, "E1S2_PER_P<7>_XF" : { "voltage" : "", "net_name" : "E1S2_PER_P<7>_XF", "diff_pair_mate" : "E1S2_PER_N<7>_XF", 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"voltage" : "", "node_list" : [ "TP19.1", "U1.9", "X1.3" ] }, "UNNAMED_4_TIMINGCAPNPOL_I15_A_MP" : { "voltage" : "", "net_name" : "UNNAMED_4_TIMINGCAPNPOL_I15_A_MP", "node_list" : [ "C10_MP.1", "U2_MP.9" ] }, "UNNAMED_3_LTM4675_I40_VOUT1CFG_SD" : { "node_list" : [ "PM4_SD_XF.G4", "R7_SD_XF.2" ], "net_name" : "UNNAMED_3_LTM4675_I40_VOUT1CFG_SD", "voltage" : "" }, "C0_DDR4_BG<1>_XF" : { "net_name" : "C0_DDR4_BG<1>_XF", "voltage" : "", "node_list" : [ "J1_XF.207", "U1_XF.BV21" ] }, "UNNAMED_17_BYPASSCAPNPOL_I46_A_XF" : { "voltage" : "", "net_name" : "UNNAMED_17_BYPASSCAPNPOL_I46_A_XF", "node_list" : [ "C147_XF.1", "R99_XF.1", "U1_XF.BY33" ] }, "AC_E1S2_PET_N<5>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_E1S2_PET_P<5>_XF", "net_name" : "AC_E1S2_PET_N<5>_XF", "node_list" : [ "C168_XF.1", "U1_XF.AB8" ] }, "UNNAMED_3_BYPASSCAPNPOL_I144_A_SP" : { "node_list" : [ "C26_SP_XF.1", "R47_SP_XF.1", "U1_SP_XF.46" ], "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I144_A_SP", "voltage" : "" }, "C3_RDIMM_DQS_C<8>_XF" : { "net_name" : "C3_RDIMM_DQS_C<8>_XF", "diff_pair_mate" : "C3_RDIMM_DQS_T<8>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "J4_XF.196", "U1_XF.H17" ] }, "PCIE0_RXP<2>_XF" : { "node_list" : [ "J1_P0_XF.A15", "U1_XF.AW6" ], "voltage" : "", "diff_pair_mate" : "PCIE0_RXN<2>_XF", "net_name" : "PCIE0_RXP<2>_XF", "diff_pair_pol" : "POS" }, "JT_CPLD_TCK" : { "voltage" : "", "net_name" : "JT_CPLD_TCK", "node_list" : [ "J5.16", "R65.2", "U4_CPLD.1" ] }, "C2_DDR4_DQ<52>_XF" : { "node_list" : [ "J3_XF.117", "U1_XF.K50" ], "voltage" : "", "net_name" : "C2_DDR4_DQ<52>_XF" }, "UNNAMED_3_LTM4675_I40_VOUT1CFG_ND" : { "node_list" : [ "PM4_ND_XF.G4", "R7_ND_XF.2" ], "voltage" : "", "net_name" : "UNNAMED_3_LTM4675_I40_VOUT1CFG_ND" }, "C1_RDIMM_DQS_C<12>_XF" : { "node_list" : [ "J2_XF.41", "U1_XF.CC59" ], "diff_pair_mate" : "C1_RDIMM_DQS_T<12>_XF", "net_name" : "C1_RDIMM_DQS_C<12>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "OCL2_PER_N<3>_XF" : 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"diff_pair_pol" : "NEG" }, "AC_CONN_CLK_REFN<1>_2" : { "node_list" : [ "C24_E3_XF.1", "U1_E3_XF.18" ], "voltage" : "", "net_name" : "AC_CONN_CLK_REFN<1>_2", "diff_pair_mate" : "AC_CONN_CLK_REFP<1>_2", "diff_pair_pol" : "NEG" }, "FPGA_P1R8V_TMS" : { "net_name" : "FPGA_P1R8V_TMS", "voltage" : "1.8V", "node_list" : [ "U1_CPLD.F3", "U1_XF.AP17" ] }, "UNNAMED_7_LTM4671_I36_RUN3_SP" : { "net_name" : "UNNAMED_7_LTM4671_I36_RUN3_SP", "voltage" : "", "node_list" : [ "PM1_SP_XF.P7", "R103_SP_XF.2", "R107_SP_XF.1" ] }, "UNNAMED_6_LT3071_I30_EN_FL" : { "node_list" : [ "R30_FL_XF.1", "U2_FL_XF.28" ], "voltage" : "", "net_name" : "UNNAMED_6_LT3071_I30_EN_FL" }, "E1S0_PER_N<4>_XF" : { "node_list" : [ "J1_E0_XF.A30", "U1_XF.J1" ], "voltage" : "", "diff_pair_mate" : "E1S0_PER_P<4>_XF", "net_name" : "E1S0_PER_N<4>_XF", "diff_pair_pol" : "NEG" }, "CPLD_TDI_PIN_CPLD" : { "voltage" : "", "net_name" : "CPLD_TDI_PIN_CPLD", "node_list" : [ "R17_CPLD.2", "U1_CPLD.A6" ] }, "PCIE0_TXN<7>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "PCIE0_TXN<7>_XF", "diff_pair_mate" : "PCIE0_TXP<7>_XF", "node_list" : [ "C50_XF.2", "J2_P0_XF.B19" ] }, "C3_DDR4_DQ<22>_XF" : { "node_list" : [ "J4_XF.32", "U1_XF.F26" ], "net_name" : "C3_DDR4_DQ<22>_XF", "voltage" : "" }, "PCIE0_WAKE_F_XF" : { "node_list" : [ "J1_P0_XF.B10", "U1_XF.BD17" ], "net_name" : "PCIE0_WAKE_F_XF", "voltage" : "" }, "E1S2_PET_P<4>_XF" : { "net_name" : "E1S2_PET_P<4>_XF", "diff_pair_mate" : "E1S2_PET_N<4>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "C151_XF.2", "J1_E2_XF.B31" ] }, "PCIE1_TXP<6>_XF" : { "node_list" : [ "C27_XF.2", "J2_P1_XF.B15" ], "diff_pair_mate" : "PCIE1_TXN<6>_XF", "net_name" : "PCIE1_TXP<6>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "UNNAMED_7_LTM4671_I36_FREQ3_SP" : { "node_list" : [ "PM1_SP_XF.P8", "R106_SP_XF.2", "R110_SP_XF.1" ], "voltage" : "", "net_name" : "UNNAMED_7_LTM4671_I36_FREQ3_SP" }, "OCL3_PER_N<0>_XF" : { "voltage" : "", "diff_pair_mate" : "OCL3_PER_P<0>_XF", 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"U1_XF.BB12" ] }, "E1S3_PER_P<1>_XF" : { "diff_pair_mate" : "E1S3_PER_N<1>_XF", "net_name" : "E1S3_PER_P<1>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "J1_E3_XF.A21", "U1_XF.AJ2" ] }, "C1_DDR4_DQ<33>_XF" : { "node_list" : [ "J2_XF.242", "U1_XF.BR63" ], "net_name" : "C1_DDR4_DQ<33>_XF", "voltage" : "" }, "OCL0_FPGA_REFCLK_N_XF" : { "node_list" : [ "C370_XF.2", "R211_XF.2", "R219_XF.2", "R220_XF.1", "U1_XF.CB12" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "OCL0_FPGA_REFCLK_N_XF", "diff_pair_mate" : "OCL0_FPGA_REFCLK_P_XF" }, "UNNAMED_12_LT3071_I30_V01_FL" : { "node_list" : [ "R97_FL_XF.2", "R99_FL_XF.1", "U10_FL_XF.24" ], "voltage" : "", "net_name" : "UNNAMED_12_LT3071_I30_V01_FL" }, "UNNAMED_6_LTM4671_I516_MODECLKIN0_SP" : { "node_list" : [ "PM2_SP_XF.G11", "R93_SP_XF.1" ], "net_name" : "UNNAMED_6_LTM4671_I516_MODECLKIN0_SP", "voltage" : "" }, "C3_DDR4_ADR<0>_XF" : { "net_name" : "C3_DDR4_ADR<0>_XF", "voltage" : "", "node_list" : [ "J4_XF.79", "U1_XF.R23" ] }, "UNNAMED_3_OCULINKX4CONN_I86_REFCLKN_P1" : { "net_name" : "UNNAMED_3_OCULINKX4CONN_I86_REFCLKN_P1", "voltage" : "", "node_list" : [ "J1_P1_XF.B13", "R2_P1_XF.1" ] }, "OCL1_PER_N<1>_XF" : { "diff_pair_pol" : "NEG", "net_name" : "OCL1_PER_N<1>_XF", "diff_pair_mate" : "OCL1_PER_P<1>_XF", "voltage" : "", "node_list" : [ "J1_O1_XF.A7", "U1_XF.BU1" ] }, "CPLD_TCK_PIN_CPLD" : { "node_list" : [ "R18_CPLD.2", "U1_CPLD.A7" ], "voltage" : "", "net_name" : "CPLD_TCK_PIN_CPLD" }, "UNNAMED_22_RESISTOR_I38_B_XF" : { "net_name" : "UNNAMED_22_RESISTOR_I38_B_XF", "voltage" : "", "node_list" : [ "R52_XF.2", "U1_XF.U26" ] }, "PCIE_X1_REFN_XF" : { "voltage" : "", "net_name" : "PCIE_X1_REFN_XF", "diff_pair_mate" : "PCIE_X1_REFP_XF", "diff_pair_pol" : "NEG", "node_list" : [ "C289_XF.1", "J1_PX1_XF.A14" ] }, "C2_RDIMM_DQS_C<7>_XF" : { "node_list" : [ "J3_XF.277", "U1_XF.M51" ], "net_name" : "C2_RDIMM_DQS_C<7>_XF", "diff_pair_mate" : "C2_RDIMM_DQS_T<7>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "C1_RDIMM_DQS_C<14>_XF" : { "node_list" : [ "J2_XF.111", "U1_XF.BN63" ], "net_name" : "C1_RDIMM_DQS_C<14>_XF", "diff_pair_mate" : "C1_RDIMM_DQS_T<14>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "CLKIN_P_E3" : { "node_list" : [ "C16_E3_XF.2", "R14_E3_XF.2", "R16_E3_XF.1", "R17_E3_XF.1", "U1_E3_XF.5" ], "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "CLKIN_P_E3", "diff_pair_mate" : "CLKIN_N_E3" }, "UNNAMED_4_BYPASSCAPNPOL_I31_A_FL" : { "net_name" : "UNNAMED_4_BYPASSCAPNPOL_I31_A_FL", "voltage" : "", "node_list" : [ "C19_FL_XF.1", "U6_FL_XF.3" ] }, "C2_RDIMM_DQS_T<16>_XF" : { "node_list" : [ "J3_XF.132", "U1_XF.N49" ], "diff_pair_pol" : "POS", "net_name" : "C2_RDIMM_DQS_T<16>_XF", "diff_pair_mate" : "C2_RDIMM_DQS_C<16>_XF", "voltage" : "" }, "C2_DDR4_DQ<59>_XF" : { "net_name" : "C2_DDR4_DQ<59>_XF", "voltage" : "", "node_list" : [ "J3_XF.282", "U1_XF.K47" ] }, "SI5341_DIS_CLKS" : { "node_list" : [ "U1.11", "U1_CPLD.F2" ], "voltage" : "", "net_name" : "SI5341_DIS_CLKS" }, "IS_VCCINTLR_SW_N_SP" : { "voltage" : "", "diff_pair_mate" : "IS_VCCINTLR_SW_P_SP", "net_name" : "IS_VCCINTLR_SW_N_SP", "diff_pair_pol" : "NEG", "node_list" : [ "C181_SP_XF.1", "R191_SP_XF.1", "R192_SP_XF.2", "R47_SP_XF.2" ] }, "C2_DDR4_ADR<17>_XF" : { "net_name" : "C2_DDR4_ADR<17>_XF", "voltage" : "", "node_list" : [ "J3_XF.234" ] }, "C1_DDR4_DQ<51>_XF" : { "node_list" : [ "J2_XF.271", "U1_XF.BK59" ], "net_name" : "C1_DDR4_DQ<51>_XF", "voltage" : "" }, "NC_TL_1_SP" : { "net_name" : "NC_TL_1_SP", "voltage" : "", "node_list" : [ "C35_SP_XF.2" ] }, "UNNAMED_7_RESISTOR_I42_A_SP" : { "node_list" : [ "R58_SP_XF.2", "R69_SP_XF.1" ], "net_name" : "UNNAMED_7_RESISTOR_I42_A_SP", "voltage" : "" }, "SW1_NODE_ND" : { "node_list" : [ "PM4_ND_XF.L8" ], "voltage" : "12", "net_name" : "SW1_NODE_ND" }, "E1S_REF_CLK_P<1>" : { "node_list" : [ "C16_E1_XF.1", "U1.31" ], "diff_pair_pol" : "POS", "diff_pair_mate" : "E1S_REF_CLK_N<1>", "net_name" : "E1S_REF_CLK_P<1>", "voltage" : "" }, "C1_DDR4_DQ<46>_XF" : { "node_list" : [ "J2_XF.113", "U1_XF.BL63" ], "voltage" : "", "net_name" : "C1_DDR4_DQ<46>_XF" }, "C1_RDIMM_DQS_T<12>_XF" : { "node_list" : [ "J2_XF.40", "U1_XF.CC58" ], "net_name" : "C1_RDIMM_DQS_T<12>_XF", "diff_pair_mate" : "C1_RDIMM_DQS_C<12>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "C3_DDR4_DQ<35>_XF" : { "net_name" : "C3_DDR4_DQ<35>_XF", "voltage" : "", "node_list" : [ "J4_XF.249", "U1_XF.D25" ] }, "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF" : { "node_list" : [ "C67_ND_XF.1", "C68_ND_XF.1", "C81_ND_XF.2", "NS13_ND_XF.2", "PM4_ND_XF.F5", "PM4_ND_XF.F6", "PM4_ND_XF.G5", "PM4_ND_XF.G6", "R122_XF.1", "R26_ND_XF.1", "R5_ND_XF.1", "R6_ND_XF.1", "R7_ND_XF.1", "R8_ND_XF.1", "R9_ND_XF.1" ], "voltage" : "0V", "net_name" : "UNNAMED_27_DIMMPWRBLK_I1_ANAGND4675_XF" }, "C1_DDR4_DQ<63>_XF" : { "node_list" : [ "J2_XF.280", "U1_XF.BL52" ], "voltage" : "", "net_name" : "C1_DDR4_DQ<63>_XF" }, "C3_RDIMM_DQS_T<8>_XF" : { "diff_pair_mate" : "C3_RDIMM_DQS_C<8>_XF", "net_name" : "C3_RDIMM_DQS_T<8>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "J4_XF.197", "U1_XF.H18" ] }, "C1_DDR4_ODT<0>_XF" : { "voltage" : "", "net_name" : "C1_DDR4_ODT<0>_XF", "node_list" : [ "J2_XF.87", "U1_XF.CC56" ] }, "CPLD_SELF_TCK_CPLD" : { "voltage" : "", "net_name" : "CPLD_SELF_TCK_CPLD", "node_list" : [ "U1_CPLD.B14", "U4_CPLD.3" ] }, "E1S3_PET_P<4>_XF" : { "diff_pair_mate" : "E1S3_PET_N<4>_XF", "net_name" : "E1S3_PET_P<4>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "C339_XF.2", "J1_E3_XF.B31" ] }, "OCL2_PER_N<0>_XF" : { "node_list" : [ "J1_O2_XF.A4", "U1_XF.BM3" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "OCL2_PER_N<0>_XF", "diff_pair_mate" : "OCL2_PER_P<0>_XF" }, "PCIE1_TXN<6>_XF" : { "diff_pair_pol" : "NEG", "diff_pair_mate" : "PCIE1_TXP<6>_XF", "net_name" : "PCIE1_TXN<6>_XF", "voltage" : "", "node_list" : [ "C43_XF.2", "J2_P1_XF.B16" ] }, "HOST_3R3V_SDA" : { "node_list" : [ "R38.2", "U1_CPLD.B12" ], "net_name" : "HOST_3R3V_SDA", "voltage" : "3.3V" }, "VMON_AVCC_RUC_LIN_XF" : { "node_list" : [ "R102_FL_XF.2", "R39_XF.2" ], "net_name" : "VMON_AVCC_RUC_LIN_XF", "voltage" : "" }, "C3_RDIMM_DQS_T<6>_XF" : { "node_list" : [ "J4_XF.267", "U1_XF.D16" ], "net_name" : "C3_RDIMM_DQS_T<6>_XF", "diff_pair_mate" : "C3_RDIMM_DQS_C<6>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "AC_CONN_CLK_REFN<1>_1" : { "node_list" : [ "C24_E0_XF.1", "U1_E0_XF.18" ], "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_CONN_CLK_REFP<1>_1", "net_name" : "AC_CONN_CLK_REFN<1>_1", "voltage" : "" }, "C2_RDIMM_DQS_C<3>_XF" : { "node_list" : [ "J3_XF.185", "U1_XF.H54" ], "diff_pair_pol" : "NEG", "diff_pair_mate" : "C2_RDIMM_DQS_T<3>_XF", "net_name" : "C2_RDIMM_DQS_C<3>_XF", "voltage" : "" }, "UNNAMED_29_PI6CB33401_I89_SCLK_XF" : { "node_list" : [ "R125_XF.2", "U7_XF.9" ], "net_name" : "UNNAMED_29_PI6CB33401_I89_SCLK_XF", "voltage" : "" }, "PCIE0_RXN<5>_XF" : { "node_list" : [ "J2_P0_XF.A7", "U1_XF.BA5" ], "diff_pair_pol" : "NEG", "diff_pair_mate" : "PCIE0_RXP<5>_XF", "net_name" : "PCIE0_RXN<5>_XF", "voltage" : "" }, "C0_DDR4_DQ<24>_XF" : { "net_name" : "C0_DDR4_DQ<24>_XF", "voltage" : "", "node_list" : [ "J1_XF.38", "U1_XF.BW22" ] }, "PWR_AVCC_RS_RLC_XF" : { "node_list" : [ "C120_XF.1", "C121_XF.1", "C122_XF.1", "C13_FL_XF.1", "C15_FL_XF.1", "C463_XF.1", "C464_XF.1", "C465_XF.1", "C466_XF.1", "C479_XF.1", "C67_FL_XF.1", "C68_FL_XF.1", "NS2_FL_XF.1", "R146_XF.1", "U1_XF.AV15", "U1_XF.AY15", "U1_XF.BA13", "U1_XF.BB15", "U1_XF.BC13", "U1_XF.BD15", "U1_XF.BE13", "U1_XF.BF15", "U1_XF.BG13", "U1_XF.BJ13", "U1_XF.BL13", "U1_XF.BM15", "U1_XF.BN13", "U1_XF.BR13", "U1_XF.BU13", "U1_XF.BW13", "U1_XF.CA13", "U3_FL_XF.15", "U3_FL_XF.16", "U3_FL_XF.17", "U3_FL_XF.18" ], "voltage" : "0.9", "net_name" : "PWR_AVCC_RS_RLC_XF" }, "VMON_NDIMM_VTT_LIN" : { "node_list" : [ "R45.2", "R4_ND_XF.2" ], "voltage" : "", "net_name" : "VMON_NDIMM_VTT_LIN" }, "PCIE1_RXP<1>_XF" : { "node_list" : [ "J1_P1_XF.A6", "U1_XF.AN6" ], "net_name" : "PCIE1_RXP<1>_XF", "diff_pair_mate" : "PCIE1_RXN<1>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "AC_PCIE0_TXN<5>_XF" : { "node_list" : [ "C77_XF.1", "U1_XF.BA10" ], "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_PCIE0_TXP<5>_XF", "net_name" : "AC_PCIE0_TXN<5>_XF", "voltage" : "" }, "C1_DDR4_RESET_N_XF" : { "node_list" : [ "J2_XF.58", "U1_XF.CA55" ], "voltage" : "", "net_name" : "C1_DDR4_RESET_N_XF" }, "VMON_SDIMM_VPP_SW" : { "node_list" : [ "R124_SP_XF.2", "R52.1" ], "net_name" : "VMON_SDIMM_VPP_SW", "voltage" : "" }, "ENB3V_SEQ_A" : { "voltage" : "", "net_name" : "ENB3V_SEQ_A", "node_list" : [ "R16_CPLD.1", "R16_SP_XF.1", "R197_SP_XF.1", "R199_SP_XF.1", "R78_SP_XF.1", "U1_CPLD.P15" ] }, "UNNAMED_9_598BICOLORLED_I16_L2A_CPLD" : { "net_name" : "UNNAMED_9_598BICOLORLED_I16_L2A_CPLD", "voltage" : "", "node_list" : [ "D1_CPLD.1", "R119_CPLD.1" ] }, "C1_DDR4_DQ<71>_XF" : { "voltage" : "", "net_name" : "C1_DDR4_DQ<71>_XF", "node_list" : [ "J2_XF.199", "U1_XF.BT57" ] }, "C0_DDR4_DQ<45>_XF" : { "node_list" : [ "J1_XF.251", "U1_XF.BP25" ], "voltage" : "", "net_name" : "C0_DDR4_DQ<45>_XF" }, "OCL0_PET_P<0>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "diff_pair_mate" : "OCL0_PET_N<0>_XF", "net_name" : "OCL0_PET_P<0>_XF", "node_list" : [ "C180_XF.2", "J1_O0_XF.B3" ] }, "PCIE0_TXP<7>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "PCIE0_TXP<7>_XF", "diff_pair_mate" : "PCIE0_TXN<7>_XF", "node_list" : [ "C34_XF.2", "J2_P0_XF.B18" ] }, "UNNAMED_7_LTM4671_I36_TRACKSS3_SP" : { "voltage" : "", "net_name" : "UNNAMED_7_LTM4671_I36_TRACKSS3_SP", "node_list" : [ "C106_SP_XF.2", "PM1_SP_XF.P9" ] }, "AC_E1S1_PET_N<4>_XF" : { "diff_pair_pol" : "NEG", "net_name" : "AC_E1S1_PET_N<4>_XF", "diff_pair_mate" : "AC_E1S1_PET_P<4>_XF", "voltage" : "", "node_list" : [ "C133_XF.1", "U1_XF.U6" ] }, "C0_DDR4_CS_N<2>_XF" : { "net_name" : "C0_DDR4_CS_N<2>_XF", "voltage" : "", "node_list" : [ "J1_XF.93", "U1_XF.CB16" ] }, "AC_E1S0_PET_P<5>_XF" : { "net_name" : "AC_E1S0_PET_P<5>_XF", "diff_pair_mate" : "AC_E1S0_PET_N<5>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "C104_XF.1", "U1_XF.E11" ] }, "E1S0_FPGA_REFCLK_N<0>_XF" : { "node_list" : [ "C23_E0_XF.2", "R164_XF.2", "R174_XF.2", "R175_XF.1", "U1_XF.D12" ], "diff_pair_pol" : "NEG", "diff_pair_mate" : "E1S0_FPGA_REFCLK_P<0>_XF", "net_name" : "E1S0_FPGA_REFCLK_N<0>_XF", "voltage" : "" }, "NDIMM_I2C_ASEL_RESISTOR_XF" : { "net_name" : "NDIMM_I2C_ASEL_RESISTOR_XF", "voltage" : "", "node_list" : [ "PM4_ND_XF.G2", "R122_XF.2" ] }, "C0_RDIMM_DQS_C<6>_XF" : { "net_name" : "C0_RDIMM_DQS_C<6>_XF", "diff_pair_mate" : "C0_RDIMM_DQS_T<6>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "J1_XF.266", "U1_XF.BH23" ] }, "ENB3V_SEQ_D" : { "voltage" : "", "net_name" : "ENB3V_SEQ_D", "node_list" : [ "PM2_SP_XF.F11", "PM2_SP_XF.P7", "R13_CPLD.1", "U1_CPLD.N14" ] }, "MGTRREF_LS_XF" : { "net_name" : "MGTRREF_LS_XF", "voltage" : "", "node_list" : [ "R268_XF.2", "U1_XF.BE14" ] }, "C0_DDR4_DQ<31>_XF" : { "net_name" : "C0_DDR4_DQ<31>_XF", "voltage" : "", "node_list" : [ "J1_XF.188", "U1_XF.BV24" ] }, "UNNAMED_4_RESISTOR_I17_A_ND" : { "voltage" : "", "net_name" : "UNNAMED_4_RESISTOR_I17_A_ND", "node_list" : [ "R66_ND_XF.1", "U2_ND_XF.7" ] }, "UNNAMED_17_RESISTOR_I52_A_XF" : { "node_list" : [ "R3_XF.2", "R4_XF.2", "R77_XF.1" ], "net_name" : "UNNAMED_17_RESISTOR_I52_A_XF", "voltage" : "" }, "UNNAMED_7_SM050TP_I154_1_CPLD" : { "node_list" : [ "TP14_CPLD.1", "U1_CPLD.C15" ], "net_name" : "UNNAMED_7_SM050TP_I154_1_CPLD", "voltage" : "" }, "AC_E1S0_PET_P<1>_XF" : { "node_list" : [ "C108_XF.1", "U1_XF.B9" ], "diff_pair_pol" : "POS", "net_name" : "AC_E1S0_PET_P<1>_XF", "diff_pair_mate" : "AC_E1S0_PET_N<1>_XF", "voltage" : "" }, "AC_OCL3_PET_N<2>_XF" : { "node_list" : [ "C279_XF.1", "U1_XF.BG10" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "AC_OCL3_PET_N<2>_XF", "diff_pair_mate" : "AC_OCL3_PET_P<2>_XF" }, "UNNAMED_7_RESISTOR_I61_A_SP" : { "voltage" : "", "net_name" : "UNNAMED_7_RESISTOR_I61_A_SP", "node_list" : [ "R64_SP_XF.2", "R72_SP_XF.1" ] }, "C2_DDR4_DQ<3>_XF" : { "node_list" : [ "J3_XF.157", "U1_XF.T48" ], "voltage" : "", "net_name" : "C2_DDR4_DQ<3>_XF" }, "PSU_PWR_ON" : { "voltage" : "", "net_name" : "PSU_PWR_ON", "node_list" : [ "R57.2", "R61.1", "U1_CPLD.P7" ] }, "UNNAMED_7_LT3071_I30_VIOC_FL" : { "net_name" : "UNNAMED_7_LT3071_I30_VIOC_FL", "voltage" : "", "node_list" : [ "C36_FL_XF.1", "U4_FL_XF.1" ] }, "VDDO5" : { "node_list" : [ "C10.1", "R13.2", "U1.40" ], "net_name" : "VDDO5", "voltage" : "1.8" }, "UNNAMED_11_LTM4650FIXED_I150_PGOOD1_SP" : { "net_name" : "UNNAMED_11_LTM4650FIXED_I150_PGOOD1_SP", "voltage" : "", "node_list" : [ "PM7_SP_XF.G9", "R95_SP_XF.1" ] }, "C0_DDR4_DQ<53>_XF" : { "net_name" : "C0_DDR4_DQ<53>_XF", "voltage" : "", "node_list" : [ "J1_XF.262", "U1_XF.BJ21" ] }, "C2_DDR4_DQ<6>_XF" : { "net_name" : "C2_DDR4_DQ<6>_XF", "voltage" : "", "node_list" : [ "J3_XF.10", "U1_XF.T51" ] }, "C0_DDR4_ADR<16>_XF" : { "voltage" : "", "net_name" : "C0_DDR4_ADR<16>_XF", "node_list" : [ "J1_XF.82", "U1_XF.CC18" ] }, "AC_FPGA_CLK_REF_P<0>_2" : { "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "AC_FPGA_CLK_REF_P<0>_2", "diff_pair_mate" : "AC_FPGA_CLK_REF_N<0>_2", "node_list" : [ "C19_E3_XF.1", "U1_E3_XF.22" ] }, "UNNAMED_5_LT3071_I30_V00_FL" : { "node_list" : [ "R1_FL_XF.2", "R35_FL_XF.1", "U1_FL_XF.23" ], "net_name" : "UNNAMED_5_LT3071_I30_V00_FL", "voltage" : "" }, "E1S3_PET_P<0>_XF" : { "node_list" : [ "C343_XF.2", "J1_E3_XF.B18" ], "diff_pair_mate" : "E1S3_PET_N<0>_XF", "net_name" : "E1S3_PET_P<0>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "AC_OCL2_PET_P<1>_XF" : { "diff_pair_mate" : "AC_OCL2_PET_N<1>_XF", "net_name" : "AC_OCL2_PET_P<1>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "C237_XF.1", "U1_XF.BM9" ] }, "SW2_4650_TR_SP" : { "voltage" : "12", "net_name" : "SW2_4650_TR_SP", "node_list" : [ "PM5_SP_XF.G11" ] }, "C2_RDIMM_DQS_T<11>_XF" : { "diff_pair_pol" : "POS", "diff_pair_mate" : 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"J1_E2_XF.B27" ], "diff_pair_pol" : "POS", "net_name" : "E1S2_PET_P<3>_XF", "diff_pair_mate" : "E1S2_PET_N<3>_XF", "voltage" : "" }, "E1S0_PER_N<6>_XF" : { "voltage" : "", "diff_pair_mate" : "E1S0_PER_P<6>_XF", "net_name" : "E1S0_PER_N<6>_XF", "diff_pair_pol" : "NEG", "node_list" : [ "J1_E0_XF.A36", "U1_XF.G5" ] }, "PSU_3R3V_SDA" : { "net_name" : "PSU_3R3V_SDA", "voltage" : "3.3V", "node_list" : [ "J4.2", "Q11.3", "R24.2" ] }, "E1S2_3R3V_PERST_CLKREQ_F<1>_XF" : { "node_list" : [ "J1_E2_XF.A11", "R7_E2_XF.2", "U1_XF.P17" ], "net_name" : "E1S2_3R3V_PERST_CLKREQ_F<1>_XF", "voltage" : "3.3V" }, "UNNAMED_7_SM050TP_I165_1_CPLD" : { "node_list" : [ "TP5_CPLD.1", "U1_CPLD.B5" ], "voltage" : "", "net_name" : "UNNAMED_7_SM050TP_I165_1_CPLD" }, "C0_DDR4_ADR<11>_XF" : { "node_list" : [ "J1_XF.210", "U1_XF.CA21" ], "voltage" : "", "net_name" : "C0_DDR4_ADR<11>_XF" }, "E1S3_PER_P<7>_XF" : { "diff_pair_pol" : "POS", "net_name" : "E1S3_PER_P<7>_XF", "diff_pair_mate" : "E1S3_PER_N<7>_XF", "voltage" : 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"diff_pair_pol" : "POS", "diff_pair_mate" : "E1S2_PET_N<6>_XF", "net_name" : "E1S2_PET_P<6>_XF", "node_list" : [ "C149_XF.2", "J1_E2_XF.B37" ] }, "E1S0_PER_N<3>_XF" : { "node_list" : [ "J1_E0_XF.A26", "U1_XF.D3" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "E1S0_PER_N<3>_XF", "diff_pair_mate" : "E1S0_PER_P<3>_XF" }, "E1S1_3R3V_SCL_XF" : { "node_list" : [ "J1_E1_XF.A7", "R184_XF.2", "R3_E1_XF.2", "U1_XF.AG19" ], "voltage" : "3.3V", "net_name" : "E1S1_3R3V_SCL_XF" }, "UNNAMED_7_SM050TP_I159_1_CPLD" : { "voltage" : "", "net_name" : "UNNAMED_7_SM050TP_I159_1_CPLD", "node_list" : [ "TP13_CPLD.1", "U1_CPLD.T2" ] }, "AC_E1S2_PET_N<0>_XF" : { "node_list" : [ "C173_XF.1", "U1_XF.W10" ], "voltage" : "", "net_name" : "AC_E1S2_PET_N<0>_XF", "diff_pair_mate" : "AC_E1S2_PET_P<0>_XF", "diff_pair_pol" : "NEG" }, "UNNAMED_4_LT3071_I30_EN_FL" : { "node_list" : [ "R27_FL_XF.1", "U6_FL_XF.28" ], "net_name" : "UNNAMED_4_LT3071_I30_EN_FL", "voltage" : "" }, "UNNAMED_20_NMOSFETVMT3_I8_G" : { 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"voltage" : "", "node_list" : [ "C357_XF.1", "U5_XF.27" ] }, "UNNAMED_3_LTC2975_I168_ASEL0_SP" : { "node_list" : [ "R19_SP_XF.2", "R21_SP_XF.2", "U1_SP_XF.35" ], "net_name" : "UNNAMED_3_LTC2975_I168_ASEL0_SP", "voltage" : "" }, "OCL1_PET_P<3>_XF" : { "node_list" : [ "C181_XF.2", "J1_O1_XF.B18" ], "diff_pair_pol" : "POS", "net_name" : "OCL1_PET_P<3>_XF", "diff_pair_mate" : "OCL1_PET_N<3>_XF", "voltage" : "" }, "C3_RDIMM_DQS_C<3>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "C3_RDIMM_DQS_C<3>_XF", "diff_pair_mate" : "C3_RDIMM_DQS_T<3>_XF", "node_list" : [ "J4_XF.185", "U1_XF.G21" ] }, "OCL0_3R3V_PERST_F_XF" : { "net_name" : "OCL0_3R3V_PERST_F_XF", "voltage" : "3.3V", "node_list" : [ "J1_O0_XF.A12", "U1_XF.BM20" ] }, "POK_OD_AVCC_SW_P<0>" : { "node_list" : [ "PM2_SP_XF.H8", "U1_CPLD.N11" ], "voltage" : "", "net_name" : "POK_OD_AVCC_SW_P<0>" }, "C0_DDR4_DQ<57>_XF" : { "node_list" : [ "J1_XF.275", "U1_XF.BH26" ], "net_name" : "C0_DDR4_DQ<57>_XF", "voltage" : "" }, "DDR4_SYS_CLK_P<2>_XF" : { "diff_pair_pol" : "POS", "diff_pair_mate" : "DDR4_SYS_CLK_N<2>_XF", "net_name" : "DDR4_SYS_CLK_P<2>_XF", "voltage" : "", "node_list" : [ "C364_XF.1", "U6_XF.12" ] }, "AC_CONN_CLK_REFP<1>_2" : { "diff_pair_pol" : "POS", "net_name" : "AC_CONN_CLK_REFP<1>_2", "diff_pair_mate" : "AC_CONN_CLK_REFN<1>_2", "voltage" : "", "node_list" : [ "C20_E3_XF.1", "U1_E3_XF.17" ] }, "LTC2975_CPLD_ENB_C" : { "node_list" : [ "U1_CPLD.L12", "U1_SP_XF.5" ], "voltage" : "", "net_name" : "LTC2975_CPLD_ENB_C" }, "SGND_PM4_SP" : { "node_list" : [ "C20_SP_XF.2", "C4_SP_XF.1", "C6_SP_XF.2", "C71_SP_XF.1", "NS7_SP_XF.2", "PM4_SP_XF.C7", "PM4_SP_XF.D6", "PM4_SP_XF.F6", "PM4_SP_XF.F7", "PM4_SP_XF.G6", "PM4_SP_XF.G7", "R12_SP_XF.1", "R2_SP_XF.1", "R4_SP_XF.1", "R63_SP_XF.1" ], "voltage" : "0V", "net_name" : "SGND_PM4_SP" }, "E1S2_PER_N<7>_XF" : { "net_name" : "E1S2_PER_N<7>_XF", "diff_pair_mate" : "E1S2_PER_P<7>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "J1_E2_XF.A39", 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"SDA_P1" : { "node_list" : [ "J1_P1_XF.A10" ], "net_name" : "SDA_P1", "voltage" : "" }, "SI5341_RST_N" : { "node_list" : [ "U1.6", "U1_CPLD.E2" ], "net_name" : "SI5341_RST_N", "voltage" : "" }, "AC_OCL2_CONN_REFCLK_N_XF" : { "node_list" : [ "C388_XF.1", "U5_XF.14" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "AC_OCL2_CONN_REFCLK_N_XF", "diff_pair_mate" : "AC_OCL2_CONN_REFCLK_P_XF" }, "C0_RDIMM_DQS_T<9>_XF" : { "diff_pair_mate" : "C0_RDIMM_DQS_C<9>_XF", "net_name" : "C0_RDIMM_DQS_T<9>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "J1_XF.7", "U1_XF.CB23" ] }, "UNNAMED_17_BYPASSCAPNPOL_I57_B_XF" : { "node_list" : [ "C140_XF.2", "R81_XF.2", "U1_XF.CC37" ], "net_name" : "UNNAMED_17_BYPASSCAPNPOL_I57_B_XF", "voltage" : "" }, "UNNAMED_7_LTM4671_I87_COMP0A_SP" : { "voltage" : "0V", "net_name" : "UNNAMED_7_LTM4671_I87_COMP0A_SP", "node_list" : [ "PM1_SP_XF.H10", "PM1_SP_XF.H11" ] }, "INTVCC_4650_TL_SP" : { "net_name" : "INTVCC_4650_TL_SP", "voltage" : "5", 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"net_name" : "C0_DDR4_DQ<8>_XF", "node_list" : [ "J1_XF.16", "U1_XF.CC28" ] }, "AC_E1S1_PET_N<0>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_E1S1_PET_P<0>_XF", "net_name" : "AC_E1S1_PET_N<0>_XF", "node_list" : [ "C137_XF.1", "U1_XF.P8" ] }, "UNNAMED_4_PI6CB33401_I37_OE2F_E1" : { "node_list" : [ "R2_E1_XF.2", "U1_E1_XF.24", "U1_E1_XF.29" ], "voltage" : "", "net_name" : "UNNAMED_4_PI6CB33401_I37_OE2F_E1" }, "FP_JT_VREF" : { "node_list" : [ "C15.2", "J5.17", "R41.2" ], "voltage" : "", "net_name" : "FP_JT_VREF" }, "OCL0_PET_N<3>_XF" : { "node_list" : [ "C258_XF.2", "J1_O0_XF.B19" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "OCL0_PET_N<3>_XF", "diff_pair_mate" : "OCL0_PET_P<3>_XF" }, "PWR_NDIMM_VTT_XF" : { "node_list" : [ "C36_ND_XF.1", "C37_ND_XF.1", "C38_ND_XF.1", "C44_ND_XF.1", "J3_XF.221", "J3_XF.77", "J4_XF.221", "J4_XF.77", "NS3_ND_XF.1", "R92_XF.1", "U2_ND_XF.3" ], "voltage" : "0.6", "net_name" : "PWR_NDIMM_VTT_XF" }, "UNNAMED_3_LTC2975_I168_FAULT0F_SP" : { "net_name" : "UNNAMED_3_LTC2975_I168_FAULT0F_SP", "voltage" : "", "node_list" : [ "R119_SP_XF.2", "U1_SP_XF.25" ] }, "UNNAMED_21_RESISTOR_I25_B_XF" : { "node_list" : [ "R115_XF.2", "U1_XF.T47" ], "net_name" : "UNNAMED_21_RESISTOR_I25_B_XF", "voltage" : "" }, "C0_RDIMM_DQS_T<3>_XF" : { "voltage" : "", "diff_pair_mate" : "C0_RDIMM_DQS_C<3>_XF", "net_name" : "C0_RDIMM_DQS_T<3>_XF", "diff_pair_pol" : "POS", "node_list" : [ "J1_XF.186", "U1_XF.BT23" ] }, "SCL_P1" : { "net_name" : "SCL_P1", "voltage" : "", "node_list" : [ "J1_P1_XF.A9" ] }, "RFU_<2>_E2" : { "net_name" : "RFU_<2>_E2", "voltage" : "", "node_list" : [ "J1_E2_XF.B8" ] }, "C3_RDIMM_DQS_C<9>_XF" : { "diff_pair_pol" : "NEG", "net_name" : "C3_RDIMM_DQS_C<9>_XF", "diff_pair_mate" : "C3_RDIMM_DQS_T<9>_XF", "voltage" : "", "node_list" : [ "J4_XF.8", "U1_XF.K15" ] }, "UNNAMED_7_BYPASSCAPNPOL_I64_B_SP" : { "node_list" : [ "C107_SP_XF.2", "PM1_SP_XF.K9", "R111_SP_XF.2", "R117_SP_XF.2" ], "net_name" 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"diff_pair_pol" : "POS", "voltage" : "" }, "AC_PCIE0_TXP<5>_XF" : { "node_list" : [ "C36_XF.1", "U1_XF.BA11" ], "diff_pair_pol" : "POS", "diff_pair_mate" : "AC_PCIE0_TXN<5>_XF", "net_name" : "AC_PCIE0_TXP<5>_XF", "voltage" : "" }, "BP_TYPE_P0" : { "net_name" : "BP_TYPE_P0", "voltage" : "", "node_list" : [ "J1_P0_XF.B9" ] }, "OCL1_PER_N<2>_XF" : { "node_list" : [ "J1_O1_XF.A16", "U1_XF.BT3" ], "diff_pair_pol" : "NEG", "net_name" : "OCL1_PER_N<2>_XF", "diff_pair_mate" : "OCL1_PER_P<2>_XF", "voltage" : "" }, "C2_DDR4_DQ<56>_XF" : { "node_list" : [ "J3_XF.130", "U1_XF.L51" ], "net_name" : "C2_DDR4_DQ<56>_XF", "voltage" : "" }, "C3_DDR4_SA<0>_XF" : { "net_name" : "C3_DDR4_SA<0>_XF", "voltage" : "", "node_list" : [ "J4_XF.139", "R15_XF.2" ] }, "VS_AVTT_RS_LIN_FL" : { "node_list" : [ "NS5_FL_XF.2", "R4_FL_XF.1", "U2_FL_XF.19" ], "voltage" : "", "net_name" : "VS_AVTT_RS_LIN_FL" }, "C0_RDIMM_DQS_T<7>_XF" : { "node_list" : [ "J1_XF.278", "U1_XF.BJ27" ], "diff_pair_pol" : "POS", "net_name" : "C0_RDIMM_DQS_T<7>_XF", "diff_pair_mate" : "C0_RDIMM_DQS_C<7>_XF", "voltage" : "" }, "C1_DDR4_DQ<67>_XF" : { "node_list" : [ "J2_XF.201", "U1_XF.BP59" ], "net_name" : "C1_DDR4_DQ<67>_XF", "voltage" : "" }, "C3_DDR4_CK_C<0>_XF" : { "node_list" : [ "J4_XF.75", "U1_XF.N26" ], "diff_pair_pol" : "NEG", "net_name" : "C3_DDR4_CK_C<0>_XF", "diff_pair_mate" : "C3_DDR4_CK_T<0>_XF", "voltage" : "" }, "AC_OCL0_PET_P<3>_XF" : { "diff_pair_pol" : "POS", "net_name" : "AC_OCL0_PET_P<3>_XF", "diff_pair_mate" : "AC_OCL0_PET_N<3>_XF", "voltage" : "", "node_list" : [ "C176_XF.1", "U1_XF.CA11" ] }, "C2_DDR4_DQ<41>_XF" : { "node_list" : [ "J3_XF.253", "U1_XF.A53" ], "voltage" : "", "net_name" : "C2_DDR4_DQ<41>_XF" }, "UNNAMED_7_LTM4671_I37_FB1_SP" : { "voltage" : "", "net_name" : "UNNAMED_7_LTM4671_I37_FB1_SP", "node_list" : [ "C137_SP_XF.2", "PM1_SP_XF.H9", "R72_SP_XF.2" ] }, "PCIE1_RXP<6>_XF" : { "node_list" : [ "J2_P1_XF.A15", "U1_XF.AU2" ], "diff_pair_pol" : "POS", "diff_pair_mate" : "PCIE1_RXN<6>_XF", "net_name" : "PCIE1_RXP<6>_XF", "voltage" : "" }, "C0_RDIMM_DQS_C<16>_XF" : { "net_name" : "C0_RDIMM_DQS_C<16>_XF", "diff_pair_mate" : "C0_RDIMM_DQS_T<16>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "J1_XF.133", "U1_XF.BH28" ] }, "UNNAMED_11_LTM4650FIXED_I150_CLKOUT_SP" : { "net_name" : "UNNAMED_11_LTM4650FIXED_I150_CLKOUT_SP", "voltage" : "", "node_list" : [ "PM7_SP_XF.G5", "R136_SP_XF.1" ] }, "E1S3_PER_P<2>_XF" : { "voltage" : "", "net_name" : "E1S3_PER_P<2>_XF", "diff_pair_mate" : "E1S3_PER_N<2>_XF", "diff_pair_pol" : "POS", "node_list" : [ "J1_E3_XF.A24", "U1_XF.AH4" ] }, "UNNAMED_9_LT3071_I30_IMON_FL" : { "node_list" : [ "IMON_VCCAUX_A_TP_FL_XF.1", "R90_FL_XF.2", "U7_FL_XF.21" ], "voltage" : "", "net_name" : "UNNAMED_9_LT3071_I30_IMON_FL" }, "C2_DDR4_BG<1>_XF" : { "node_list" : [ "J3_XF.207", "U1_XF.M55" ], "net_name" : "C2_DDR4_BG<1>_XF", "voltage" : "" }, "OCL0_3R3V_CWAKE_F_XF" : { "node_list" : [ "J1_O0_XF.B10", "U1_XF.BM18" ], "net_name" : "OCL0_3R3V_CWAKE_F_XF", "voltage" : "3.3V" }, "E1S3_FPGA_REFCLK_N<1>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "E1S3_FPGA_REFCLK_P<1>_XF", "net_name" : "E1S3_FPGA_REFCLK_N<1>_XF", "node_list" : [ "C22_E3_XF.2", "R191_XF.2", "R201_XF.2", "R202_XF.1", "U1_XF.AN14" ] }, "C1_DDR4_DQ<49>_XF" : { "node_list" : [ "J2_XF.264", "U1_XF.BM58" ], "net_name" : "C1_DDR4_DQ<49>_XF", "voltage" : "" }, "UNNAMED_8_LT3071_I30_V00_FL" : { "net_name" : "UNNAMED_8_LT3071_I30_V00_FL", "voltage" : "", "node_list" : [ "R17_FL_XF.2", "R54_FL_XF.1", "U5_FL_XF.23" ] }, "AC_E1S2_PET_P<3>_XF" : { "node_list" : [ "C152_XF.1", "U1_XF.U11" ], "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "AC_E1S2_PET_P<3>_XF", "diff_pair_mate" : "AC_E1S2_PET_N<3>_XF" }, "UNNAMED_9_LED_I13_A_CPLD" : { "node_list" : [ "D5_CPLD.2", "R116_CPLD.1" ], "net_name" : "UNNAMED_9_LED_I13_A_CPLD", "voltage" : "" }, "C1_DDR4_DQ<37>_XF" : { "node_list" : [ "J2_XF.240", "U1_XF.BU63" ], "voltage" : "", "net_name" : "C1_DDR4_DQ<37>_XF" }, "C1_RDIMM_DQS_T<13>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "C1_RDIMM_DQS_T<13>_XF", "diff_pair_mate" : "C1_RDIMM_DQS_C<13>_XF", "node_list" : [ "J2_XF.99", "U1_XF.BV61" ] }, "PCIE0_RXN<7>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "PCIE0_RXP<7>_XF", "net_name" : "PCIE0_RXN<7>_XF", "node_list" : [ "J2_P0_XF.A19", "U1_XF.BC1" ] }, "E1S1_PET_N<5>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "E1S1_PET_N<5>_XF", "diff_pair_mate" : "E1S1_PET_P<5>_XF", "node_list" : [ "C132_XF.2", "J1_E1_XF.B33" ] }, "AC_OCL3_PET_N<0>_XF" : { "node_list" : [ "C281_XF.1", "U1_XF.BJ10" ], "diff_pair_mate" : "AC_OCL3_PET_P<0>_XF", "net_name" : "AC_OCL3_PET_N<0>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "C0_DDR4_DQ<52>_XF" : { "node_list" : [ "J1_XF.117", "U1_XF.BK23" ], "voltage" : "", "net_name" : "C0_DDR4_DQ<52>_XF" }, "BASE_1R8V_SCL" : { "voltage" : "1.8V", "net_name" : "BASE_1R8V_SCL", "node_list" : [ "Q3.2", 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"CLKIN_P_E2" : { "diff_pair_pol" : "POS", "net_name" : "CLKIN_P_E2", "diff_pair_mate" : "CLKIN_N_E2", "voltage" : "", "node_list" : [ "C16_E2_XF.2", "R14_E2_XF.2", "R16_E2_XF.1", "R17_E2_XF.1", "U1_E2_XF.5" ] }, "C3_RDIMM_DQS_T<9>_XF" : { "diff_pair_mate" : "C3_RDIMM_DQS_C<9>_XF", "net_name" : "C3_RDIMM_DQS_T<9>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "J4_XF.7", "U1_XF.L15" ] }, "PCIE0_TXN<2>_XF" : { "node_list" : [ "C84_XF.2", "J1_P0_XF.B16" ], "diff_pair_mate" : "PCIE0_TXP<2>_XF", "net_name" : "PCIE0_TXN<2>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "C1_DDR4_DQ<7>_XF" : { "node_list" : [ "J2_XF.155", "U1_XF.BL51" ], "net_name" : "C1_DDR4_DQ<7>_XF", "voltage" : "" }, "AC_PCIE1_TXN<5>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "AC_PCIE1_TXN<5>_XF", "diff_pair_mate" : "AC_PCIE1_TXP<5>_XF", "node_list" : [ "C44_XF.1", "U1_XF.AR10" ] }, "DIMM_EVENT_OD_F<2>" : { "node_list" : [ "J3_XF.78", "U1_CPLD.K13" ], "net_name" : "DIMM_EVENT_OD_F<2>", "voltage" : "" }, "C3_RDIMM_DQS_C<11>_XF" : { "diff_pair_mate" : "C3_RDIMM_DQS_T<11>_XF", "net_name" : "C3_RDIMM_DQS_C<11>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "J4_XF.30", "U1_XF.E27" ] }, "C2_DDR4_CS_N<2>_XF" : { "node_list" : [ "J3_XF.93", "U1_XF.J55" ], "net_name" : "C2_DDR4_CS_N<2>_XF", "voltage" : "" }, "AC_E1S0_PET_N<3>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "AC_E1S0_PET_P<3>_XF", "net_name" : "AC_E1S0_PET_N<3>_XF", "node_list" : [ "C126_XF.1", "U1_XF.A6" ] }, "UNNAMED_3_LTM4675_I40_COMP0B_ND" : { "node_list" : [ "PM4_ND_XF.D6", "PM4_ND_XF.J6", "R108_ND_XF.1", "R109_ND_XF.1", "R111_ND_XF.2" ], "net_name" : "UNNAMED_3_LTM4675_I40_COMP0B_ND", "voltage" : "0V" }, "TS_1428_SPARE_N_SP" : { "node_list" : [ "TS_SP_N_SP_XF.1", "U4_SP_XF.14" ], "net_name" : "TS_1428_SPARE_N_SP", "diff_pair_mate" : "TS_1428_SPARE_P_SP", "diff_pair_pol" : "NEG", "voltage" : "" }, "C2_DDR4_DQ<45>_XF" : { "net_name" : "C2_DDR4_DQ<45>_XF", "voltage" : "", "node_list" : [ "J3_XF.251", "U1_XF.D54" ] }, "UNNAMED_3_LTM4675_I40_VTRIM0CFG_SD" : { "net_name" : "UNNAMED_3_LTM4675_I40_VTRIM0CFG_SD", "voltage" : "", "node_list" : [ "PM4_SD_XF.H3", "R6_SD_XF.2" ] }, "E1S3_3R3V_PERST_CLKREQ_F<1>_XF" : { "net_name" : "E1S3_3R3V_PERST_CLKREQ_F<1>_XF", "voltage" : "3.3V", "node_list" : [ "J1_E3_XF.A11", "R7_E3_XF.2", "U1_XF.T21" ] }, "UNNAMED_3_BYPASSCAPNPOL_I149_A_SP" : { "node_list" : [ "C40_SP_XF.1", "R52_SP_XF.1", "U1_SP_XF.41" ], "voltage" : "", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I149_A_SP" }, "UNNAMED_9_LUMEXRGBLED_I91_GREENK_CPLD" : { "node_list" : [ "D3_CPLD.4", "R22_CPLD.1" ], "net_name" : "UNNAMED_9_LUMEXRGBLED_I91_GREENK_CPLD", "voltage" : "" }, "AC_OCL2_PET_N<3>_XF" : { "net_name" : "AC_OCL2_PET_N<3>_XF", "diff_pair_mate" : "AC_OCL2_PET_P<3>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "C274_XF.1", "U1_XF.BK8" ] }, "UNNAMED_3_LT3071_I32_V02_FL" : { "net_name" : "UNNAMED_3_LT3071_I32_V02_FL", "voltage" : "", "node_list" : [ "R45_FL_XF.1", "R47_FL_XF.2", "U3_FL_XF.25" ] }, "UNNAMED_7_SM050TP_I158_1_CPLD" : { "voltage" : "", "net_name" : "UNNAMED_7_SM050TP_I158_1_CPLD", "node_list" : [ "TP16_CPLD.1", "U1_CPLD.R3" ] }, "E1S3_PER_N<1>_XF" : { "node_list" : [ "J1_E3_XF.A20", "U1_XF.AJ1" ], "diff_pair_mate" : "E1S3_PER_P<1>_XF", "net_name" : "E1S3_PER_N<1>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "UNNAMED_4_PI6CB33401_I37_OE2F_E2" : { "net_name" : "UNNAMED_4_PI6CB33401_I37_OE2F_E2", "voltage" : "", "node_list" : [ "R2_E2_XF.2", "U1_E2_XF.24", "U1_E2_XF.29" ] }, "UNNAMED_4_PI6CB33401_I37_SCLK_E0" : { "node_list" : [ "R11_E0_XF.2", "U1_E0_XF.9" ], "voltage" : "", "net_name" : "UNNAMED_4_PI6CB33401_I37_SCLK_E0" }, "UNNAMED_8_LT3071_I30_EN_FL" : { "net_name" : "UNNAMED_8_LT3071_I30_EN_FL", "voltage" : "", "node_list" : [ "R34_FL_XF.1", "U5_FL_XF.28" ] }, "C0_RDIMM_DQS_C<3>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "C0_RDIMM_DQS_C<3>_XF", "diff_pair_mate" : "C0_RDIMM_DQS_T<3>_XF", "node_list" : [ "J1_XF.185", "U1_XF.BT22" ] }, "SW1_4650_TR_SP" : { "voltage" : "12", "net_name" : "SW1_4650_TR_SP", "node_list" : [ "PM5_SP_XF.G2" ] }, "C3_DDR4_DQ<57>_XF" : { "node_list" : [ "J4_XF.275", "U1_XF.A20" ], "net_name" : "C3_DDR4_DQ<57>_XF", "voltage" : "" }, "AC_E1S3_PET_P<0>_XF" : { "node_list" : [ "C343_XF.1", "U1_XF.AH13" ], "diff_pair_pol" : "POS", "diff_pair_mate" : "AC_E1S3_PET_N<0>_XF", "net_name" : "AC_E1S3_PET_P<0>_XF", "voltage" : "" }, "C2_DDR4_DQ<24>_XF" : { "voltage" : "", "net_name" : "C2_DDR4_DQ<24>_XF", "node_list" : [ "J3_XF.38", "U1_XF.L52" ] }, "OCL1_PER_P<1>_XF" : { "diff_pair_pol" : "POS", "diff_pair_mate" : "OCL1_PER_N<1>_XF", "net_name" : "OCL1_PER_P<1>_XF", "voltage" : "", "node_list" : [ "J1_O1_XF.A6", "U1_XF.BU2" ] }, "UNNAMED_7_SM050TP_I163_1_CPLD" : { "node_list" : [ "TP3_CPLD.1", "U1_CPLD.B4" ], "net_name" : "UNNAMED_7_SM050TP_I163_1_CPLD", "voltage" : "" }, "C3_DDR4_ADR<12>_XF" : { "net_name" : "C3_DDR4_ADR<12>_XF", "voltage" : "", "node_list" : [ "J4_XF.65", "U1_XF.T26" ] }, "PSU_1R8V_SCL" : { "net_name" : "PSU_1R8V_SCL", "voltage" : "1.8V", "node_list" : [ "Q10.2", "R9.1", "U1_XF.CA35" ] }, "UNNAMED_3_BYPASSCAPNPOL_I31_B_FL" : { "voltage" : "", "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I31_B_FL", "node_list" : [ "C66_FL_XF.2", "R11_FL_XF.2", "R12_FL_XF.1" ] }, "C1_RDIMM_DQS_C<13>_XF" : { "node_list" : [ "J2_XF.100", "U1_XF.BV62" ], "diff_pair_mate" : "C1_RDIMM_DQS_T<13>_XF", "net_name" : "C1_RDIMM_DQS_C<13>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "LTC2975_CPLD_ENB_A" : { "voltage" : "", "net_name" : "LTC2975_CPLD_ENB_A", "node_list" : [ "U1_CPLD.K15", "U1_SP_XF.3" ] }, "UNNAMED_3_RESISTOR_I70_B_E1" : { "voltage" : "", "net_name" : "UNNAMED_3_RESISTOR_I70_B_E1", "node_list" : [ "J1_E1_XF.MH1", "J1_E1_XF.MH2", "J1_E1_XF.MH3", "R1_E1_XF.2" ] }, "CPLD_FPGA_DQ<0>" : { "voltage" : "", "net_name" : "CPLD_FPGA_DQ<0>", "node_list" : [ "U1_CPLD.B10", "U1_XF.BV34" ] }, "DP4_DN<5>_SP" : { "net_name" : "DP4_DN<5>_SP", "voltage" : "", "node_list" : [ "PM1_SP_XF.A7", "PM1_SP_XF.W7", "U4_SP_XF.10" ] }, "C0_DDR4_ADR<17>_XF" : { "node_list" : [ "J1_XF.234" ], "voltage" : "", "net_name" : "C0_DDR4_ADR<17>_XF" }, "AC_OCL1_PET_P<0>_XF" : { "voltage" : "", "diff_pair_mate" : "AC_OCL1_PET_N<0>_XF", "net_name" : "AC_OCL1_PET_P<0>_XF", "diff_pair_pol" : "POS", "node_list" : [ "C232_XF.1", "U1_XF.CA7" ] }, "UNNAMED_4_PI6CB33401_I37_SDATA_E0" : { "net_name" : "UNNAMED_4_PI6CB33401_I37_SDATA_E0", "voltage" : "", "node_list" : [ "R9_E0_XF.2", "U1_E0_XF.10" ] }, "C1_DDR4_CKE<0>_XF" : { "node_list" : [ "J2_XF.60", "U1_XF.CB50" ], "net_name" : "C1_DDR4_CKE<0>_XF", "voltage" : "" }, "C1_DDR4_DQ<5>_XF" : { "node_list" : [ "J2_XF.148", "U1_XF.BN49" ], "net_name" : "C1_DDR4_DQ<5>_XF", "voltage" : "" }, "PCIE1_TXP<0>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "net_name" : "PCIE1_TXP<0>_XF", "diff_pair_mate" : "PCIE1_TXN<0>_XF", "node_list" : [ "C33_XF.2", "J1_P1_XF.B3" ] }, "C3_DDR4_DQ<0>_XF" : { "voltage" : "", "net_name" : "C3_DDR4_DQ<0>_XF", "node_list" : [ "J4_XF.5", "U1_XF.L17" ] }, "SW1_4650_BL_SP" : { "node_list" : [ "PM3_SP_XF.G2" ], "voltage" : "12", "net_name" : "SW1_4650_BL_SP" }, "SI5341_INTR" : { "voltage" : "", "net_name" : "SI5341_INTR", "node_list" : [ "R434.2", "U1_CPLD.C1" ] }, "OCL0_PET_N<0>_XF" : { "net_name" : "OCL0_PET_N<0>_XF", "diff_pair_mate" : "OCL0_PET_P<0>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "C266_XF.2", "J1_O0_XF.B4" ] }, "AC_PCIE1_REFN_XF" : { "voltage" : "", "diff_pair_mate" : "AC_PCIE1_REFP_XF", "net_name" : "AC_PCIE1_REFN_XF", "diff_pair_pol" : "NEG", "node_list" : [ "C231_XF.2", "U1_XF.AU14" ] }, "UNNAMED_20_MLXKK1004PINBOSS_I26_P4" : { "node_list" : [ "P4.4", "Q7.3" ], "net_name" : "UNNAMED_20_MLXKK1004PINBOSS_I26_P4", "voltage" : "" }, "SW0_NODE_SD" : { "node_list" : [ "PM4_SD_XF.B8" ], "net_name" : "SW0_NODE_SD", "voltage" : "12" }, "OCL2_PER_P<0>_XF" : { "diff_pair_pol" : "POS", "net_name" : "OCL2_PER_P<0>_XF", "diff_pair_mate" : "OCL2_PER_N<0>_XF", "voltage" : "", "node_list" : [ "J1_O2_XF.A3", "U1_XF.BM4" ] }, "C1_DDR4_DQ<42>_XF" : { "node_list" : [ "J2_XF.115", "U1_XF.BL60" ], "net_name" : "C1_DDR4_DQ<42>_XF", "voltage" : "" }, "C1_SYS_CLK_N_XF" : { "voltage" : "", "net_name" : "C1_SYS_CLK_N_XF", "diff_pair_mate" : "C1_SYS_CLK_P_XF", "diff_pair_pol" : "NEG", "node_list" : [ "C363_XF.2", "R150_XF.2", "R243_XF.2", "R244_XF.1", "U1_XF.BY55" ] }, "CPLD_FPGA_DQ<1>" : { "node_list" : [ "U1_CPLD.E10", "U1_XF.BV33" ], "voltage" : "", "net_name" : "CPLD_FPGA_DQ<1>" }, "UNNAMED_6_BYPASSCAPNPOL_I31_A_FL" : { "node_list" : [ "C38_FL_XF.1", "U2_FL_XF.3" ], "net_name" : "UNNAMED_6_BYPASSCAPNPOL_I31_A_FL", "voltage" : "" }, "E1S3_PET_N<4>_XF" : { "node_list" : [ "C310_XF.2", "J1_E3_XF.B30" ], "diff_pair_mate" : "E1S3_PET_P<4>_XF", "net_name" : "E1S3_PET_N<4>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "E1S1_FPGA_REFCLK_N<0>_XF" : { "node_list" : [ "C23_E1_XF.2", "R169_XF.2", "R180_XF.2", "R181_XF.1", "U1_XF.P12" ], "diff_pair_mate" : "E1S1_FPGA_REFCLK_P<0>_XF", "net_name" : "E1S1_FPGA_REFCLK_N<0>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "RGB_LED_GREEN<0>_CPLD" : { "voltage" : "", "net_name" : "RGB_LED_GREEN<0>_CPLD", "node_list" : [ "R25_CPLD.2", "U1_CPLD.E8" ] }, "C1_DDR4_BA<1>_XF" : { "net_name" : "C1_DDR4_BA<1>_XF", "voltage" : "", "node_list" : [ "J2_XF.224", "U1_XF.CA58" ] }, "VDD_VS_P_ND" : { "diff_pair_pol" : "POS", "diff_pair_mate" : "VDD_VS_N_ND", "net_name" : "VDD_VS_P_ND", "voltage" : "", "node_list" : [ "NS2_ND_XF.2", "PM4_ND_XF.D7", "PM4_ND_XF.J7" ] }, "C0_RDIMM_DQS_T<16>_XF" : { "diff_pair_mate" : "C0_RDIMM_DQS_C<16>_XF", "net_name" : "C0_RDIMM_DQS_T<16>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "J1_XF.132", "U1_XF.BH29" ] }, "C0_DDR4_DQ<59>_XF" : { "node_list" : [ "J1_XF.282", "U1_XF.BH27" ], "voltage" : "", "net_name" : "C0_DDR4_DQ<59>_XF" }, "DN4_DP<5>_SP" : { "node_list" : [ "PM1_SP_XF.A6", "PM1_SP_XF.W6", "U4_SP_XF.9" ], "net_name" : "DN4_DP<5>_SP", "voltage" : "" }, "C3_DDR4_DQ<18>_XF" : { "node_list" : [ "J4_XF.34", "U1_XF.E25" ], "voltage" : "", "net_name" : "C3_DDR4_DQ<18>_XF" }, "PM2_SP_AGND_SP" : { "node_list" : [ "C131_SP_XF.1", "C132_SP_XF.1", "C133_SP_XF.1", "C134_SP_XF.1", "C81_SP_XF.1", "C82_SP_XF.1", "C83_SP_XF.1", "C84_SP_XF.1", "C85_SP_XF.1", "C86_SP_XF.1", "C87_SP_XF.1", "NS2_SP_XF.1", "R41_SP_XF.1", "R43_SP_XF.1", "R53_SP_XF.1", "R76_SP_XF.1", "R77_SP_XF.1", "R79_SP_XF.1", "R81_SP_XF.1", "R83_SP_XF.1", "R97_SP_XF.1" ], "voltage" : "0V", "net_name" : "PM2_SP_AGND_SP" }, "C0_RDIMM_DQS_C<7>_XF" : { "node_list" : [ "J1_XF.277", "U1_XF.BJ26" ], "diff_pair_mate" : "C0_RDIMM_DQS_T<7>_XF", "net_name" : "C0_RDIMM_DQS_C<7>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "STAT_LED_ON_F<0>_CPLD" : { "voltage" : "", "net_name" : "STAT_LED_ON_F<0>_CPLD", "node_list" : [ "D1_CPLD.2", "U1_CPLD.A3" ] }, "C2_RDIMM_DQS_C<8>_XF" : { "voltage" : "", "net_name" : "C2_RDIMM_DQS_C<8>_XF", "diff_pair_mate" : "C2_RDIMM_DQS_T<8>_XF", "diff_pair_pol" : "NEG", "node_list" : [ "J3_XF.196", "U1_XF.B60" ] }, "C3_DDR4_DQ<52>_XF" : { "node_list" : [ "J4_XF.117", "U1_XF.E19" ], "voltage" : "", "net_name" : "C3_DDR4_DQ<52>_XF" }, "UNNAMED_3_RESISTOR_I56_B" : { "node_list" : [ "FPNL_CONN.7", "R44.2" ], "voltage" : "", "net_name" : "UNNAMED_3_RESISTOR_I56_B" }, "AC_E1S3_PET_N<6>_XF" : { "diff_pair_mate" : "AC_E1S3_PET_P<6>_XF", "net_name" : "AC_E1S3_PET_N<6>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "C175_XF.1", "U1_XF.AK8" ] }, "AC_PCIE1_TXP<3>_XF" : { "diff_pair_mate" : "AC_PCIE1_TXN<3>_XF", "net_name" : "AC_PCIE1_TXP<3>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "C30_XF.1", "U1_XF.AP9" ] }, "E1S3_PET_N<0>_XF" : { "diff_pair_pol" : "NEG", "net_name" : "E1S3_PET_N<0>_XF", "diff_pair_mate" : "E1S3_PET_P<0>_XF", "voltage" : "", "node_list" : [ "C314_XF.2", "J1_E3_XF.B17" ] }, "AC_E1S3_PET_P<7>_XF" : { "voltage" : "", "diff_pair_pol" : "POS", "diff_pair_mate" : "AC_E1S3_PET_N<7>_XF", "net_name" : "AC_E1S3_PET_P<7>_XF", "node_list" : [ "C235_XF.1", "U1_XF.AJ11" ] }, "UNNAMED_17_RESISTOR_I201_A_XF" : { "node_list" : [ "R10_XF.2", "R17_XF.1" ], "voltage" : "", "net_name" : "UNNAMED_17_RESISTOR_I201_A_XF" }, "CONN_CLK_REFP<1>_E2" : { "node_list" : [ "C20_E2_XF.2", "J1_E2_XF.A15" ], "diff_pair_pol" : "POS", "diff_pair_mate" : "CONN_CLK_REFN<1>_E2", "net_name" : "CONN_CLK_REFP<1>_E2", "voltage" : "" }, "AC_CONN_CLK_REFN<0>_1" : { "node_list" : [ "C25_E0_XF.1", "U1_E0_XF.14" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "AC_CONN_CLK_REFN<0>_1", "diff_pair_mate" : "AC_CONN_CLK_REFP<0>_1" }, "OCL1_PET_P<0>_XF" : { "net_name" : "OCL1_PET_P<0>_XF", "diff_pair_mate" : "OCL1_PET_N<0>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "C232_XF.2", "J1_O1_XF.B3" ] }, "CPLD_P3R3V" : { "net_name" : "CPLD_P3R3V", "voltage" : "3.3", "node_list" : [ "C12_CPLD.1", "C13_CPLD.1", "C13_MP.1", "C14_CPLD.1", "C14_MP.1", "C15_CPLD.2", "C45_CPLD.2", "C46_CPLD.2", "C47_CPLD.2", "C48_CPLD.2", "C4_CPLD.1", "C50_CPLD.2", "C51_CPLD.2", "C52_CPLD.2", "C53_CPLD.2", "C54_CPLD.2", "C5_CPLD.1", "C6_CPLD.1", "D2_CPLD.1", "D3_CPLD.1", "D4_CPLD.1", "L2_MP.2", "R116_CPLD.2", "R117_CPLD.2", "R118_CPLD.2", "R119_CPLD.2", "R13_MP.2", "R14_MP.1", "U1_CPLD.A1", "U1_CPLD.A16", "U1_CPLD.E13", "U1_CPLD.G10", "U1_CPLD.G7", "U1_CPLD.H10", "U1_CPLD.J10", "U1_CPLD.K10", "U1_CPLD.K7", "U1_CPLD.K8", "U1_CPLD.K9", "U1_CPLD.M13", "U1_CPLD.N12", "U1_CPLD.N5", "U1_CPLD.T1", "U1_CPLD.T16" ] }, "E1S3_3R3V_SMB_RST_F_XF" : { "net_name" : "E1S3_3R3V_SMB_RST_F_XF", "voltage" : "3.3V", "node_list" : [ "J1_E3_XF.A9", "R5_E3_XF.2", "U1_XF.U19" ] }, "C3_RDIMM_DQS_C<16>_XF" : { "node_list" : [ "J4_XF.133", "U1_XF.B15" ], "diff_pair_mate" : "C3_RDIMM_DQS_T<16>_XF", "net_name" : "C3_RDIMM_DQS_C<16>_XF", "diff_pair_pol" : "NEG", "voltage" : "" }, "UNNAMED_6_LT3071_I30_V01_FL" : { "node_list" : [ "R39_FL_XF.1", "R61_FL_XF.2", "U2_FL_XF.24" ], "net_name" : "UNNAMED_6_LT3071_I30_V01_FL", "voltage" : "" }, "UNNAMED_3_LTM4675_I40_VTRIM1CFG_ND" : { "net_name" : "UNNAMED_3_LTM4675_I40_VTRIM1CFG_ND", "voltage" : "", "node_list" : [ "PM4_ND_XF.H4", "R8_ND_XF.2" ] }, "C0_DDR4_SA<0>_XF" : { "voltage" : "", "net_name" : "C0_DDR4_SA<0>_XF", "node_list" : [ "J1_XF.139", "R19_XF.2" ] }, "C3_RDIMM_DQS_T<7>_XF" : { "voltage" : "", "diff_pair_mate" : "C3_RDIMM_DQS_C<7>_XF", "net_name" : "C3_RDIMM_DQS_T<7>_XF", "diff_pair_pol" : "POS", "node_list" : [ "J4_XF.278", "U1_XF.B19" ] }, "C0_DDR4_CK_C<0>_XF" : { "node_list" : [ "J1_XF.75", "U1_XF.BW16" ], "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "C0_DDR4_CK_C<0>_XF", "diff_pair_mate" : "C0_DDR4_CK_T<0>_XF" }, "UNNAMED_17_BYPASSCAPNPOL_I49_A_XF" : { "voltage" : "", "net_name" : "UNNAMED_17_BYPASSCAPNPOL_I49_A_XF", "node_list" : [ "C141_XF.1", "R82_XF.2", "U1_XF.BY38" ] }, "E1S_REF_CLK_N<3>" : { "net_name" : "E1S_REF_CLK_N<3>", "diff_pair_mate" : "E1S_REF_CLK_P<3>", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "C17_E3_XF.1", "U1.37" ] }, "PCIE1_RXP<4>_XF" : { "voltage" : "", "diff_pair_mate" : "PCIE1_RXN<4>_XF", "net_name" : "PCIE1_RXP<4>_XF", "diff_pair_pol" : "POS", "node_list" : [ "J2_P1_XF.A3", "U1_XF.AR6" ] }, "CPLD_FPGA_DCLK_1" : { "voltage" : "", "net_name" : "CPLD_FPGA_DCLK_1", "node_list" : [ "U1_CPLD.D10", "U1_XF.BL31" ] }, "C2_DDR4_DQ<28>_XF" : { "voltage" : "", "net_name" : "C2_DDR4_DQ<28>_XF", "node_list" : [ "J3_XF.36", "U1_XF.K52" ] }, "UNNAMED_12_LT3071_I30_V02_FL" : { "node_list" : [ "R101_FL_XF.2", "R98_FL_XF.1", "U10_FL_XF.25" ], "net_name" : "UNNAMED_12_LT3071_I30_V02_FL", "voltage" : "" }, "UNNAMED_3_RESISTOR_I70_B_E3" : { "node_list" : [ "J1_E3_XF.MH1", "J1_E3_XF.MH2", "J1_E3_XF.MH3", "R1_E3_XF.2" ], "voltage" : "", "net_name" : "UNNAMED_3_RESISTOR_I70_B_E3" }, "UNNAMED_6_LT3071_I30_PWRGD_FL" : { "voltage" : "", "net_name" : "UNNAMED_6_LT3071_I30_PWRGD_FL", "node_list" : [ "R18_FL_XF.1", "U2_FL_XF.2" ] }, "C3_DDR4_DQ<4>_XF" : { "node_list" : [ "J4_XF.3", "U1_XF.J15" ], "net_name" : "C3_DDR4_DQ<4>_XF", "voltage" : "" }, "PWR_AVTT_RLC_XF" : { "node_list" : [ "C27_FL_XF.1", "C467_XF.1", "C468_XF.1", "C469_XF.1", "C470_XF.1", "C471_XF.1", "C472_XF.1", "C52_FL_XF.1", "C53_FL_XF.1", "C54_FL_XF.1", "NS3_FL_XF.1", "R268_XF.1", "U1_FL_XF.15", "U1_FL_XF.16", "U1_FL_XF.17", "U1_FL_XF.18", "U1_XF.AL13", "U1_XF.AN13", "U1_XF.AN9", "U1_XF.AR13", "U1_XF.AR9", "U1_XF.AU13", "U1_XF.AU9", "U1_XF.AW13", "U1_XF.AW9", "U1_XF.BA9", "U1_XF.BB11", "U1_XF.BC9", "U1_XF.BD11", "U1_XF.BE15", "U1_XF.BE9", "U1_XF.BF11" ], "voltage" : "1.2", "net_name" : "PWR_AVTT_RLC_XF" }, "C0_RDIMM_DQS_T<11>_XF" : { "node_list" : [ "J1_XF.29", "U1_XF.BU18" ], "voltage" : "", "net_name" : "C0_RDIMM_DQS_T<11>_XF", "diff_pair_mate" : "C0_RDIMM_DQS_C<11>_XF", "diff_pair_pol" : "POS" }, "OCL2_PET_P<1>_XF" : { "diff_pair_pol" : "POS", "diff_pair_mate" : "OCL2_PET_N<1>_XF", "net_name" : "OCL2_PET_P<1>_XF", "voltage" : "", "node_list" : [ "C237_XF.2", "J1_O2_XF.B6" ] }, "C2_DDR4_DQ<53>_XF" : { "voltage" : "", "net_name" : "C2_DDR4_DQ<53>_XF", "node_list" : [ "J3_XF.262", "U1_XF.J50" ] }, "C0_DDR4_DQ<6>_XF" : { "node_list" : [ "J1_XF.10", "U1_XF.BY22" ], "net_name" : "C0_DDR4_DQ<6>_XF", "voltage" : "" }, "E1S3_3R3V_PRSNT_F<1>_XF" : { "node_list" : [ "J1_E3_XF.B42", "U1_XF.T18" ], "voltage" : "3.3V", "net_name" : "E1S3_3R3V_PRSNT_F<1>_XF" }, "UNNAMED_9_BYPASSCAPNPOL_I25_B_FL" : { "node_list" : [ "C75_FL_XF.2", "R77_FL_XF.2", "R81_FL_XF.1" ], "net_name" : "UNNAMED_9_BYPASSCAPNPOL_I25_B_FL", "voltage" : "" }, "C2_DDR4_ADR<16>_XF" : { "node_list" : [ "J3_XF.82", "U1_XF.J61" ], "net_name" : "C2_DDR4_ADR<16>_XF", "voltage" : "" }, "UNNAMED_3_RESISTOR_I28_B_MP" : { "voltage" : "", "net_name" : "UNNAMED_3_RESISTOR_I28_B_MP", "node_list" : [ "R10_MP.2", "U1_MP.8" ] }, "C1_DDR4_DQ<39>_XF" : { "node_list" : [ "J2_XF.247", "U1_XF.BU61" ], "voltage" : "", "net_name" : "C1_DDR4_DQ<39>_XF" }, "UNNAMED_22_RESISTOR_I42_B_XF" : { "net_name" : "UNNAMED_22_RESISTOR_I42_B_XF", "voltage" : "", "node_list" : [ "R61_XF.2", "U1_XF.BL25" ] }, "UNNAMED_17_BYPASSCAPNPOL_I107_A_XF" : { "voltage" : "", "net_name" : "UNNAMED_17_BYPASSCAPNPOL_I107_A_XF", "node_list" : [ "C267_XF.1", "R127_XF.1", "U1_XF.CB33" ] }, "EMC1428_ALERT_OD_F" : { "node_list" : [ "R126_SP_XF.1", "U1_CPLD.N7", "U4_SP_XF.7" ], "voltage" : "", "net_name" : "EMC1428_ALERT_OD_F" }, "C2_DDR4_ALERT_N_XF" : { "node_list" : [ "J3_XF.208", "R247_XF.2", "U1_XF.H57" ], "voltage" : "", "net_name" : "C2_DDR4_ALERT_N_XF" }, "C1_DDR4_DQ<47>_XF" : { "node_list" : [ "J2_XF.258", "U1_XF.BL62" ], "voltage" : "", "net_name" : "C1_DDR4_DQ<47>_XF" }, "POK_OD_VCCINT_BRSW_P<1>" : { "net_name" : "POK_OD_VCCINT_BRSW_P<1>", "voltage" : "", "node_list" : [ "R96_SP_XF.2", "U1_CPLD.R13" ] }, "C0_RDIMM_DQS_C<9>_XF" : { "net_name" : "C0_RDIMM_DQS_C<9>_XF", "diff_pair_mate" : "C0_RDIMM_DQS_T<9>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "J1_XF.8", "U1_XF.CC23" ] }, "UNNAMED_5_LTM4650FIXED_I78_PGOOD1_SP" : { "voltage" : "", "net_name" : "UNNAMED_5_LTM4650FIXED_I78_PGOOD1_SP", "node_list" : [ "PM5_SP_XF.G9", "R91_SP_XF.1" ] }, "C2_DDR4_DQ<61>_XF" : { "node_list" : [ "J3_XF.273", "U1_XF.L47" ], "voltage" : "", "net_name" : "C2_DDR4_DQ<61>_XF" }, "C3_RDIMM_DQS_T<3>_XF" : { "diff_pair_pol" : "POS", "net_name" : "C3_RDIMM_DQS_T<3>_XF", "diff_pair_mate" : "C3_RDIMM_DQS_C<3>_XF", "voltage" : "", "node_list" : [ "J4_XF.186", "U1_XF.H21" ] }, "UNNAMED_3_BYPASSCAPNPOL_I150_A_SP" : { "node_list" : [ "C24_SP_XF.1", "R36_SP_XF.1", "U1_SP_XF.49" ], "net_name" : "UNNAMED_3_BYPASSCAPNPOL_I150_A_SP", "voltage" : "" }, "OCL2_3R3V_CPRSNT_F_XF" : { "node_list" : [ "J1_O2_XF.A13", "U1_XF.AW17" ], "voltage" : "3.3V", "net_name" : "OCL2_3R3V_CPRSNT_F_XF" }, "C2_DDR4_DQ<31>_XF" : { "node_list" : [ "J3_XF.188", "U1_XF.G53" ], "voltage" : "", "net_name" : "C2_DDR4_DQ<31>_XF" }, "OCL1_FPGA_REFCLK_N_XF" : { "net_name" : "OCL1_FPGA_REFCLK_N_XF", "diff_pair_mate" : "OCL1_FPGA_REFCLK_P_XF", "diff_pair_pol" : "NEG", "voltage" : "", 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"voltage" : "", "net_name" : "MFG_E1" }, "UNNAMED_5_LT3071_I30_MARGA_FL" : { "net_name" : "UNNAMED_5_LT3071_I30_MARGA_FL", "voltage" : "", "node_list" : [ "R31_FL_XF.2", "U1_FL_XF.22" ] }, "C2_RDIMM_DQS_C<1>_XF" : { "net_name" : "C2_RDIMM_DQS_C<1>_XF", "diff_pair_mate" : "C2_RDIMM_DQS_T<1>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "J3_XF.163", "U1_XF.N46" ] }, "E1S1_3R3V_CKEN_F<1>_XF" : { "voltage" : "", "net_name" : "E1S1_3R3V_CKEN_F<1>_XF", "node_list" : [ "U1_E1_XF.19", "U1_XF.AD17" ] }, "CLKIN_N_E0" : { "node_list" : [ "C17_E0_XF.2", "R15_E0_XF.2", "R17_E0_XF.2", "R18_E0_XF.1", "U1_E0_XF.6" ], "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "CLKIN_P_E0", "net_name" : "CLKIN_N_E0" }, "OCL3_PET_N<2>_XF" : { "node_list" : [ "C279_XF.2", "J1_O3_XF.B16" ], "voltage" : "", "diff_pair_pol" : "NEG", "diff_pair_mate" : "OCL3_PET_P<2>_XF", "net_name" : "OCL3_PET_N<2>_XF" }, "FP_LAN_ACTLED_N<2>" : { "node_list" : [ "FPNL_CONN.24", "U1_CPLD.G16" ], "net_name" : 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"voltage" : "", "net_name" : "FPGA_INIT_F_1", "node_list" : [ "R28_XF.2", "U1_CPLD.J6", "U1_XF.AJ19" ] }, "C1_DDR4_CS_N<3>_XF" : { "node_list" : [ "J2_XF.237", "U1_XF.BY62" ], "voltage" : "", "net_name" : "C1_DDR4_CS_N<3>_XF" }, "C2_RDIMM_DQS_C<0>_XF" : { "voltage" : "", "net_name" : "C2_RDIMM_DQS_C<0>_XF", "diff_pair_mate" : "C2_RDIMM_DQS_T<0>_XF", "diff_pair_pol" : "NEG", "node_list" : [ "J3_XF.152", "U1_XF.V48" ] }, "C1_DDR4_DQ<25>_XF" : { "node_list" : [ "J2_XF.183", "U1_XF.BY59" ], "net_name" : "C1_DDR4_DQ<25>_XF", "voltage" : "" }, "TS_FPGA_P_XF" : { "node_list" : [ "U1_XF.AP25", "U4_SP_XF.1" ], "voltage" : "", "net_name" : "TS_FPGA_P_XF", "diff_pair_mate" : "TS_FPGA_N_XF", "diff_pair_pol" : "POS" }, "IS_VCCINTLR_SW_P_SP" : { "node_list" : [ "C183_SP_XF.1", "R195_SP_XF.1", "R196_SP_XF.2", "R48_SP_XF.2" ], "net_name" : "IS_VCCINTLR_SW_P_SP", "diff_pair_mate" : "IS_VCCINTLR_SW_N_SP", "diff_pair_pol" : "POS", "voltage" : "" }, "C1_RDIMM_DQS_C<17>_XF" : { "diff_pair_pol" : "NEG", "diff_pair_mate" : "C1_RDIMM_DQS_T<17>_XF", "net_name" : "C1_RDIMM_DQS_C<17>_XF", "voltage" : "", "node_list" : [ "J2_XF.52", "U1_XF.BR58" ] }, "C3_DDR4_CS_N<0>_XF" : { "node_list" : [ "J4_XF.84", "U1_XF.N22" ], "net_name" : "C3_DDR4_CS_N<0>_XF", "voltage" : "" }, "E1S2_PET_N<6>_XF" : { "net_name" : "E1S2_PET_N<6>_XF", "diff_pair_mate" : "E1S2_PET_P<6>_XF", "diff_pair_pol" : "NEG", "voltage" : "", "node_list" : [ "C157_XF.2", "J1_E2_XF.B36" ] }, "E1S0_PER_P<3>_XF" : { "net_name" : "E1S0_PER_P<3>_XF", "diff_pair_mate" : "E1S0_PER_N<3>_XF", "diff_pair_pol" : "POS", "voltage" : "", "node_list" : [ "J1_E0_XF.A27", "U1_XF.D4" ] }, "UNNAMED_3_LTM4675_I40_TSNS01_SD" : { "voltage" : "", "net_name" : "UNNAMED_3_LTM4675_I40_TSNS01_SD", "node_list" : [ "PM4_SD_XF.C3", "PM4_SD_XF.D3" ] }, "FPGA_CPLD_SSTAT_CLK" : { "net_name" : "FPGA_CPLD_SSTAT_CLK", "voltage" : "", "node_list" : [ "U1_CPLD.J1", "U1_XF.BV37" ] }, "AC_CONN_CLK_REFP<1>_1" : { "voltage" : "", "diff_pair_pol" : "POS", "net_name" : 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"node_list" : [ "J1_XF.72", "U1_XF.CA16" ], "voltage" : "", "net_name" : "C0_DDR4_ADR<1>_XF" }, "JTAG_CTL_TMS" : { "net_name" : "JTAG_CTL_TMS", "voltage" : "", "node_list" : [ "U1_CPLD.G4", "U1_XF.CA31" ] }, "E1S1_3R3V_LED_XF" : { "voltage" : "3.3V", "net_name" : "E1S1_3R3V_LED_XF", "node_list" : [ "J1_E1_XF.A10", "R6_E1_XF.2", "U1_XF.AF17" ] }, "POK_OD_SDIMM_VDD_SW" : { "node_list" : [ "R2_SD_XF.2", "R3_SD_XF.2", "U1_CPLD.L9" ], "net_name" : "POK_OD_SDIMM_VDD_SW", "voltage" : "" }, "PWR_AVTT_RUC_XF" : { "node_list" : [ "C34_FL_XF.1", "C457_XF.1", "C458_XF.1", "C459_XF.1", "C460_XF.1", "C461_XF.1", "C462_XF.1", "C58_FL_XF.1", "C61_FL_XF.1", "C64_FL_XF.1", "NS9_FL_XF.1", "R267_XF.1", "U1_XF.AA9", "U1_XF.AC13", "U1_XF.AC9", "U1_XF.AE13", "U1_XF.AE9", "U1_XF.AG13", "U1_XF.AG9", "U1_XF.AJ13", "U1_XF.AJ15", "U1_XF.AJ9", "U1_XF.AL9", "U1_XF.U9", "U1_XF.V11", "U1_XF.W9", "U1_XF.Y11", "U5_FL_XF.15", "U5_FL_XF.16", "U5_FL_XF.17", "U5_FL_XF.18" ], "net_name" : "PWR_AVTT_RUC_XF", "voltage" : "1.2" }, "UNNAMED_9_LT3071_I66_SENSE_FL" : { "net_name" : "UNNAMED_9_LT3071_I66_SENSE_FL", "voltage" : "", "node_list" : [ "NS11_FL_XF.2", "U11_FL_XF.19" ] }, "VMON_AVTT_RLC_LIN_XF" : { "voltage" : "", "net_name" : "VMON_AVTT_RLC_LIN_XF", "node_list" : [ "R110_XF.1", "R56_FL_XF.2" ] }, "VDD_VS_P_SD" : { "node_list" : [ "NS2_SD_XF.2", "PM4_SD_XF.D7", "PM4_SD_XF.J7" ], "diff_pair_pol" : "POS", "net_name" : "VDD_VS_P_SD", "diff_pair_mate" : "VDD_VS_N_SD", "voltage" : "" }, "AC_OCL0_FPGA_REFCLK_N_XF" : { "node_list" : [ "C370_XF.1", "U7_XF.23" ], "voltage" : "", "diff_pair_mate" : "AC_OCL0_FPGA_REFCLK_P_XF", "net_name" : "AC_OCL0_FPGA_REFCLK_N_XF", "diff_pair_pol" : "NEG" }, "VS_AVCC_RN_LIN_FL" : { "node_list" : [ "NS4_FL_XF.2", "R84_FL_XF.1", "U6_FL_XF.19" ], "net_name" : "VS_AVCC_RN_LIN_FL", "voltage" : "" }, "E1S3_PER_N<7>_XF" : { "voltage" : "", "diff_pair_pol" : "NEG", "net_name" : "E1S3_PER_N<7>_XF", "diff_pair_mate" : "E1S3_PER_P<7>_XF", "node_list" : [ "J1_E3_XF.A39", "U1_XF.AK3" ] }, "C0_DDR4_DQ<19>_XF" : { "voltage" : "", "net_name" : "C0_DDR4_DQ<19>_XF", "node_list" : [ "J1_XF.179", "U1_XF.BR17" ] }, "AC_E1S0_PET_P<4>_XF" : { "diff_pair_pol" : "POS", "net_name" : "AC_E1S0_PET_P<4>_XF", "diff_pair_mate" : "AC_E1S0_PET_N<4>_XF", "voltage" : "", "node_list" : [ "C105_XF.1", "U1_XF.F9" ] }, "SW0_NODE_ND" : { "node_list" : [ "PM4_ND_XF.B8" ], "net_name" : "SW0_NODE_ND", "voltage" : "12" }, "UNNAMED_3_598BICOLORLED_I68_L2A" : { "net_name" : "UNNAMED_3_598BICOLORLED_I68_L2A", "voltage" : "", "node_list" : [ "D1.1", "R79.2" ] }, "AC_E1S1_PET_N<5>_XF" : { "node_list" : [ "C132_XF.1", "U1_XF.T8" ], "voltage" : "", "diff_pair_mate" : "AC_E1S1_PET_P<5>_XF", "net_name" : "AC_E1S1_PET_N<5>_XF", "diff_pair_pol" : "NEG" }, "C0_DDR4_DQ<26>_XF" : { "net_name" : "C0_DDR4_DQ<26>_XF", "voltage" : "", "node_list" : [ "J1_XF.45", "U1_XF.BT25" ] }, "E1S0_PER_P<6>_XF" : { "node_list" : [ "J1_E0_XF.A37", "U1_XF.G6" ], "diff_pair_mate" : "E1S0_PER_N<6>_XF", "net_name" : "E1S0_PER_P<6>_XF", "diff_pair_pol" : "POS", "voltage" : "" }, "C3_DDR4_DQ<58>_XF" : { "node_list" : [ "J4_XF.137", "U1_XF.C18" ], "voltage" : "", "net_name" : "C3_DDR4_DQ<58>_XF" }, "E1S2_PET_N<3>_XF" : { "node_list" : [ "C170_XF.2", "J1_E2_XF.B26" ], "diff_pair_pol" : "NEG", "diff_pair_mate" : "E1S2_PET_P<3>_XF", "net_name" : "E1S2_PET_N<3>_XF", "voltage" : "" }, "C3_DDR4_BA<0>_XF" : { "node_list" : [ "J4_XF.81", "U1_XF.R22" ], "net_name" : "C3_DDR4_BA<0>_XF", "voltage" : "" }, "UNNAMED_7_LT3071_I30_PWRGD_FL" : { "voltage" : "", "net_name" : "UNNAMED_7_LT3071_I30_PWRGD_FL", "node_list" : [ "R19_FL_XF.1", "U4_FL_XF.2" ] } } }